1 /* smp.c: Sparc64 SMP support.
3 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
10 #include <linux/pagemap.h>
11 #include <linux/threads.h>
12 #include <linux/smp.h>
13 #include <linux/smp_lock.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/delay.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
20 #include <linux/seq_file.h>
21 #include <linux/cache.h>
22 #include <linux/jiffies.h>
23 #include <linux/profile.h>
24 #include <linux/bootmem.h>
27 #include <asm/ptrace.h>
28 #include <asm/atomic.h>
29 #include <asm/tlbflush.h>
30 #include <asm/mmu_context.h>
31 #include <asm/cpudata.h>
34 #include <asm/irq_regs.h>
36 #include <asm/pgtable.h>
37 #include <asm/oplib.h>
38 #include <asm/uaccess.h>
39 #include <asm/timer.h>
40 #include <asm/starfire.h>
42 #include <asm/sections.h>
45 extern void calibrate_delay(void);
47 /* Please don't make this stuff initdata!!! --DaveM */
48 unsigned char boot_cpu_id;
50 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
51 cpumask_t phys_cpu_present_map __read_mostly = CPU_MASK_NONE;
52 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly =
53 { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
54 static cpumask_t smp_commenced_mask;
55 static cpumask_t cpu_callout_map;
57 void smp_info(struct seq_file *m)
61 seq_printf(m, "State:\n");
62 for_each_online_cpu(i)
63 seq_printf(m, "CPU%d:\t\tonline\n", i);
66 void smp_bogo(struct seq_file *m)
70 for_each_online_cpu(i)
72 "Cpu%dBogo\t: %lu.%02lu\n"
73 "Cpu%dClkTck\t: %016lx\n",
74 i, cpu_data(i).udelay_val / (500000/HZ),
75 (cpu_data(i).udelay_val / (5000/HZ)) % 100,
76 i, cpu_data(i).clock_tick);
79 void __init smp_store_cpu_info(int id)
81 struct device_node *dp;
84 cpu_data(id).udelay_val = loops_per_jiffy;
86 cpu_find_by_mid(id, &dp);
87 cpu_data(id).clock_tick =
88 of_getintprop_default(dp, "clock-frequency", 0);
90 def = ((tlb_type == hypervisor) ? (8 * 1024) : (16 * 1024));
91 cpu_data(id).dcache_size =
92 of_getintprop_default(dp, "dcache-size", def);
95 cpu_data(id).dcache_line_size =
96 of_getintprop_default(dp, "dcache-line-size", def);
99 cpu_data(id).icache_size =
100 of_getintprop_default(dp, "icache-size", def);
103 cpu_data(id).icache_line_size =
104 of_getintprop_default(dp, "icache-line-size", def);
106 def = ((tlb_type == hypervisor) ?
109 cpu_data(id).ecache_size =
110 of_getintprop_default(dp, "ecache-size", def);
113 cpu_data(id).ecache_line_size =
114 of_getintprop_default(dp, "ecache-line-size", def);
116 printk("CPU[%d]: Caches "
117 "D[sz(%d):line_sz(%d)] "
118 "I[sz(%d):line_sz(%d)] "
119 "E[sz(%d):line_sz(%d)]\n",
121 cpu_data(id).dcache_size, cpu_data(id).dcache_line_size,
122 cpu_data(id).icache_size, cpu_data(id).icache_line_size,
123 cpu_data(id).ecache_size, cpu_data(id).ecache_line_size);
126 static void smp_setup_percpu_timer(void);
128 static volatile unsigned long callin_flag = 0;
130 void __init smp_callin(void)
132 int cpuid = hard_smp_processor_id();
134 __local_per_cpu_offset = __per_cpu_offset(cpuid);
136 if (tlb_type == hypervisor)
137 sun4v_ktsb_register();
141 smp_setup_percpu_timer();
143 if (cheetah_pcache_forced_on)
144 cheetah_enable_pcache();
149 smp_store_cpu_info(cpuid);
151 __asm__ __volatile__("membar #Sync\n\t"
152 "flush %%g6" : : : "memory");
154 /* Clear this or we will die instantly when we
155 * schedule back to this idler...
157 current_thread_info()->new_child = 0;
159 /* Attach to the address space of init_task. */
160 atomic_inc(&init_mm.mm_count);
161 current->active_mm = &init_mm;
163 while (!cpu_isset(cpuid, smp_commenced_mask))
166 cpu_set(cpuid, cpu_online_map);
168 /* idle thread is expected to have preempt disabled */
174 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
175 panic("SMP bolixed\n");
178 static unsigned long current_tick_offset __read_mostly;
180 /* This tick register synchronization scheme is taken entirely from
181 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
183 * The only change I've made is to rework it so that the master
184 * initiates the synchonization instead of the slave. -DaveM
188 #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
190 #define NUM_ROUNDS 64 /* magic value */
191 #define NUM_ITERS 5 /* likewise */
193 static DEFINE_SPINLOCK(itc_sync_lock);
194 static unsigned long go[SLAVE + 1];
196 #define DEBUG_TICK_SYNC 0
198 static inline long get_delta (long *rt, long *master)
200 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
201 unsigned long tcenter, t0, t1, tm;
204 for (i = 0; i < NUM_ITERS; i++) {
205 t0 = tick_ops->get_tick();
208 while (!(tm = go[SLAVE]))
212 t1 = tick_ops->get_tick();
214 if (t1 - t0 < best_t1 - best_t0)
215 best_t0 = t0, best_t1 = t1, best_tm = tm;
218 *rt = best_t1 - best_t0;
219 *master = best_tm - best_t0;
221 /* average best_t0 and best_t1 without overflow: */
222 tcenter = (best_t0/2 + best_t1/2);
223 if (best_t0 % 2 + best_t1 % 2 == 2)
225 return tcenter - best_tm;
228 void smp_synchronize_tick_client(void)
230 long i, delta, adj, adjust_latency = 0, done = 0;
231 unsigned long flags, rt, master_time_stamp, bound;
234 long rt; /* roundtrip time */
235 long master; /* master's timestamp */
236 long diff; /* difference between midpoint and master's timestamp */
237 long lat; /* estimate of itc adjustment latency */
246 local_irq_save(flags);
248 for (i = 0; i < NUM_ROUNDS; i++) {
249 delta = get_delta(&rt, &master_time_stamp);
251 done = 1; /* let's lock on to this... */
257 adjust_latency += -delta;
258 adj = -delta + adjust_latency/4;
262 tick_ops->add_tick(adj, current_tick_offset);
266 t[i].master = master_time_stamp;
268 t[i].lat = adjust_latency/4;
272 local_irq_restore(flags);
275 for (i = 0; i < NUM_ROUNDS; i++)
276 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
277 t[i].rt, t[i].master, t[i].diff, t[i].lat);
280 printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
281 "maxerr %lu cycles)\n", smp_processor_id(), delta, rt);
284 static void smp_start_sync_tick_client(int cpu);
286 static void smp_synchronize_one_tick(int cpu)
288 unsigned long flags, i;
292 smp_start_sync_tick_client(cpu);
294 /* wait for client to be ready */
298 /* now let the client proceed into his loop */
302 spin_lock_irqsave(&itc_sync_lock, flags);
304 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
309 go[SLAVE] = tick_ops->get_tick();
313 spin_unlock_irqrestore(&itc_sync_lock, flags);
316 extern void sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load);
318 extern unsigned long sparc64_cpu_startup;
320 /* The OBP cpu startup callback truncates the 3rd arg cookie to
321 * 32-bits (I think) so to be safe we have it read the pointer
322 * contained here so we work on >4GB machines. -DaveM
324 static struct thread_info *cpu_new_thread = NULL;
326 static int __devinit smp_boot_one_cpu(unsigned int cpu)
328 unsigned long entry =
329 (unsigned long)(&sparc64_cpu_startup);
330 unsigned long cookie =
331 (unsigned long)(&cpu_new_thread);
332 struct task_struct *p;
337 cpu_new_thread = task_thread_info(p);
338 cpu_set(cpu, cpu_callout_map);
340 if (tlb_type == hypervisor) {
341 /* Alloc the mondo queues, cpu will load them. */
342 sun4v_init_mondo_queues(0, cpu, 1, 0);
344 prom_startcpu_cpuid(cpu, entry, cookie);
346 struct device_node *dp;
348 cpu_find_by_mid(cpu, &dp);
349 prom_startcpu(dp->node, entry, cookie);
352 for (timeout = 0; timeout < 5000000; timeout++) {
361 printk("Processor %d is stuck.\n", cpu);
362 cpu_clear(cpu, cpu_callout_map);
365 cpu_new_thread = NULL;
370 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
375 if (this_is_starfire) {
376 /* map to real upaid */
377 cpu = (((cpu & 0x3c) << 1) |
378 ((cpu & 0x40) >> 4) |
382 target = (cpu << 14) | 0x70;
384 /* Ok, this is the real Spitfire Errata #54.
385 * One must read back from a UDB internal register
386 * after writes to the UDB interrupt dispatch, but
387 * before the membar Sync for that write.
388 * So we use the high UDB control register (ASI 0x7f,
389 * ADDR 0x20) for the dummy read. -DaveM
392 __asm__ __volatile__(
393 "wrpr %1, %2, %%pstate\n\t"
394 "stxa %4, [%0] %3\n\t"
395 "stxa %5, [%0+%8] %3\n\t"
397 "stxa %6, [%0+%8] %3\n\t"
399 "stxa %%g0, [%7] %3\n\t"
402 "ldxa [%%g1] 0x7f, %%g0\n\t"
405 : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
406 "r" (data0), "r" (data1), "r" (data2), "r" (target),
407 "r" (0x10), "0" (tmp)
410 /* NOTE: PSTATE_IE is still clear. */
413 __asm__ __volatile__("ldxa [%%g0] %1, %0"
415 : "i" (ASI_INTR_DISPATCH_STAT));
417 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
424 } while (result & 0x1);
425 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
428 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
429 smp_processor_id(), result);
436 static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
441 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
442 for_each_cpu_mask(i, mask)
443 spitfire_xcall_helper(data0, data1, data2, pstate, i);
446 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
447 * packet, but we have no use for that. However we do take advantage of
448 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
450 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
453 int nack_busy_id, is_jbus;
455 if (cpus_empty(mask))
458 /* Unfortunately, someone at Sun had the brilliant idea to make the
459 * busy/nack fields hard-coded by ITID number for this Ultra-III
460 * derivative processor.
462 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
463 is_jbus = ((ver >> 32) == __JALAPENO_ID ||
464 (ver >> 32) == __SERRANO_ID);
466 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
469 __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
470 : : "r" (pstate), "i" (PSTATE_IE));
472 /* Setup the dispatch data registers. */
473 __asm__ __volatile__("stxa %0, [%3] %6\n\t"
474 "stxa %1, [%4] %6\n\t"
475 "stxa %2, [%5] %6\n\t"
478 : "r" (data0), "r" (data1), "r" (data2),
479 "r" (0x40), "r" (0x50), "r" (0x60),
486 for_each_cpu_mask(i, mask) {
487 u64 target = (i << 14) | 0x70;
490 target |= (nack_busy_id << 24);
491 __asm__ __volatile__(
492 "stxa %%g0, [%0] %1\n\t"
495 : "r" (target), "i" (ASI_INTR_W));
500 /* Now, poll for completion. */
505 stuck = 100000 * nack_busy_id;
507 __asm__ __volatile__("ldxa [%%g0] %1, %0"
508 : "=r" (dispatch_stat)
509 : "i" (ASI_INTR_DISPATCH_STAT));
510 if (dispatch_stat == 0UL) {
511 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
517 } while (dispatch_stat & 0x5555555555555555UL);
519 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
522 if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) {
523 /* Busy bits will not clear, continue instead
524 * of freezing up on this cpu.
526 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
527 smp_processor_id(), dispatch_stat);
529 int i, this_busy_nack = 0;
531 /* Delay some random time with interrupts enabled
532 * to prevent deadlock.
534 udelay(2 * nack_busy_id);
536 /* Clear out the mask bits for cpus which did not
539 for_each_cpu_mask(i, mask) {
543 check_mask = (0x2UL << (2*i));
545 check_mask = (0x2UL <<
547 if ((dispatch_stat & check_mask) == 0)
557 /* Multi-cpu list version. */
558 static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
560 struct trap_per_cpu *tb;
563 cpumask_t error_mask;
564 unsigned long flags, status;
565 int cnt, retries, this_cpu, prev_sent, i;
567 /* We have to do this whole thing with interrupts fully disabled.
568 * Otherwise if we send an xcall from interrupt context it will
569 * corrupt both our mondo block and cpu list state.
571 * One consequence of this is that we cannot use timeout mechanisms
572 * that depend upon interrupts being delivered locally. So, for
573 * example, we cannot sample jiffies and expect it to advance.
575 * Fortunately, udelay() uses %stick/%tick so we can use that.
577 local_irq_save(flags);
579 this_cpu = smp_processor_id();
580 tb = &trap_block[this_cpu];
582 mondo = __va(tb->cpu_mondo_block_pa);
588 cpu_list = __va(tb->cpu_list_pa);
590 /* Setup the initial cpu list. */
592 for_each_cpu_mask(i, mask)
595 cpus_clear(error_mask);
599 int forward_progress, n_sent;
601 status = sun4v_cpu_mondo_send(cnt,
603 tb->cpu_mondo_block_pa);
605 /* HV_EOK means all cpus received the xcall, we're done. */
606 if (likely(status == HV_EOK))
609 /* First, see if we made any forward progress.
611 * The hypervisor indicates successful sends by setting
612 * cpu list entries to the value 0xffff.
615 for (i = 0; i < cnt; i++) {
616 if (likely(cpu_list[i] == 0xffff))
620 forward_progress = 0;
621 if (n_sent > prev_sent)
622 forward_progress = 1;
626 /* If we get a HV_ECPUERROR, then one or more of the cpus
627 * in the list are in error state. Use the cpu_state()
628 * hypervisor call to find out which cpus are in error state.
630 if (unlikely(status == HV_ECPUERROR)) {
631 for (i = 0; i < cnt; i++) {
639 err = sun4v_cpu_state(cpu);
641 err == HV_CPU_STATE_ERROR) {
642 cpu_list[i] = 0xffff;
643 cpu_set(cpu, error_mask);
646 } else if (unlikely(status != HV_EWOULDBLOCK))
647 goto fatal_mondo_error;
649 /* Don't bother rewriting the CPU list, just leave the
650 * 0xffff and non-0xffff entries in there and the
651 * hypervisor will do the right thing.
653 * Only advance timeout state if we didn't make any
656 if (unlikely(!forward_progress)) {
657 if (unlikely(++retries > 10000))
658 goto fatal_mondo_timeout;
660 /* Delay a little bit to let other cpus catch up
661 * on their cpu mondo queue work.
667 local_irq_restore(flags);
669 if (unlikely(!cpus_empty(error_mask)))
670 goto fatal_mondo_cpu_error;
674 fatal_mondo_cpu_error:
675 printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
676 "were in error state\n",
678 printk(KERN_CRIT "CPU[%d]: Error mask [ ", this_cpu);
679 for_each_cpu_mask(i, error_mask)
685 local_irq_restore(flags);
686 printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
687 " progress after %d retries.\n",
689 goto dump_cpu_list_and_out;
692 local_irq_restore(flags);
693 printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
695 printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
696 "mondo_block_pa(%lx)\n",
697 this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
699 dump_cpu_list_and_out:
700 printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
701 for (i = 0; i < cnt; i++)
702 printk("%u ", cpu_list[i]);
706 /* Send cross call to all processors mentioned in MASK
709 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
711 u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
712 int this_cpu = get_cpu();
714 cpus_and(mask, mask, cpu_online_map);
715 cpu_clear(this_cpu, mask);
717 if (tlb_type == spitfire)
718 spitfire_xcall_deliver(data0, data1, data2, mask);
719 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
720 cheetah_xcall_deliver(data0, data1, data2, mask);
722 hypervisor_xcall_deliver(data0, data1, data2, mask);
723 /* NOTE: Caller runs local copy on master. */
728 extern unsigned long xcall_sync_tick;
730 static void smp_start_sync_tick_client(int cpu)
732 cpumask_t mask = cpumask_of_cpu(cpu);
734 smp_cross_call_masked(&xcall_sync_tick,
738 /* Send cross call to all processors except self. */
739 #define smp_cross_call(func, ctx, data1, data2) \
740 smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
742 struct call_data_struct {
743 void (*func) (void *info);
749 static __cacheline_aligned_in_smp DEFINE_SPINLOCK(call_lock);
750 static struct call_data_struct *call_data;
752 extern unsigned long xcall_call_function;
755 * smp_call_function(): Run a function on all other CPUs.
756 * @func: The function to run. This must be fast and non-blocking.
757 * @info: An arbitrary pointer to pass to the function.
758 * @nonatomic: currently unused.
759 * @wait: If true, wait (atomically) until function has completed on other CPUs.
761 * Returns 0 on success, else a negative status code. Does not return until
762 * remote CPUs are nearly ready to execute <<func>> or are or have executed.
764 * You must not call this function with disabled interrupts or from a
765 * hardware interrupt handler or from a bottom half handler.
767 static int smp_call_function_mask(void (*func)(void *info), void *info,
768 int nonatomic, int wait, cpumask_t mask)
770 struct call_data_struct data;
773 /* Can deadlock when called with interrupts disabled */
774 WARN_ON(irqs_disabled());
778 atomic_set(&data.finished, 0);
781 spin_lock(&call_lock);
783 cpu_clear(smp_processor_id(), mask);
784 cpus = cpus_weight(mask);
791 smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask);
793 /* Wait for response */
794 while (atomic_read(&data.finished) != cpus)
798 spin_unlock(&call_lock);
803 int smp_call_function(void (*func)(void *info), void *info,
804 int nonatomic, int wait)
806 return smp_call_function_mask(func, info, nonatomic, wait,
810 void smp_call_function_client(int irq, struct pt_regs *regs)
812 void (*func) (void *info) = call_data->func;
813 void *info = call_data->info;
815 clear_softint(1 << irq);
816 if (call_data->wait) {
817 /* let initiator proceed only after completion */
819 atomic_inc(&call_data->finished);
821 /* let initiator proceed after getting data */
822 atomic_inc(&call_data->finished);
827 static void tsb_sync(void *info)
829 struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
830 struct mm_struct *mm = info;
832 /* It is not valid to test "currrent->active_mm == mm" here.
834 * The value of "current" is not changed atomically with
835 * switch_mm(). But that's OK, we just need to check the
836 * current cpu's trap block PGD physical address.
838 if (tp->pgd_paddr == __pa(mm->pgd))
839 tsb_context_switch(mm);
842 void smp_tsb_sync(struct mm_struct *mm)
844 smp_call_function_mask(tsb_sync, mm, 0, 1, mm->cpu_vm_mask);
847 extern unsigned long xcall_flush_tlb_mm;
848 extern unsigned long xcall_flush_tlb_pending;
849 extern unsigned long xcall_flush_tlb_kernel_range;
850 extern unsigned long xcall_report_regs;
851 extern unsigned long xcall_receive_signal;
852 extern unsigned long xcall_new_mmu_context_version;
854 #ifdef DCACHE_ALIASING_POSSIBLE
855 extern unsigned long xcall_flush_dcache_page_cheetah;
857 extern unsigned long xcall_flush_dcache_page_spitfire;
859 #ifdef CONFIG_DEBUG_DCFLUSH
860 extern atomic_t dcpage_flushes;
861 extern atomic_t dcpage_flushes_xcall;
864 static __inline__ void __local_flush_dcache_page(struct page *page)
866 #ifdef DCACHE_ALIASING_POSSIBLE
867 __flush_dcache_page(page_address(page),
868 ((tlb_type == spitfire) &&
869 page_mapping(page) != NULL));
871 if (page_mapping(page) != NULL &&
872 tlb_type == spitfire)
873 __flush_icache_page(__pa(page_address(page)));
877 void smp_flush_dcache_page_impl(struct page *page, int cpu)
879 cpumask_t mask = cpumask_of_cpu(cpu);
882 if (tlb_type == hypervisor)
885 #ifdef CONFIG_DEBUG_DCFLUSH
886 atomic_inc(&dcpage_flushes);
889 this_cpu = get_cpu();
891 if (cpu == this_cpu) {
892 __local_flush_dcache_page(page);
893 } else if (cpu_online(cpu)) {
894 void *pg_addr = page_address(page);
897 if (tlb_type == spitfire) {
899 ((u64)&xcall_flush_dcache_page_spitfire);
900 if (page_mapping(page) != NULL)
901 data0 |= ((u64)1 << 32);
902 spitfire_xcall_deliver(data0,
906 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
907 #ifdef DCACHE_ALIASING_POSSIBLE
909 ((u64)&xcall_flush_dcache_page_cheetah);
910 cheetah_xcall_deliver(data0,
915 #ifdef CONFIG_DEBUG_DCFLUSH
916 atomic_inc(&dcpage_flushes_xcall);
923 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
925 void *pg_addr = page_address(page);
926 cpumask_t mask = cpu_online_map;
930 if (tlb_type == hypervisor)
933 this_cpu = get_cpu();
935 cpu_clear(this_cpu, mask);
937 #ifdef CONFIG_DEBUG_DCFLUSH
938 atomic_inc(&dcpage_flushes);
940 if (cpus_empty(mask))
942 if (tlb_type == spitfire) {
943 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
944 if (page_mapping(page) != NULL)
945 data0 |= ((u64)1 << 32);
946 spitfire_xcall_deliver(data0,
950 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
951 #ifdef DCACHE_ALIASING_POSSIBLE
952 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
953 cheetah_xcall_deliver(data0,
958 #ifdef CONFIG_DEBUG_DCFLUSH
959 atomic_inc(&dcpage_flushes_xcall);
962 __local_flush_dcache_page(page);
967 static void __smp_receive_signal_mask(cpumask_t mask)
969 smp_cross_call_masked(&xcall_receive_signal, 0, 0, 0, mask);
972 void smp_receive_signal(int cpu)
974 cpumask_t mask = cpumask_of_cpu(cpu);
977 __smp_receive_signal_mask(mask);
980 void smp_receive_signal_client(int irq, struct pt_regs *regs)
982 clear_softint(1 << irq);
985 void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
987 struct mm_struct *mm;
990 clear_softint(1 << irq);
992 /* See if we need to allocate a new TLB context because
993 * the version of the one we are using is now out of date.
995 mm = current->active_mm;
996 if (unlikely(!mm || (mm == &init_mm)))
999 spin_lock_irqsave(&mm->context.lock, flags);
1001 if (unlikely(!CTX_VALID(mm->context)))
1002 get_new_mmu_context(mm);
1004 spin_unlock_irqrestore(&mm->context.lock, flags);
1006 load_secondary_context(mm);
1007 __flush_tlb_mm(CTX_HWBITS(mm->context),
1011 void smp_new_mmu_context_version(void)
1013 smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
1016 void smp_report_regs(void)
1018 smp_cross_call(&xcall_report_regs, 0, 0, 0);
1021 /* We know that the window frames of the user have been flushed
1022 * to the stack before we get here because all callers of us
1023 * are flush_tlb_*() routines, and these run after flush_cache_*()
1024 * which performs the flushw.
1026 * The SMP TLB coherency scheme we use works as follows:
1028 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1029 * space has (potentially) executed on, this is the heuristic
1030 * we use to avoid doing cross calls.
1032 * Also, for flushing from kswapd and also for clones, we
1033 * use cpu_vm_mask as the list of cpus to make run the TLB.
1035 * 2) TLB context numbers are shared globally across all processors
1036 * in the system, this allows us to play several games to avoid
1039 * One invariant is that when a cpu switches to a process, and
1040 * that processes tsk->active_mm->cpu_vm_mask does not have the
1041 * current cpu's bit set, that tlb context is flushed locally.
1043 * If the address space is non-shared (ie. mm->count == 1) we avoid
1044 * cross calls when we want to flush the currently running process's
1045 * tlb state. This is done by clearing all cpu bits except the current
1046 * processor's in current->active_mm->cpu_vm_mask and performing the
1047 * flush locally only. This will force any subsequent cpus which run
1048 * this task to flush the context from the local tlb if the process
1049 * migrates to another cpu (again).
1051 * 3) For shared address spaces (threads) and swapping we bite the
1052 * bullet for most cases and perform the cross call (but only to
1053 * the cpus listed in cpu_vm_mask).
1055 * The performance gain from "optimizing" away the cross call for threads is
1056 * questionable (in theory the big win for threads is the massive sharing of
1057 * address space state across processors).
1060 /* This currently is only used by the hugetlb arch pre-fault
1061 * hook on UltraSPARC-III+ and later when changing the pagesize
1062 * bits of the context register for an address space.
1064 void smp_flush_tlb_mm(struct mm_struct *mm)
1066 u32 ctx = CTX_HWBITS(mm->context);
1067 int cpu = get_cpu();
1069 if (atomic_read(&mm->mm_users) == 1) {
1070 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1071 goto local_flush_and_out;
1074 smp_cross_call_masked(&xcall_flush_tlb_mm,
1078 local_flush_and_out:
1079 __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1084 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1086 u32 ctx = CTX_HWBITS(mm->context);
1087 int cpu = get_cpu();
1089 if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
1090 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1092 smp_cross_call_masked(&xcall_flush_tlb_pending,
1093 ctx, nr, (unsigned long) vaddrs,
1096 __flush_tlb_pending(ctx, nr, vaddrs);
1101 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1104 end = PAGE_ALIGN(end);
1106 smp_cross_call(&xcall_flush_tlb_kernel_range,
1109 __flush_tlb_kernel_range(start, end);
1114 /* #define CAPTURE_DEBUG */
1115 extern unsigned long xcall_capture;
1117 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1118 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1119 static unsigned long penguins_are_doing_time;
1121 void smp_capture(void)
1123 int result = atomic_add_ret(1, &smp_capture_depth);
1126 int ncpus = num_online_cpus();
1128 #ifdef CAPTURE_DEBUG
1129 printk("CPU[%d]: Sending penguins to jail...",
1130 smp_processor_id());
1132 penguins_are_doing_time = 1;
1133 membar_storestore_loadstore();
1134 atomic_inc(&smp_capture_registry);
1135 smp_cross_call(&xcall_capture, 0, 0, 0);
1136 while (atomic_read(&smp_capture_registry) != ncpus)
1138 #ifdef CAPTURE_DEBUG
1144 void smp_release(void)
1146 if (atomic_dec_and_test(&smp_capture_depth)) {
1147 #ifdef CAPTURE_DEBUG
1148 printk("CPU[%d]: Giving pardon to "
1149 "imprisoned penguins\n",
1150 smp_processor_id());
1152 penguins_are_doing_time = 0;
1153 membar_storeload_storestore();
1154 atomic_dec(&smp_capture_registry);
1158 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
1159 * can service tlb flush xcalls...
1161 extern void prom_world(int);
1163 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
1165 clear_softint(1 << irq);
1169 __asm__ __volatile__("flushw");
1171 atomic_inc(&smp_capture_registry);
1172 membar_storeload_storestore();
1173 while (penguins_are_doing_time)
1175 atomic_dec(&smp_capture_registry);
1181 static void __init smp_setup_percpu_timer(void)
1183 unsigned long pstate;
1185 /* Guarantee that the following sequences execute
1188 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
1189 "wrpr %0, %1, %%pstate"
1193 tick_ops->init_tick(current_tick_offset);
1195 /* Restore PSTATE_IE. */
1196 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
1201 void __init smp_tick_init(void)
1203 boot_cpu_id = hard_smp_processor_id();
1204 current_tick_offset = timer_tick_offset;
1207 /* /proc/profile writes can call this, don't __init it please. */
1208 int setup_profiling_timer(unsigned int multiplier)
1213 static void __init smp_tune_scheduling(void)
1215 struct device_node *dp;
1217 unsigned int def, smallest = ~0U;
1219 def = ((tlb_type == hypervisor) ?
1224 while (!cpu_find_by_instance(instance, &dp, NULL)) {
1227 val = of_getintprop_default(dp, "ecache-size", def);
1234 /* Any value less than 256K is nonsense. */
1235 if (smallest < (256U * 1024U))
1236 smallest = 256 * 1024;
1238 max_cache_size = smallest;
1240 if (smallest < 1U * 1024U * 1024U)
1241 printk(KERN_INFO "Using max_cache_size of %uKB\n",
1244 printk(KERN_INFO "Using max_cache_size of %uMB\n",
1245 smallest / 1024U / 1024U);
1248 /* Constrain the number of cpus to max_cpus. */
1249 void __init smp_prepare_cpus(unsigned int max_cpus)
1253 if (num_possible_cpus() > max_cpus) {
1257 while (!cpu_find_by_instance(instance, NULL, &mid)) {
1258 if (mid != boot_cpu_id) {
1259 cpu_clear(mid, phys_cpu_present_map);
1260 cpu_clear(mid, cpu_present_map);
1261 if (num_possible_cpus() <= max_cpus)
1268 for_each_possible_cpu(i) {
1269 if (tlb_type == hypervisor) {
1272 /* XXX get this mapping from machine description */
1273 for_each_possible_cpu(j) {
1274 if ((j >> 2) == (i >> 2))
1275 cpu_set(j, cpu_sibling_map[i]);
1278 cpu_set(i, cpu_sibling_map[i]);
1282 smp_store_cpu_info(boot_cpu_id);
1283 smp_tune_scheduling();
1286 /* Set this up early so that things like the scheduler can init
1287 * properly. We use the same cpu mask for both the present and
1290 void __init smp_setup_cpu_possible_map(void)
1295 while (!cpu_find_by_instance(instance, NULL, &mid)) {
1296 if (mid < NR_CPUS) {
1297 cpu_set(mid, phys_cpu_present_map);
1298 cpu_set(mid, cpu_present_map);
1304 void __devinit smp_prepare_boot_cpu(void)
1308 int __cpuinit __cpu_up(unsigned int cpu)
1310 int ret = smp_boot_one_cpu(cpu);
1313 cpu_set(cpu, smp_commenced_mask);
1314 while (!cpu_isset(cpu, cpu_online_map))
1316 if (!cpu_isset(cpu, cpu_online_map)) {
1319 /* On SUN4V, writes to %tick and %stick are
1322 if (tlb_type != hypervisor)
1323 smp_synchronize_one_tick(cpu);
1329 void __init smp_cpus_done(unsigned int max_cpus)
1331 unsigned long bogosum = 0;
1334 for_each_online_cpu(i)
1335 bogosum += cpu_data(i).udelay_val;
1336 printk("Total of %ld processors activated "
1337 "(%lu.%02lu BogoMIPS).\n",
1338 (long) num_online_cpus(),
1339 bogosum/(500000/HZ),
1340 (bogosum/(5000/HZ))%100);
1343 void smp_send_reschedule(int cpu)
1345 smp_receive_signal(cpu);
1348 /* This is a nop because we capture all other cpus
1349 * anyways when making the PROM active.
1351 void smp_send_stop(void)
1355 unsigned long __per_cpu_base __read_mostly;
1356 unsigned long __per_cpu_shift __read_mostly;
1358 EXPORT_SYMBOL(__per_cpu_base);
1359 EXPORT_SYMBOL(__per_cpu_shift);
1361 void __init setup_per_cpu_areas(void)
1363 unsigned long goal, size, i;
1366 /* Copy section for each CPU (we discard the original) */
1367 goal = PERCPU_ENOUGH_ROOM;
1369 __per_cpu_shift = 0;
1370 for (size = 1UL; size < goal; size <<= 1UL)
1373 ptr = alloc_bootmem(size * NR_CPUS);
1375 __per_cpu_base = ptr - __per_cpu_start;
1377 for (i = 0; i < NR_CPUS; i++, ptr += size)
1378 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1380 /* Setup %g5 for the boot cpu. */
1381 __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());