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   1 /*
   2  * linux/arch/arm/plat-omap/dmtimer.c
   3  *
   4  * OMAP Dual-Mode Timers
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * OMAP2 support by Juha Yrjola
   8  * API improvements and OMAP2 clock framework support by Timo Teras
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License as published by the
  12  * Free Software Foundation; either version 2 of the License, or (at your
  13  * option) any later version.
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  17  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  18  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  21  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  * You should have received a copy of the  GNU General Public License along
  25  * with this program; if not, write  to the Free Software Foundation, Inc.,
  26  * 675 Mass Ave, Cambridge, MA 02139, USA.
  27  */
  28
  29 #include <linux/init.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/errno.h>
  32 #include <linux/list.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <asm/hardware.h>
  36 #include <asm/arch/dmtimer.h>
  37 #include <asm/io.h>
  38 #include <asm/arch/irqs.h>
  39
  40 /* register offsets */
  41 #define OMAP_TIMER_ID_REG               0x00
  42 #define OMAP_TIMER_OCP_CFG_REG          0x10
  43 #define OMAP_TIMER_SYS_STAT_REG         0x14
  44 #define OMAP_TIMER_STAT_REG             0x18
  45 #define OMAP_TIMER_INT_EN_REG           0x1c
  46 #define OMAP_TIMER_WAKEUP_EN_REG        0x20
  47 #define OMAP_TIMER_CTRL_REG             0x24
  48 #define OMAP_TIMER_COUNTER_REG          0x28
  49 #define OMAP_TIMER_LOAD_REG             0x2c
  50 #define OMAP_TIMER_TRIGGER_REG          0x30
  51 #define OMAP_TIMER_WRITE_PEND_REG       0x34
  52 #define OMAP_TIMER_MATCH_REG            0x38
  53 #define OMAP_TIMER_CAPTURE_REG          0x3c
  54 #define OMAP_TIMER_IF_CTRL_REG          0x40
  55
  56 /* timer control reg bits */
  57 #define OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
  58 #define OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
  59 #define OMAP_TIMER_CTRL_PT              (1 << 12)
  60 #define OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
  61 #define OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
  62 #define OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
  63 #define OMAP_TIMER_CTRL_SCPWM           (1 << 7)
  64 #define OMAP_TIMER_CTRL_CE              (1 << 6)        /* compare enable */
  65 #define OMAP_TIMER_CTRL_PRE             (1 << 5)        /* prescaler enable */
  66 #define OMAP_TIMER_CTRL_PTV_SHIFT       2               /* how much to shift the prescaler value */
  67 #define OMAP_TIMER_CTRL_AR              (1 << 1)        /* auto-reload enable */
  68 #define OMAP_TIMER_CTRL_ST              (1 << 0)        /* start timer */
  69
  70 struct omap_dm_timer {
  71         unsigned long phys_base;
  72         int irq;
  73 #ifdef CONFIG_ARCH_OMAP2
  74         struct clk *iclk, *fclk;
  75 #endif
  76         void __iomem *io_base;
  77         unsigned reserved:1;
  78 };
  79
  80 #ifdef CONFIG_ARCH_OMAP1
  81
  82 static struct omap_dm_timer dm_timers[] = {
  83         { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
  84         { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
  85         { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
  86         { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
  87         { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
  88         { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
  89         { .phys_base = 0xfffb4400, .irq = INT_1610_GPTIMER7 },
  90         { .phys_base = 0xfffb4c00, .irq = INT_1610_GPTIMER8 },
  91 };
  92
  93 #elif defined(CONFIG_ARCH_OMAP2)
  94
  95 static struct omap_dm_timer dm_timers[] = {
  96         { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
  97         { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
  98         { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
  99         { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
 100         { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
 101         { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
 102         { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
 103         { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
 104         { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
 105         { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
 106         { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
 107         { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
 108 };
 109
 110 #else
 111
 112 #error OMAP architecture not supported!
 113
 114 #endif
 115
 116 static const int dm_timer_count = ARRAY_SIZE(dm_timers);
 117
 118 static spinlock_t dm_timer_lock;
 119
 120 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
 121 {
 122         return readl(timer->io_base + reg);
 123 }
 124
 125 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value)
 126 {
 127         writel(value, timer->io_base + reg);
 128         while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG))
 129                 ;
 130 }
 131
 132 static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
 133 {
 134         int c;
 135
 136         c = 0;
 137         while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
 138                 c++;
 139                 if (c > 100000) {
 140                         printk(KERN_ERR "Timer failed to reset\n");
 141                         return;
 142                 }
 143         }
 144 }
 145
 146 static void omap_dm_timer_reset(struct omap_dm_timer *timer)
 147 {
 148         u32 l;
 149
 150         omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
 151         omap_dm_timer_wait_for_reset(timer);
 152
 153         omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_SYS_CLK);
 154
 155         /* Set to smart-idle mode */
 156         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
 157         l |= 0x02 << 3;
 158         omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
 159 }
 160
 161 static void omap_dm_timer_reserve(struct omap_dm_timer *timer)
 162 {
 163         timer->reserved = 1;
 164 #ifdef CONFIG_ARCH_OMAP2
 165         clk_enable(timer->iclk);
 166         clk_enable(timer->fclk);
 167 #endif
 168         omap_dm_timer_reset(timer);
 169 }
 170
 171 struct omap_dm_timer *omap_dm_timer_request(void)
 172 {
 173         struct omap_dm_timer *timer = NULL;
 174         unsigned long flags;
 175         int i;
 176
 177         spin_lock_irqsave(&dm_timer_lock, flags);
 178         for (i = 0; i < dm_timer_count; i++) {
 179                 if (dm_timers[i].reserved)
 180                         continue;
 181
 182                 timer = &dm_timers[i];
 183                 omap_dm_timer_reserve(timer);
 184                 break;
 185         }
 186         spin_unlock_irqrestore(&dm_timer_lock, flags);
 187
 188         return timer;
 189 }
 190
 191 struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 192 {
 193         struct omap_dm_timer *timer;
 194         unsigned long flags;
 195
 196         spin_lock_irqsave(&dm_timer_lock, flags);
 197         if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
 198                 spin_unlock_irqrestore(&dm_timer_lock, flags);
 199                 printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
 200                        __FILE__, __LINE__, __FUNCTION__, id);
 201                 dump_stack();
 202                 return NULL;
 203         }
 204
 205         timer = &dm_timers[id-1];
 206         omap_dm_timer_reserve(timer);
 207         spin_unlock_irqrestore(&dm_timer_lock, flags);
 208
 209         return timer;
 210 }
 211
 212 void omap_dm_timer_free(struct omap_dm_timer *timer)
 213 {
 214         omap_dm_timer_reset(timer);
 215 #ifdef CONFIG_ARCH_OMAP2
 216         clk_disable(timer->iclk);
 217         clk_disable(timer->fclk);
 218 #endif
 219         WARN_ON(!timer->reserved);
 220         timer->reserved = 0;
 221 }
 222
 223 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
 224 {
 225         return timer->irq;
 226 }
 227
 228 #if defined(CONFIG_ARCH_OMAP1)
 229
 230 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 231 {
 232         BUG();
 233 }
 234
 235 /**
 236  * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
 237  * @inputmask: current value of idlect mask
 238  */
 239 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 240 {
 241         int i;
 242
 243         /* If ARMXOR cannot be idled this function call is unnecessary */
 244         if (!(inputmask & (1 << 1)))
 245                 return inputmask;
 246
 247         /* If any active timer is using ARMXOR return modified mask */
 248         for (i = 0; i < dm_timer_count; i++) {
 249                 u32 l;
 250
 251                 l = omap_dm_timer_read_reg(&dm_timers[n], OMAP_TIMER_CTRL_REG);
 252                 if (l & OMAP_TIMER_CTRL_ST) {
 253                         if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
 254                                 inputmask &= ~(1 << 1);
 255                         else
 256                                 inputmask &= ~(1 << 2);
 257                 }
 258         }
 259
 260         return inputmask;
 261 }
 262
 263 #elif defined(CONFIG_ARCH_OMAP2)
 264
 265 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 266 {
 267         return timer->fclk;
 268 }
 269
 270 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 271 {
 272         BUG();
 273 }
 274
 275 #endif
 276
 277 void omap_dm_timer_trigger(struct omap_dm_timer *timer)
 278 {
 279         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 280 }
 281
 282 void omap_dm_timer_start(struct omap_dm_timer *timer)
 283 {
 284         u32 l;
 285
 286         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 287         if (!(l & OMAP_TIMER_CTRL_ST)) {
 288                 l |= OMAP_TIMER_CTRL_ST;
 289                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 290         }
 291 }
 292
 293 void omap_dm_timer_stop(struct omap_dm_timer *timer)
 294 {
 295         u32 l;
 296
 297         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 298         if (l & OMAP_TIMER_CTRL_ST) {
 299                 l &= ~0x1;
 300                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 301         }
 302 }
 303
 304 #ifdef CONFIG_ARCH_OMAP1
 305
 306 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 307 {
 308         int n = (timer - dm_timers) << 1;
 309         u32 l;
 310
 311         l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
 312         l |= source << n;
 313         omap_writel(l, MOD_CONF_CTRL_1);
 314 }
 315
 316 #else
 317
 318 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 319 {
 320         static const char *source_timers[] = {
 321                 "sys_ck",
 322                 "func_32k_ck",
 323                 "alt_ck"
 324         };
 325         struct clk *parent;
 326
 327         if (source < 0 || source >= 3)
 328                 return;
 329
 330         parent = clk_get(NULL, source_timers[source]);
 331         clk_disable(timer->fclk);
 332         clk_set_parent(timer->fclk, parent);
 333         clk_enable(timer->fclk);
 334         clk_put(parent);
 335
 336         /* When the functional clock disappears, too quick writes seem to
 337          * cause an abort. */
 338         udelay(50);
 339 }
 340
 341 #endif
 342
 343 void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
 344                             unsigned int load)
 345 {
 346         u32 l;
 347
 348         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 349         if (autoreload)
 350                 l |= OMAP_TIMER_CTRL_AR;
 351         else
 352                 l &= ~OMAP_TIMER_CTRL_AR;
 353         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 354         omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
 355         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 356 }
 357
 358 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
 359                              unsigned int match)
 360 {
 361         u32 l;
 362
 363         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 364         if (enable)
 365                 l |= OMAP_TIMER_CTRL_CE;
 366         else
 367                 l &= ~OMAP_TIMER_CTRL_CE;
 368         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 369         omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
 370 }
 371
 372
 373 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
 374                            int toggle, int trigger)
 375 {
 376         u32 l;
 377
 378         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 379         l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
 380                OMAP_TIMER_CTRL_PT | (0x03 << 10));
 381         if (def_on)
 382                 l |= OMAP_TIMER_CTRL_SCPWM;
 383         if (toggle)
 384                 l |= OMAP_TIMER_CTRL_PT;
 385         l |= trigger << 10;
 386         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 387 }
 388
 389 void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
 390 {
 391         u32 l;
 392
 393         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 394         l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
 395         if (prescaler >= 0x00 && prescaler <= 0x07) {
 396                 l |= OMAP_TIMER_CTRL_PRE;
 397                 l |= prescaler << 2;
 398         }
 399         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 400 }
 401
 402 void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
 403                                   unsigned int value)
 404 {
 405         omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
 406 }
 407
 408 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
 409 {
 410         return omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
 411 }
 412
 413 void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
 414 {
 415         omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
 416 }
 417
 418 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
 419 {
 420         return omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
 421 }
 422
 423 int omap_dm_timers_active(void)
 424 {
 425         int i;
 426
 427         for (i = 0; i < dm_timer_count; i++) {
 428                 struct omap_dm_timer *timer;
 429
 430                 timer = &dm_timers[i];
 431                 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
 432                     OMAP_TIMER_CTRL_ST)
 433                         return 1;
 434         }
 435         return 0;
 436 }
 437
 438 int omap_dm_timer_init(void)
 439 {
 440         struct omap_dm_timer *timer;
 441         int i;
 442
 443         if (!(cpu_is_omap16xx() || cpu_is_omap24xx()))
 444                 return -ENODEV;
 445
 446         spin_lock_init(&dm_timer_lock);
 447         for (i = 0; i < dm_timer_count; i++) {
 448 #ifdef CONFIG_ARCH_OMAP2
 449                 char clk_name[16];
 450 #endif
 451
 452                 timer = &dm_timers[i];
 453                 timer->io_base = (void __iomem *) io_p2v(timer->phys_base);
 454 #ifdef CONFIG_ARCH_OMAP2
 455                 sprintf(clk_name, "gpt%d_ick", i + 1);
 456                 timer->iclk = clk_get(NULL, clk_name);
 457                 sprintf(clk_name, "gpt%d_fck", i + 1);
 458                 timer->fclk = clk_get(NULL, clk_name);
 459 #endif
 460         }
 461
 462         return 0;
 463 }