2 * linux/arch/i386/kernel/time_hpet.c
3 * This code largely copied from arch/x86_64/kernel/time.c
4 * See that file for credits.
6 * 2003-06-30 Venkatesh Pallipadi - Additional changes for HPET support
9 #include <linux/errno.h>
10 #include <linux/kernel.h>
11 #include <linux/param.h>
12 #include <linux/string.h>
13 #include <linux/init.h>
14 #include <linux/smp.h>
16 #include <asm/timer.h>
17 #include <asm/fixmap.h>
20 #include <linux/timex.h>
21 #include <linux/config.h>
24 #include <linux/hpet.h>
26 static unsigned long hpet_period; /* fsecs / HPET clock */
27 unsigned long hpet_tick; /* hpet clks count per tick */
28 unsigned long hpet_address; /* hpet memory map physical address */
31 static int use_hpet; /* can be used for runtime check of hpet */
32 static int boot_hpet_disable; /* boottime override for HPET timer */
33 static void __iomem * hpet_virt_address; /* hpet kernel virtual address */
35 #define FSEC_TO_USEC (1000000000UL)
37 int hpet_readl(unsigned long a)
39 return readl(hpet_virt_address + a);
42 static void hpet_writel(unsigned long d, unsigned long a)
44 writel(d, hpet_virt_address + a);
47 #ifdef CONFIG_X86_LOCAL_APIC
49 * HPET counters dont wrap around on every tick. They just change the
50 * comparator value and continue. Next tick can be caught by checking
51 * for a change in the comparator value. Used in apic.c.
53 static void __devinit wait_hpet_tick(void)
55 unsigned int start_cmp_val, end_cmp_val;
57 start_cmp_val = hpet_readl(HPET_T0_CMP);
59 end_cmp_val = hpet_readl(HPET_T0_CMP);
60 } while (start_cmp_val == end_cmp_val);
64 static int hpet_timer_stop_set_go(unsigned long tick)
69 * Stop the timers and reset the main counter.
71 cfg = hpet_readl(HPET_CFG);
72 cfg &= ~HPET_CFG_ENABLE;
73 hpet_writel(cfg, HPET_CFG);
74 hpet_writel(0, HPET_COUNTER);
75 hpet_writel(0, HPET_COUNTER + 4);
79 * Set up timer 0, as periodic with first interrupt to happen at
80 * hpet_tick, and period also hpet_tick.
82 cfg = hpet_readl(HPET_T0_CFG);
83 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
84 HPET_TN_SETVAL | HPET_TN_32BIT;
85 hpet_writel(cfg, HPET_T0_CFG);
88 * The first write after writing TN_SETVAL to the config register sets
89 * the counter value, the second write sets the threshold.
91 hpet_writel(tick, HPET_T0_CMP);
92 hpet_writel(tick, HPET_T0_CMP);
97 cfg = hpet_readl(HPET_CFG);
99 cfg |= HPET_CFG_LEGACY;
100 cfg |= HPET_CFG_ENABLE;
101 hpet_writel(cfg, HPET_CFG);
107 * Check whether HPET was found by ACPI boot parse. If yes setup HPET
108 * counter 0 for kernel base timer.
110 int __init hpet_enable(void)
113 unsigned long tick_fsec_low, tick_fsec_high; /* tick in femto sec */
114 unsigned long hpet_tick_rem;
116 if (boot_hpet_disable)
122 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
124 * Read the period, compute tick and quotient.
126 id = hpet_readl(HPET_ID);
129 * We are checking for value '1' or more in number field if
130 * CONFIG_HPET_EMULATE_RTC is set because we will need an
131 * additional timer for RTC emulation.
132 * However, we can do with one timer otherwise using the
133 * the single HPET timer for system time.
135 #ifdef CONFIG_HPET_EMULATE_RTC
136 if (!(id & HPET_ID_NUMBER))
141 hpet_period = hpet_readl(HPET_PERIOD);
142 if ((hpet_period < HPET_MIN_PERIOD) || (hpet_period > HPET_MAX_PERIOD))
147 * First changing tick into fsec
148 * Then 64 bit div to find number of hpet clk per tick
150 ASM_MUL64_REG(tick_fsec_low, tick_fsec_high,
151 KERNEL_TICK_USEC, FSEC_TO_USEC);
152 ASM_DIV64_REG(hpet_tick, hpet_tick_rem,
153 hpet_period, tick_fsec_low, tick_fsec_high);
155 if (hpet_tick_rem > (hpet_period >> 1))
156 hpet_tick++; /* rounding the result */
158 hpet_use_timer = id & HPET_ID_LEGSUP;
160 if (hpet_timer_stop_set_go(hpet_tick))
170 memset(&hd, 0, sizeof (hd));
172 ntimer = hpet_readl(HPET_ID);
173 ntimer = (ntimer & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
177 * Register with driver.
178 * Timer0 and Timer1 is used by platform.
180 hd.hd_phys_address = hpet_address;
181 hd.hd_address = hpet_virt_address;
182 hd.hd_nirqs = ntimer;
183 hd.hd_flags = HPET_DATA_PLATFORM;
184 hpet_reserve_timer(&hd, 0);
185 #ifdef CONFIG_HPET_EMULATE_RTC
186 hpet_reserve_timer(&hd, 1);
188 hd.hd_irq[0] = HPET_LEGACY_8254;
189 hd.hd_irq[1] = HPET_LEGACY_RTC;
191 struct hpet __iomem *hpet;
192 struct hpet_timer __iomem *timer;
195 hpet = hpet_virt_address;
197 for (i = 2, timer = &hpet->hpet_timers[2]; i < ntimer;
199 hd.hd_irq[i] = (timer->hpet_config &
200 Tn_INT_ROUTE_CNF_MASK) >>
201 Tn_INT_ROUTE_CNF_SHIFT;
209 #ifdef CONFIG_X86_LOCAL_APIC
211 wait_timer_tick = wait_hpet_tick;
216 int hpet_reenable(void)
218 return hpet_timer_stop_set_go(hpet_tick);
221 int is_hpet_enabled(void)
226 int is_hpet_capable(void)
228 if (!boot_hpet_disable && hpet_address)
233 static int __init hpet_setup(char* str)
236 if (!strncmp("disable", str, 7))
237 boot_hpet_disable = 1;
242 __setup("hpet=", hpet_setup);
244 #ifdef CONFIG_HPET_EMULATE_RTC
245 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
246 * is enabled, we support RTC interrupt functionality in software.
247 * RTC has 3 kinds of interrupts:
248 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
250 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
251 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
252 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
253 * (1) and (2) above are implemented using polling at a frequency of
254 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
255 * overhead. (DEFAULT_RTC_INT_FREQ)
256 * For (3), we use interrupts at 64Hz or user specified periodic
257 * frequency, whichever is higher.
259 #include <linux/mc146818rtc.h>
260 #include <linux/rtc.h>
262 extern irqreturn_t rtc_interrupt(int irq, void *dev_id, struct pt_regs *regs);
264 #define DEFAULT_RTC_INT_FREQ 64
265 #define RTC_NUM_INTS 1
267 static unsigned long UIE_on;
268 static unsigned long prev_update_sec;
270 static unsigned long AIE_on;
271 static struct rtc_time alarm_time;
273 static unsigned long PIE_on;
274 static unsigned long PIE_freq = DEFAULT_RTC_INT_FREQ;
275 static unsigned long PIE_count;
277 static unsigned long hpet_rtc_int_freq; /* RTC interrupt frequency */
278 static unsigned int hpet_t1_cmp; /* cached comparator register */
281 * Timer 1 for RTC, we do not use periodic interrupt feature,
282 * even if HPET supports periodic interrupts on Timer 1.
283 * The reason being, to set up a periodic interrupt in HPET, we need to
284 * stop the main counter. And if we do that everytime someone diables/enables
285 * RTC, we will have adverse effect on main kernel timer running on Timer 0.
286 * So, for the time being, simulate the periodic interrupt in software.
288 * hpet_rtc_timer_init() is called for the first time and during subsequent
289 * interuppts reinit happens through hpet_rtc_timer_reinit().
291 int hpet_rtc_timer_init(void)
293 unsigned int cfg, cnt;
296 if (!is_hpet_enabled())
299 * Set the counter 1 and enable the interrupts.
301 if (PIE_on && (PIE_freq > DEFAULT_RTC_INT_FREQ))
302 hpet_rtc_int_freq = PIE_freq;
304 hpet_rtc_int_freq = DEFAULT_RTC_INT_FREQ;
306 local_irq_save(flags);
307 cnt = hpet_readl(HPET_COUNTER);
308 cnt += ((hpet_tick*HZ)/hpet_rtc_int_freq);
309 hpet_writel(cnt, HPET_T1_CMP);
311 local_irq_restore(flags);
313 cfg = hpet_readl(HPET_T1_CFG);
314 cfg &= ~HPET_TN_PERIODIC;
315 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
316 hpet_writel(cfg, HPET_T1_CFG);
321 static void hpet_rtc_timer_reinit(void)
323 unsigned int cfg, cnt;
325 if (unlikely(!(PIE_on | AIE_on | UIE_on))) {
326 cfg = hpet_readl(HPET_T1_CFG);
327 cfg &= ~HPET_TN_ENABLE;
328 hpet_writel(cfg, HPET_T1_CFG);
332 if (PIE_on && (PIE_freq > DEFAULT_RTC_INT_FREQ))
333 hpet_rtc_int_freq = PIE_freq;
335 hpet_rtc_int_freq = DEFAULT_RTC_INT_FREQ;
337 /* It is more accurate to use the comparator value than current count.*/
339 cnt += hpet_tick*HZ/hpet_rtc_int_freq;
340 hpet_writel(cnt, HPET_T1_CMP);
345 * The functions below are called from rtc driver.
346 * Return 0 if HPET is not being used.
347 * Otherwise do the necessary changes and return 1.
349 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
351 if (!is_hpet_enabled())
354 if (bit_mask & RTC_UIE)
356 if (bit_mask & RTC_PIE)
358 if (bit_mask & RTC_AIE)
364 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
366 int timer_init_reqd = 0;
368 if (!is_hpet_enabled())
371 if (!(PIE_on | AIE_on | UIE_on))
374 if (bit_mask & RTC_UIE) {
377 if (bit_mask & RTC_PIE) {
381 if (bit_mask & RTC_AIE) {
386 hpet_rtc_timer_init();
391 int hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec)
393 if (!is_hpet_enabled())
396 alarm_time.tm_hour = hrs;
397 alarm_time.tm_min = min;
398 alarm_time.tm_sec = sec;
403 int hpet_set_periodic_freq(unsigned long freq)
405 if (!is_hpet_enabled())
414 int hpet_rtc_dropped_irq(void)
416 if (!is_hpet_enabled())
422 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
424 struct rtc_time curr_time;
425 unsigned long rtc_int_flag = 0;
426 int call_rtc_interrupt = 0;
428 hpet_rtc_timer_reinit();
430 if (UIE_on | AIE_on) {
431 rtc_get_rtc_time(&curr_time);
434 if (curr_time.tm_sec != prev_update_sec) {
435 /* Set update int info, call real rtc int routine */
436 call_rtc_interrupt = 1;
437 rtc_int_flag = RTC_UF;
438 prev_update_sec = curr_time.tm_sec;
443 if (PIE_count >= hpet_rtc_int_freq/PIE_freq) {
444 /* Set periodic int info, call real rtc int routine */
445 call_rtc_interrupt = 1;
446 rtc_int_flag |= RTC_PF;
451 if ((curr_time.tm_sec == alarm_time.tm_sec) &&
452 (curr_time.tm_min == alarm_time.tm_min) &&
453 (curr_time.tm_hour == alarm_time.tm_hour)) {
454 /* Set alarm int info, call real rtc int routine */
455 call_rtc_interrupt = 1;
456 rtc_int_flag |= RTC_AF;
459 if (call_rtc_interrupt) {
460 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
461 rtc_interrupt(rtc_int_flag, dev_id, regs);