2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 /* TODO: Clean up channel debuging -doesn't work anyway- and start
22 * working on reg. control code using all available eeprom information
23 * -rev. engineering needed- */
27 #include <linux/types.h>
28 #include <net/mac80211.h>
30 /* RX/TX descriptor hw structs
31 * TODO: Driver part should only see sw structs */
34 /* EEPROM structs/offsets
35 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
36 * and clean up common bits, then introduce set/get functions in eeprom.c */
40 #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
41 #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
42 #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
43 #define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
44 #define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
45 #define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
46 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
47 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
48 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
49 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
50 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
51 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
52 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
53 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
54 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
55 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
56 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
57 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
58 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
59 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
60 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
61 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
62 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
63 #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
64 #define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
65 #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
66 #define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
67 #define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
69 /****************************\
70 GENERIC DRIVER DEFINITIONS
71 \****************************/
73 #define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__)
75 #define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
76 printk(_level "ath5k %s: " _fmt, \
77 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
80 #define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
81 if (net_ratelimit()) \
82 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
85 #define ATH5K_INFO(_sc, _fmt, ...) \
86 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
88 #define ATH5K_WARN(_sc, _fmt, ...) \
89 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
91 #define ATH5K_ERR(_sc, _fmt, ...) \
92 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
95 * AR5K REGISTER ACCESS
98 /* Some macros to read/write fields */
100 /* First shift, then mask */
101 #define AR5K_REG_SM(_val, _flags) \
102 (((_val) << _flags##_S) & (_flags))
104 /* First mask, then shift */
105 #define AR5K_REG_MS(_val, _flags) \
106 (((_val) & (_flags)) >> _flags##_S)
108 /* Some registers can hold multiple values of interest. For this
109 * reason when we want to write to these registers we must first
110 * retrieve the values which we do not want to clear (lets call this
111 * old_data) and then set the register with this and our new_value:
112 * ( old_data | new_value) */
113 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
114 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
115 (((_val) << _flags##_S) & (_flags)), _reg)
117 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
118 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
119 (_mask)) | (_flags), _reg)
121 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
122 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
124 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
125 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
127 /* Access to PHY registers */
128 #define AR5K_PHY_READ(ah, _reg) \
129 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
131 #define AR5K_PHY_WRITE(ah, _reg, _val) \
132 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
134 /* Access QCU registers per queue */
135 #define AR5K_REG_READ_Q(ah, _reg, _queue) \
136 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
138 #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
139 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
141 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
142 _reg |= 1 << _queue; \
145 #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
146 _reg &= ~(1 << _queue); \
149 /* Used while writing initvals */
150 #define AR5K_REG_WAIT(_i) do { \
155 /* Register dumps are done per operation mode */
156 #define AR5K_INI_RFGAIN_5GHZ 0
157 #define AR5K_INI_RFGAIN_2GHZ 1
159 /* TODO: Clean this up */
160 #define AR5K_INI_VAL_11A 0
161 #define AR5K_INI_VAL_11A_TURBO 1
162 #define AR5K_INI_VAL_11B 2
163 #define AR5K_INI_VAL_11G 3
164 #define AR5K_INI_VAL_11G_TURBO 4
165 #define AR5K_INI_VAL_XR 0
166 #define AR5K_INI_VAL_MAX 5
168 #define AR5K_RF5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
169 #define AR5K_RF5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
171 /* Used for BSSID etc manipulation */
172 #define AR5K_LOW_ID(_a)( \
173 (_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
176 #define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8)
179 * Some tuneable values (these should be changeable by the user)
180 * TODO: Make use of them and add more options OR use debug/configfs
182 #define AR5K_TUNE_DMA_BEACON_RESP 2
183 #define AR5K_TUNE_SW_BEACON_RESP 10
184 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
185 #define AR5K_TUNE_RADAR_ALERT false
186 #define AR5K_TUNE_MIN_TX_FIFO_THRES 1
187 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1)
188 #define AR5K_TUNE_REGISTER_TIMEOUT 20000
189 /* Register for RSSI threshold has a mask of 0xff, so 255 seems to
190 * be the max value. */
191 #define AR5K_TUNE_RSSI_THRES 129
192 /* This must be set when setting the RSSI threshold otherwise it can
193 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
194 * the BMISS_THRES will be seen as 0, seems harware doesn't keep
195 * track of it. Max value depends on harware. For AR5210 this is just 7.
196 * For AR5211+ this seems to be up to 255. */
197 #define AR5K_TUNE_BMISS_THRES 7
198 #define AR5K_TUNE_REGISTER_DWELL_TIME 20000
199 #define AR5K_TUNE_BEACON_INTERVAL 100
200 #define AR5K_TUNE_AIFS 2
201 #define AR5K_TUNE_AIFS_11B 2
202 #define AR5K_TUNE_AIFS_XR 0
203 #define AR5K_TUNE_CWMIN 15
204 #define AR5K_TUNE_CWMIN_11B 31
205 #define AR5K_TUNE_CWMIN_XR 3
206 #define AR5K_TUNE_CWMAX 1023
207 #define AR5K_TUNE_CWMAX_11B 1023
208 #define AR5K_TUNE_CWMAX_XR 7
209 #define AR5K_TUNE_NOISE_FLOOR -72
210 #define AR5K_TUNE_MAX_TXPOWER 60
211 #define AR5K_TUNE_DEFAULT_TXPOWER 30
212 #define AR5K_TUNE_TPC_TXPOWER true
213 #define AR5K_TUNE_ANT_DIVERSITY true
214 #define AR5K_TUNE_HWTXTRIES 4
216 #define AR5K_INIT_CARR_SENSE_EN 1
218 /*Swap RX/TX Descriptor for big endian archs*/
219 #if defined(__BIG_ENDIAN)
220 #define AR5K_INIT_CFG ( \
221 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
224 #define AR5K_INIT_CFG 0x00000000
228 #define AR5K_INIT_TX_LATENCY 502
229 #define AR5K_INIT_USEC 39
230 #define AR5K_INIT_USEC_TURBO 79
231 #define AR5K_INIT_USEC_32 31
232 #define AR5K_INIT_SLOT_TIME 396
233 #define AR5K_INIT_SLOT_TIME_TURBO 480
234 #define AR5K_INIT_ACK_CTS_TIMEOUT 1024
235 #define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
236 #define AR5K_INIT_PROG_IFS 920
237 #define AR5K_INIT_PROG_IFS_TURBO 960
238 #define AR5K_INIT_EIFS 3440
239 #define AR5K_INIT_EIFS_TURBO 6880
240 #define AR5K_INIT_SIFS 560
241 #define AR5K_INIT_SIFS_TURBO 480
242 #define AR5K_INIT_SH_RETRY 10
243 #define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
244 #define AR5K_INIT_SSH_RETRY 32
245 #define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
246 #define AR5K_INIT_TX_RETRY 10
248 #define AR5K_INIT_TRANSMIT_LATENCY ( \
249 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
252 #define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
253 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
254 (AR5K_INIT_USEC_TURBO) \
256 #define AR5K_INIT_PROTO_TIME_CNTRL ( \
257 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
258 (AR5K_INIT_PROG_IFS) \
260 #define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
261 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
262 (AR5K_INIT_PROG_IFS_TURBO) \
265 /* token to use for aifs, cwmin, cwmax in MadWiFi */
266 #define AR5K_TXQ_USEDEFAULT ((u32) -1)
268 /* GENERIC CHIPSET DEFINITIONS */
290 * Common silicon revision/version values
293 enum ath5k_srev_type {
298 struct ath5k_srev_name {
300 enum ath5k_srev_type sr_type;
304 #define AR5K_SREV_UNKNOWN 0xffff
306 #define AR5K_SREV_AR5210 0x00 /* Crete */
307 #define AR5K_SREV_AR5311 0x10 /* Maui 1 */
308 #define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
309 #define AR5K_SREV_AR5311B 0x30 /* Spirit */
310 #define AR5K_SREV_AR5211 0x40 /* Oahu */
311 #define AR5K_SREV_AR5212 0x50 /* Venice */
312 #define AR5K_SREV_AR5213 0x55 /* ??? */
313 #define AR5K_SREV_AR5213A 0x59 /* Hainan */
314 #define AR5K_SREV_AR2413 0x78 /* Griffin lite */
315 #define AR5K_SREV_AR2414 0x70 /* Griffin */
316 #define AR5K_SREV_AR5424 0x90 /* Condor */
317 #define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
318 #define AR5K_SREV_AR5414 0xa0 /* Eagle */
319 #define AR5K_SREV_AR2415 0xb0 /* Cobra */
320 #define AR5K_SREV_AR5416 0xc0 /* PCI-E */
321 #define AR5K_SREV_AR5418 0xca /* PCI-E */
322 #define AR5K_SREV_AR2425 0xe0 /* Swan */
323 #define AR5K_SREV_AR2417 0xf0 /* Nala */
325 #define AR5K_SREV_RAD_5110 0x00
326 #define AR5K_SREV_RAD_5111 0x10
327 #define AR5K_SREV_RAD_5111A 0x15
328 #define AR5K_SREV_RAD_2111 0x20
329 #define AR5K_SREV_RAD_5112 0x30
330 #define AR5K_SREV_RAD_5112A 0x35
331 #define AR5K_SREV_RAD_5112B 0x36
332 #define AR5K_SREV_RAD_2112 0x40
333 #define AR5K_SREV_RAD_2112A 0x45
334 #define AR5K_SREV_RAD_2112B 0x46
335 #define AR5K_SREV_RAD_2413 0x50
336 #define AR5K_SREV_RAD_5413 0x60
337 #define AR5K_SREV_RAD_2316 0x70
338 #define AR5K_SREV_RAD_2317 0x80
339 #define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
340 #define AR5K_SREV_RAD_2425 0xa2
341 #define AR5K_SREV_RAD_5133 0xc0
343 #define AR5K_SREV_PHY_5211 0x30
344 #define AR5K_SREV_PHY_5212 0x41
345 #define AR5K_SREV_PHY_2112B 0x43
346 #define AR5K_SREV_PHY_2413 0x45
347 #define AR5K_SREV_PHY_5413 0x61
348 #define AR5K_SREV_PHY_2425 0x70
351 #define IEEE80211_MAX_LEN 2500
353 /* TODO add support to mac80211 for vendor-specific rates and modes */
356 * Some of this information is based on Documentation from:
358 * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
360 * Modulation for Atheros' eXtended Range - range enhancing extension that is
361 * supposed to double the distance an Atheros client device can keep a
362 * connection with an Atheros access point. This is achieved by increasing
363 * the receiver sensitivity up to, -105dBm, which is about 20dB above what
364 * the 802.11 specifications demand. In addition, new (proprietary) data rates
365 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
367 * Please note that can you either use XR or TURBO but you cannot use both,
368 * they are exclusive.
371 #define MODULATION_XR 0x00000200
373 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
374 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
375 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
376 * channels. To use this feature your Access Point must also suport it.
377 * There is also a distinction between "static" and "dynamic" turbo modes:
379 * - Static: is the dumb version: devices set to this mode stick to it until
380 * the mode is turned off.
381 * - Dynamic: is the intelligent version, the network decides itself if it
382 * is ok to use turbo. As soon as traffic is detected on adjacent channels
383 * (which would get used in turbo mode), or when a non-turbo station joins
384 * the network, turbo mode won't be used until the situation changes again.
385 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
386 * monitors the used radio band in order to decide whether turbo mode may
389 * This article claims Super G sticks to bonding of channels 5 and 6 for
392 * http://www.pcworld.com/article/id,113428-page,1/article.html
394 * The channel bonding seems to be driver specific though. In addition to
395 * deciding what channels will be used, these "Turbo" modes are accomplished
396 * by also enabling the following features:
398 * - Bursting: allows multiple frames to be sent at once, rather than pausing
399 * after each frame. Bursting is a standards-compliant feature that can be
400 * used with any Access Point.
401 * - Fast frames: increases the amount of information that can be sent per
402 * frame, also resulting in a reduction of transmission overhead. It is a
403 * proprietary feature that needs to be supported by the Access Point.
404 * - Compression: data frames are compressed in real time using a Lempel Ziv
405 * algorithm. This is done transparently. Once this feature is enabled,
406 * compression and decompression takes place inside the chipset, without
407 * putting additional load on the host CPU.
410 #define MODULATION_TURBO 0x00000080
412 enum ath5k_driver_mode {
414 AR5K_MODE_11A_TURBO = 1,
417 AR5K_MODE_11G_TURBO = 4,
428 * TX Status descriptor
430 struct ath5k_tx_status {
442 #define AR5K_TXSTAT_ALTRATE 0x80
443 #define AR5K_TXERR_XRETRY 0x01
444 #define AR5K_TXERR_FILT 0x02
445 #define AR5K_TXERR_FIFO 0x04
448 * enum ath5k_tx_queue - Queue types used to classify tx queues.
449 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
450 * @AR5K_TX_QUEUE_DATA: A normal data queue
451 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
452 * @AR5K_TX_QUEUE_BEACON: The beacon queue
453 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
454 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
456 enum ath5k_tx_queue {
457 AR5K_TX_QUEUE_INACTIVE = 0,
459 AR5K_TX_QUEUE_XR_DATA,
460 AR5K_TX_QUEUE_BEACON,
465 #define AR5K_NUM_TX_QUEUES 10
466 #define AR5K_NUM_TX_QUEUES_NOQCU 2
469 * Queue syb-types to classify normal data queues.
470 * These are the 4 Access Categories as defined in
471 * WME spec. 0 is the lowest priority and 4 is the
472 * highest. Normal data that hasn't been classified
473 * goes to the Best Effort AC.
475 enum ath5k_tx_queue_subtype {
476 AR5K_WME_AC_BK = 0, /*Background traffic*/
477 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/
478 AR5K_WME_AC_VI, /*Video traffic*/
479 AR5K_WME_AC_VO, /*Voice traffic*/
483 * Queue ID numbers as returned by the hw functions, each number
484 * represents a hw queue. If hw does not support hw queues
485 * (eg 5210) all data goes in one queue. These match
486 * d80211 definitions (net80211/MadWiFi don't use them).
488 enum ath5k_tx_queue_id {
489 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
490 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
491 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/
492 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/
493 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
494 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
495 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/
496 AR5K_TX_QUEUE_ID_UAPSD = 8,
497 AR5K_TX_QUEUE_ID_XR_DATA = 9,
501 * Flags to set hw queue's parameters...
503 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
504 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
505 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
506 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
507 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
508 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0020 /* Disable random post-backoff */
509 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0040 /* Enable ready time expiry policy (?)*/
510 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0080 /* Enable backoff while bursting */
511 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x0100 /* Disable backoff while bursting */
512 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x0200 /* Enable hw compression -not implemented-*/
515 * A struct to hold tx queue's parameters
517 struct ath5k_txq_info {
518 enum ath5k_tx_queue tqi_type;
519 enum ath5k_tx_queue_subtype tqi_subtype;
520 u16 tqi_flags; /* Tx queue flags (see above) */
521 u32 tqi_aifs; /* Arbitrated Interframe Space */
522 s32 tqi_cw_min; /* Minimum Contention Window */
523 s32 tqi_cw_max; /* Maximum Contention Window */
524 u32 tqi_cbr_period; /* Constant bit rate period */
525 u32 tqi_cbr_overflow_limit;
527 u32 tqi_ready_time; /* Not used */
531 * Transmit packet types.
532 * used on tx control descriptor
533 * TODO: Use them inside base.c corectly
535 enum ath5k_pkt_type {
536 AR5K_PKT_TYPE_NORMAL = 0,
537 AR5K_PKT_TYPE_ATIM = 1,
538 AR5K_PKT_TYPE_PSPOLL = 2,
539 AR5K_PKT_TYPE_BEACON = 3,
540 AR5K_PKT_TYPE_PROBE_RESP = 4,
541 AR5K_PKT_TYPE_PIFS = 5,
545 * TX power and TPC settings
547 #define AR5K_TXPOWER_OFDM(_r, _v) ( \
548 ((0 & 1) << ((_v) + 6)) | \
549 (((ah->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \
552 #define AR5K_TXPOWER_CCK(_r, _v) ( \
553 (ah->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \
557 * DMA size definitions (2^n+2)
576 * RX Status descriptor
578 struct ath5k_rx_status {
590 #define AR5K_RXERR_CRC 0x01
591 #define AR5K_RXERR_PHY 0x02
592 #define AR5K_RXERR_FIFO 0x04
593 #define AR5K_RXERR_DECRYPT 0x08
594 #define AR5K_RXERR_MIC 0x10
595 #define AR5K_RXKEYIX_INVALID ((u8) - 1)
596 #define AR5K_TXKEYIX_INVALID ((u32) - 1)
599 /**************************\
600 BEACON TIMERS DEFINITIONS
601 \**************************/
603 #define AR5K_BEACON_PERIOD 0x0000ffff
604 #define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
605 #define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
609 * struct ath5k_beacon_state - Per-station beacon timer state.
610 * @bs_interval: in TU's, can also include the above flags
611 * @bs_cfp_max_duration: if non-zero hw is setup to coexist with a
612 * Point Coordination Function capable AP
614 struct ath5k_beacon_state {
620 u16 bs_cfp_max_duration;
621 u16 bs_cfp_du_remain;
623 u16 bs_sleep_duration;
624 u16 bs_bmiss_threshold;
631 * TSF to TU conversion:
633 * TSF is a 64bit value in usec (microseconds).
634 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
635 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
637 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
640 /*******************************\
641 GAIN OPTIMIZATION DEFINITIONS
642 \*******************************/
645 AR5K_RFGAIN_INACTIVE = 0,
646 AR5K_RFGAIN_READ_REQUESTED,
647 AR5K_RFGAIN_NEED_CHANGE,
650 #define AR5K_GAIN_CRN_FIX_BITS_5111 4
651 #define AR5K_GAIN_CRN_FIX_BITS_5112 7
652 #define AR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112
653 #define AR5K_GAIN_DYN_ADJUST_HI_MARGIN 15
654 #define AR5K_GAIN_DYN_ADJUST_LO_MARGIN 20
655 #define AR5K_GAIN_CCK_PROBE_CORR 5
656 #define AR5K_GAIN_CCK_OFDM_GAIN_DELTA 15
657 #define AR5K_GAIN_STEP_COUNT 10
658 #define AR5K_GAIN_PARAM_TX_CLIP 0
659 #define AR5K_GAIN_PARAM_PD_90 1
660 #define AR5K_GAIN_PARAM_PD_84 2
661 #define AR5K_GAIN_PARAM_GAIN_SEL 3
662 #define AR5K_GAIN_PARAM_MIX_ORN 0
663 #define AR5K_GAIN_PARAM_PD_138 1
664 #define AR5K_GAIN_PARAM_PD_137 2
665 #define AR5K_GAIN_PARAM_PD_136 3
666 #define AR5K_GAIN_PARAM_PD_132 4
667 #define AR5K_GAIN_PARAM_PD_131 5
668 #define AR5K_GAIN_PARAM_PD_130 6
669 #define AR5K_GAIN_CHECK_ADJUST(_g) \
670 ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high)
672 struct ath5k_gain_opt_step {
673 s16 gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS];
685 const struct ath5k_gain_opt_step *g_step;
689 /********************\
691 \********************/
693 #define AR5K_SLOT_TIME_9 396
694 #define AR5K_SLOT_TIME_20 880
695 #define AR5K_SLOT_TIME_MAX 0xffff
698 #define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */
699 #define CHANNEL_TURBO 0x0010 /* Turbo Channel */
700 #define CHANNEL_CCK 0x0020 /* CCK channel */
701 #define CHANNEL_OFDM 0x0040 /* OFDM channel */
702 #define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */
703 #define CHANNEL_5GHZ 0x0100 /* 5GHz channel */
704 #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */
705 #define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
706 #define CHANNEL_XR 0x0800 /* XR channel */
708 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
709 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
710 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
711 #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
712 #define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
713 #define CHANNEL_108A CHANNEL_T
714 #define CHANNEL_108G CHANNEL_TG
715 #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
717 #define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
720 #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO)
721 #define CHANNEL_MODES CHANNEL_ALL
724 * Used internaly for reset_tx_queue).
725 * Also see struct struct ieee80211_channel.
727 #define IS_CHAN_XR(_c) ((_c.hw_value & CHANNEL_XR) != 0)
728 #define IS_CHAN_B(_c) ((_c.hw_value & CHANNEL_B) != 0)
731 * The following structure is used to map 2GHz channels to
732 * 5GHz Atheros channels.
735 struct ath5k_athchan_2ghz {
746 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
748 * The rate code is used to get the RX rate or set the TX rate on the
749 * hardware descriptors. It is also used for internal modulation control
752 * This is the hardware rate map we are aware of:
754 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
755 * rate_kbps 3000 1000 ? ? ? 2000 500 48000
757 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
758 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
760 * rate_code 17 18 19 20 21 22 23 24
761 * rate_kbps ? ? ? ? ? ? ? 11000
763 * rate_code 25 26 27 28 29 30 31 32
764 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
766 * "S" indicates CCK rates with short preamble.
768 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
769 * lowest 4 bits, so they are the same as below with a 0xF mask.
770 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
771 * We handle this in ath5k_setup_bands().
773 #define AR5K_MAX_RATES 32
776 #define ATH5K_RATE_CODE_1M 0x1B
777 #define ATH5K_RATE_CODE_2M 0x1A
778 #define ATH5K_RATE_CODE_5_5M 0x19
779 #define ATH5K_RATE_CODE_11M 0x18
781 #define ATH5K_RATE_CODE_6M 0x0B
782 #define ATH5K_RATE_CODE_9M 0x0F
783 #define ATH5K_RATE_CODE_12M 0x0A
784 #define ATH5K_RATE_CODE_18M 0x0E
785 #define ATH5K_RATE_CODE_24M 0x09
786 #define ATH5K_RATE_CODE_36M 0x0D
787 #define ATH5K_RATE_CODE_48M 0x08
788 #define ATH5K_RATE_CODE_54M 0x0C
790 #define ATH5K_RATE_CODE_XR_500K 0x07
791 #define ATH5K_RATE_CODE_XR_1M 0x02
792 #define ATH5K_RATE_CODE_XR_2M 0x06
793 #define ATH5K_RATE_CODE_XR_3M 0x01
795 /* adding this flag to rate_code enables short preamble */
796 #define AR5K_SET_SHORT_PREAMBLE 0x04
802 #define AR5K_KEYCACHE_SIZE 8
804 /***********************\
805 HW RELATED DEFINITIONS
806 \***********************/
811 #define AR5K_RSSI_EP_MULTIPLIER (1<<7)
813 #define AR5K_ASSERT_ENTRY(_e, _s) do { \
818 enum ath5k_ant_setting {
819 AR5K_ANT_VARIABLE = 0, /* variable by programming */
820 AR5K_ANT_FIXED_A = 1, /* fixed to 11a frequencies */
821 AR5K_ANT_FIXED_B = 2, /* fixed to 11b frequencies */
826 * Hardware interrupt abstraction
830 * enum ath5k_int - Hardware interrupt masks helpers
832 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
833 * AR5K_ISR_RXOK or AR5K_ISR_RXERR
834 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
835 * @AR5K_INT_RXNOFRM: No frame received (?)
836 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
837 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
838 * LinkPtr is NULL. For more details, refer to:
839 * http://www.freepatentsonline.com/20030225739.html
840 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
841 * Note that Rx overrun is not always fatal, on some chips we can continue
842 * operation without reseting the card, that's why int_fatal is not
843 * common for all chips.
844 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
845 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
846 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
847 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
848 * We currently do increments on interrupt by
849 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
850 * @AR5K_INT_MIB: Indicates the Management Information Base counters should be
851 * checked. We should do this with ath5k_hw_update_mib_counters() but
852 * it seems we should also then do some noise immunity work.
853 * @AR5K_INT_RXPHY: RX PHY Error
854 * @AR5K_INT_RXKCM: ??
855 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
856 * beacon that must be handled in software. The alternative is if you
857 * have VEOL support, in that case you let the hardware deal with things.
858 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
859 * beacons from the AP have associated with, we should probably try to
860 * reassociate. When in IBSS mode this might mean we have not received
861 * any beacons from any local stations. Note that every station in an
862 * IBSS schedules to send beacons at the Target Beacon Transmission Time
863 * (TBTT) with a random backoff.
864 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
865 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
866 * until properly handled
867 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
868 * errors. These types of errors we can enable seem to be of type
869 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
870 * @AR5K_INT_GLOBAL: Seems to be used to clear and set the IER
871 * @AR5K_INT_NOCARD: signals the card has been removed
872 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
875 * These are mapped to take advantage of some common bits
876 * between the MACs, to be able to set intr properties
877 * easier. Some of them are not used yet inside hw.c. Most map
878 * to the respective hw interrupt value as they are common amogst different
882 AR5K_INT_RX = 0x00000001, /* Not common */
883 AR5K_INT_RXDESC = 0x00000002,
884 AR5K_INT_RXNOFRM = 0x00000008,
885 AR5K_INT_RXEOL = 0x00000010,
886 AR5K_INT_RXORN = 0x00000020,
887 AR5K_INT_TX = 0x00000040, /* Not common */
888 AR5K_INT_TXDESC = 0x00000080,
889 AR5K_INT_TXURN = 0x00000800,
890 AR5K_INT_MIB = 0x00001000,
891 AR5K_INT_RXPHY = 0x00004000,
892 AR5K_INT_RXKCM = 0x00008000,
893 AR5K_INT_SWBA = 0x00010000,
894 AR5K_INT_BMISS = 0x00040000,
895 AR5K_INT_BNR = 0x00100000, /* Not common */
896 AR5K_INT_GPIO = 0x01000000,
897 AR5K_INT_FATAL = 0x40000000, /* Not common */
898 AR5K_INT_GLOBAL = 0x80000000,
900 AR5K_INT_COMMON = AR5K_INT_RXNOFRM
912 AR5K_INT_NOCARD = 0xffffffff
918 enum ath5k_power_mode {
919 AR5K_PM_UNDEFINED = 0,
923 AR5K_PM_NETWORK_SLEEP,
927 * These match net80211 definitions (not used in
929 * TODO: Clean this up
931 #define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
932 #define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
933 #define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
934 #define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
935 #define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
937 /* GPIO-controlled software LED */
938 #define AR5K_SOFTLED_PIN 0
939 #define AR5K_SOFTLED_ON 0
940 #define AR5K_SOFTLED_OFF 1
943 * Chipset capabilities -see ath5k_hw_get_capability-
944 * get_capability function is not yet fully implemented
945 * in ath5k so most of these don't work yet...
946 * TODO: Implement these & merge with _TUNE_ stuff above
948 enum ath5k_capability_type {
949 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */
950 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */
951 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */
952 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */
953 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */
954 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */
955 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */
956 AR5K_CAP_COMPRESSION = 8, /* Supports compression */
957 AR5K_CAP_BURST = 9, /* Supports packet bursting */
958 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */
959 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */
960 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */
961 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */
962 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */
963 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */
964 AR5K_CAP_XR = 16, /* Supports XR mode */
965 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */
966 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */
967 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */
968 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */
972 /* XXX: we *may* move cap_range stuff to struct wiphy */
973 struct ath5k_capabilities {
975 * Supported PHY modes
976 * (ie. CHANNEL_A, CHANNEL_B, ...)
978 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
981 * Frequency range (without regulation restrictions)
991 * Values stored in the EEPROM (some of them...)
993 struct ath5k_eeprom_info cap_eeprom;
1004 /***************************************\
1005 HARDWARE ABSTRACTION LAYER STRUCTURE
1006 \***************************************/
1012 #define AR5K_MAX_GPIO 10
1013 #define AR5K_MAX_RF_BANKS 8
1015 /* TODO: Clean up and merge with ath5k_softc */
1019 struct ath5k_softc *ah_sc;
1020 void __iomem *ah_iobase;
1022 enum ath5k_int ah_imr;
1024 enum nl80211_iftype ah_op_mode;
1025 enum ath5k_power_mode ah_power_mode;
1026 struct ieee80211_channel ah_current_channel;
1028 bool ah_calibration;
1030 bool ah_single_chip;
1031 enum ath5k_rfgain ah_rf_gain;
1035 u16 ah_mac_revision;
1036 u16 ah_phy_revision;
1037 u16 ah_radio_5ghz_revision;
1038 u16 ah_radio_2ghz_revision;
1039 u32 ah_phy_spending;
1041 enum ath5k_version ah_version;
1042 enum ath5k_radio ah_radio;
1048 #define ah_regdomain ah_capabilities.cap_regdomain.reg_current
1049 #define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw
1050 #define ah_modes ah_capabilities.cap_mode
1051 #define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1057 bool ah_software_retry;
1058 u32 ah_limit_tx_retries;
1060 u32 ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1061 bool ah_ant_diversity;
1063 u8 ah_sta_id[ETH_ALEN];
1065 /* Current BSSID we are trying to assoc to / creating.
1066 * This is passed by mac80211 on config_interface() and cached here for
1068 u8 ah_bssid[ETH_ALEN];
1070 u32 ah_gpio[AR5K_MAX_GPIO];
1073 struct ath5k_capabilities ah_capabilities;
1075 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
1077 u32 ah_txq_imr_txok;
1078 u32 ah_txq_imr_txerr;
1079 u32 ah_txq_imr_txurn;
1080 u32 ah_txq_imr_txdesc;
1081 u32 ah_txq_imr_txeol;
1083 size_t ah_rf_banks_size;
1084 struct ath5k_gain ah_gain;
1085 u32 ah_offset[AR5K_MAX_RF_BANKS];
1088 u16 txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE];
1089 u16 txp_rates[AR5K_MAX_RATES];
1099 struct ieee80211_channel r_last_channel;
1102 /* noise floor from last periodic calibration */
1108 int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc,
1109 u32 size, unsigned int flags);
1110 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1111 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
1112 unsigned int, unsigned int, unsigned int, unsigned int,
1113 unsigned int, unsigned int, unsigned int);
1114 int (*ah_setup_mrr_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1115 unsigned int, unsigned int, unsigned int, unsigned int,
1116 unsigned int, unsigned int);
1117 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1118 struct ath5k_tx_status *);
1119 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1120 struct ath5k_rx_status *);
1127 /* Attach/Detach Functions */
1128 extern struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version);
1129 extern void ath5k_hw_detach(struct ath5k_hw *ah);
1131 /* Reset Functions */
1132 extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
1133 extern int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, struct ieee80211_channel *channel, bool change_channel);
1134 /* Power management functions */
1135 extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration);
1137 /* DMA Related Functions */
1138 extern void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
1139 extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
1140 extern u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1141 extern void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1142 extern int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1143 extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1144 extern u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1145 extern int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1147 extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1148 /* Interrupt handling */
1149 extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1150 extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1151 extern enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum
1152 ath5k_int new_mask);
1153 extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_low_level_stats *stats);
1155 /* EEPROM access functions */
1156 extern int ath5k_eeprom_init(struct ath5k_hw *ah);
1157 extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
1159 /* Protocol Control Unit Functions */
1160 extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
1161 /* BSSID Functions */
1162 extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac);
1163 extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1164 extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id);
1165 extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1166 /* Receive start/stop functions */
1167 extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1168 extern void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
1169 /* RX Filter functions */
1170 extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1171 extern int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
1172 extern int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
1173 extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1174 extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1175 /* Beacon control functions */
1176 extern u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah);
1177 extern u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1178 extern void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1179 extern void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
1181 extern int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, const struct ath5k_beacon_state *state);
1182 extern void ath5k_hw_reset_beacon(struct ath5k_hw *ah);
1183 extern int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr);
1186 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
1187 /* ACK/CTS Timeouts */
1188 extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout);
1189 extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah);
1190 extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout);
1191 extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah);
1192 /* Key table (WEP) functions */
1193 extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
1194 extern int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry);
1195 extern int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac);
1196 extern int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac);
1198 /* Queue Control Unit, DFS Control Unit Functions */
1199 extern int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, struct ath5k_txq_info *queue_info);
1200 extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1201 const struct ath5k_txq_info *queue_info);
1202 extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1203 enum ath5k_tx_queue queue_type,
1204 struct ath5k_txq_info *queue_info);
1205 extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1206 extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1207 extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1208 extern unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah);
1209 extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
1211 /* Hardware Descriptor Functions */
1212 extern int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1214 /* GPIO Functions */
1215 extern void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1216 extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1217 extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1218 extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1219 extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1220 extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level);
1222 /* Misc functions */
1223 int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
1224 extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
1225 extern int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1226 extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
1228 /* Initial register settings functions */
1229 extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
1232 extern int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int mode);
1233 extern int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq);
1234 extern enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath5k_hw *ah);
1235 extern int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah);
1236 /* PHY/RF channel functions */
1237 extern bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
1238 extern int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1239 /* PHY calibration */
1240 extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1241 extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq);
1242 /* Misc PHY functions */
1243 extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1244 extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant);
1245 extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
1246 extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1247 /* TX power setup */
1248 extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int txpower);
1249 extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power);
1252 * Functions used internaly
1256 * Translate usec to hw clock units
1258 static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
1260 return turbo ? (usec * 80) : (usec * 40);
1264 * Translate hw clock units to usec
1266 static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
1268 return turbo ? (clock / 80) : (clock / 40);
1272 * Read from a register
1274 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1276 return ioread32(ah->ah_iobase + reg);
1280 * Write to a register
1282 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1284 iowrite32(val, ah->ah_iobase + reg);
1287 #if defined(_ATH5K_RESET) || defined(_ATH5K_PHY)
1289 * Check if a register write has been completed
1291 static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag,
1292 u32 val, bool is_set)
1297 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
1298 data = ath5k_hw_reg_read(ah, reg);
1299 if (is_set && (data & flag))
1301 else if ((data & flag) == val)
1306 return (i <= 0) ? -EAGAIN : 0;
1310 static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1312 u32 retval = 0, bit, i;
1314 for (i = 0; i < bits; i++) {
1315 bit = (val >> i) & 1;
1316 retval = (retval << 1) | bit;