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   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/ipv6.h>
  38 #include <net/checksum.h>
  39 #include <net/ip6_checksum.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42
  43 #include "ixgbe.h"
  44 #include "ixgbe_common.h"
  45
  46 char ixgbe_driver_name[] = "ixgbe";
  47 static const char ixgbe_driver_string[] =
  48                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  49
  50 #define DRV_VERSION "1.3.30-k2"
  51 const char ixgbe_driver_version[] = DRV_VERSION;
  52 static char ixgbe_copyright[] = "Copyright (c) 1999-2007 Intel Corporation.";
  53
  54 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  55         [board_82598] = &ixgbe_82598_info,
  56 };
  57
  58 /* ixgbe_pci_tbl - PCI Device ID Table
  59  *
  60  * Wildcard entries (PCI_ANY_ID) should come last
  61  * Last entry must be all 0s
  62  *
  63  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  64  *   Class, Class Mask, private data (not used) }
  65  */
  66 static struct pci_device_id ixgbe_pci_tbl[] = {
  67         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  68          board_82598 },
  69         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  70          board_82598 },
  71         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  72          board_82598 },
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  84          board_82598 },
  85
  86         /* required last entry */
  87         {0, }
  88 };
  89 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
  90
  91 #ifdef CONFIG_IXGBE_DCA
  92 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
  93                             void *p);
  94 static struct notifier_block dca_notifier = {
  95         .notifier_call = ixgbe_notify_dca,
  96         .next          = NULL,
  97         .priority      = 0
  98 };
  99 #endif
 100
 101 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 102 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 103 MODULE_LICENSE("GPL");
 104 MODULE_VERSION(DRV_VERSION);
 105
 106 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 107
 108 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 109 {
 110         u32 ctrl_ext;
 111
 112         /* Let firmware take over control of h/w */
 113         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 114         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 115                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 116 }
 117
 118 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 119 {
 120         u32 ctrl_ext;
 121
 122         /* Let firmware know the driver has taken over */
 123         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 124         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 125                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 126 }
 127
 128 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
 129                            u8 msix_vector)
 130 {
 131         u32 ivar, index;
 132
 133         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 134         index = (int_alloc_entry >> 2) & 0x1F;
 135         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
 136         ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
 137         ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
 138         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
 139 }
 140
 141 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 142                                              struct ixgbe_tx_buffer
 143                                              *tx_buffer_info)
 144 {
 145         if (tx_buffer_info->dma) {
 146                 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
 147                                tx_buffer_info->length, PCI_DMA_TODEVICE);
 148                 tx_buffer_info->dma = 0;
 149         }
 150         if (tx_buffer_info->skb) {
 151                 dev_kfree_skb_any(tx_buffer_info->skb);
 152                 tx_buffer_info->skb = NULL;
 153         }
 154         /* tx_buffer_info must be completely set up in the transmit path */
 155 }
 156
 157 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 158                                        struct ixgbe_ring *tx_ring,
 159                                        unsigned int eop)
 160 {
 161         struct ixgbe_hw *hw = &adapter->hw;
 162         u32 head, tail;
 163
 164         /* Detect a transmit hang in hardware, this serializes the
 165          * check with the clearing of time_stamp and movement of eop */
 166         head = IXGBE_READ_REG(hw, tx_ring->head);
 167         tail = IXGBE_READ_REG(hw, tx_ring->tail);
 168         adapter->detect_tx_hung = false;
 169         if ((head != tail) &&
 170             tx_ring->tx_buffer_info[eop].time_stamp &&
 171             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 172             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 173                 /* detected Tx unit hang */
 174                 union ixgbe_adv_tx_desc *tx_desc;
 175                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 176                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 177                         "  Tx Queue             <%d>\n"
 178                         "  TDH, TDT             <%x>, <%x>\n"
 179                         "  next_to_use          <%x>\n"
 180                         "  next_to_clean        <%x>\n"
 181                         "tx_buffer_info[next_to_clean]\n"
 182                         "  time_stamp           <%lx>\n"
 183                         "  jiffies              <%lx>\n",
 184                         tx_ring->queue_index,
 185                         head, tail,
 186                         tx_ring->next_to_use, eop,
 187                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 188                 return true;
 189         }
 190
 191         return false;
 192 }
 193
 194 #define IXGBE_MAX_TXD_PWR       14
 195 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 196
 197 /* Tx Descriptors needed, worst case */
 198 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 199                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 200 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 201         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 202
 203 #define GET_TX_HEAD_FROM_RING(ring) (\
 204         *(volatile u32 *) \
 205         ((union ixgbe_adv_tx_desc *)(ring)->desc + (ring)->count))
 206 static void ixgbe_tx_timeout(struct net_device *netdev);
 207
 208 /**
 209  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 210  * @adapter: board private structure
 211  * @tx_ring: tx ring to clean
 212  **/
 213 static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
 214                                struct ixgbe_ring *tx_ring)
 215 {
 216         union ixgbe_adv_tx_desc *tx_desc;
 217         struct ixgbe_tx_buffer *tx_buffer_info;
 218         struct net_device *netdev = adapter->netdev;
 219         struct sk_buff *skb;
 220         unsigned int i;
 221         u32 head, oldhead;
 222         unsigned int count = 0;
 223         unsigned int total_bytes = 0, total_packets = 0;
 224
 225         rmb();
 226         head = GET_TX_HEAD_FROM_RING(tx_ring);
 227         head = le32_to_cpu(head);
 228         i = tx_ring->next_to_clean;
 229         while (1) {
 230                 while (i != head) {
 231                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 232                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 233                         skb = tx_buffer_info->skb;
 234
 235                         if (skb) {
 236                                 unsigned int segs, bytecount;
 237
 238                                 /* gso_segs is currently only valid for tcp */
 239                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 240                                 /* multiply data chunks by size of headers */
 241                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
 242                                             skb->len;
 243                                 total_packets += segs;
 244                                 total_bytes += bytecount;
 245                         }
 246
 247                         ixgbe_unmap_and_free_tx_resource(adapter,
 248                                                          tx_buffer_info);
 249
 250                         i++;
 251                         if (i == tx_ring->count)
 252                                 i = 0;
 253
 254                         count++;
 255                         if (count == tx_ring->count)
 256                                 goto done_cleaning;
 257                 }
 258                 oldhead = head;
 259                 rmb();
 260                 head = GET_TX_HEAD_FROM_RING(tx_ring);
 261                 head = le32_to_cpu(head);
 262                 if (head == oldhead)
 263                         goto done_cleaning;
 264         } /* while (1) */
 265
 266 done_cleaning:
 267         tx_ring->next_to_clean = i;
 268
 269 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 270         if (unlikely(count && netif_carrier_ok(netdev) &&
 271                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 272                 /* Make sure that anybody stopping the queue after this
 273                  * sees the new next_to_clean.
 274                  */
 275                 smp_mb();
 276                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 277                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 278                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 279                         ++adapter->restart_queue;
 280                 }
 281         }
 282
 283         if (adapter->detect_tx_hung) {
 284                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 285                         /* schedule immediate reset if we believe we hung */
 286                         DPRINTK(PROBE, INFO,
 287                                 "tx hang %d detected, resetting adapter\n",
 288                                 adapter->tx_timeout_count + 1);
 289                         ixgbe_tx_timeout(adapter->netdev);
 290                 }
 291         }
 292
 293         /* re-arm the interrupt */
 294         if ((total_packets >= tx_ring->work_limit) ||
 295             (count == tx_ring->count))
 296                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
 297
 298         tx_ring->total_bytes += total_bytes;
 299         tx_ring->total_packets += total_packets;
 300         tx_ring->stats.bytes += total_bytes;
 301         tx_ring->stats.packets += total_packets;
 302         adapter->net_stats.tx_bytes += total_bytes;
 303         adapter->net_stats.tx_packets += total_packets;
 304         return (total_packets ? true : false);
 305 }
 306
 307 #ifdef CONFIG_IXGBE_DCA
 308 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 309                                 struct ixgbe_ring *rx_ring)
 310 {
 311         u32 rxctrl;
 312         int cpu = get_cpu();
 313         int q = rx_ring - adapter->rx_ring;
 314
 315         if (rx_ring->cpu != cpu) {
 316                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 317                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 318                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 319                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 320                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 321                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 322                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 323                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 324                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 325                 rx_ring->cpu = cpu;
 326         }
 327         put_cpu();
 328 }
 329
 330 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 331                                 struct ixgbe_ring *tx_ring)
 332 {
 333         u32 txctrl;
 334         int cpu = get_cpu();
 335         int q = tx_ring - adapter->tx_ring;
 336
 337         if (tx_ring->cpu != cpu) {
 338                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 339                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 340                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 341                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 342                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 343                 tx_ring->cpu = cpu;
 344         }
 345         put_cpu();
 346 }
 347
 348 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 349 {
 350         int i;
 351
 352         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 353                 return;
 354
 355         for (i = 0; i < adapter->num_tx_queues; i++) {
 356                 adapter->tx_ring[i].cpu = -1;
 357                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 358         }
 359         for (i = 0; i < adapter->num_rx_queues; i++) {
 360                 adapter->rx_ring[i].cpu = -1;
 361                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 362         }
 363 }
 364
 365 static int __ixgbe_notify_dca(struct device *dev, void *data)
 366 {
 367         struct net_device *netdev = dev_get_drvdata(dev);
 368         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 369         unsigned long event = *(unsigned long *)data;
 370
 371         switch (event) {
 372         case DCA_PROVIDER_ADD:
 373                 /* if we're already enabled, don't do it again */
 374                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 375                         break;
 376                 /* Always use CB2 mode, difference is masked
 377                  * in the CB driver. */
 378                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 379                 if (dca_add_requester(dev) == 0) {
 380                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 381                         ixgbe_setup_dca(adapter);
 382                         break;
 383                 }
 384                 /* Fall Through since DCA is disabled. */
 385         case DCA_PROVIDER_REMOVE:
 386                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 387                         dca_remove_requester(dev);
 388                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 389                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 390                 }
 391                 break;
 392         }
 393
 394         return 0;
 395 }
 396
 397 #endif /* CONFIG_IXGBE_DCA */
 398 /**
 399  * ixgbe_receive_skb - Send a completed packet up the stack
 400  * @adapter: board private structure
 401  * @skb: packet to send up
 402  * @status: hardware indication of status of receive
 403  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 404  * @rx_desc: rx descriptor
 405  **/
 406 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 407                               struct sk_buff *skb, u8 status,
 408                               union ixgbe_adv_rx_desc *rx_desc)
 409 {
 410         struct ixgbe_adapter *adapter = q_vector->adapter;
 411         struct napi_struct *napi = &q_vector->napi;
 412         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 413         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 414
 415         if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
 416                 if (adapter->vlgrp && is_vlan && (tag != 0))
 417                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 418                 else
 419                         napi_gro_receive(napi, skb);
 420         } else {
 421                 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 422                         if (adapter->vlgrp && is_vlan && (tag != 0))
 423                                 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
 424                         else
 425                                 netif_receive_skb(skb);
 426                 } else {
 427                         if (adapter->vlgrp && is_vlan && (tag != 0))
 428                                 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 429                         else
 430                                 netif_rx(skb);
 431                 }
 432         }
 433 }
 434
 435 /**
 436  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 437  * @adapter: address of board private structure
 438  * @status_err: hardware indication of status of receive
 439  * @skb: skb currently being received and modified
 440  **/
 441 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 442                                      u32 status_err, struct sk_buff *skb)
 443 {
 444         skb->ip_summed = CHECKSUM_NONE;
 445
 446         /* Rx csum disabled */
 447         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 448                 return;
 449
 450         /* if IP and error */
 451         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 452             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 453                 adapter->hw_csum_rx_error++;
 454                 return;
 455         }
 456
 457         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 458                 return;
 459
 460         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 461                 adapter->hw_csum_rx_error++;
 462                 return;
 463         }
 464
 465         /* It must be a TCP or UDP packet with a valid checksum */
 466         skb->ip_summed = CHECKSUM_UNNECESSARY;
 467         adapter->hw_csum_rx_good++;
 468 }
 469
 470 /**
 471  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 472  * @adapter: address of board private structure
 473  **/
 474 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 475                                    struct ixgbe_ring *rx_ring,
 476                                    int cleaned_count)
 477 {
 478         struct pci_dev *pdev = adapter->pdev;
 479         union ixgbe_adv_rx_desc *rx_desc;
 480         struct ixgbe_rx_buffer *bi;
 481         unsigned int i;
 482
 483         i = rx_ring->next_to_use;
 484         bi = &rx_ring->rx_buffer_info[i];
 485
 486         while (cleaned_count--) {
 487                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 488
 489                 if (!bi->page_dma &&
 490                     (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
 491                         if (!bi->page) {
 492                                 bi->page = alloc_page(GFP_ATOMIC);
 493                                 if (!bi->page) {
 494                                         adapter->alloc_rx_page_failed++;
 495                                         goto no_buffers;
 496                                 }
 497                                 bi->page_offset = 0;
 498                         } else {
 499                                 /* use a half page if we're re-using */
 500                                 bi->page_offset ^= (PAGE_SIZE / 2);
 501                         }
 502
 503                         bi->page_dma = pci_map_page(pdev, bi->page,
 504                                                     bi->page_offset,
 505                                                     (PAGE_SIZE / 2),
 506                                                     PCI_DMA_FROMDEVICE);
 507                 }
 508
 509                 if (!bi->skb) {
 510                         struct sk_buff *skb;
 511                         skb = netdev_alloc_skb(adapter->netdev,
 512                                                (rx_ring->rx_buf_len +
 513                                                 NET_IP_ALIGN));
 514
 515                         if (!skb) {
 516                                 adapter->alloc_rx_buff_failed++;
 517                                 goto no_buffers;
 518                         }
 519
 520                         /*
 521                          * Make buffer alignment 2 beyond a 16 byte boundary
 522                          * this will result in a 16 byte aligned IP header after
 523                          * the 14 byte MAC header is removed
 524                          */
 525                         skb_reserve(skb, NET_IP_ALIGN);
 526
 527                         bi->skb = skb;
 528                         bi->dma = pci_map_single(pdev, skb->data,
 529                                                  rx_ring->rx_buf_len,
 530                                                  PCI_DMA_FROMDEVICE);
 531                 }
 532                 /* Refresh the desc even if buffer_addrs didn't change because
 533                  * each write-back erases this info. */
 534                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 535                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 536                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 537                 } else {
 538                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 539                 }
 540
 541                 i++;
 542                 if (i == rx_ring->count)
 543                         i = 0;
 544                 bi = &rx_ring->rx_buffer_info[i];
 545         }
 546
 547 no_buffers:
 548         if (rx_ring->next_to_use != i) {
 549                 rx_ring->next_to_use = i;
 550                 if (i-- == 0)
 551                         i = (rx_ring->count - 1);
 552
 553                 /*
 554                  * Force memory writes to complete before letting h/w
 555                  * know there are new descriptors to fetch.  (Only
 556                  * applicable for weak-ordered memory model archs,
 557                  * such as IA-64).
 558                  */
 559                 wmb();
 560                 writel(i, adapter->hw.hw_addr + rx_ring->tail);
 561         }
 562 }
 563
 564 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 565 {
 566         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 567 }
 568
 569 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 570 {
 571         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 572 }
 573
 574 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 575                                struct ixgbe_ring *rx_ring,
 576                                int *work_done, int work_to_do)
 577 {
 578         struct ixgbe_adapter *adapter = q_vector->adapter;
 579         struct pci_dev *pdev = adapter->pdev;
 580         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 581         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 582         struct sk_buff *skb;
 583         unsigned int i;
 584         u32 len, staterr;
 585         u16 hdr_info;
 586         bool cleaned = false;
 587         int cleaned_count = 0;
 588         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 589
 590         i = rx_ring->next_to_clean;
 591         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 592         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 593         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 594
 595         while (staterr & IXGBE_RXD_STAT_DD) {
 596                 u32 upper_len = 0;
 597                 if (*work_done >= work_to_do)
 598                         break;
 599                 (*work_done)++;
 600
 601                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 602                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 603                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 604                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 605                         if (hdr_info & IXGBE_RXDADV_SPH)
 606                                 adapter->rx_hdr_split++;
 607                         if (len > IXGBE_RX_HDR_SIZE)
 608                                 len = IXGBE_RX_HDR_SIZE;
 609                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 610                 } else {
 611                         len = le16_to_cpu(rx_desc->wb.upper.length);
 612                 }
 613
 614                 cleaned = true;
 615                 skb = rx_buffer_info->skb;
 616                 prefetch(skb->data - NET_IP_ALIGN);
 617                 rx_buffer_info->skb = NULL;
 618
 619                 if (len && !skb_shinfo(skb)->nr_frags) {
 620                         pci_unmap_single(pdev, rx_buffer_info->dma,
 621                                          rx_ring->rx_buf_len,
 622                                          PCI_DMA_FROMDEVICE);
 623                         skb_put(skb, len);
 624                 }
 625
 626                 if (upper_len) {
 627                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 628                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 629                         rx_buffer_info->page_dma = 0;
 630                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 631                                            rx_buffer_info->page,
 632                                            rx_buffer_info->page_offset,
 633                                            upper_len);
 634
 635                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 636                             (page_count(rx_buffer_info->page) != 1))
 637                                 rx_buffer_info->page = NULL;
 638                         else
 639                                 get_page(rx_buffer_info->page);
 640
 641                         skb->len += upper_len;
 642                         skb->data_len += upper_len;
 643                         skb->truesize += upper_len;
 644                 }
 645
 646                 i++;
 647                 if (i == rx_ring->count)
 648                         i = 0;
 649                 next_buffer = &rx_ring->rx_buffer_info[i];
 650
 651                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 652                 prefetch(next_rxd);
 653
 654                 cleaned_count++;
 655                 if (staterr & IXGBE_RXD_STAT_EOP) {
 656                         rx_ring->stats.packets++;
 657                         rx_ring->stats.bytes += skb->len;
 658                 } else {
 659                         rx_buffer_info->skb = next_buffer->skb;
 660                         rx_buffer_info->dma = next_buffer->dma;
 661                         next_buffer->skb = skb;
 662                         next_buffer->dma = 0;
 663                         adapter->non_eop_descs++;
 664                         goto next_desc;
 665                 }
 666
 667                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 668                         dev_kfree_skb_irq(skb);
 669                         goto next_desc;
 670                 }
 671
 672                 ixgbe_rx_checksum(adapter, staterr, skb);
 673
 674                 /* probably a little skewed due to removing CRC */
 675                 total_rx_bytes += skb->len;
 676                 total_rx_packets++;
 677
 678                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 679                 ixgbe_receive_skb(q_vector, skb, staterr, rx_desc);
 680
 681 next_desc:
 682                 rx_desc->wb.upper.status_error = 0;
 683
 684                 /* return some buffers to hardware, one at a time is too slow */
 685                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 686                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 687                         cleaned_count = 0;
 688                 }
 689
 690                 /* use prefetched values */
 691                 rx_desc = next_rxd;
 692                 rx_buffer_info = next_buffer;
 693
 694                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 695         }
 696
 697         rx_ring->next_to_clean = i;
 698         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 699
 700         if (cleaned_count)
 701                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 702
 703         rx_ring->total_packets += total_rx_packets;
 704         rx_ring->total_bytes += total_rx_bytes;
 705         adapter->net_stats.rx_bytes += total_rx_bytes;
 706         adapter->net_stats.rx_packets += total_rx_packets;
 707
 708         return cleaned;
 709 }
 710
 711 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 712 /**
 713  * ixgbe_configure_msix - Configure MSI-X hardware
 714  * @adapter: board private structure
 715  *
 716  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 717  * interrupts.
 718  **/
 719 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 720 {
 721         struct ixgbe_q_vector *q_vector;
 722         int i, j, q_vectors, v_idx, r_idx;
 723         u32 mask;
 724
 725         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 726
 727         /* Populate the IVAR table and set the ITR values to the
 728          * corresponding register.
 729          */
 730         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 731                 q_vector = &adapter->q_vector[v_idx];
 732                 /* XXX for_each_bit(...) */
 733                 r_idx = find_first_bit(q_vector->rxr_idx,
 734                                        adapter->num_rx_queues);
 735
 736                 for (i = 0; i < q_vector->rxr_count; i++) {
 737                         j = adapter->rx_ring[r_idx].reg_idx;
 738                         ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
 739                         r_idx = find_next_bit(q_vector->rxr_idx,
 740                                               adapter->num_rx_queues,
 741                                               r_idx + 1);
 742                 }
 743                 r_idx = find_first_bit(q_vector->txr_idx,
 744                                        adapter->num_tx_queues);
 745
 746                 for (i = 0; i < q_vector->txr_count; i++) {
 747                         j = adapter->tx_ring[r_idx].reg_idx;
 748                         ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
 749                         r_idx = find_next_bit(q_vector->txr_idx,
 750                                               adapter->num_tx_queues,
 751                                               r_idx + 1);
 752                 }
 753
 754                 /* if this is a tx only vector halve the interrupt rate */
 755                 if (q_vector->txr_count && !q_vector->rxr_count)
 756                         q_vector->eitr = (adapter->eitr_param >> 1);
 757                 else
 758                         /* rx only */
 759                         q_vector->eitr = adapter->eitr_param;
 760
 761                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
 762                                 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
 763         }
 764
 765         ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
 766         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 767
 768         /* set up to autoclear timer, and the vectors */
 769         mask = IXGBE_EIMS_ENABLE_MASK;
 770         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 771         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 772 }
 773
 774 enum latency_range {
 775         lowest_latency = 0,
 776         low_latency = 1,
 777         bulk_latency = 2,
 778         latency_invalid = 255
 779 };
 780
 781 /**
 782  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 783  * @adapter: pointer to adapter
 784  * @eitr: eitr setting (ints per sec) to give last timeslice
 785  * @itr_setting: current throttle rate in ints/second
 786  * @packets: the number of packets during this measurement interval
 787  * @bytes: the number of bytes during this measurement interval
 788  *
 789  *      Stores a new ITR value based on packets and byte
 790  *      counts during the last interrupt.  The advantage of per interrupt
 791  *      computation is faster updates and more accurate ITR for the current
 792  *      traffic pattern.  Constants in this function were computed
 793  *      based on theoretical maximum wire speed and thresholds were set based
 794  *      on testing data as well as attempting to minimize response time
 795  *      while increasing bulk throughput.
 796  *      this functionality is controlled by the InterruptThrottleRate module
 797  *      parameter (see ixgbe_param.c)
 798  **/
 799 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 800                            u32 eitr, u8 itr_setting,
 801                            int packets, int bytes)
 802 {
 803         unsigned int retval = itr_setting;
 804         u32 timepassed_us;
 805         u64 bytes_perint;
 806
 807         if (packets == 0)
 808                 goto update_itr_done;
 809
 810
 811         /* simple throttlerate management
 812          *    0-20MB/s lowest (100000 ints/s)
 813          *   20-100MB/s low   (20000 ints/s)
 814          *  100-1249MB/s bulk (8000 ints/s)
 815          */
 816         /* what was last interrupt timeslice? */
 817         timepassed_us = 1000000/eitr;
 818         bytes_perint = bytes / timepassed_us; /* bytes/usec */
 819
 820         switch (itr_setting) {
 821         case lowest_latency:
 822                 if (bytes_perint > adapter->eitr_low)
 823                         retval = low_latency;
 824                 break;
 825         case low_latency:
 826                 if (bytes_perint > adapter->eitr_high)
 827                         retval = bulk_latency;
 828                 else if (bytes_perint <= adapter->eitr_low)
 829                         retval = lowest_latency;
 830                 break;
 831         case bulk_latency:
 832                 if (bytes_perint <= adapter->eitr_high)
 833                         retval = low_latency;
 834                 break;
 835         }
 836
 837 update_itr_done:
 838         return retval;
 839 }
 840
 841 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
 842 {
 843         struct ixgbe_adapter *adapter = q_vector->adapter;
 844         struct ixgbe_hw *hw = &adapter->hw;
 845         u32 new_itr;
 846         u8 current_itr, ret_itr;
 847         int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
 848                                sizeof(struct ixgbe_q_vector);
 849         struct ixgbe_ring *rx_ring, *tx_ring;
 850
 851         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 852         for (i = 0; i < q_vector->txr_count; i++) {
 853                 tx_ring = &(adapter->tx_ring[r_idx]);
 854                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
 855                                            q_vector->tx_itr,
 856                                            tx_ring->total_packets,
 857                                            tx_ring->total_bytes);
 858                 /* if the result for this queue would decrease interrupt
 859                  * rate for this vector then use that result */
 860                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
 861                                     q_vector->tx_itr - 1 : ret_itr);
 862                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
 863                                       r_idx + 1);
 864         }
 865
 866         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
 867         for (i = 0; i < q_vector->rxr_count; i++) {
 868                 rx_ring = &(adapter->rx_ring[r_idx]);
 869                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
 870                                            q_vector->rx_itr,
 871                                            rx_ring->total_packets,
 872                                            rx_ring->total_bytes);
 873                 /* if the result for this queue would decrease interrupt
 874                  * rate for this vector then use that result */
 875                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
 876                                     q_vector->rx_itr - 1 : ret_itr);
 877                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
 878                                       r_idx + 1);
 879         }
 880
 881         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
 882
 883         switch (current_itr) {
 884         /* counts and packets in update_itr are dependent on these numbers */
 885         case lowest_latency:
 886                 new_itr = 100000;
 887                 break;
 888         case low_latency:
 889                 new_itr = 20000; /* aka hwitr = ~200 */
 890                 break;
 891         case bulk_latency:
 892         default:
 893                 new_itr = 8000;
 894                 break;
 895         }
 896
 897         if (new_itr != q_vector->eitr) {
 898                 u32 itr_reg;
 899                 /* do an exponential smoothing */
 900                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
 901                 q_vector->eitr = new_itr;
 902                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
 903                 /* must write high and low 16 bits to reset counter */
 904                 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
 905                         itr_reg);
 906                 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
 907         }
 908
 909         return;
 910 }
 911
 912 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
 913 {
 914         struct ixgbe_hw *hw = &adapter->hw;
 915
 916         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
 917             (eicr & IXGBE_EICR_GPI_SDP1)) {
 918                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
 919                 /* write to clear the interrupt */
 920                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
 921         }
 922 }
 923
 924 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
 925 {
 926         struct ixgbe_hw *hw = &adapter->hw;
 927
 928         adapter->lsc_int++;
 929         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
 930         adapter->link_check_timeout = jiffies;
 931         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
 932                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
 933                 schedule_work(&adapter->watchdog_task);
 934         }
 935 }
 936
 937 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
 938 {
 939         struct net_device *netdev = data;
 940         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 941         struct ixgbe_hw *hw = &adapter->hw;
 942         u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
 943
 944         if (eicr & IXGBE_EICR_LSC)
 945                 ixgbe_check_lsc(adapter);
 946
 947         ixgbe_check_fan_failure(adapter, eicr);
 948
 949         if (!test_bit(__IXGBE_DOWN, &adapter->state))
 950                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
 951
 952         return IRQ_HANDLED;
 953 }
 954
 955 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
 956 {
 957         struct ixgbe_q_vector *q_vector = data;
 958         struct ixgbe_adapter  *adapter = q_vector->adapter;
 959         struct ixgbe_ring     *tx_ring;
 960         int i, r_idx;
 961
 962         if (!q_vector->txr_count)
 963                 return IRQ_HANDLED;
 964
 965         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 966         for (i = 0; i < q_vector->txr_count; i++) {
 967                 tx_ring = &(adapter->tx_ring[r_idx]);
 968 #ifdef CONFIG_IXGBE_DCA
 969                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 970                         ixgbe_update_tx_dca(adapter, tx_ring);
 971 #endif
 972                 tx_ring->total_bytes = 0;
 973                 tx_ring->total_packets = 0;
 974                 ixgbe_clean_tx_irq(adapter, tx_ring);
 975                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
 976                                       r_idx + 1);
 977         }
 978
 979         return IRQ_HANDLED;
 980 }
 981
 982 /**
 983  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
 984  * @irq: unused
 985  * @data: pointer to our q_vector struct for this interrupt vector
 986  **/
 987 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
 988 {
 989         struct ixgbe_q_vector *q_vector = data;
 990         struct ixgbe_adapter  *adapter = q_vector->adapter;
 991         struct ixgbe_ring  *rx_ring;
 992         int r_idx;
 993         int i;
 994
 995         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
 996         for (i = 0;  i < q_vector->rxr_count; i++) {
 997                 rx_ring = &(adapter->rx_ring[r_idx]);
 998                 rx_ring->total_bytes = 0;
 999                 rx_ring->total_packets = 0;
1000                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1001                                       r_idx + 1);
1002         }
1003
1004         if (!q_vector->rxr_count)
1005                 return IRQ_HANDLED;
1006
1007         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1008         rx_ring = &(adapter->rx_ring[r_idx]);
1009         /* disable interrupts on this vector only */
1010         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1011         napi_schedule(&q_vector->napi);
1012
1013         return IRQ_HANDLED;
1014 }
1015
1016 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1017 {
1018         ixgbe_msix_clean_rx(irq, data);
1019         ixgbe_msix_clean_tx(irq, data);
1020
1021         return IRQ_HANDLED;
1022 }
1023
1024 /**
1025  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1026  * @napi: napi struct with our devices info in it
1027  * @budget: amount of work driver is allowed to do this pass, in packets
1028  *
1029  * This function is optimized for cleaning one queue only on a single
1030  * q_vector!!!
1031  **/
1032 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1033 {
1034         struct ixgbe_q_vector *q_vector =
1035                                container_of(napi, struct ixgbe_q_vector, napi);
1036         struct ixgbe_adapter *adapter = q_vector->adapter;
1037         struct ixgbe_ring *rx_ring = NULL;
1038         int work_done = 0;
1039         long r_idx;
1040
1041         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1042         rx_ring = &(adapter->rx_ring[r_idx]);
1043 #ifdef CONFIG_IXGBE_DCA
1044         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1045                 ixgbe_update_rx_dca(adapter, rx_ring);
1046 #endif
1047
1048         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1049
1050         /* If all Rx work done, exit the polling mode */
1051         if (work_done < budget) {
1052                 napi_complete(napi);
1053                 if (adapter->itr_setting & 3)
1054                         ixgbe_set_itr_msix(q_vector);
1055                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1056                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
1057         }
1058
1059         return work_done;
1060 }
1061
1062 /**
1063  * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1064  * @napi: napi struct with our devices info in it
1065  * @budget: amount of work driver is allowed to do this pass, in packets
1066  *
1067  * This function will clean more than one rx queue associated with a
1068  * q_vector.
1069  **/
1070 static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1071 {
1072         struct ixgbe_q_vector *q_vector =
1073                                container_of(napi, struct ixgbe_q_vector, napi);
1074         struct ixgbe_adapter *adapter = q_vector->adapter;
1075         struct ixgbe_ring *rx_ring = NULL;
1076         int work_done = 0, i;
1077         long r_idx;
1078         u16 enable_mask = 0;
1079
1080         /* attempt to distribute budget to each queue fairly, but don't allow
1081          * the budget to go below 1 because we'll exit polling */
1082         budget /= (q_vector->rxr_count ?: 1);
1083         budget = max(budget, 1);
1084         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1085         for (i = 0; i < q_vector->rxr_count; i++) {
1086                 rx_ring = &(adapter->rx_ring[r_idx]);
1087 #ifdef CONFIG_IXGBE_DCA
1088                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1089                         ixgbe_update_rx_dca(adapter, rx_ring);
1090 #endif
1091                 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1092                 enable_mask |= rx_ring->v_idx;
1093                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1094                                       r_idx + 1);
1095         }
1096
1097         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1098         rx_ring = &(adapter->rx_ring[r_idx]);
1099         /* If all Rx work done, exit the polling mode */
1100         if (work_done < budget) {
1101                 napi_complete(napi);
1102                 if (adapter->itr_setting & 3)
1103                         ixgbe_set_itr_msix(q_vector);
1104                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1105                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1106                 return 0;
1107         }
1108
1109         return work_done;
1110 }
1111 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1112                                      int r_idx)
1113 {
1114         a->q_vector[v_idx].adapter = a;
1115         set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1116         a->q_vector[v_idx].rxr_count++;
1117         a->rx_ring[r_idx].v_idx = 1 << v_idx;
1118 }
1119
1120 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1121                                      int r_idx)
1122 {
1123         a->q_vector[v_idx].adapter = a;
1124         set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1125         a->q_vector[v_idx].txr_count++;
1126         a->tx_ring[r_idx].v_idx = 1 << v_idx;
1127 }
1128
1129 /**
1130  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1131  * @adapter: board private structure to initialize
1132  * @vectors: allotted vector count for descriptor rings
1133  *
1134  * This function maps descriptor rings to the queue-specific vectors
1135  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1136  * one vector per ring/queue, but on a constrained vector budget, we
1137  * group the rings as "efficiently" as possible.  You would add new
1138  * mapping configurations in here.
1139  **/
1140 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1141                                       int vectors)
1142 {
1143         int v_start = 0;
1144         int rxr_idx = 0, txr_idx = 0;
1145         int rxr_remaining = adapter->num_rx_queues;
1146         int txr_remaining = adapter->num_tx_queues;
1147         int i, j;
1148         int rqpv, tqpv;
1149         int err = 0;
1150
1151         /* No mapping required if MSI-X is disabled. */
1152         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1153                 goto out;
1154
1155         /*
1156          * The ideal configuration...
1157          * We have enough vectors to map one per queue.
1158          */
1159         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1160                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1161                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1162
1163                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1164                         map_vector_to_txq(adapter, v_start, txr_idx);
1165
1166                 goto out;
1167         }
1168
1169         /*
1170          * If we don't have enough vectors for a 1-to-1
1171          * mapping, we'll have to group them so there are
1172          * multiple queues per vector.
1173          */
1174         /* Re-adjusting *qpv takes care of the remainder. */
1175         for (i = v_start; i < vectors; i++) {
1176                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1177                 for (j = 0; j < rqpv; j++) {
1178                         map_vector_to_rxq(adapter, i, rxr_idx);
1179                         rxr_idx++;
1180                         rxr_remaining--;
1181                 }
1182         }
1183         for (i = v_start; i < vectors; i++) {
1184                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1185                 for (j = 0; j < tqpv; j++) {
1186                         map_vector_to_txq(adapter, i, txr_idx);
1187                         txr_idx++;
1188                         txr_remaining--;
1189                 }
1190         }
1191
1192 out:
1193         return err;
1194 }
1195
1196 /**
1197  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1198  * @adapter: board private structure
1199  *
1200  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1201  * interrupts from the kernel.
1202  **/
1203 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1204 {
1205         struct net_device *netdev = adapter->netdev;
1206         irqreturn_t (*handler)(int, void *);
1207         int i, vector, q_vectors, err;
1208         int ri=0, ti=0;
1209
1210         /* Decrement for Other and TCP Timer vectors */
1211         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1212
1213         /* Map the Tx/Rx rings to the vectors we were allotted. */
1214         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1215         if (err)
1216                 goto out;
1217
1218 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1219                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1220                          &ixgbe_msix_clean_many)
1221         for (vector = 0; vector < q_vectors; vector++) {
1222                 handler = SET_HANDLER(&adapter->q_vector[vector]);
1223
1224                 if(handler == &ixgbe_msix_clean_rx) {
1225                         sprintf(adapter->name[vector], "%s-%s-%d",
1226                                 netdev->name, "rx", ri++);
1227                 }
1228                 else if(handler == &ixgbe_msix_clean_tx) {
1229                         sprintf(adapter->name[vector], "%s-%s-%d",
1230                                 netdev->name, "tx", ti++);
1231                 }
1232                 else
1233                         sprintf(adapter->name[vector], "%s-%s-%d",
1234                                 netdev->name, "TxRx", vector);
1235
1236                 err = request_irq(adapter->msix_entries[vector].vector,
1237                                   handler, 0, adapter->name[vector],
1238                                   &(adapter->q_vector[vector]));
1239                 if (err) {
1240                         DPRINTK(PROBE, ERR,
1241                                 "request_irq failed for MSIX interrupt "
1242                                 "Error: %d\n", err);
1243                         goto free_queue_irqs;
1244                 }
1245         }
1246
1247         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1248         err = request_irq(adapter->msix_entries[vector].vector,
1249                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1250         if (err) {
1251                 DPRINTK(PROBE, ERR,
1252                         "request_irq for msix_lsc failed: %d\n", err);
1253                 goto free_queue_irqs;
1254         }
1255
1256         return 0;
1257
1258 free_queue_irqs:
1259         for (i = vector - 1; i >= 0; i--)
1260                 free_irq(adapter->msix_entries[--vector].vector,
1261                          &(adapter->q_vector[i]));
1262         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1263         pci_disable_msix(adapter->pdev);
1264         kfree(adapter->msix_entries);
1265         adapter->msix_entries = NULL;
1266 out:
1267         return err;
1268 }
1269
1270 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1271 {
1272         struct ixgbe_hw *hw = &adapter->hw;
1273         struct ixgbe_q_vector *q_vector = adapter->q_vector;
1274         u8 current_itr;
1275         u32 new_itr = q_vector->eitr;
1276         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1277         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1278
1279         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1280                                             q_vector->tx_itr,
1281                                             tx_ring->total_packets,
1282                                             tx_ring->total_bytes);
1283         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1284                                             q_vector->rx_itr,
1285                                             rx_ring->total_packets,
1286                                             rx_ring->total_bytes);
1287
1288         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1289
1290         switch (current_itr) {
1291         /* counts and packets in update_itr are dependent on these numbers */
1292         case lowest_latency:
1293                 new_itr = 100000;
1294                 break;
1295         case low_latency:
1296                 new_itr = 20000; /* aka hwitr = ~200 */
1297                 break;
1298         case bulk_latency:
1299                 new_itr = 8000;
1300                 break;
1301         default:
1302                 break;
1303         }
1304
1305         if (new_itr != q_vector->eitr) {
1306                 u32 itr_reg;
1307                 /* do an exponential smoothing */
1308                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1309                 q_vector->eitr = new_itr;
1310                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1311                 /* must write high and low 16 bits to reset counter */
1312                 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1313         }
1314
1315         return;
1316 }
1317
1318 /**
1319  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1320  * @adapter: board private structure
1321  **/
1322 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1323 {
1324         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1325         IXGBE_WRITE_FLUSH(&adapter->hw);
1326         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1327                 int i;
1328                 for (i = 0; i < adapter->num_msix_vectors; i++)
1329                         synchronize_irq(adapter->msix_entries[i].vector);
1330         } else {
1331                 synchronize_irq(adapter->pdev->irq);
1332         }
1333 }
1334
1335 /**
1336  * ixgbe_irq_enable - Enable default interrupt generation settings
1337  * @adapter: board private structure
1338  **/
1339 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1340 {
1341         u32 mask;
1342         mask = IXGBE_EIMS_ENABLE_MASK;
1343         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1344                 mask |= IXGBE_EIMS_GPI_SDP1;
1345         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1346         IXGBE_WRITE_FLUSH(&adapter->hw);
1347 }
1348
1349 /**
1350  * ixgbe_intr - legacy mode Interrupt Handler
1351  * @irq: interrupt number
1352  * @data: pointer to a network interface device structure
1353  **/
1354 static irqreturn_t ixgbe_intr(int irq, void *data)
1355 {
1356         struct net_device *netdev = data;
1357         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1358         struct ixgbe_hw *hw = &adapter->hw;
1359         u32 eicr;
1360
1361         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1362          * therefore no explict interrupt disable is necessary */
1363         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1364         if (!eicr) {
1365                 /* shared interrupt alert!
1366                  * make sure interrupts are enabled because the read will
1367                  * have disabled interrupts due to EIAM */
1368                 ixgbe_irq_enable(adapter);
1369                 return IRQ_NONE;        /* Not our interrupt */
1370         }
1371
1372         if (eicr & IXGBE_EICR_LSC)
1373                 ixgbe_check_lsc(adapter);
1374
1375         ixgbe_check_fan_failure(adapter, eicr);
1376
1377         if (napi_schedule_prep(&adapter->q_vector[0].napi)) {
1378                 adapter->tx_ring[0].total_packets = 0;
1379                 adapter->tx_ring[0].total_bytes = 0;
1380                 adapter->rx_ring[0].total_packets = 0;
1381                 adapter->rx_ring[0].total_bytes = 0;
1382                 /* would disable interrupts here but EIAM disabled it */
1383                 __napi_schedule(&adapter->q_vector[0].napi);
1384         }
1385
1386         return IRQ_HANDLED;
1387 }
1388
1389 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1390 {
1391         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1392
1393         for (i = 0; i < q_vectors; i++) {
1394                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1395                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1396                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1397                 q_vector->rxr_count = 0;
1398                 q_vector->txr_count = 0;
1399         }
1400 }
1401
1402 /**
1403  * ixgbe_request_irq - initialize interrupts
1404  * @adapter: board private structure
1405  *
1406  * Attempts to configure interrupts using the best available
1407  * capabilities of the hardware and kernel.
1408  **/
1409 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1410 {
1411         struct net_device *netdev = adapter->netdev;
1412         int err;
1413
1414         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1415                 err = ixgbe_request_msix_irqs(adapter);
1416         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1417                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1418                                   netdev->name, netdev);
1419         } else {
1420                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1421                                   netdev->name, netdev);
1422         }
1423
1424         if (err)
1425                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1426
1427         return err;
1428 }
1429
1430 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1431 {
1432         struct net_device *netdev = adapter->netdev;
1433
1434         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1435                 int i, q_vectors;
1436
1437                 q_vectors = adapter->num_msix_vectors;
1438
1439                 i = q_vectors - 1;
1440                 free_irq(adapter->msix_entries[i].vector, netdev);
1441
1442                 i--;
1443                 for (; i >= 0; i--) {
1444                         free_irq(adapter->msix_entries[i].vector,
1445                                  &(adapter->q_vector[i]));
1446                 }
1447
1448                 ixgbe_reset_q_vectors(adapter);
1449         } else {
1450                 free_irq(adapter->pdev->irq, netdev);
1451         }
1452 }
1453
1454 /**
1455  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1456  *
1457  **/
1458 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1459 {
1460         struct ixgbe_hw *hw = &adapter->hw;
1461
1462         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1463                         EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1464
1465         ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
1466         ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1467
1468         map_vector_to_rxq(adapter, 0, 0);
1469         map_vector_to_txq(adapter, 0, 0);
1470
1471         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1472 }
1473
1474 /**
1475  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1476  * @adapter: board private structure
1477  *
1478  * Configure the Tx unit of the MAC after a reset.
1479  **/
1480 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1481 {
1482         u64 tdba, tdwba;
1483         struct ixgbe_hw *hw = &adapter->hw;
1484         u32 i, j, tdlen, txctrl;
1485
1486         /* Setup the HW Tx Head and Tail descriptor pointers */
1487         for (i = 0; i < adapter->num_tx_queues; i++) {
1488                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1489                 j = ring->reg_idx;
1490                 tdba = ring->dma;
1491                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1492                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1493                                 (tdba & DMA_32BIT_MASK));
1494                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1495                 tdwba = ring->dma +
1496                         (ring->count * sizeof(union ixgbe_adv_tx_desc));
1497                 tdwba |= IXGBE_TDWBAL_HEAD_WB_ENABLE;
1498                 IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(j), tdwba & DMA_32BIT_MASK);
1499                 IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(j), (tdwba >> 32));
1500                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1501                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1502                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1503                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1504                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1505                 /* Disable Tx Head Writeback RO bit, since this hoses
1506                  * bookkeeping if things aren't delivered in order.
1507                  */
1508                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1509                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1510                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1511         }
1512 }
1513
1514 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1515
1516 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1517 {
1518         struct ixgbe_ring *rx_ring;
1519         u32 srrctl;
1520         int queue0;
1521         unsigned long mask;
1522
1523         /* program one srrctl register per VMDq index */
1524         if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
1525                 long shift, len;
1526                 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1527                 len = sizeof(adapter->ring_feature[RING_F_VMDQ].mask) * 8;
1528                 shift = find_first_bit(&mask, len);
1529                 queue0 = index & mask;
1530                 index = (index & mask) >> shift;
1531         /* program one srrctl per RSS queue since RDRXCTL.MVMEN is enabled */
1532         } else {
1533                 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1534                 queue0 = index & mask;
1535                 index = index & mask;
1536         }
1537
1538         rx_ring = &adapter->rx_ring[queue0];
1539
1540         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1541
1542         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1543         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1544
1545         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1546                 srrctl |= IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1547                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1548                 srrctl |= ((IXGBE_RX_HDR_SIZE <<
1549                             IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1550                            IXGBE_SRRCTL_BSIZEHDR_MASK);
1551         } else {
1552                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1553
1554                 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1555                         srrctl |= IXGBE_RXBUFFER_2048 >>
1556                                   IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1557                 else
1558                         srrctl |= rx_ring->rx_buf_len >>
1559                                   IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1560         }
1561         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1562 }
1563
1564 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1565                            (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1566
1567 /**
1568  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1569  * @adapter: board private structure
1570  *
1571  * Configure the Rx unit of the MAC after a reset.
1572  **/
1573 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1574 {
1575         u64 rdba;
1576         struct ixgbe_hw *hw = &adapter->hw;
1577         struct net_device *netdev = adapter->netdev;
1578         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1579         int i, j;
1580         u32 rdlen, rxctrl, rxcsum;
1581         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1582                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1583                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
1584         u32 fctrl, hlreg0;
1585         u32 pages;
1586         u32 reta = 0, mrqc;
1587         u32 rdrxctl;
1588         int rx_buf_len;
1589
1590         /* Decide whether to use packet split mode or not */
1591         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1592
1593         /* Set the RX buffer length according to the mode */
1594         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1595                 rx_buf_len = IXGBE_RX_HDR_SIZE;
1596         } else {
1597                 if (netdev->mtu <= ETH_DATA_LEN)
1598                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1599                 else
1600                         rx_buf_len = ALIGN(max_frame, 1024);
1601         }
1602
1603         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1604         fctrl |= IXGBE_FCTRL_BAM;
1605         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
1606         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1607
1608         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1609         if (adapter->netdev->mtu <= ETH_DATA_LEN)
1610                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1611         else
1612                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1613         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1614
1615         pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1616
1617         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1618         /* disable receives while setting up the descriptors */
1619         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1620         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1621
1622         /* Setup the HW Rx Head and Tail Descriptor Pointers and
1623          * the Base and Length of the Rx Descriptor Ring */
1624         for (i = 0; i < adapter->num_rx_queues; i++) {
1625                 rdba = adapter->rx_ring[i].dma;
1626                 j = adapter->rx_ring[i].reg_idx;
1627                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1628                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1629                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1630                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1631                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1632                 adapter->rx_ring[i].head = IXGBE_RDH(j);
1633                 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1634                 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1635
1636                 ixgbe_configure_srrctl(adapter, j);
1637         }
1638
1639         /*
1640          * For VMDq support of different descriptor types or
1641          * buffer sizes through the use of multiple SRRCTL
1642          * registers, RDRXCTL.MVMEN must be set to 1
1643          *
1644          * also, the manual doesn't mention it clearly but DCA hints
1645          * will only use queue 0's tags unless this bit is set.  Side
1646          * effects of setting this bit are only that SRRCTL must be
1647          * fully programmed [0..15]
1648          */
1649         if (adapter->flags &
1650             (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_VMDQ_ENABLED)) {
1651                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1652                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1653                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1654         }
1655
1656         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
1657                 /* Fill out redirection table */
1658                 for (i = 0, j = 0; i < 128; i++, j++) {
1659                         if (j == adapter->ring_feature[RING_F_RSS].indices)
1660                                 j = 0;
1661                         /* reta = 4-byte sliding window of
1662                          * 0x00..(indices-1)(indices-1)00..etc. */
1663                         reta = (reta << 8) | (j * 0x11);
1664                         if ((i & 3) == 3)
1665                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
1666                 }
1667
1668                 /* Fill out hash function seeds */
1669                 for (i = 0; i < 10; i++)
1670                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
1671
1672                 mrqc = IXGBE_MRQC_RSSEN
1673                     /* Perform hash on these packet types */
1674                        | IXGBE_MRQC_RSS_FIELD_IPV4
1675                        | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1676                        | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1677                        | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1678                        | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1679                        | IXGBE_MRQC_RSS_FIELD_IPV6
1680                        | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1681                        | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1682                        | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
1683                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
1684         }
1685
1686         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1687
1688         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1689             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1690                 /* Disable indicating checksum in descriptor, enables
1691                  * RSS hash */
1692                 rxcsum |= IXGBE_RXCSUM_PCSD;
1693         }
1694         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1695                 /* Enable IPv4 payload checksum for UDP fragments
1696                  * if PCSD is not set */
1697                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1698         }
1699
1700         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
1701 }
1702
1703 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1704 {
1705         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1706         struct ixgbe_hw *hw = &adapter->hw;
1707
1708         /* add VID to filter table */
1709         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1710 }
1711
1712 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1713 {
1714         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1715         struct ixgbe_hw *hw = &adapter->hw;
1716
1717         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1718                 ixgbe_irq_disable(adapter);
1719
1720         vlan_group_set_device(adapter->vlgrp, vid, NULL);
1721
1722         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1723                 ixgbe_irq_enable(adapter);
1724
1725         /* remove VID from filter table */
1726         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
1727 }
1728
1729 static void ixgbe_vlan_rx_register(struct net_device *netdev,
1730                                    struct vlan_group *grp)
1731 {
1732         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1733         u32 ctrl;
1734
1735         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1736                 ixgbe_irq_disable(adapter);
1737         adapter->vlgrp = grp;
1738
1739         /*
1740          * For a DCB driver, always enable VLAN tag stripping so we can
1741          * still receive traffic from a DCB-enabled host even if we're
1742          * not in DCB mode.
1743          */
1744         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1745         ctrl |= IXGBE_VLNCTRL_VME;
1746         ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1747         IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1748         ixgbe_vlan_rx_add_vid(netdev, 0);
1749
1750         if (grp) {
1751                 /* enable VLAN tag insert/strip */
1752                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1753                 ctrl |= IXGBE_VLNCTRL_VME;
1754                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1755                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1756         }
1757
1758         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1759                 ixgbe_irq_enable(adapter);
1760 }
1761
1762 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1763 {
1764         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1765
1766         if (adapter->vlgrp) {
1767                 u16 vid;
1768                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1769                         if (!vlan_group_get_device(adapter->vlgrp, vid))
1770                                 continue;
1771                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1772                 }
1773         }
1774 }
1775
1776 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1777 {
1778         struct dev_mc_list *mc_ptr;
1779         u8 *addr = *mc_addr_ptr;
1780         *vmdq = 0;
1781
1782         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1783         if (mc_ptr->next)
1784                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1785         else
1786                 *mc_addr_ptr = NULL;
1787
1788         return addr;
1789 }
1790
1791 /**
1792  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
1793  * @netdev: network interface device structure
1794  *
1795  * The set_rx_method entry point is called whenever the unicast/multicast
1796  * address list or the network interface flags are updated.  This routine is
1797  * responsible for configuring the hardware for proper unicast, multicast and
1798  * promiscuous mode.
1799  **/
1800 static void ixgbe_set_rx_mode(struct net_device *netdev)
1801 {
1802         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1803         struct ixgbe_hw *hw = &adapter->hw;
1804         u32 fctrl, vlnctrl;
1805         u8 *addr_list = NULL;
1806         int addr_count = 0;
1807
1808         /* Check for Promiscuous and All Multicast modes */
1809
1810         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1811         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1812
1813         if (netdev->flags & IFF_PROMISC) {
1814                 hw->addr_ctrl.user_set_promisc = 1;
1815                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1816                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1817         } else {
1818                 if (netdev->flags & IFF_ALLMULTI) {
1819                         fctrl |= IXGBE_FCTRL_MPE;
1820                         fctrl &= ~IXGBE_FCTRL_UPE;
1821                 } else {
1822                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1823                 }
1824                 vlnctrl |= IXGBE_VLNCTRL_VFE;
1825                 hw->addr_ctrl.user_set_promisc = 0;
1826         }
1827
1828         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1829         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1830
1831         /* reprogram secondary unicast list */
1832         addr_count = netdev->uc_count;
1833         if (addr_count)
1834                 addr_list = netdev->uc_list->dmi_addr;
1835         hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
1836                                           ixgbe_addr_list_itr);
1837
1838         /* reprogram multicast list */
1839         addr_count = netdev->mc_count;
1840         if (addr_count)
1841                 addr_list = netdev->mc_list->dmi_addr;
1842         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
1843                                         ixgbe_addr_list_itr);
1844 }
1845
1846 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1847 {
1848         int q_idx;
1849         struct ixgbe_q_vector *q_vector;
1850         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1851
1852         /* legacy and MSI only use one vector */
1853         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1854                 q_vectors = 1;
1855
1856         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1857                 struct napi_struct *napi;
1858                 q_vector = &adapter->q_vector[q_idx];
1859                 if (!q_vector->rxr_count)
1860                         continue;
1861                 napi = &q_vector->napi;
1862                 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
1863                     (q_vector->rxr_count > 1))
1864                         napi->poll = &ixgbe_clean_rxonly_many;
1865
1866                 napi_enable(napi);
1867         }
1868 }
1869
1870 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1871 {
1872         int q_idx;
1873         struct ixgbe_q_vector *q_vector;
1874         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1875
1876         /* legacy and MSI only use one vector */
1877         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1878                 q_vectors = 1;
1879
1880         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1881                 q_vector = &adapter->q_vector[q_idx];
1882                 if (!q_vector->rxr_count)
1883                         continue;
1884                 napi_disable(&q_vector->napi);
1885         }
1886 }
1887
1888 #ifdef CONFIG_IXGBE_DCB
1889 /*
1890  * ixgbe_configure_dcb - Configure DCB hardware
1891  * @adapter: ixgbe adapter struct
1892  *
1893  * This is called by the driver on open to configure the DCB hardware.
1894  * This is also called by the gennetlink interface when reconfiguring
1895  * the DCB state.
1896  */
1897 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
1898 {
1899         struct ixgbe_hw *hw = &adapter->hw;
1900         u32 txdctl, vlnctrl;
1901         int i, j;
1902
1903         ixgbe_dcb_check_config(&adapter->dcb_cfg);
1904         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
1905         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
1906
1907         /* reconfigure the hardware */
1908         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
1909
1910         for (i = 0; i < adapter->num_tx_queues; i++) {
1911                 j = adapter->tx_ring[i].reg_idx;
1912                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
1913                 /* PThresh workaround for Tx hang with DFP enabled. */
1914                 txdctl |= 32;
1915                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1916         }
1917         /* Enable VLAN tag insert/strip */
1918         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1919         vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
1920         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1921         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1922         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
1923 }
1924
1925 #endif
1926 static void ixgbe_configure(struct ixgbe_adapter *adapter)
1927 {
1928         struct net_device *netdev = adapter->netdev;
1929         int i;
1930
1931         ixgbe_set_rx_mode(netdev);
1932
1933         ixgbe_restore_vlan(adapter);
1934 #ifdef CONFIG_IXGBE_DCB
1935         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1936                 netif_set_gso_max_size(netdev, 32768);
1937                 ixgbe_configure_dcb(adapter);
1938         } else {
1939                 netif_set_gso_max_size(netdev, 65536);
1940         }
1941 #else
1942         netif_set_gso_max_size(netdev, 65536);
1943 #endif
1944
1945         ixgbe_configure_tx(adapter);
1946         ixgbe_configure_rx(adapter);
1947         for (i = 0; i < adapter->num_rx_queues; i++)
1948                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
1949                                        (adapter->rx_ring[i].count - 1));
1950 }
1951
1952 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1953 {
1954         struct net_device *netdev = adapter->netdev;
1955         struct ixgbe_hw *hw = &adapter->hw;
1956         int i, j = 0;
1957         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1958         u32 txdctl, rxdctl, mhadd;
1959         u32 gpie;
1960
1961         ixgbe_get_hw_control(adapter);
1962
1963         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
1964             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
1965                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1966                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
1967                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
1968                 } else {
1969                         /* MSI only */
1970                         gpie = 0;
1971                 }
1972                 /* XXX: to interrupt immediately for EICS writes, enable this */
1973                 /* gpie |= IXGBE_GPIE_EIMEN; */
1974                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
1975         }
1976
1977         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
1978                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
1979                  * specifically only auto mask tx and rx interrupts */
1980                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
1981         }
1982
1983         /* Enable fan failure interrupt if media type is copper */
1984         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
1985                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
1986                 gpie |= IXGBE_SDP1_GPIEN;
1987                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
1988         }
1989
1990         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
1991         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
1992                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
1993                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
1994
1995                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
1996         }
1997
1998         for (i = 0; i < adapter->num_tx_queues; i++) {
1999                 j = adapter->tx_ring[i].reg_idx;
2000                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2001                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2002                 txdctl |= (8 << 16);
2003                 txdctl |= IXGBE_TXDCTL_ENABLE;
2004                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2005         }
2006
2007         for (i = 0; i < adapter->num_rx_queues; i++) {
2008                 j = adapter->rx_ring[i].reg_idx;
2009                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2010                 /* enable PTHRESH=32 descriptors (half the internal cache)
2011                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2012                  * this also removes a pesky rx_no_buffer_count increment */
2013                 rxdctl |= 0x0020;
2014                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2015                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2016         }
2017         /* enable all receives */
2018         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2019         rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2020         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
2021
2022         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2023                 ixgbe_configure_msix(adapter);
2024         else
2025                 ixgbe_configure_msi_and_legacy(adapter);
2026
2027         ixgbe_napi_add_all(adapter);
2028
2029         clear_bit(__IXGBE_DOWN, &adapter->state);
2030         ixgbe_napi_enable_all(adapter);
2031
2032         /* clear any pending interrupts, may auto mask */
2033         IXGBE_READ_REG(hw, IXGBE_EICR);
2034
2035         ixgbe_irq_enable(adapter);
2036
2037         /* enable transmits */
2038         netif_tx_start_all_queues(netdev);
2039
2040         /* bring the link up in the watchdog, this could race with our first
2041          * link up interrupt but shouldn't be a problem */
2042         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2043         adapter->link_check_timeout = jiffies;
2044         mod_timer(&adapter->watchdog_timer, jiffies);
2045         return 0;
2046 }
2047
2048 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2049 {
2050         WARN_ON(in_interrupt());
2051         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2052                 msleep(1);
2053         ixgbe_down(adapter);
2054         ixgbe_up(adapter);
2055         clear_bit(__IXGBE_RESETTING, &adapter->state);
2056 }
2057
2058 int ixgbe_up(struct ixgbe_adapter *adapter)
2059 {
2060         /* hardware has been reset, we need to reload some things */
2061         ixgbe_configure(adapter);
2062
2063         return ixgbe_up_complete(adapter);
2064 }
2065
2066 void ixgbe_reset(struct ixgbe_adapter *adapter)
2067 {
2068         struct ixgbe_hw *hw = &adapter->hw;
2069         if (hw->mac.ops.init_hw(hw))
2070                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
2071
2072         /* reprogram the RAR[0] in case user changed it. */
2073         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2074
2075 }
2076
2077 /**
2078  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2079  * @adapter: board private structure
2080  * @rx_ring: ring to free buffers from
2081  **/
2082 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2083                                 struct ixgbe_ring *rx_ring)
2084 {
2085         struct pci_dev *pdev = adapter->pdev;
2086         unsigned long size;
2087         unsigned int i;
2088
2089         /* Free all the Rx ring sk_buffs */
2090
2091         for (i = 0; i < rx_ring->count; i++) {
2092                 struct ixgbe_rx_buffer *rx_buffer_info;
2093
2094                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2095                 if (rx_buffer_info->dma) {
2096                         pci_unmap_single(pdev, rx_buffer_info->dma,
2097                                          rx_ring->rx_buf_len,
2098                                          PCI_DMA_FROMDEVICE);
2099                         rx_buffer_info->dma = 0;
2100                 }
2101                 if (rx_buffer_info->skb) {
2102                         dev_kfree_skb(rx_buffer_info->skb);
2103                         rx_buffer_info->skb = NULL;
2104                 }
2105                 if (!rx_buffer_info->page)
2106                         continue;
2107                 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2108                                PCI_DMA_FROMDEVICE);
2109                 rx_buffer_info->page_dma = 0;
2110                 put_page(rx_buffer_info->page);
2111                 rx_buffer_info->page = NULL;
2112                 rx_buffer_info->page_offset = 0;
2113         }
2114
2115         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2116         memset(rx_ring->rx_buffer_info, 0, size);
2117
2118         /* Zero out the descriptor ring */
2119         memset(rx_ring->desc, 0, rx_ring->size);
2120
2121         rx_ring->next_to_clean = 0;
2122         rx_ring->next_to_use = 0;
2123
2124         writel(0, adapter->hw.hw_addr + rx_ring->head);
2125         writel(0, adapter->hw.hw_addr + rx_ring->tail);
2126 }
2127
2128 /**
2129  * ixgbe_clean_tx_ring - Free Tx Buffers
2130  * @adapter: board private structure
2131  * @tx_ring: ring to be cleaned
2132  **/
2133 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2134                                 struct ixgbe_ring *tx_ring)
2135 {
2136         struct ixgbe_tx_buffer *tx_buffer_info;
2137         unsigned long size;
2138         unsigned int i;
2139
2140         /* Free all the Tx ring sk_buffs */
2141
2142         for (i = 0; i < tx_ring->count; i++) {
2143                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2144                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2145         }
2146
2147         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2148         memset(tx_ring->tx_buffer_info, 0, size);
2149
2150         /* Zero out the descriptor ring */
2151         memset(tx_ring->desc, 0, tx_ring->size);
2152
2153         tx_ring->next_to_use = 0;
2154         tx_ring->next_to_clean = 0;
2155
2156         writel(0, adapter->hw.hw_addr + tx_ring->head);
2157         writel(0, adapter->hw.hw_addr + tx_ring->tail);
2158 }
2159
2160 /**
2161  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2162  * @adapter: board private structure
2163  **/
2164 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2165 {
2166         int i;
2167
2168         for (i = 0; i < adapter->num_rx_queues; i++)
2169                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2170 }
2171
2172 /**
2173  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2174  * @adapter: board private structure
2175  **/
2176 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2177 {
2178         int i;
2179
2180         for (i = 0; i < adapter->num_tx_queues; i++)
2181                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2182 }
2183
2184 void ixgbe_down(struct ixgbe_adapter *adapter)
2185 {
2186         struct net_device *netdev = adapter->netdev;
2187         struct ixgbe_hw *hw = &adapter->hw;
2188         u32 rxctrl;
2189         u32 txdctl;
2190         int i, j;
2191
2192         /* signal that we are down to the interrupt handler */
2193         set_bit(__IXGBE_DOWN, &adapter->state);
2194
2195         /* disable receives */
2196         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2197         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2198
2199         netif_tx_disable(netdev);
2200
2201         IXGBE_WRITE_FLUSH(hw);
2202         msleep(10);
2203
2204         netif_tx_stop_all_queues(netdev);
2205
2206         ixgbe_irq_disable(adapter);
2207
2208         ixgbe_napi_disable_all(adapter);
2209
2210         del_timer_sync(&adapter->watchdog_timer);
2211         cancel_work_sync(&adapter->watchdog_task);
2212
2213         /* disable transmits in the hardware now that interrupts are off */
2214         for (i = 0; i < adapter->num_tx_queues; i++) {
2215                 j = adapter->tx_ring[i].reg_idx;
2216                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2217                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2218                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2219         }
2220
2221         netif_carrier_off(netdev);
2222
2223 #ifdef CONFIG_IXGBE_DCA
2224         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2225                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2226                 dca_remove_requester(&adapter->pdev->dev);
2227         }
2228
2229 #endif
2230         if (!pci_channel_offline(adapter->pdev))
2231                 ixgbe_reset(adapter);
2232         ixgbe_clean_all_tx_rings(adapter);
2233         ixgbe_clean_all_rx_rings(adapter);
2234
2235 #ifdef CONFIG_IXGBE_DCA
2236         /* since we reset the hardware DCA settings were cleared */
2237         if (dca_add_requester(&adapter->pdev->dev) == 0) {
2238                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2239                 /* always use CB2 mode, difference is masked
2240                  * in the CB driver */
2241                 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
2242                 ixgbe_setup_dca(adapter);
2243         }
2244 #endif
2245 }
2246
2247 /**
2248  * ixgbe_poll - NAPI Rx polling callback
2249  * @napi: structure for representing this polling device
2250  * @budget: how many packets driver is allowed to clean
2251  *
2252  * This function is used for legacy and MSI, NAPI mode
2253  **/
2254 static int ixgbe_poll(struct napi_struct *napi, int budget)
2255 {
2256         struct ixgbe_q_vector *q_vector = container_of(napi,
2257                                                   struct ixgbe_q_vector, napi);
2258         struct ixgbe_adapter *adapter = q_vector->adapter;
2259         int tx_cleaned, work_done = 0;
2260
2261 #ifdef CONFIG_IXGBE_DCA
2262         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2263                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2264                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2265         }
2266 #endif
2267
2268         tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
2269         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2270
2271         if (tx_cleaned)
2272                 work_done = budget;
2273
2274         /* If budget not fully consumed, exit the polling mode */
2275         if (work_done < budget) {
2276                 napi_complete(napi);
2277                 if (adapter->itr_setting & 3)
2278                         ixgbe_set_itr(adapter);
2279                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2280                         ixgbe_irq_enable(adapter);
2281         }
2282         return work_done;
2283 }
2284
2285 /**
2286  * ixgbe_tx_timeout - Respond to a Tx Hang
2287  * @netdev: network interface device structure
2288  **/
2289 static void ixgbe_tx_timeout(struct net_device *netdev)
2290 {
2291         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2292
2293         /* Do the reset outside of interrupt context */
2294         schedule_work(&adapter->reset_task);
2295 }
2296
2297 static void ixgbe_reset_task(struct work_struct *work)
2298 {
2299         struct ixgbe_adapter *adapter;
2300         adapter = container_of(work, struct ixgbe_adapter, reset_task);
2301
2302         /* If we're already down or resetting, just bail */
2303         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2304             test_bit(__IXGBE_RESETTING, &adapter->state))
2305                 return;
2306
2307         adapter->tx_timeout_count++;
2308
2309         ixgbe_reinit_locked(adapter);
2310 }
2311
2312 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2313 {
2314         int nrq = 1, ntq = 1;
2315         int feature_mask = 0, rss_i, rss_m;
2316         int dcb_i, dcb_m;
2317
2318         /* Number of supported queues */
2319         switch (adapter->hw.mac.type) {
2320         case ixgbe_mac_82598EB:
2321                 dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2322                 dcb_m = 0;
2323                 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2324                 rss_m = 0;
2325                 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2326                 feature_mask |= IXGBE_FLAG_DCB_ENABLED;
2327
2328                 switch (adapter->flags & feature_mask) {
2329                 case (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_DCB_ENABLED):
2330                         dcb_m = 0x7 << 3;
2331                         rss_i = min(8, rss_i);
2332                         rss_m = 0x7;
2333                         nrq = dcb_i * rss_i;
2334                         ntq = min(MAX_TX_QUEUES, dcb_i * rss_i);
2335                         break;
2336                 case (IXGBE_FLAG_DCB_ENABLED):
2337                         dcb_m = 0x7 << 3;
2338                         nrq = dcb_i;
2339                         ntq = dcb_i;
2340                         break;
2341                 case (IXGBE_FLAG_RSS_ENABLED):
2342                         rss_m = 0xF;
2343                         nrq = rss_i;
2344                         ntq = rss_i;
2345                         break;
2346                 case 0:
2347                 default:
2348                         dcb_i = 0;
2349                         dcb_m = 0;
2350                         rss_i = 0;
2351                         rss_m = 0;
2352                         nrq = 1;
2353                         ntq = 1;
2354                         break;
2355                 }
2356
2357                 /* Sanity check, we should never have zero queues */
2358                 nrq = (nrq ?:1);
2359                 ntq = (ntq ?:1);
2360
2361                 adapter->ring_feature[RING_F_DCB].indices = dcb_i;
2362                 adapter->ring_feature[RING_F_DCB].mask = dcb_m;
2363                 adapter->ring_feature[RING_F_RSS].indices = rss_i;
2364                 adapter->ring_feature[RING_F_RSS].mask = rss_m;
2365                 break;
2366         default:
2367                 nrq = 1;
2368                 ntq = 1;
2369                 break;
2370         }
2371
2372         adapter->num_rx_queues = nrq;
2373         adapter->num_tx_queues = ntq;
2374 }
2375
2376 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2377                                        int vectors)
2378 {
2379         int err, vector_threshold;
2380
2381         /* We'll want at least 3 (vector_threshold):
2382          * 1) TxQ[0] Cleanup
2383          * 2) RxQ[0] Cleanup
2384          * 3) Other (Link Status Change, etc.)
2385          * 4) TCP Timer (optional)
2386          */
2387         vector_threshold = MIN_MSIX_COUNT;
2388
2389         /* The more we get, the more we will assign to Tx/Rx Cleanup
2390          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2391          * Right now, we simply care about how many we'll get; we'll
2392          * set them up later while requesting irq's.
2393          */
2394         while (vectors >= vector_threshold) {
2395                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2396                                       vectors);
2397                 if (!err) /* Success in acquiring all requested vectors. */
2398                         break;
2399                 else if (err < 0)
2400                         vectors = 0; /* Nasty failure, quit now */
2401                 else /* err == number of vectors we should try again with */
2402                         vectors = err;
2403         }
2404
2405         if (vectors < vector_threshold) {
2406                 /* Can't allocate enough MSI-X interrupts?  Oh well.
2407                  * This just means we'll go with either a single MSI
2408                  * vector or fall back to legacy interrupts.
2409                  */
2410                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2411                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2412                 kfree(adapter->msix_entries);
2413                 adapter->msix_entries = NULL;
2414                 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2415                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2416                 ixgbe_set_num_queues(adapter);
2417         } else {
2418                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2419                 adapter->num_msix_vectors = vectors;
2420         }
2421 }
2422
2423 /**
2424  * ixgbe_cache_ring_register - Descriptor ring to register mapping
2425  * @adapter: board private structure to initialize
2426  *
2427  * Once we know the feature-set enabled for the device, we'll cache
2428  * the register offset the descriptor ring is assigned to.
2429  **/
2430 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2431 {
2432         int feature_mask = 0, rss_i;
2433         int i, txr_idx, rxr_idx;
2434         int dcb_i;
2435
2436         /* Number of supported queues */
2437         switch (adapter->hw.mac.type) {
2438         case ixgbe_mac_82598EB:
2439                 dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2440                 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2441                 txr_idx = 0;
2442                 rxr_idx = 0;
2443                 feature_mask |= IXGBE_FLAG_DCB_ENABLED;
2444                 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2445                 switch (adapter->flags & feature_mask) {
2446                 case (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_DCB_ENABLED):
2447                         for (i = 0; i < dcb_i; i++) {
2448                                 int j;
2449                                 /* Rx first */
2450                                 for (j = 0; j < adapter->num_rx_queues; j++) {
2451                                         adapter->rx_ring[rxr_idx].reg_idx =
2452                                                 i << 3 | j;
2453                                         rxr_idx++;
2454                                 }
2455                                 /* Tx now */
2456                                 for (j = 0; j < adapter->num_tx_queues; j++) {
2457                                         adapter->tx_ring[txr_idx].reg_idx =
2458                                                 i << 2 | (j >> 1);
2459                                         if (j & 1)
2460                                                 txr_idx++;
2461                                 }
2462                         }
2463                 case (IXGBE_FLAG_DCB_ENABLED):
2464                         /* the number of queues is assumed to be symmetric */
2465                         for (i = 0; i < dcb_i; i++) {
2466                                 adapter->rx_ring[i].reg_idx = i << 3;
2467                                 adapter->tx_ring[i].reg_idx = i << 2;
2468                         }
2469                         break;
2470                 case (IXGBE_FLAG_RSS_ENABLED):
2471                         for (i = 0; i < adapter->num_rx_queues; i++)
2472                                 adapter->rx_ring[i].reg_idx = i;
2473                         for (i = 0; i < adapter->num_tx_queues; i++)
2474                                 adapter->tx_ring[i].reg_idx = i;
2475                         break;
2476                 case 0:
2477                 default:
2478                         break;
2479                 }
2480                 break;
2481         default:
2482                 break;
2483         }
2484 }
2485
2486 /**
2487  * ixgbe_alloc_queues - Allocate memory for all rings
2488  * @adapter: board private structure to initialize
2489  *
2490  * We allocate one ring per queue at run-time since we don't know the
2491  * number of queues at compile-time.
2492  **/
2493 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2494 {
2495         int i;
2496
2497         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
2498                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
2499         if (!adapter->tx_ring)
2500                 goto err_tx_ring_allocation;
2501
2502         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
2503                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
2504         if (!adapter->rx_ring)
2505                 goto err_rx_ring_allocation;
2506
2507         for (i = 0; i < adapter->num_tx_queues; i++) {
2508                 adapter->tx_ring[i].count = adapter->tx_ring_count;
2509                 adapter->tx_ring[i].queue_index = i;
2510         }
2511
2512         for (i = 0; i < adapter->num_rx_queues; i++) {
2513                 adapter->rx_ring[i].count = adapter->rx_ring_count;
2514                 adapter->rx_ring[i].queue_index = i;
2515         }
2516
2517         ixgbe_cache_ring_register(adapter);
2518
2519         return 0;
2520
2521 err_rx_ring_allocation:
2522         kfree(adapter->tx_ring);
2523 err_tx_ring_allocation:
2524         return -ENOMEM;
2525 }
2526
2527 /**
2528  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2529  * @adapter: board private structure to initialize
2530  *
2531  * Attempt to configure the interrupts using the best available
2532  * capabilities of the hardware and the kernel.
2533  **/
2534 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
2535 {
2536         int err = 0;
2537         int vector, v_budget;
2538
2539         /*
2540          * It's easy to be greedy for MSI-X vectors, but it really
2541          * doesn't do us much good if we have a lot more vectors
2542          * than CPU's.  So let's be conservative and only ask for
2543          * (roughly) twice the number of vectors as there are CPU's.
2544          */
2545         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
2546                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
2547
2548         /*
2549          * At the same time, hardware can only support a maximum of
2550          * MAX_MSIX_COUNT vectors.  With features such as RSS and VMDq,
2551          * we can easily reach upwards of 64 Rx descriptor queues and
2552          * 32 Tx queues.  Thus, we cap it off in those rare cases where
2553          * the cpu count also exceeds our vector limit.
2554          */
2555         v_budget = min(v_budget, MAX_MSIX_COUNT);
2556
2557         /* A failure in MSI-X entry allocation isn't fatal, but it does
2558          * mean we disable MSI-X capabilities of the adapter. */
2559         adapter->msix_entries = kcalloc(v_budget,
2560                                         sizeof(struct msix_entry), GFP_KERNEL);
2561         if (!adapter->msix_entries) {
2562                 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2563                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2564                 ixgbe_set_num_queues(adapter);
2565                 kfree(adapter->tx_ring);
2566                 kfree(adapter->rx_ring);
2567                 err = ixgbe_alloc_queues(adapter);
2568                 if (err) {
2569                         DPRINTK(PROBE, ERR, "Unable to allocate memory "
2570                                 "for queues\n");
2571                         goto out;
2572                 }
2573
2574                 goto try_msi;
2575         }
2576
2577         for (vector = 0; vector < v_budget; vector++)
2578                 adapter->msix_entries[vector].entry = vector;
2579
2580         ixgbe_acquire_msix_vectors(adapter, v_budget);
2581
2582         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2583                 goto out;
2584
2585 try_msi:
2586         err = pci_enable_msi(adapter->pdev);
2587         if (!err) {
2588                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2589         } else {
2590                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
2591                         "falling back to legacy.  Error: %d\n", err);
2592                 /* reset err */
2593                 err = 0;
2594         }
2595
2596 out:
2597         /* Notify the stack of the (possibly) reduced Tx Queue count. */
2598         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
2599
2600         return err;
2601 }
2602
2603 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
2604 {
2605         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2606                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2607                 pci_disable_msix(adapter->pdev);
2608                 kfree(adapter->msix_entries);
2609                 adapter->msix_entries = NULL;
2610         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2611                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2612                 pci_disable_msi(adapter->pdev);
2613         }
2614         return;
2615 }
2616
2617 /**
2618  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2619  * @adapter: board private structure to initialize
2620  *
2621  * We determine which interrupt scheme to use based on...
2622  * - Kernel support (MSI, MSI-X)
2623  *   - which can be user-defined (via MODULE_PARAM)
2624  * - Hardware queue count (num_*_queues)
2625  *   - defined by miscellaneous hardware support/features (RSS, etc.)
2626  **/
2627 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
2628 {
2629         int err;
2630
2631         /* Number of supported queues */
2632         ixgbe_set_num_queues(adapter);
2633
2634         err = ixgbe_alloc_queues(adapter);
2635         if (err) {
2636                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2637                 goto err_alloc_queues;
2638         }
2639
2640         err = ixgbe_set_interrupt_capability(adapter);
2641         if (err) {
2642                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2643                 goto err_set_interrupt;
2644         }
2645
2646         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
2647                 "Tx Queue count = %u\n",
2648                 (adapter->num_rx_queues > 1) ? "Enabled" :
2649                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2650
2651         set_bit(__IXGBE_DOWN, &adapter->state);
2652
2653         return 0;
2654
2655 err_set_interrupt:
2656         kfree(adapter->tx_ring);
2657         kfree(adapter->rx_ring);
2658 err_alloc_queues:
2659         return err;
2660 }
2661
2662 /**
2663  * ixgbe_sfp_timer - worker thread to find a missing module
2664  * @data: pointer to our adapter struct
2665  **/
2666 static void ixgbe_sfp_timer(unsigned long data)
2667 {
2668         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
2669
2670         /* Do the sfp_timer outside of interrupt context due to the
2671          * delays that sfp+ detection requires
2672          */
2673         schedule_work(&adapter->sfp_task);
2674 }
2675
2676 /**
2677  * ixgbe_sfp_task - worker thread to find a missing module
2678  * @work: pointer to work_struct containing our data
2679  **/
2680 static void ixgbe_sfp_task(struct work_struct *work)
2681 {
2682         struct ixgbe_adapter *adapter = container_of(work,
2683                                                      struct ixgbe_adapter,
2684                                                      sfp_task);
2685         struct ixgbe_hw *hw = &adapter->hw;
2686
2687         if ((hw->phy.type == ixgbe_phy_nl) &&
2688             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
2689                 s32 ret = hw->phy.ops.identify_sfp(hw);
2690                 if (ret)
2691                         goto reschedule;
2692                 ret = hw->phy.ops.reset(hw);
2693                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2694                         DPRINTK(PROBE, ERR, "failed to initialize because an "
2695                                 "unsupported SFP+ module type was detected.\n"
2696                                 "Reload the driver after installing a "
2697                                 "supported module.\n");
2698                         unregister_netdev(adapter->netdev);
2699                 } else {
2700                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
2701                                 hw->phy.sfp_type);
2702                 }
2703                 /* don't need this routine any more */
2704                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
2705         }
2706         return;
2707 reschedule:
2708         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
2709                 mod_timer(&adapter->sfp_timer,
2710                           round_jiffies(jiffies + (2 * HZ)));
2711 }
2712
2713 /**
2714  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2715  * @adapter: board private structure to initialize
2716  *
2717  * ixgbe_sw_init initializes the Adapter private data structure.
2718  * Fields are initialized based on PCI device information and
2719  * OS network device settings (MTU size).
2720  **/
2721 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2722 {
2723         struct ixgbe_hw *hw = &adapter->hw;
2724         struct pci_dev *pdev = adapter->pdev;
2725         unsigned int rss;
2726 #ifdef CONFIG_IXGBE_DCB
2727         int j;
2728         struct tc_configuration *tc;
2729 #endif
2730
2731         /* PCI config space info */
2732
2733         hw->vendor_id = pdev->vendor;
2734         hw->device_id = pdev->device;
2735         hw->revision_id = pdev->revision;
2736         hw->subsystem_vendor_id = pdev->subsystem_vendor;
2737         hw->subsystem_device_id = pdev->subsystem_device;
2738
2739         /* Set capability flags */
2740         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2741         adapter->ring_feature[RING_F_RSS].indices = rss;
2742         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2743         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
2744
2745 #ifdef CONFIG_IXGBE_DCB
2746         /* Configure DCB traffic classes */
2747         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
2748                 tc = &adapter->dcb_cfg.tc_config[j];
2749                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
2750                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
2751                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
2752                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
2753                 tc->dcb_pfc = pfc_disabled;
2754         }
2755         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
2756         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
2757         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
2758         adapter->dcb_cfg.round_robin_enable = false;
2759         adapter->dcb_set_bitmap = 0x00;
2760         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
2761                            adapter->ring_feature[RING_F_DCB].indices);
2762
2763 #endif
2764         if (hw->mac.ops.get_media_type &&
2765             (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper))
2766                 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
2767
2768         /* default flow control settings */
2769         hw->fc.original_type = ixgbe_fc_none;
2770         hw->fc.type = ixgbe_fc_none;
2771         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
2772         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
2773         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
2774         hw->fc.send_xon = true;
2775
2776         /* select 10G link by default */
2777         hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
2778
2779         /* enable itr by default in dynamic mode */
2780         adapter->itr_setting = 1;
2781         adapter->eitr_param = 20000;
2782
2783         /* set defaults for eitr in MegaBytes */
2784         adapter->eitr_low = 10;
2785         adapter->eitr_high = 20;
2786
2787         /* set default ring sizes */
2788         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
2789         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
2790
2791         /* initialize eeprom parameters */
2792         if (ixgbe_init_eeprom_params_generic(hw)) {
2793                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2794                 return -EIO;
2795         }
2796
2797         /* enable rx csum by default */
2798         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2799
2800         set_bit(__IXGBE_DOWN, &adapter->state);
2801
2802         return 0;
2803 }
2804
2805 /**
2806  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2807  * @adapter: board private structure
2808  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
2809  *
2810  * Return 0 on success, negative on failure
2811  **/
2812 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
2813                              struct ixgbe_ring *tx_ring)
2814 {
2815         struct pci_dev *pdev = adapter->pdev;
2816         int size;
2817
2818         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2819         tx_ring->tx_buffer_info = vmalloc(size);
2820         if (!tx_ring->tx_buffer_info)
2821                 goto err;
2822         memset(tx_ring->tx_buffer_info, 0, size);
2823
2824         /* round up to nearest 4K */
2825         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc) +
2826                         sizeof(u32);
2827         tx_ring->size = ALIGN(tx_ring->size, 4096);
2828
2829         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2830                                              &tx_ring->dma);
2831         if (!tx_ring->desc)
2832                 goto err;
2833
2834         tx_ring->next_to_use = 0;
2835         tx_ring->next_to_clean = 0;
2836         tx_ring->work_limit = tx_ring->count;
2837         return 0;
2838
2839 err:
2840         vfree(tx_ring->tx_buffer_info);
2841         tx_ring->tx_buffer_info = NULL;
2842         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
2843                             "descriptor ring\n");
2844         return -ENOMEM;
2845 }
2846
2847 /**
2848  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
2849  * @adapter: board private structure
2850  *
2851  * If this function returns with an error, then it's possible one or
2852  * more of the rings is populated (while the rest are not).  It is the
2853  * callers duty to clean those orphaned rings.
2854  *
2855  * Return 0 on success, negative on failure
2856  **/
2857 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2858 {
2859         int i, err = 0;
2860
2861         for (i = 0; i < adapter->num_tx_queues; i++) {
2862                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2863                 if (!err)
2864                         continue;
2865                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
2866                 break;
2867         }
2868
2869         return err;
2870 }
2871
2872 /**
2873  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2874  * @adapter: board private structure
2875  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
2876  *
2877  * Returns 0 on success, negative on failure
2878  **/
2879 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
2880                              struct ixgbe_ring *rx_ring)
2881 {
2882         struct pci_dev *pdev = adapter->pdev;
2883         int size;
2884
2885         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2886         rx_ring->rx_buffer_info = vmalloc(size);
2887         if (!rx_ring->rx_buffer_info) {
2888                 DPRINTK(PROBE, ERR,
2889                         "vmalloc allocation failed for the rx desc ring\n");
2890                 goto alloc_failed;
2891         }
2892         memset(rx_ring->rx_buffer_info, 0, size);
2893
2894         /* Round up to nearest 4K */
2895         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2896         rx_ring->size = ALIGN(rx_ring->size, 4096);
2897
2898         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
2899
2900         if (!rx_ring->desc) {
2901                 DPRINTK(PROBE, ERR,
2902                         "Memory allocation failed for the rx desc ring\n");
2903                 vfree(rx_ring->rx_buffer_info);
2904                 goto alloc_failed;
2905         }
2906
2907         rx_ring->next_to_clean = 0;
2908         rx_ring->next_to_use = 0;
2909
2910         return 0;
2911
2912 alloc_failed:
2913         return -ENOMEM;
2914 }
2915
2916 /**
2917  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
2918  * @adapter: board private structure
2919  *
2920  * If this function returns with an error, then it's possible one or
2921  * more of the rings is populated (while the rest are not).  It is the
2922  * callers duty to clean those orphaned rings.
2923  *
2924  * Return 0 on success, negative on failure
2925  **/
2926
2927 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2928 {
2929         int i, err = 0;
2930
2931         for (i = 0; i < adapter->num_rx_queues; i++) {
2932                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2933                 if (!err)
2934                         continue;
2935                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
2936                 break;
2937         }
2938
2939         return err;
2940 }
2941
2942 /**
2943  * ixgbe_free_tx_resources - Free Tx Resources per Queue
2944  * @adapter: board private structure
2945  * @tx_ring: Tx descriptor ring for a specific queue
2946  *
2947  * Free all transmit software resources
2948  **/
2949 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
2950                              struct ixgbe_ring *tx_ring)
2951 {
2952         struct pci_dev *pdev = adapter->pdev;
2953
2954         ixgbe_clean_tx_ring(adapter, tx_ring);
2955
2956         vfree(tx_ring->tx_buffer_info);
2957         tx_ring->tx_buffer_info = NULL;
2958
2959         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2960
2961         tx_ring->desc = NULL;
2962 }
2963
2964 /**
2965  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
2966  * @adapter: board private structure
2967  *
2968  * Free all transmit software resources
2969  **/
2970 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
2971 {
2972         int i;
2973
2974         for (i = 0; i < adapter->num_tx_queues; i++)
2975                 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
2976 }
2977
2978 /**
2979  * ixgbe_free_rx_resources - Free Rx Resources
2980  * @adapter: board private structure
2981  * @rx_ring: ring to clean the resources from
2982  *
2983  * Free all receive software resources
2984  **/
2985 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
2986                              struct ixgbe_ring *rx_ring)
2987 {
2988         struct pci_dev *pdev = adapter->pdev;
2989
2990         ixgbe_clean_rx_ring(adapter, rx_ring);
2991
2992         vfree(rx_ring->rx_buffer_info);
2993         rx_ring->rx_buffer_info = NULL;
2994
2995         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2996
2997         rx_ring->desc = NULL;
2998 }
2999
3000 /**
3001  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3002  * @adapter: board private structure
3003  *
3004  * Free all receive software resources
3005  **/
3006 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3007 {
3008         int i;
3009
3010         for (i = 0; i < adapter->num_rx_queues; i++)
3011                 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
3012 }
3013
3014 /**
3015  * ixgbe_change_mtu - Change the Maximum Transfer Unit
3016  * @netdev: network interface device structure
3017  * @new_mtu: new value for maximum frame size
3018  *
3019  * Returns 0 on success, negative on failure
3020  **/
3021 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3022 {
3023         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3024         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3025
3026         /* MTU < 68 is an error and causes problems on some kernels */
3027         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
3028                 return -EINVAL;
3029
3030         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
3031                 netdev->mtu, new_mtu);
3032         /* must set new MTU before calling down or up */
3033         netdev->mtu = new_mtu;
3034
3035         if (netif_running(netdev))
3036                 ixgbe_reinit_locked(adapter);
3037
3038         return 0;
3039 }
3040
3041 /**
3042  * ixgbe_open - Called when a network interface is made active
3043  * @netdev: network interface device structure
3044  *
3045  * Returns 0 on success, negative value on failure
3046  *
3047  * The open entry point is called when a network interface is made
3048  * active by the system (IFF_UP).  At this point all resources needed
3049  * for transmit and receive operations are allocated, the interrupt
3050  * handler is registered with the OS, the watchdog timer is started,
3051  * and the stack is notified that the interface is ready.
3052  **/
3053 static int ixgbe_open(struct net_device *netdev)
3054 {
3055         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3056         int err;
3057
3058         /* disallow open during test */
3059         if (test_bit(__IXGBE_TESTING, &adapter->state))
3060                 return -EBUSY;
3061
3062         /* allocate transmit descriptors */
3063         err = ixgbe_setup_all_tx_resources(adapter);
3064         if (err)
3065                 goto err_setup_tx;
3066
3067         /* allocate receive descriptors */
3068         err = ixgbe_setup_all_rx_resources(adapter);
3069         if (err)
3070                 goto err_setup_rx;
3071
3072         ixgbe_configure(adapter);
3073
3074         err = ixgbe_request_irq(adapter);
3075         if (err)
3076                 goto err_req_irq;
3077
3078         err = ixgbe_up_complete(adapter);
3079         if (err)
3080                 goto err_up;
3081
3082         netif_tx_start_all_queues(netdev);
3083
3084         return 0;
3085
3086 err_up:
3087         ixgbe_release_hw_control(adapter);
3088         ixgbe_free_irq(adapter);
3089 err_req_irq:
3090         ixgbe_free_all_rx_resources(adapter);
3091 err_setup_rx:
3092         ixgbe_free_all_tx_resources(adapter);
3093 err_setup_tx:
3094         ixgbe_reset(adapter);
3095
3096         return err;
3097 }
3098
3099 /**
3100  * ixgbe_close - Disables a network interface
3101  * @netdev: network interface device structure
3102  *
3103  * Returns 0, this is not allowed to fail
3104  *
3105  * The close entry point is called when an interface is de-activated
3106  * by the OS.  The hardware is still under the drivers control, but
3107  * needs to be disabled.  A global MAC reset is issued to stop the
3108  * hardware, and all transmit and receive resources are freed.
3109  **/
3110 static int ixgbe_close(struct net_device *netdev)
3111 {
3112         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3113
3114         ixgbe_down(adapter);
3115         ixgbe_free_irq(adapter);
3116
3117         ixgbe_free_all_tx_resources(adapter);
3118         ixgbe_free_all_rx_resources(adapter);
3119
3120         ixgbe_release_hw_control(adapter);
3121
3122         return 0;
3123 }
3124
3125 /**
3126  * ixgbe_napi_add_all - prep napi structs for use
3127  * @adapter: private struct
3128  * helper function to napi_add each possible q_vector->napi
3129  */
3130 void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
3131 {
3132         int q_idx, q_vectors;
3133         struct net_device *netdev = adapter->netdev;
3134         int (*poll)(struct napi_struct *, int);
3135
3136         /* check if we already have our netdev->napi_list populated */
3137         if (&netdev->napi_list != netdev->napi_list.next)
3138                 return;
3139
3140         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3141                 poll = &ixgbe_clean_rxonly;
3142                 /* Only enable as many vectors as we have rx queues. */
3143                 q_vectors = adapter->num_rx_queues;
3144         } else {
3145                 poll = &ixgbe_poll;
3146                 /* only one q_vector for legacy modes */
3147                 q_vectors = 1;
3148         }
3149
3150         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3151                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3152                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3153         }
3154 }
3155
3156 void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
3157 {
3158         int q_idx;
3159         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3160
3161         /* legacy and MSI only use one vector */
3162         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3163                 q_vectors = 1;
3164
3165         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3166                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3167                 if (!q_vector->rxr_count)
3168                         continue;
3169                 netif_napi_del(&q_vector->napi);
3170         }
3171 }
3172
3173 #ifdef CONFIG_PM
3174 static int ixgbe_resume(struct pci_dev *pdev)
3175 {
3176         struct net_device *netdev = pci_get_drvdata(pdev);
3177         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3178         u32 err;
3179
3180         pci_set_power_state(pdev, PCI_D0);
3181         pci_restore_state(pdev);
3182         err = pci_enable_device(pdev);
3183         if (err) {
3184                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
3185                                 "suspend\n");
3186                 return err;
3187         }
3188         pci_set_master(pdev);
3189
3190         pci_enable_wake(pdev, PCI_D3hot, 0);
3191         pci_enable_wake(pdev, PCI_D3cold, 0);
3192
3193         err = ixgbe_init_interrupt_scheme(adapter);
3194         if (err) {
3195                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3196                                 "device\n");
3197                 return err;
3198         }
3199
3200         ixgbe_napi_add_all(adapter);
3201         ixgbe_reset(adapter);
3202
3203         if (netif_running(netdev)) {
3204                 err = ixgbe_open(adapter->netdev);
3205                 if (err)
3206                         return err;
3207         }
3208
3209         netif_device_attach(netdev);
3210
3211         return 0;
3212 }
3213
3214 #endif /* CONFIG_PM */
3215 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3216 {
3217         struct net_device *netdev = pci_get_drvdata(pdev);
3218         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3219 #ifdef CONFIG_PM
3220         int retval = 0;
3221 #endif
3222
3223         netif_device_detach(netdev);
3224
3225         if (netif_running(netdev)) {
3226                 ixgbe_down(adapter);
3227                 ixgbe_free_irq(adapter);
3228                 ixgbe_free_all_tx_resources(adapter);
3229                 ixgbe_free_all_rx_resources(adapter);
3230         }
3231         ixgbe_reset_interrupt_capability(adapter);
3232         ixgbe_napi_del_all(adapter);
3233         INIT_LIST_HEAD(&netdev->napi_list);
3234         kfree(adapter->tx_ring);
3235         kfree(adapter->rx_ring);
3236
3237 #ifdef CONFIG_PM
3238         retval = pci_save_state(pdev);
3239         if (retval)
3240                 return retval;
3241 #endif
3242
3243         pci_enable_wake(pdev, PCI_D3hot, 0);
3244         pci_enable_wake(pdev, PCI_D3cold, 0);
3245
3246         ixgbe_release_hw_control(adapter);
3247
3248         pci_disable_device(pdev);
3249
3250         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3251
3252         return 0;
3253 }
3254
3255 static void ixgbe_shutdown(struct pci_dev *pdev)
3256 {
3257         ixgbe_suspend(pdev, PMSG_SUSPEND);
3258 }
3259
3260 /**
3261  * ixgbe_update_stats - Update the board statistics counters.
3262  * @adapter: board private structure
3263  **/
3264 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3265 {
3266         struct ixgbe_hw *hw = &adapter->hw;
3267         u64 total_mpc = 0;
3268         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
3269
3270         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3271         for (i = 0; i < 8; i++) {
3272                 /* for packet buffers not used, the register should read 0 */
3273                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3274                 missed_rx += mpc;
3275                 adapter->stats.mpc[i] += mpc;
3276                 total_mpc += adapter->stats.mpc[i];
3277                 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3278                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3279                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3280                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3281                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
3282                 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3283                                                             IXGBE_PXONRXC(i));
3284                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3285                                                             IXGBE_PXONTXC(i));
3286                 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3287                                                             IXGBE_PXOFFRXC(i));
3288                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
3289                                                             IXGBE_PXOFFTXC(i));
3290         }
3291         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3292         /* work around hardware counting issue */
3293         adapter->stats.gprc -= missed_rx;
3294
3295         /* 82598 hardware only has a 32 bit counter in the high register */
3296         adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3297         adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3298         adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3299         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3300         adapter->stats.bprc += bprc;
3301         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3302         adapter->stats.mprc -= bprc;
3303         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3304         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3305         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3306         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3307         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3308         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3309         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3310         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3311         adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3312         adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3313         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3314         adapter->stats.lxontxc += lxon;
3315         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3316         adapter->stats.lxofftxc += lxoff;
3317         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3318         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
3319         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3320         /*
3321          * 82598 errata - tx of flow control packets is included in tx counters
3322          */
3323         xon_off_tot = lxon + lxoff;
3324         adapter->stats.gptc -= xon_off_tot;
3325         adapter->stats.mptc -= xon_off_tot;
3326         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
3327         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3328         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3329         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3330         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3331         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3332         adapter->stats.ptc64 -= xon_off_tot;
3333         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3334         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3335         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3336         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3337         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3338         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3339
3340         /* Fill out the OS statistics structure */
3341         adapter->net_stats.multicast = adapter->stats.mprc;
3342
3343         /* Rx Errors */
3344         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
3345                                        adapter->stats.rlec;
3346         adapter->net_stats.rx_dropped = 0;
3347         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3348         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3349         adapter->net_stats.rx_missed_errors = total_mpc;
3350 }
3351
3352 /**
3353  * ixgbe_watchdog - Timer Call-back
3354  * @data: pointer to adapter cast into an unsigned long
3355  **/
3356 static void ixgbe_watchdog(unsigned long data)
3357 {
3358         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3359         struct ixgbe_hw *hw = &adapter->hw;
3360
3361         /* Do the watchdog outside of interrupt context due to the lovely
3362          * delays that some of the newer hardware requires */
3363         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3364                 /* Cause software interrupt to ensure rx rings are cleaned */
3365                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3366                         u32 eics =
3367                          (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
3368                         IXGBE_WRITE_REG(hw, IXGBE_EICS, eics);
3369                 } else {
3370                         /* For legacy and MSI interrupts don't set any bits that
3371                          * are enabled for EIAM, because this operation would
3372                          * set *both* EIMS and EICS for any bit in EIAM */
3373                         IXGBE_WRITE_REG(hw, IXGBE_EICS,
3374                                     (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3375                 }
3376                 /* Reset the timer */
3377                 mod_timer(&adapter->watchdog_timer,
3378                           round_jiffies(jiffies + 2 * HZ));
3379         }
3380
3381         schedule_work(&adapter->watchdog_task);
3382 }
3383
3384 /**
3385  * ixgbe_watchdog_task - worker thread to bring link up
3386  * @work: pointer to work_struct containing our data
3387  **/
3388 static void ixgbe_watchdog_task(struct work_struct *work)
3389 {
3390         struct ixgbe_adapter *adapter = container_of(work,
3391                                                      struct ixgbe_adapter,
3392                                                      watchdog_task);
3393         struct net_device *netdev = adapter->netdev;
3394         struct ixgbe_hw *hw = &adapter->hw;
3395         u32 link_speed = adapter->link_speed;
3396         bool link_up = adapter->link_up;
3397
3398         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
3399
3400         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3401                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3402                 if (link_up ||
3403                     time_after(jiffies, (adapter->link_check_timeout +
3404                                          IXGBE_TRY_LINK_TIMEOUT))) {
3405                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
3406                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3407                 }
3408                 adapter->link_up = link_up;
3409                 adapter->link_speed = link_speed;
3410         }
3411
3412         if (link_up) {
3413                 if (!netif_carrier_ok(netdev)) {
3414                         u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3415                         u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
3416 #define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
3417 #define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
3418                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
3419                                "Flow Control: %s\n",
3420                                netdev->name,
3421                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3422                                 "10 Gbps" :
3423                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
3424                                  "1 Gbps" : "unknown speed")),
3425                                ((FLOW_RX && FLOW_TX) ? "RX/TX" :
3426                                 (FLOW_RX ? "RX" :
3427                                 (FLOW_TX ? "TX" : "None"))));
3428
3429                         netif_carrier_on(netdev);
3430                 } else {
3431                         /* Force detection of hung controller */
3432                         adapter->detect_tx_hung = true;
3433                 }
3434         } else {
3435                 adapter->link_up = false;
3436                 adapter->link_speed = 0;
3437                 if (netif_carrier_ok(netdev)) {
3438                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
3439                                netdev->name);
3440                         netif_carrier_off(netdev);
3441                 }
3442         }
3443
3444         ixgbe_update_stats(adapter);
3445         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
3446 }
3447
3448 static int ixgbe_tso(struct ixgbe_adapter *adapter,
3449                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
3450                      u32 tx_flags, u8 *hdr_len)
3451 {
3452         struct ixgbe_adv_tx_context_desc *context_desc;
3453         unsigned int i;
3454         int err;
3455         struct ixgbe_tx_buffer *tx_buffer_info;
3456         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
3457         u32 mss_l4len_idx, l4len;
3458
3459         if (skb_is_gso(skb)) {
3460                 if (skb_header_cloned(skb)) {
3461                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3462                         if (err)
3463                                 return err;
3464                 }
3465                 l4len = tcp_hdrlen(skb);
3466                 *hdr_len += l4len;
3467
3468                 if (skb->protocol == htons(ETH_P_IP)) {
3469                         struct iphdr *iph = ip_hdr(skb);
3470                         iph->tot_len = 0;
3471                         iph->check = 0;
3472                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3473                                                                  iph->daddr, 0,
3474                                                                  IPPROTO_TCP,
3475                                                                  0);
3476                         adapter->hw_tso_ctxt++;
3477                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3478                         ipv6_hdr(skb)->payload_len = 0;
3479                         tcp_hdr(skb)->check =
3480                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3481                                              &ipv6_hdr(skb)->daddr,
3482                                              0, IPPROTO_TCP, 0);
3483                         adapter->hw_tso6_ctxt++;
3484                 }
3485
3486                 i = tx_ring->next_to_use;
3487
3488                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3489                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3490
3491                 /* VLAN MACLEN IPLEN */
3492                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3493                         vlan_macip_lens |=
3494                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3495                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
3496                                     IXGBE_ADVTXD_MACLEN_SHIFT);
3497                 *hdr_len += skb_network_offset(skb);
3498                 vlan_macip_lens |=
3499                     (skb_transport_header(skb) - skb_network_header(skb));
3500                 *hdr_len +=
3501                     (skb_transport_header(skb) - skb_network_header(skb));
3502                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3503                 context_desc->seqnum_seed = 0;
3504
3505                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3506                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
3507                                    IXGBE_ADVTXD_DTYP_CTXT);
3508
3509                 if (skb->protocol == htons(ETH_P_IP))
3510                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3511                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3512                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3513
3514                 /* MSS L4LEN IDX */
3515                 mss_l4len_idx =
3516                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3517                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
3518                 /* use index 1 for TSO */
3519                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
3520                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3521
3522                 tx_buffer_info->time_stamp = jiffies;
3523                 tx_buffer_info->next_to_watch = i;
3524
3525                 i++;
3526                 if (i == tx_ring->count)
3527                         i = 0;
3528                 tx_ring->next_to_use = i;
3529
3530                 return true;
3531         }
3532         return false;
3533 }
3534
3535 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
3536                           struct ixgbe_ring *tx_ring,
3537                           struct sk_buff *skb, u32 tx_flags)
3538 {
3539         struct ixgbe_adv_tx_context_desc *context_desc;
3540         unsigned int i;
3541         struct ixgbe_tx_buffer *tx_buffer_info;
3542         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3543
3544         if (skb->ip_summed == CHECKSUM_PARTIAL ||
3545             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
3546                 i = tx_ring->next_to_use;
3547                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3548                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3549
3550                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3551                         vlan_macip_lens |=
3552                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3553                 vlan_macip_lens |= (skb_network_offset(skb) <<
3554                                     IXGBE_ADVTXD_MACLEN_SHIFT);
3555                 if (skb->ip_summed == CHECKSUM_PARTIAL)
3556                         vlan_macip_lens |= (skb_transport_header(skb) -
3557                                             skb_network_header(skb));
3558
3559                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3560                 context_desc->seqnum_seed = 0;
3561
3562                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
3563                                     IXGBE_ADVTXD_DTYP_CTXT);
3564
3565                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3566                         switch (skb->protocol) {
3567                         case __constant_htons(ETH_P_IP):
3568                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3569                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3570                                         type_tucmd_mlhl |=
3571                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3572                                 break;
3573                         case __constant_htons(ETH_P_IPV6):
3574                                 /* XXX what about other V6 headers?? */
3575                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3576                                         type_tucmd_mlhl |=
3577                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3578                                 break;
3579                         default:
3580                                 if (unlikely(net_ratelimit())) {
3581                                         DPRINTK(PROBE, WARNING,
3582                                          "partial checksum but proto=%x!\n",
3583                                          skb->protocol);
3584                                 }
3585                                 break;
3586                         }
3587                 }
3588
3589                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3590                 /* use index zero for tx checksum offload */
3591                 context_desc->mss_l4len_idx = 0;
3592
3593                 tx_buffer_info->time_stamp = jiffies;
3594                 tx_buffer_info->next_to_watch = i;
3595
3596                 adapter->hw_csum_tx_good++;
3597                 i++;
3598                 if (i == tx_ring->count)
3599                         i = 0;
3600                 tx_ring->next_to_use = i;
3601
3602                 return true;
3603         }
3604
3605         return false;
3606 }
3607
3608 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
3609                         struct ixgbe_ring *tx_ring,
3610                         struct sk_buff *skb, unsigned int first)
3611 {
3612         struct ixgbe_tx_buffer *tx_buffer_info;
3613         unsigned int len = skb->len;
3614         unsigned int offset = 0, size, count = 0, i;
3615         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3616         unsigned int f;
3617
3618         len -= skb->data_len;
3619
3620         i = tx_ring->next_to_use;
3621
3622         while (len) {
3623                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3624                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3625
3626                 tx_buffer_info->length = size;
3627                 tx_buffer_info->dma = pci_map_single(adapter->pdev,
3628                                                      skb->data + offset,
3629                                                      size, PCI_DMA_TODEVICE);
3630                 tx_buffer_info->time_stamp = jiffies;
3631                 tx_buffer_info->next_to_watch = i;
3632
3633                 len -= size;
3634                 offset += size;
3635                 count++;
3636                 i++;
3637                 if (i == tx_ring->count)
3638                         i = 0;
3639         }
3640
3641         for (f = 0; f < nr_frags; f++) {
3642                 struct skb_frag_struct *frag;
3643
3644                 frag = &skb_shinfo(skb)->frags[f];
3645                 len = frag->size;
3646                 offset = frag->page_offset;
3647
3648                 while (len) {
3649                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
3650                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3651
3652                         tx_buffer_info->length = size;
3653                         tx_buffer_info->dma = pci_map_page(adapter->pdev,
3654                                                            frag->page,
3655                                                            offset,
3656                                                            size,
3657                                                            PCI_DMA_TODEVICE);
3658                         tx_buffer_info->time_stamp = jiffies;
3659                         tx_buffer_info->next_to_watch = i;
3660
3661                         len -= size;
3662                         offset += size;
3663                         count++;
3664                         i++;
3665                         if (i == tx_ring->count)
3666                                 i = 0;
3667                 }
3668         }
3669         if (i == 0)
3670                 i = tx_ring->count - 1;
3671         else
3672                 i = i - 1;
3673         tx_ring->tx_buffer_info[i].skb = skb;
3674         tx_ring->tx_buffer_info[first].next_to_watch = i;
3675
3676         return count;
3677 }
3678
3679 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
3680                            struct ixgbe_ring *tx_ring,
3681                            int tx_flags, int count, u32 paylen, u8 hdr_len)
3682 {
3683         union ixgbe_adv_tx_desc *tx_desc = NULL;
3684         struct ixgbe_tx_buffer *tx_buffer_info;
3685         u32 olinfo_status = 0, cmd_type_len = 0;
3686         unsigned int i;
3687         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3688
3689         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3690
3691         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3692
3693         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3694                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3695
3696         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3697                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3698
3699                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3700                                  IXGBE_ADVTXD_POPTS_SHIFT;
3701
3702                 /* use index 1 context for tso */
3703                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
3704                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3705                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
3706                                          IXGBE_ADVTXD_POPTS_SHIFT;
3707
3708         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3709                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3710                                  IXGBE_ADVTXD_POPTS_SHIFT;
3711
3712         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3713
3714         i = tx_ring->next_to_use;
3715         while (count--) {
3716                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3717                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3718                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3719                 tx_desc->read.cmd_type_len =
3720                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
3721                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3722                 i++;
3723                 if (i == tx_ring->count)
3724                         i = 0;
3725         }
3726
3727         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3728
3729         /*
3730          * Force memory writes to complete before letting h/w
3731          * know there are new descriptors to fetch.  (Only
3732          * applicable for weak-ordered memory model archs,
3733          * such as IA-64).
3734          */
3735         wmb();
3736
3737         tx_ring->next_to_use = i;
3738         writel(i, adapter->hw.hw_addr + tx_ring->tail);
3739 }
3740
3741 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
3742                                  struct ixgbe_ring *tx_ring, int size)
3743 {
3744         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3745
3746         netif_stop_subqueue(netdev, tx_ring->queue_index);
3747         /* Herbert's original patch had:
3748          *  smp_mb__after_netif_stop_queue();
3749          * but since that doesn't exist yet, just open code it. */
3750         smp_mb();
3751
3752         /* We need to check again in a case another CPU has just
3753          * made room available. */
3754         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3755                 return -EBUSY;
3756
3757         /* A reprieve! - use start_queue because it doesn't call schedule */
3758         netif_start_subqueue(netdev, tx_ring->queue_index);
3759         ++adapter->restart_queue;
3760         return 0;
3761 }
3762
3763 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
3764                               struct ixgbe_ring *tx_ring, int size)
3765 {
3766         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3767                 return 0;
3768         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
3769 }
3770
3771 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3772 {
3773         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3774         struct ixgbe_ring *tx_ring;
3775         unsigned int first;
3776         unsigned int tx_flags = 0;
3777         u8 hdr_len = 0;
3778         int r_idx = 0, tso;
3779         int count = 0;
3780         unsigned int f;
3781
3782         r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
3783         tx_ring = &adapter->tx_ring[r_idx];
3784
3785         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3786                 tx_flags |= vlan_tx_tag_get(skb);
3787                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3788                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
3789                         tx_flags |= (skb->queue_mapping << 13);
3790                 }
3791                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3792                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3793         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3794                 tx_flags |= (skb->queue_mapping << 13);
3795                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3796                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3797         }
3798         /* three things can cause us to need a context descriptor */
3799         if (skb_is_gso(skb) ||
3800             (skb->ip_summed == CHECKSUM_PARTIAL) ||
3801             (tx_flags & IXGBE_TX_FLAGS_VLAN))
3802                 count++;
3803
3804         count += TXD_USE_COUNT(skb_headlen(skb));
3805         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
3806                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3807
3808         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
3809                 adapter->tx_busy++;
3810                 return NETDEV_TX_BUSY;
3811         }
3812
3813         if (skb->protocol == htons(ETH_P_IP))
3814                 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3815         first = tx_ring->next_to_use;
3816         tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3817         if (tso < 0) {
3818                 dev_kfree_skb_any(skb);
3819                 return NETDEV_TX_OK;
3820         }
3821
3822         if (tso)
3823                 tx_flags |= IXGBE_TX_FLAGS_TSO;
3824         else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
3825                  (skb->ip_summed == CHECKSUM_PARTIAL))
3826                 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3827
3828         ixgbe_tx_queue(adapter, tx_ring, tx_flags,
3829                        ixgbe_tx_map(adapter, tx_ring, skb, first),
3830                        skb->len, hdr_len);
3831
3832         netdev->trans_start = jiffies;
3833
3834         ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
3835
3836         return NETDEV_TX_OK;
3837 }
3838
3839 /**
3840  * ixgbe_get_stats - Get System Network Statistics
3841  * @netdev: network interface device structure
3842  *
3843  * Returns the address of the device statistics structure.
3844  * The statistics are actually updated from the timer callback.
3845  **/
3846 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
3847 {
3848         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3849
3850         /* only return the current stats */
3851         return &adapter->net_stats;
3852 }
3853
3854 /**
3855  * ixgbe_set_mac - Change the Ethernet Address of the NIC
3856  * @netdev: network interface device structure
3857  * @p: pointer to an address structure
3858  *
3859  * Returns 0 on success, negative on failure
3860  **/
3861 static int ixgbe_set_mac(struct net_device *netdev, void *p)
3862 {
3863         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3864         struct ixgbe_hw *hw = &adapter->hw;
3865         struct sockaddr *addr = p;
3866
3867         if (!is_valid_ether_addr(addr->sa_data))
3868                 return -EADDRNOTAVAIL;
3869
3870         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3871         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3872
3873         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3874
3875         return 0;
3876 }
3877
3878 #ifdef CONFIG_NET_POLL_CONTROLLER
3879 /*
3880  * Polling 'interrupt' - used by things like netconsole to send skbs
3881  * without having to re-enable interrupts. It's not called while
3882  * the interrupt routine is executing.
3883  */
3884 static void ixgbe_netpoll(struct net_device *netdev)
3885 {
3886         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3887
3888         disable_irq(adapter->pdev->irq);
3889         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3890         ixgbe_intr(adapter->pdev->irq, netdev);
3891         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3892         enable_irq(adapter->pdev->irq);
3893 }
3894 #endif
3895
3896 /**
3897  * ixgbe_link_config - set up initial link with default speed and duplex
3898  * @hw: pointer to private hardware struct
3899  *
3900  * Returns 0 on success, negative on failure
3901  **/
3902 static int ixgbe_link_config(struct ixgbe_hw *hw)
3903 {
3904         u32 autoneg = IXGBE_LINK_SPEED_10GB_FULL;
3905
3906         /* must always autoneg for both 1G and 10G link */
3907         hw->mac.autoneg = true;
3908
3909         if ((hw->mac.type == ixgbe_mac_82598EB) &&
3910             (hw->phy.media_type == ixgbe_media_type_copper))
3911                 autoneg = IXGBE_LINK_SPEED_82598_AUTONEG;
3912
3913         return hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
3914 }
3915
3916 static const struct net_device_ops ixgbe_netdev_ops = {
3917         .ndo_open               = ixgbe_open,
3918         .ndo_stop               = ixgbe_close,
3919         .ndo_start_xmit         = ixgbe_xmit_frame,
3920         .ndo_get_stats          = ixgbe_get_stats,
3921         .ndo_set_multicast_list = ixgbe_set_rx_mode,
3922         .ndo_validate_addr      = eth_validate_addr,
3923         .ndo_set_mac_address    = ixgbe_set_mac,
3924         .ndo_change_mtu         = ixgbe_change_mtu,
3925         .ndo_tx_timeout         = ixgbe_tx_timeout,
3926         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
3927         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
3928         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
3929 #ifdef CONFIG_NET_POLL_CONTROLLER
3930         .ndo_poll_controller    = ixgbe_netpoll,
3931 #endif
3932 };
3933
3934 /**
3935  * ixgbe_probe - Device Initialization Routine
3936  * @pdev: PCI device information struct
3937  * @ent: entry in ixgbe_pci_tbl
3938  *
3939  * Returns 0 on success, negative on failure
3940  *
3941  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3942  * The OS initialization, configuring of the adapter private structure,
3943  * and a hardware reset occur.
3944  **/
3945 static int __devinit ixgbe_probe(struct pci_dev *pdev,
3946                                  const struct pci_device_id *ent)
3947 {
3948         struct net_device *netdev;
3949         struct ixgbe_adapter *adapter = NULL;
3950         struct ixgbe_hw *hw;
3951         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
3952         static int cards_found;
3953         int i, err, pci_using_dac;
3954         u16 link_status, link_speed, link_width;
3955         u32 part_num, eec;
3956
3957         err = pci_enable_device(pdev);
3958         if (err)
3959                 return err;
3960
3961         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3962             !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
3963                 pci_using_dac = 1;
3964         } else {
3965                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3966                 if (err) {
3967                         err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3968                         if (err) {
3969                                 dev_err(&pdev->dev, "No usable DMA "
3970                                         "configuration, aborting\n");
3971                                 goto err_dma;
3972                         }
3973                 }
3974                 pci_using_dac = 0;
3975         }
3976
3977         err = pci_request_regions(pdev, ixgbe_driver_name);
3978         if (err) {
3979                 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3980                 goto err_pci_reg;
3981         }
3982
3983         err = pci_enable_pcie_error_reporting(pdev);
3984         if (err) {
3985                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
3986                                     "0x%x\n", err);
3987                 /* non-fatal, continue */
3988         }
3989
3990         pci_set_master(pdev);
3991         pci_save_state(pdev);
3992
3993         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
3994         if (!netdev) {
3995                 err = -ENOMEM;
3996                 goto err_alloc_etherdev;
3997         }
3998
3999         SET_NETDEV_DEV(netdev, &pdev->dev);
4000
4001         pci_set_drvdata(pdev, netdev);
4002         adapter = netdev_priv(netdev);
4003
4004         adapter->netdev = netdev;
4005         adapter->pdev = pdev;
4006         hw = &adapter->hw;
4007         hw->back = adapter;
4008         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4009
4010         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4011                               pci_resource_len(pdev, 0));
4012         if (!hw->hw_addr) {
4013                 err = -EIO;
4014                 goto err_ioremap;
4015         }
4016
4017         for (i = 1; i <= 5; i++) {
4018                 if (pci_resource_len(pdev, i) == 0)
4019                         continue;
4020         }
4021
4022         netdev->netdev_ops = &ixgbe_netdev_ops;
4023         ixgbe_set_ethtool_ops(netdev);
4024         netdev->watchdog_timeo = 5 * HZ;
4025         strcpy(netdev->name, pci_name(pdev));
4026
4027         adapter->bd_number = cards_found;
4028
4029         /* Setup hw api */
4030         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
4031         hw->mac.type  = ii->mac;
4032
4033         /* EEPROM */
4034         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4035         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4036         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4037         if (!(eec & (1 << 8)))
4038                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4039
4040         /* PHY */
4041         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
4042         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4043
4044         /* set up this timer and work struct before calling get_invariants
4045          * which might start the timer
4046          */
4047         init_timer(&adapter->sfp_timer);
4048         adapter->sfp_timer.function = &ixgbe_sfp_timer;
4049         adapter->sfp_timer.data = (unsigned long) adapter;
4050
4051         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
4052
4053         err = ii->get_invariants(hw);
4054         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4055                 /* start a kernel thread to watch for a module to arrive */
4056                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4057                 mod_timer(&adapter->sfp_timer,
4058                           round_jiffies(jiffies + (2 * HZ)));
4059                 err = 0;
4060         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4061                 DPRINTK(PROBE, ERR, "failed to load because an "
4062                         "unsupported SFP+ module type was detected.\n");
4063                 goto err_hw_init;
4064         } else if (err) {
4065                 goto err_hw_init;
4066         }
4067
4068         /* setup the private structure */
4069         err = ixgbe_sw_init(adapter);
4070         if (err)
4071                 goto err_sw_init;
4072
4073         /* reset_hw fills in the perm_addr as well */
4074         err = hw->mac.ops.reset_hw(hw);
4075         if (err) {
4076                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4077                 goto err_sw_init;
4078         }
4079
4080         netdev->features = NETIF_F_SG |
4081                            NETIF_F_IP_CSUM |
4082                            NETIF_F_HW_VLAN_TX |
4083                            NETIF_F_HW_VLAN_RX |
4084                            NETIF_F_HW_VLAN_FILTER;
4085
4086         netdev->features |= NETIF_F_IPV6_CSUM;
4087         netdev->features |= NETIF_F_TSO;
4088         netdev->features |= NETIF_F_TSO6;
4089         netdev->features |= NETIF_F_GRO;
4090
4091         netdev->vlan_features |= NETIF_F_TSO;
4092         netdev->vlan_features |= NETIF_F_TSO6;
4093         netdev->vlan_features |= NETIF_F_IP_CSUM;
4094         netdev->vlan_features |= NETIF_F_SG;
4095
4096         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4097                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4098
4099 #ifdef CONFIG_IXGBE_DCB
4100         netdev->dcbnl_ops = &dcbnl_ops;
4101 #endif
4102
4103         if (pci_using_dac)
4104                 netdev->features |= NETIF_F_HIGHDMA;
4105
4106         /* make sure the EEPROM is good */
4107         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
4108                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4109                 err = -EIO;
4110                 goto err_eeprom;
4111         }
4112
4113         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4114         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4115
4116         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4117                 dev_err(&pdev->dev, "invalid MAC address\n");
4118                 err = -EIO;
4119                 goto err_eeprom;
4120         }
4121
4122         init_timer(&adapter->watchdog_timer);
4123         adapter->watchdog_timer.function = &ixgbe_watchdog;
4124         adapter->watchdog_timer.data = (unsigned long)adapter;
4125
4126         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
4127         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
4128
4129         err = ixgbe_init_interrupt_scheme(adapter);
4130         if (err)
4131                 goto err_sw_init;
4132
4133         /* print bus type/speed/width info */
4134         pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
4135         link_speed = link_status & IXGBE_PCI_LINK_SPEED;
4136         link_width = link_status & IXGBE_PCI_LINK_WIDTH;
4137         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
4138                 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
4139                  (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
4140                  "Unknown"),
4141                 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
4142                  (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
4143                  (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
4144                  (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
4145                  "Unknown"),
4146                 netdev->dev_addr);
4147         ixgbe_read_pba_num_generic(hw, &part_num);
4148         dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
4149                  hw->mac.type, hw->phy.type,
4150                  (part_num >> 8), (part_num & 0xff));
4151
4152         if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
4153                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
4154                          "this card is not sufficient for optimal "
4155                          "performance.\n");
4156                 dev_warn(&pdev->dev, "For optimal performance a x8 "
4157                          "PCI-Express slot is required.\n");
4158         }
4159
4160         /* reset the hardware with the new settings */
4161         hw->mac.ops.start_hw(hw);
4162
4163         /* link_config depends on start_hw being called at least once */
4164         err = ixgbe_link_config(hw);
4165         if (err) {
4166                 dev_err(&pdev->dev, "setup_link_speed FAILED %d\n", err);
4167                 goto err_register;
4168         }
4169
4170         netif_carrier_off(netdev);
4171
4172         strcpy(netdev->name, "eth%d");
4173         err = register_netdev(netdev);
4174         if (err)
4175                 goto err_register;
4176
4177 #ifdef CONFIG_IXGBE_DCA
4178         if (dca_add_requester(&pdev->dev) == 0) {
4179                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
4180                 /* always use CB2 mode, difference is masked
4181                  * in the CB driver */
4182                 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
4183                 ixgbe_setup_dca(adapter);
4184         }
4185 #endif
4186
4187         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
4188         cards_found++;
4189         return 0;
4190
4191 err_register:
4192         ixgbe_release_hw_control(adapter);
4193 err_hw_init:
4194 err_sw_init:
4195         ixgbe_reset_interrupt_capability(adapter);
4196 err_eeprom:
4197         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4198         del_timer_sync(&adapter->sfp_timer);
4199         cancel_work_sync(&adapter->sfp_task);
4200         iounmap(hw->hw_addr);
4201 err_ioremap:
4202         free_netdev(netdev);
4203 err_alloc_etherdev:
4204         pci_release_regions(pdev);
4205 err_pci_reg:
4206 err_dma:
4207         pci_disable_device(pdev);
4208         return err;
4209 }
4210
4211 /**
4212  * ixgbe_remove - Device Removal Routine
4213  * @pdev: PCI device information struct
4214  *
4215  * ixgbe_remove is called by the PCI subsystem to alert the driver
4216  * that it should release a PCI device.  The could be caused by a
4217  * Hot-Plug event, or because the driver is going to be removed from
4218  * memory.
4219  **/
4220 static void __devexit ixgbe_remove(struct pci_dev *pdev)
4221 {
4222         struct net_device *netdev = pci_get_drvdata(pdev);
4223         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4224         int err;
4225
4226         set_bit(__IXGBE_DOWN, &adapter->state);
4227         /* clear the module not found bit to make sure the worker won't
4228          * reschedule
4229          */
4230         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4231         del_timer_sync(&adapter->watchdog_timer);
4232
4233         del_timer_sync(&adapter->sfp_timer);
4234         cancel_work_sync(&adapter->watchdog_task);
4235         cancel_work_sync(&adapter->sfp_task);
4236         flush_scheduled_work();
4237
4238 #ifdef CONFIG_IXGBE_DCA
4239         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4240                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
4241                 dca_remove_requester(&pdev->dev);
4242                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
4243         }
4244
4245 #endif
4246         if (netdev->reg_state == NETREG_REGISTERED)
4247                 unregister_netdev(netdev);
4248
4249         ixgbe_reset_interrupt_capability(adapter);
4250
4251         ixgbe_release_hw_control(adapter);
4252
4253         iounmap(adapter->hw.hw_addr);
4254         pci_release_regions(pdev);
4255
4256         DPRINTK(PROBE, INFO, "complete\n");
4257         kfree(adapter->tx_ring);
4258         kfree(adapter->rx_ring);
4259
4260         free_netdev(netdev);
4261
4262         err = pci_disable_pcie_error_reporting(pdev);
4263         if (err)
4264                 dev_err(&pdev->dev,
4265                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
4266
4267         pci_disable_device(pdev);
4268 }
4269
4270 /**
4271  * ixgbe_io_error_detected - called when PCI error is detected
4272  * @pdev: Pointer to PCI device
4273  * @state: The current pci connection state
4274  *
4275  * This function is called after a PCI bus error affecting
4276  * this device has been detected.
4277  */
4278 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
4279                                                 pci_channel_state_t state)
4280 {
4281         struct net_device *netdev = pci_get_drvdata(pdev);
4282         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4283
4284         netif_device_detach(netdev);
4285
4286         if (netif_running(netdev))
4287                 ixgbe_down(adapter);
4288         pci_disable_device(pdev);
4289
4290         /* Request a slot reset. */
4291         return PCI_ERS_RESULT_NEED_RESET;
4292 }
4293
4294 /**
4295  * ixgbe_io_slot_reset - called after the pci bus has been reset.
4296  * @pdev: Pointer to PCI device
4297  *
4298  * Restart the card from scratch, as if from a cold-boot.
4299  */
4300 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4301 {
4302         struct net_device *netdev = pci_get_drvdata(pdev);
4303         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4304         pci_ers_result_t result;
4305         int err;
4306
4307         if (pci_enable_device(pdev)) {
4308                 DPRINTK(PROBE, ERR,
4309                         "Cannot re-enable PCI device after reset.\n");
4310                 result = PCI_ERS_RESULT_DISCONNECT;
4311         } else {
4312                 pci_set_master(pdev);
4313                 pci_restore_state(pdev);
4314
4315                 pci_enable_wake(pdev, PCI_D3hot, 0);
4316                 pci_enable_wake(pdev, PCI_D3cold, 0);
4317
4318                 ixgbe_reset(adapter);
4319
4320                 result = PCI_ERS_RESULT_RECOVERED;
4321         }
4322
4323         err = pci_cleanup_aer_uncorrect_error_status(pdev);
4324         if (err) {
4325                 dev_err(&pdev->dev,
4326                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
4327                 /* non-fatal, continue */
4328         }
4329
4330         return result;
4331 }
4332
4333 /**
4334  * ixgbe_io_resume - called when traffic can start flowing again.
4335  * @pdev: Pointer to PCI device
4336  *
4337  * This callback is called when the error recovery driver tells us that
4338  * its OK to resume normal operation.
4339  */
4340 static void ixgbe_io_resume(struct pci_dev *pdev)
4341 {
4342         struct net_device *netdev = pci_get_drvdata(pdev);
4343         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4344
4345         if (netif_running(netdev)) {
4346                 if (ixgbe_up(adapter)) {
4347                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
4348                         return;
4349                 }
4350         }
4351
4352         netif_device_attach(netdev);
4353 }
4354
4355 static struct pci_error_handlers ixgbe_err_handler = {
4356         .error_detected = ixgbe_io_error_detected,
4357         .slot_reset = ixgbe_io_slot_reset,
4358         .resume = ixgbe_io_resume,
4359 };
4360
4361 static struct pci_driver ixgbe_driver = {
4362         .name     = ixgbe_driver_name,
4363         .id_table = ixgbe_pci_tbl,
4364         .probe    = ixgbe_probe,
4365         .remove   = __devexit_p(ixgbe_remove),
4366 #ifdef CONFIG_PM
4367         .suspend  = ixgbe_suspend,
4368         .resume   = ixgbe_resume,
4369 #endif
4370         .shutdown = ixgbe_shutdown,
4371         .err_handler = &ixgbe_err_handler
4372 };
4373
4374 /**
4375  * ixgbe_init_module - Driver Registration Routine
4376  *
4377  * ixgbe_init_module is the first routine called when the driver is
4378  * loaded. All it does is register with the PCI subsystem.
4379  **/
4380 static int __init ixgbe_init_module(void)
4381 {
4382         int ret;
4383         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
4384                ixgbe_driver_string, ixgbe_driver_version);
4385
4386         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
4387
4388 #ifdef CONFIG_IXGBE_DCA
4389         dca_register_notify(&dca_notifier);
4390 #endif
4391
4392         ret = pci_register_driver(&ixgbe_driver);
4393         return ret;
4394 }
4395
4396 module_init(ixgbe_init_module);
4397
4398 /**
4399  * ixgbe_exit_module - Driver Exit Cleanup Routine
4400  *
4401  * ixgbe_exit_module is called just before the driver is removed
4402  * from memory.
4403  **/
4404 static void __exit ixgbe_exit_module(void)
4405 {
4406 #ifdef CONFIG_IXGBE_DCA
4407         dca_unregister_notify(&dca_notifier);
4408 #endif
4409         pci_unregister_driver(&ixgbe_driver);
4410 }
4411
4412 #ifdef CONFIG_IXGBE_DCA
4413 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
4414                             void *p)
4415 {
4416         int ret_val;
4417
4418         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
4419                                          __ixgbe_notify_dca);
4420
4421         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4422 }
4423 #endif /* CONFIG_IXGBE_DCA */
4424
4425 module_exit(ixgbe_exit_module);
4426
4427 /* ixgbe_main.c */