3 Broadcom BCM43xx wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Stefano Brivio <st3@riseup.net>
7 Michael Buesch <mbuesch@freenet.de>
8 Danny van Dyk <kugelfang@gentoo.org>
9 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
34 #include "bcm43xx_power.h"
35 #include "bcm43xx_main.h"
38 /* Get the Slow Clock Source */
39 static int bcm43xx_pctl_get_slowclksrc(struct bcm43xx_private *bcm)
44 assert(bcm->current_core == &bcm->core_chipcommon);
45 if (bcm->current_core->rev < 6) {
46 if (bcm->bustype == BCM43xx_BUSTYPE_PCMCIA ||
47 bcm->bustype == BCM43xx_BUSTYPE_SB)
48 return BCM43xx_PCTL_CLKSRC_XTALOS;
49 if (bcm->bustype == BCM43xx_BUSTYPE_PCI) {
50 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCTL_OUT, &tmp);
53 return BCM43xx_PCTL_CLKSRC_PCI;
54 return BCM43xx_PCTL_CLKSRC_XTALOS;
57 if (bcm->current_core->rev < 10) {
58 tmp = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_SLOWCLKCTL);
61 return BCM43xx_PCTL_CLKSRC_LOPWROS;
63 return BCM43xx_PCTL_CLKSRC_XTALOS;
65 return BCM43xx_PCTL_CLKSRC_PCI;
68 return BCM43xx_PCTL_CLKSRC_XTALOS;
71 /* Get max/min slowclock frequency
72 * as described in http://bcm-specs.sipsolutions.net/PowerControl
74 static int bcm43xx_pctl_clockfreqlimit(struct bcm43xx_private *bcm,
82 assert(bcm->chipcommon_capabilities & BCM43xx_CAPABILITIES_PCTL);
83 assert(bcm->current_core == &bcm->core_chipcommon);
85 clocksrc = bcm43xx_pctl_get_slowclksrc(bcm);
86 if (bcm->current_core->rev < 6) {
88 case BCM43xx_PCTL_CLKSRC_PCI:
91 case BCM43xx_PCTL_CLKSRC_XTALOS:
98 } else if (bcm->current_core->rev < 10) {
100 case BCM43xx_PCTL_CLKSRC_LOPWROS:
103 case BCM43xx_PCTL_CLKSRC_XTALOS:
104 case BCM43xx_PCTL_CLKSRC_PCI:
105 tmp = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_SLOWCLKCTL);
106 divisor = ((tmp & 0xFFFF0000) >> 16) + 1;
114 tmp = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_SYSCLKCTL);
115 divisor = ((tmp & 0xFFFF0000) >> 16) + 1;
120 case BCM43xx_PCTL_CLKSRC_LOPWROS:
126 case BCM43xx_PCTL_CLKSRC_XTALOS:
132 case BCM43xx_PCTL_CLKSRC_PCI:
148 /* init power control
149 * as described in http://bcm-specs.sipsolutions.net/PowerControl
151 int bcm43xx_pctl_init(struct bcm43xx_private *bcm)
154 struct bcm43xx_coreinfo *old_core;
156 if (!(bcm->chipcommon_capabilities & BCM43xx_CAPABILITIES_PCTL))
158 old_core = bcm->current_core;
159 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
165 maxfreq = bcm43xx_pctl_clockfreqlimit(bcm, 1);
166 bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_PLLONDELAY,
167 (maxfreq * 150 + 999999) / 1000000);
168 bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_FREFSELDELAY,
169 (maxfreq * 15 + 999999) / 1000000);
171 err = bcm43xx_switch_core(bcm, old_core);
178 u16 bcm43xx_pctl_powerup_delay(struct bcm43xx_private *bcm)
183 struct bcm43xx_coreinfo *old_core;
186 if (bcm->bustype != BCM43xx_BUSTYPE_PCI)
188 if (!(bcm->chipcommon_capabilities & BCM43xx_CAPABILITIES_PCTL))
190 old_core = bcm->current_core;
191 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
195 minfreq = bcm43xx_pctl_clockfreqlimit(bcm, 0);
196 pll_on_delay = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_PLLONDELAY);
197 delay = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
199 err = bcm43xx_switch_core(bcm, old_core);
206 /* set the powercontrol clock
207 * as described in http://bcm-specs.sipsolutions.net/PowerControl
209 int bcm43xx_pctl_set_clock(struct bcm43xx_private *bcm, u16 mode)
212 struct bcm43xx_coreinfo *old_core;
215 old_core = bcm->current_core;
216 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
222 if (bcm->core_chipcommon.rev < 6) {
223 if (mode == BCM43xx_PCTL_CLK_FAST) {
224 err = bcm43xx_pctl_set_crystal(bcm, 1);
229 if ((bcm->chipcommon_capabilities & BCM43xx_CAPABILITIES_PCTL) &&
230 (bcm->core_chipcommon.rev < 10)) {
232 case BCM43xx_PCTL_CLK_FAST:
233 tmp = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_SLOWCLKCTL);
234 tmp = (tmp & ~BCM43xx_PCTL_FORCE_SLOW) | BCM43xx_PCTL_FORCE_PLL;
235 bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_SLOWCLKCTL, tmp);
237 case BCM43xx_PCTL_CLK_SLOW:
238 tmp = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_SLOWCLKCTL);
239 tmp |= BCM43xx_PCTL_FORCE_SLOW;
240 bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_SLOWCLKCTL, tmp);
242 case BCM43xx_PCTL_CLK_DYNAMIC:
243 tmp = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_SLOWCLKCTL);
244 tmp &= ~BCM43xx_PCTL_FORCE_SLOW;
245 tmp |= BCM43xx_PCTL_FORCE_PLL;
246 tmp &= ~BCM43xx_PCTL_DYN_XTAL;
247 bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_SLOWCLKCTL, tmp);
252 err = bcm43xx_switch_core(bcm, old_core);
259 int bcm43xx_pctl_set_crystal(struct bcm43xx_private *bcm, int on)
262 u32 in, out, outenable;
264 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCTL_IN, &in);
267 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCTL_OUT, &out);
270 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCTL_OUTENABLE, &outenable);
274 outenable |= (BCM43xx_PCTL_XTAL_POWERUP | BCM43xx_PCTL_PLL_POWERDOWN);
280 out |= (BCM43xx_PCTL_XTAL_POWERUP | BCM43xx_PCTL_PLL_POWERDOWN);
282 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCTL_OUT, out);
285 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCTL_OUTENABLE, outenable);
290 out &= ~BCM43xx_PCTL_PLL_POWERDOWN;
291 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCTL_OUT, out);
296 if (bcm->current_core->rev < 5)
298 if (bcm->sprom.boardflags & BCM43xx_BFL_XTAL_NOSLOW)
301 /* XXX: Why BCM43xx_MMIO_RADIO_HWENABLED_xx can't be read at this time?
302 * err = bcm43xx_switch_core(bcm, bcm->active_80211_core);
305 * if (((bcm->current_core->rev >= 3) &&
306 * (bcm43xx_read32(bcm, BCM43xx_MMIO_RADIO_HWENABLED_HI) & (1 << 16))) ||
307 * ((bcm->current_core->rev < 3) &&
308 * !(bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_HWENABLED_LO) & (1 << 4))))
310 * err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
315 err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
318 out &= ~BCM43xx_PCTL_XTAL_POWERUP;
319 out |= BCM43xx_PCTL_PLL_POWERDOWN;
320 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCTL_OUT, out);
323 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCTL_OUTENABLE, outenable);
332 printk(KERN_ERR PFX "Error: pctl_set_clock() could not access PCI config space!\n");
337 /* Set the PowerSavingControlBits.
341 * -1 => calculate the bit
343 void bcm43xx_power_saving_ctl_bits(struct bcm43xx_private *bcm,
344 int bit25, int bit26)
349 //FIXME: Force 25 to off and 26 to on for now:
354 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
355 // and thus is not an AP and we are associated, set bit 25
358 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
359 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
360 // successful, set bit26
362 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
364 status |= BCM43xx_SBF_PS1;
366 status &= ~BCM43xx_SBF_PS1;
368 status |= BCM43xx_SBF_PS2;
370 status &= ~BCM43xx_SBF_PS2;
371 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
372 if (bit26 && bcm->current_core->rev >= 5) {
373 for (i = 0; i < 100; i++) {
374 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0040) != 4)