Merge branches 'release' and 'gpe-ack' into release
[linux-2.6] / drivers / char / agp / amd-k7-agp.c
1 /*
2  * AMD K7 AGPGART routines.
3  */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/agp_backend.h>
9 #include <linux/gfp.h>
10 #include <linux/page-flags.h>
11 #include <linux/mm.h>
12 #include "agp.h"
13
14 #define AMD_MMBASE      0x14
15 #define AMD_APSIZE      0xac
16 #define AMD_MODECNTL    0xb0
17 #define AMD_MODECNTL2   0xb2
18 #define AMD_GARTENABLE  0x02    /* In mmio region (16-bit register) */
19 #define AMD_ATTBASE     0x04    /* In mmio region (32-bit register) */
20 #define AMD_TLBFLUSH    0x0c    /* In mmio region (32-bit register) */
21 #define AMD_CACHEENTRY  0x10    /* In mmio region (32-bit register) */
22
23 static struct pci_device_id agp_amdk7_pci_table[];
24
25 struct amd_page_map {
26         unsigned long *real;
27         unsigned long __iomem *remapped;
28 };
29
30 static struct _amd_irongate_private {
31         volatile u8 __iomem *registers;
32         struct amd_page_map **gatt_pages;
33         int num_tables;
34 } amd_irongate_private;
35
36 static int amd_create_page_map(struct amd_page_map *page_map)
37 {
38         int i;
39
40         page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
41         if (page_map->real == NULL)
42                 return -ENOMEM;
43
44         SetPageReserved(virt_to_page(page_map->real));
45         global_cache_flush();
46         page_map->remapped = ioremap_nocache(virt_to_gart(page_map->real),
47                                             PAGE_SIZE);
48         if (page_map->remapped == NULL) {
49                 ClearPageReserved(virt_to_page(page_map->real));
50                 free_page((unsigned long) page_map->real);
51                 page_map->real = NULL;
52                 return -ENOMEM;
53         }
54         global_cache_flush();
55
56         for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
57                 writel(agp_bridge->scratch_page, page_map->remapped+i);
58                 readl(page_map->remapped+i);    /* PCI Posting. */
59         }
60
61         return 0;
62 }
63
64 static void amd_free_page_map(struct amd_page_map *page_map)
65 {
66         iounmap(page_map->remapped);
67         ClearPageReserved(virt_to_page(page_map->real));
68         free_page((unsigned long) page_map->real);
69 }
70
71 static void amd_free_gatt_pages(void)
72 {
73         int i;
74         struct amd_page_map **tables;
75         struct amd_page_map *entry;
76
77         tables = amd_irongate_private.gatt_pages;
78         for (i = 0; i < amd_irongate_private.num_tables; i++) {
79                 entry = tables[i];
80                 if (entry != NULL) {
81                         if (entry->real != NULL)
82                                 amd_free_page_map(entry);
83                         kfree(entry);
84                 }
85         }
86         kfree(tables);
87         amd_irongate_private.gatt_pages = NULL;
88 }
89
90 static int amd_create_gatt_pages(int nr_tables)
91 {
92         struct amd_page_map **tables;
93         struct amd_page_map *entry;
94         int retval = 0;
95         int i;
96
97         tables = kzalloc((nr_tables + 1) * sizeof(struct amd_page_map *),GFP_KERNEL);
98         if (tables == NULL)
99                 return -ENOMEM;
100
101         for (i = 0; i < nr_tables; i++) {
102                 entry = kzalloc(sizeof(struct amd_page_map), GFP_KERNEL);
103                 tables[i] = entry;
104                 if (entry == NULL) {
105                         retval = -ENOMEM;
106                         break;
107                 }
108                 retval = amd_create_page_map(entry);
109                 if (retval != 0)
110                         break;
111         }
112         amd_irongate_private.num_tables = i;
113         amd_irongate_private.gatt_pages = tables;
114
115         if (retval != 0)
116                 amd_free_gatt_pages();
117
118         return retval;
119 }
120
121 /* Since we don't need contiguous memory we just try
122  * to get the gatt table once
123  */
124
125 #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
126 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
127         GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
128 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
129 #define GET_GATT(addr) (amd_irongate_private.gatt_pages[\
130         GET_PAGE_DIR_IDX(addr)]->remapped)
131
132 static int amd_create_gatt_table(struct agp_bridge_data *bridge)
133 {
134         struct aper_size_info_lvl2 *value;
135         struct amd_page_map page_dir;
136         unsigned long addr;
137         int retval;
138         u32 temp;
139         int i;
140
141         value = A_SIZE_LVL2(agp_bridge->current_size);
142         retval = amd_create_page_map(&page_dir);
143         if (retval != 0)
144                 return retval;
145
146         retval = amd_create_gatt_pages(value->num_entries / 1024);
147         if (retval != 0) {
148                 amd_free_page_map(&page_dir);
149                 return retval;
150         }
151
152         agp_bridge->gatt_table_real = (u32 *)page_dir.real;
153         agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;
154         agp_bridge->gatt_bus_addr = virt_to_gart(page_dir.real);
155
156         /* Get the address for the gart region.
157          * This is a bus address even on the alpha, b/c its
158          * used to program the agp master not the cpu
159          */
160
161         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
162         addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
163         agp_bridge->gart_bus_addr = addr;
164
165         /* Calculate the agp offset */
166         for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {
167                 writel(virt_to_gart(amd_irongate_private.gatt_pages[i]->real) | 1,
168                         page_dir.remapped+GET_PAGE_DIR_OFF(addr));
169                 readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr));        /* PCI Posting. */
170         }
171
172         return 0;
173 }
174
175 static int amd_free_gatt_table(struct agp_bridge_data *bridge)
176 {
177         struct amd_page_map page_dir;
178
179         page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
180         page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;
181
182         amd_free_gatt_pages();
183         amd_free_page_map(&page_dir);
184         return 0;
185 }
186
187 static int amd_irongate_fetch_size(void)
188 {
189         int i;
190         u32 temp;
191         struct aper_size_info_lvl2 *values;
192
193         pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
194         temp = (temp & 0x0000000e);
195         values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
196         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
197                 if (temp == values[i].size_value) {
198                         agp_bridge->previous_size =
199                             agp_bridge->current_size = (void *) (values + i);
200
201                         agp_bridge->aperture_size_idx = i;
202                         return values[i].size;
203                 }
204         }
205
206         return 0;
207 }
208
209 static int amd_irongate_configure(void)
210 {
211         struct aper_size_info_lvl2 *current_size;
212         u32 temp;
213         u16 enable_reg;
214
215         current_size = A_SIZE_LVL2(agp_bridge->current_size);
216
217         /* Get the memory mapped registers */
218         pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp);
219         temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
220         amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
221         if (!amd_irongate_private.registers)
222                 return -ENOMEM;
223
224         /* Write out the address of the gatt table */
225         writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE);
226         readl(amd_irongate_private.registers+AMD_ATTBASE);      /* PCI Posting. */
227
228         /* Write the Sync register */
229         pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80);
230
231         /* Set indexing mode */
232         pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00);
233
234         /* Write the enable register */
235         enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
236         enable_reg = (enable_reg | 0x0004);
237         writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
238         readw(amd_irongate_private.registers+AMD_GARTENABLE);   /* PCI Posting. */
239
240         /* Write out the size register */
241         pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
242         temp = (((temp & ~(0x0000000e)) | current_size->size_value) | 1);
243         pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
244
245         /* Flush the tlb */
246         writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
247         readl(amd_irongate_private.registers+AMD_TLBFLUSH);     /* PCI Posting.*/
248         return 0;
249 }
250
251 static void amd_irongate_cleanup(void)
252 {
253         struct aper_size_info_lvl2 *previous_size;
254         u32 temp;
255         u16 enable_reg;
256
257         previous_size = A_SIZE_LVL2(agp_bridge->previous_size);
258
259         enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
260         enable_reg = (enable_reg & ~(0x0004));
261         writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
262         readw(amd_irongate_private.registers+AMD_GARTENABLE);   /* PCI Posting. */
263
264         /* Write back the previous size and disable gart translation */
265         pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
266         temp = ((temp & ~(0x0000000f)) | previous_size->size_value);
267         pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
268         iounmap((void __iomem *) amd_irongate_private.registers);
269 }
270
271 /*
272  * This routine could be implemented by taking the addresses
273  * written to the GATT, and flushing them individually.  However
274  * currently it just flushes the whole table.  Which is probably
275  * more efficent, since agp_memory blocks can be a large number of
276  * entries.
277  */
278
279 static void amd_irongate_tlbflush(struct agp_memory *temp)
280 {
281         writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
282         readl(amd_irongate_private.registers+AMD_TLBFLUSH);     /* PCI Posting. */
283 }
284
285 static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
286 {
287         int i, j, num_entries;
288         unsigned long __iomem *cur_gatt;
289         unsigned long addr;
290
291         num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
292
293         if (type != 0 || mem->type != 0)
294                 return -EINVAL;
295
296         if ((pg_start + mem->page_count) > num_entries)
297                 return -EINVAL;
298
299         j = pg_start;
300         while (j < (pg_start + mem->page_count)) {
301                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
302                 cur_gatt = GET_GATT(addr);
303                 if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))
304                         return -EBUSY;
305                 j++;
306         }
307
308         if (mem->is_flushed == FALSE) {
309                 global_cache_flush();
310                 mem->is_flushed = TRUE;
311         }
312
313         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
314                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
315                 cur_gatt = GET_GATT(addr);
316                 writel(agp_generic_mask_memory(agp_bridge,
317                         mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr));
318                 readl(cur_gatt+GET_GATT_OFF(addr));     /* PCI Posting. */
319         }
320         amd_irongate_tlbflush(mem);
321         return 0;
322 }
323
324 static int amd_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
325 {
326         int i;
327         unsigned long __iomem *cur_gatt;
328         unsigned long addr;
329
330         if (type != 0 || mem->type != 0)
331                 return -EINVAL;
332
333         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
334                 addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
335                 cur_gatt = GET_GATT(addr);
336                 writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
337                 readl(cur_gatt+GET_GATT_OFF(addr));     /* PCI Posting. */
338         }
339
340         amd_irongate_tlbflush(mem);
341         return 0;
342 }
343
344 static const struct aper_size_info_lvl2 amd_irongate_sizes[7] =
345 {
346         {2048, 524288, 0x0000000c},
347         {1024, 262144, 0x0000000a},
348         {512, 131072, 0x00000008},
349         {256, 65536, 0x00000006},
350         {128, 32768, 0x00000004},
351         {64, 16384, 0x00000002},
352         {32, 8192, 0x00000000}
353 };
354
355 static const struct gatt_mask amd_irongate_masks[] =
356 {
357         {.mask = 1, .type = 0}
358 };
359
360 static const struct agp_bridge_driver amd_irongate_driver = {
361         .owner                  = THIS_MODULE,
362         .aperture_sizes         = amd_irongate_sizes,
363         .size_type              = LVL2_APER_SIZE,
364         .num_aperture_sizes     = 7,
365         .configure              = amd_irongate_configure,
366         .fetch_size             = amd_irongate_fetch_size,
367         .cleanup                = amd_irongate_cleanup,
368         .tlb_flush              = amd_irongate_tlbflush,
369         .mask_memory            = agp_generic_mask_memory,
370         .masks                  = amd_irongate_masks,
371         .agp_enable             = agp_generic_enable,
372         .cache_flush            = global_cache_flush,
373         .create_gatt_table      = amd_create_gatt_table,
374         .free_gatt_table        = amd_free_gatt_table,
375         .insert_memory          = amd_insert_memory,
376         .remove_memory          = amd_remove_memory,
377         .alloc_by_type          = agp_generic_alloc_by_type,
378         .free_by_type           = agp_generic_free_by_type,
379         .agp_alloc_page         = agp_generic_alloc_page,
380         .agp_destroy_page       = agp_generic_destroy_page,
381         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
382 };
383
384 static struct agp_device_ids amd_agp_device_ids[] __devinitdata =
385 {
386         {
387                 .device_id      = PCI_DEVICE_ID_AMD_FE_GATE_7006,
388                 .chipset_name   = "Irongate",
389         },
390         {
391                 .device_id      = PCI_DEVICE_ID_AMD_FE_GATE_700E,
392                 .chipset_name   = "761",
393         },
394         {
395                 .device_id      = PCI_DEVICE_ID_AMD_FE_GATE_700C,
396                 .chipset_name   = "760MP",
397         },
398         { }, /* dummy final entry, always present */
399 };
400
401 static int __devinit agp_amdk7_probe(struct pci_dev *pdev,
402                                      const struct pci_device_id *ent)
403 {
404         struct agp_bridge_data *bridge;
405         u8 cap_ptr;
406         int j;
407
408         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
409         if (!cap_ptr)
410                 return -ENODEV;
411
412         j = ent - agp_amdk7_pci_table;
413         printk(KERN_INFO PFX "Detected AMD %s chipset\n",
414                amd_agp_device_ids[j].chipset_name);
415
416         bridge = agp_alloc_bridge();
417         if (!bridge)
418                 return -ENOMEM;
419
420         bridge->driver = &amd_irongate_driver;
421         bridge->dev_private_data = &amd_irongate_private,
422         bridge->dev = pdev;
423         bridge->capndx = cap_ptr;
424
425         /* 751 Errata (22564_B-1.PDF)
426            erratum 20: strobe glitch with Nvidia NV10 GeForce cards.
427            system controller may experience noise due to strong drive strengths
428          */
429         if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_7006) {
430                 u8 cap_ptr=0;
431                 struct pci_dev *gfxcard=NULL;
432                 while (!cap_ptr) {
433                         gfxcard = pci_get_class(PCI_CLASS_DISPLAY_VGA<<8, gfxcard);
434                         if (!gfxcard) {
435                                 printk (KERN_INFO PFX "Couldn't find an AGP VGA controller.\n");
436                                 return -ENODEV;
437                         }
438                         cap_ptr = pci_find_capability(gfxcard, PCI_CAP_ID_AGP);
439                 }
440
441                 /* With so many variants of NVidia cards, it's simpler just
442                    to blacklist them all, and then whitelist them as needed
443                    (if necessary at all). */
444                 if (gfxcard->vendor == PCI_VENDOR_ID_NVIDIA) {
445                         agp_bridge->flags |= AGP_ERRATA_1X;
446                         printk (KERN_INFO PFX "AMD 751 chipset with NVidia GeForce detected. Forcing to 1X due to errata.\n");
447                 }
448                 pci_dev_put(gfxcard);
449         }
450
451         /* 761 Errata (23613_F.pdf)
452          * Revisions B0/B1 were a disaster.
453          * erratum 44: SYSCLK/AGPCLK skew causes 2X failures -- Force mode to 1X
454          * erratum 45: Timing problem prevents fast writes -- Disable fast write.
455          * erratum 46: Setup violation on AGP SBA pins - Disable side band addressing.
456          * With this lot disabled, we should prevent lockups. */
457         if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_700E) {
458                 if (pdev->revision == 0x10 || pdev->revision == 0x11) {
459                         agp_bridge->flags = AGP_ERRATA_FASTWRITES;
460                         agp_bridge->flags |= AGP_ERRATA_SBA;
461                         agp_bridge->flags |= AGP_ERRATA_1X;
462                         printk (KERN_INFO PFX "AMD 761 chipset with errata detected - disabling AGP fast writes & SBA and forcing to 1X.\n");
463                 }
464         }
465
466         /* Fill in the mode register */
467         pci_read_config_dword(pdev,
468                         bridge->capndx+PCI_AGP_STATUS,
469                         &bridge->mode);
470
471         pci_set_drvdata(pdev, bridge);
472         return agp_add_bridge(bridge);
473 }
474
475 static void __devexit agp_amdk7_remove(struct pci_dev *pdev)
476 {
477         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
478
479         agp_remove_bridge(bridge);
480         agp_put_bridge(bridge);
481 }
482
483 /* must be the same order as name table above */
484 static struct pci_device_id agp_amdk7_pci_table[] = {
485         {
486         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
487         .class_mask     = ~0,
488         .vendor         = PCI_VENDOR_ID_AMD,
489         .device         = PCI_DEVICE_ID_AMD_FE_GATE_7006,
490         .subvendor      = PCI_ANY_ID,
491         .subdevice      = PCI_ANY_ID,
492         },
493         {
494         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
495         .class_mask     = ~0,
496         .vendor         = PCI_VENDOR_ID_AMD,
497         .device         = PCI_DEVICE_ID_AMD_FE_GATE_700E,
498         .subvendor      = PCI_ANY_ID,
499         .subdevice      = PCI_ANY_ID,
500         },
501         {
502         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
503         .class_mask     = ~0,
504         .vendor         = PCI_VENDOR_ID_AMD,
505         .device         = PCI_DEVICE_ID_AMD_FE_GATE_700C,
506         .subvendor      = PCI_ANY_ID,
507         .subdevice      = PCI_ANY_ID,
508         },
509         { }
510 };
511
512 MODULE_DEVICE_TABLE(pci, agp_amdk7_pci_table);
513
514 static struct pci_driver agp_amdk7_pci_driver = {
515         .name           = "agpgart-amdk7",
516         .id_table       = agp_amdk7_pci_table,
517         .probe          = agp_amdk7_probe,
518         .remove         = agp_amdk7_remove,
519 };
520
521 static int __init agp_amdk7_init(void)
522 {
523         if (agp_off)
524                 return -EINVAL;
525         return pci_register_driver(&agp_amdk7_pci_driver);
526 }
527
528 static void __exit agp_amdk7_cleanup(void)
529 {
530         pci_unregister_driver(&agp_amdk7_pci_driver);
531 }
532
533 module_init(agp_amdk7_init);
534 module_exit(agp_amdk7_cleanup);
535
536 MODULE_LICENSE("GPL and additional rights");