traps: i386: expand clear_mem_error and remove from mach_traps.h
[linux-2.6] / arch / x86 / kvm / i8259.c
1 /*
2  * 8259 interrupt controller emulation
3  *
4  * Copyright (c) 2003-2004 Fabrice Bellard
5  * Copyright (c) 2007 Intel Corporation
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11  * copies of the Software, and to permit persons to whom the Software is
12  * furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in
15  * all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23  * THE SOFTWARE.
24  * Authors:
25  *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
26  *   Port from Qemu.
27  */
28 #include <linux/mm.h>
29 #include "irq.h"
30
31 #include <linux/kvm_host.h>
32
33 /*
34  * set irq level. If an edge is detected, then the IRR is set to 1
35  */
36 static inline void pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
37 {
38         int mask;
39         mask = 1 << irq;
40         if (s->elcr & mask)     /* level triggered */
41                 if (level) {
42                         s->irr |= mask;
43                         s->last_irr |= mask;
44                 } else {
45                         s->irr &= ~mask;
46                         s->last_irr &= ~mask;
47                 }
48         else    /* edge triggered */
49                 if (level) {
50                         if ((s->last_irr & mask) == 0)
51                                 s->irr |= mask;
52                         s->last_irr |= mask;
53                 } else
54                         s->last_irr &= ~mask;
55 }
56
57 /*
58  * return the highest priority found in mask (highest = smallest
59  * number). Return 8 if no irq
60  */
61 static inline int get_priority(struct kvm_kpic_state *s, int mask)
62 {
63         int priority;
64         if (mask == 0)
65                 return 8;
66         priority = 0;
67         while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
68                 priority++;
69         return priority;
70 }
71
72 /*
73  * return the pic wanted interrupt. return -1 if none
74  */
75 static int pic_get_irq(struct kvm_kpic_state *s)
76 {
77         int mask, cur_priority, priority;
78
79         mask = s->irr & ~s->imr;
80         priority = get_priority(s, mask);
81         if (priority == 8)
82                 return -1;
83         /*
84          * compute current priority. If special fully nested mode on the
85          * master, the IRQ coming from the slave is not taken into account
86          * for the priority computation.
87          */
88         mask = s->isr;
89         if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
90                 mask &= ~(1 << 2);
91         cur_priority = get_priority(s, mask);
92         if (priority < cur_priority)
93                 /*
94                  * higher priority found: an irq should be generated
95                  */
96                 return (priority + s->priority_add) & 7;
97         else
98                 return -1;
99 }
100
101 /*
102  * raise irq to CPU if necessary. must be called every time the active
103  * irq may change
104  */
105 static void pic_update_irq(struct kvm_pic *s)
106 {
107         int irq2, irq;
108
109         irq2 = pic_get_irq(&s->pics[1]);
110         if (irq2 >= 0) {
111                 /*
112                  * if irq request by slave pic, signal master PIC
113                  */
114                 pic_set_irq1(&s->pics[0], 2, 1);
115                 pic_set_irq1(&s->pics[0], 2, 0);
116         }
117         irq = pic_get_irq(&s->pics[0]);
118         if (irq >= 0)
119                 s->irq_request(s->irq_request_opaque, 1);
120         else
121                 s->irq_request(s->irq_request_opaque, 0);
122 }
123
124 void kvm_pic_update_irq(struct kvm_pic *s)
125 {
126         pic_update_irq(s);
127 }
128
129 void kvm_pic_set_irq(void *opaque, int irq, int level)
130 {
131         struct kvm_pic *s = opaque;
132
133         if (irq >= 0 && irq < PIC_NUM_PINS) {
134                 pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
135                 pic_update_irq(s);
136         }
137 }
138
139 /*
140  * acknowledge interrupt 'irq'
141  */
142 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
143 {
144         if (s->auto_eoi) {
145                 if (s->rotate_on_auto_eoi)
146                         s->priority_add = (irq + 1) & 7;
147         } else
148                 s->isr |= (1 << irq);
149         /*
150          * We don't clear a level sensitive interrupt here
151          */
152         if (!(s->elcr & (1 << irq)))
153                 s->irr &= ~(1 << irq);
154 }
155
156 int kvm_pic_read_irq(struct kvm_pic *s)
157 {
158         int irq, irq2, intno;
159
160         irq = pic_get_irq(&s->pics[0]);
161         if (irq >= 0) {
162                 pic_intack(&s->pics[0], irq);
163                 if (irq == 2) {
164                         irq2 = pic_get_irq(&s->pics[1]);
165                         if (irq2 >= 0)
166                                 pic_intack(&s->pics[1], irq2);
167                         else
168                                 /*
169                                  * spurious IRQ on slave controller
170                                  */
171                                 irq2 = 7;
172                         intno = s->pics[1].irq_base + irq2;
173                         irq = irq2 + 8;
174                 } else
175                         intno = s->pics[0].irq_base + irq;
176         } else {
177                 /*
178                  * spurious IRQ on host controller
179                  */
180                 irq = 7;
181                 intno = s->pics[0].irq_base + irq;
182         }
183         pic_update_irq(s);
184
185         return intno;
186 }
187
188 void kvm_pic_reset(struct kvm_kpic_state *s)
189 {
190         s->last_irr = 0;
191         s->irr = 0;
192         s->imr = 0;
193         s->isr = 0;
194         s->priority_add = 0;
195         s->irq_base = 0;
196         s->read_reg_select = 0;
197         s->poll = 0;
198         s->special_mask = 0;
199         s->init_state = 0;
200         s->auto_eoi = 0;
201         s->rotate_on_auto_eoi = 0;
202         s->special_fully_nested_mode = 0;
203         s->init4 = 0;
204 }
205
206 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
207 {
208         struct kvm_kpic_state *s = opaque;
209         int priority, cmd, irq;
210
211         addr &= 1;
212         if (addr == 0) {
213                 if (val & 0x10) {
214                         kvm_pic_reset(s);       /* init */
215                         /*
216                          * deassert a pending interrupt
217                          */
218                         s->pics_state->irq_request(s->pics_state->
219                                                    irq_request_opaque, 0);
220                         s->init_state = 1;
221                         s->init4 = val & 1;
222                         if (val & 0x02)
223                                 printk(KERN_ERR "single mode not supported");
224                         if (val & 0x08)
225                                 printk(KERN_ERR
226                                        "level sensitive irq not supported");
227                 } else if (val & 0x08) {
228                         if (val & 0x04)
229                                 s->poll = 1;
230                         if (val & 0x02)
231                                 s->read_reg_select = val & 1;
232                         if (val & 0x40)
233                                 s->special_mask = (val >> 5) & 1;
234                 } else {
235                         cmd = val >> 5;
236                         switch (cmd) {
237                         case 0:
238                         case 4:
239                                 s->rotate_on_auto_eoi = cmd >> 2;
240                                 break;
241                         case 1: /* end of interrupt */
242                         case 5:
243                                 priority = get_priority(s, s->isr);
244                                 if (priority != 8) {
245                                         irq = (priority + s->priority_add) & 7;
246                                         s->isr &= ~(1 << irq);
247                                         if (cmd == 5)
248                                                 s->priority_add = (irq + 1) & 7;
249                                         pic_update_irq(s->pics_state);
250                                 }
251                                 break;
252                         case 3:
253                                 irq = val & 7;
254                                 s->isr &= ~(1 << irq);
255                                 pic_update_irq(s->pics_state);
256                                 break;
257                         case 6:
258                                 s->priority_add = (val + 1) & 7;
259                                 pic_update_irq(s->pics_state);
260                                 break;
261                         case 7:
262                                 irq = val & 7;
263                                 s->isr &= ~(1 << irq);
264                                 s->priority_add = (irq + 1) & 7;
265                                 pic_update_irq(s->pics_state);
266                                 break;
267                         default:
268                                 break;  /* no operation */
269                         }
270                 }
271         } else
272                 switch (s->init_state) {
273                 case 0:         /* normal mode */
274                         s->imr = val;
275                         pic_update_irq(s->pics_state);
276                         break;
277                 case 1:
278                         s->irq_base = val & 0xf8;
279                         s->init_state = 2;
280                         break;
281                 case 2:
282                         if (s->init4)
283                                 s->init_state = 3;
284                         else
285                                 s->init_state = 0;
286                         break;
287                 case 3:
288                         s->special_fully_nested_mode = (val >> 4) & 1;
289                         s->auto_eoi = (val >> 1) & 1;
290                         s->init_state = 0;
291                         break;
292                 }
293 }
294
295 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
296 {
297         int ret;
298
299         ret = pic_get_irq(s);
300         if (ret >= 0) {
301                 if (addr1 >> 7) {
302                         s->pics_state->pics[0].isr &= ~(1 << 2);
303                         s->pics_state->pics[0].irr &= ~(1 << 2);
304                 }
305                 s->irr &= ~(1 << ret);
306                 s->isr &= ~(1 << ret);
307                 if (addr1 >> 7 || ret != 2)
308                         pic_update_irq(s->pics_state);
309         } else {
310                 ret = 0x07;
311                 pic_update_irq(s->pics_state);
312         }
313
314         return ret;
315 }
316
317 static u32 pic_ioport_read(void *opaque, u32 addr1)
318 {
319         struct kvm_kpic_state *s = opaque;
320         unsigned int addr;
321         int ret;
322
323         addr = addr1;
324         addr &= 1;
325         if (s->poll) {
326                 ret = pic_poll_read(s, addr1);
327                 s->poll = 0;
328         } else
329                 if (addr == 0)
330                         if (s->read_reg_select)
331                                 ret = s->isr;
332                         else
333                                 ret = s->irr;
334                 else
335                         ret = s->imr;
336         return ret;
337 }
338
339 static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
340 {
341         struct kvm_kpic_state *s = opaque;
342         s->elcr = val & s->elcr_mask;
343 }
344
345 static u32 elcr_ioport_read(void *opaque, u32 addr1)
346 {
347         struct kvm_kpic_state *s = opaque;
348         return s->elcr;
349 }
350
351 static int picdev_in_range(struct kvm_io_device *this, gpa_t addr,
352                            int len, int is_write)
353 {
354         switch (addr) {
355         case 0x20:
356         case 0x21:
357         case 0xa0:
358         case 0xa1:
359         case 0x4d0:
360         case 0x4d1:
361                 return 1;
362         default:
363                 return 0;
364         }
365 }
366
367 static void picdev_write(struct kvm_io_device *this,
368                          gpa_t addr, int len, const void *val)
369 {
370         struct kvm_pic *s = this->private;
371         unsigned char data = *(unsigned char *)val;
372
373         if (len != 1) {
374                 if (printk_ratelimit())
375                         printk(KERN_ERR "PIC: non byte write\n");
376                 return;
377         }
378         switch (addr) {
379         case 0x20:
380         case 0x21:
381         case 0xa0:
382         case 0xa1:
383                 pic_ioport_write(&s->pics[addr >> 7], addr, data);
384                 break;
385         case 0x4d0:
386         case 0x4d1:
387                 elcr_ioport_write(&s->pics[addr & 1], addr, data);
388                 break;
389         }
390 }
391
392 static void picdev_read(struct kvm_io_device *this,
393                         gpa_t addr, int len, void *val)
394 {
395         struct kvm_pic *s = this->private;
396         unsigned char data = 0;
397
398         if (len != 1) {
399                 if (printk_ratelimit())
400                         printk(KERN_ERR "PIC: non byte read\n");
401                 return;
402         }
403         switch (addr) {
404         case 0x20:
405         case 0x21:
406         case 0xa0:
407         case 0xa1:
408                 data = pic_ioport_read(&s->pics[addr >> 7], addr);
409                 break;
410         case 0x4d0:
411         case 0x4d1:
412                 data = elcr_ioport_read(&s->pics[addr & 1], addr);
413                 break;
414         }
415         *(unsigned char *)val = data;
416 }
417
418 /*
419  * callback when PIC0 irq status changed
420  */
421 static void pic_irq_request(void *opaque, int level)
422 {
423         struct kvm *kvm = opaque;
424         struct kvm_vcpu *vcpu = kvm->vcpus[0];
425
426         pic_irqchip(kvm)->output = level;
427         if (vcpu)
428                 kvm_vcpu_kick(vcpu);
429 }
430
431 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
432 {
433         struct kvm_pic *s;
434         s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
435         if (!s)
436                 return NULL;
437         s->pics[0].elcr_mask = 0xf8;
438         s->pics[1].elcr_mask = 0xde;
439         s->irq_request = pic_irq_request;
440         s->irq_request_opaque = kvm;
441         s->pics[0].pics_state = s;
442         s->pics[1].pics_state = s;
443
444         /*
445          * Initialize PIO device
446          */
447         s->dev.read = picdev_read;
448         s->dev.write = picdev_write;
449         s->dev.in_range = picdev_in_range;
450         s->dev.private = s;
451         kvm_io_bus_register_dev(&kvm->pio_bus, &s->dev);
452         return s;
453 }