git.oblomov.eu Git - linux-2.6/blob - arch/mips/sibyte/sb1250/bcm1250_tbprof.c

   1 /*
   2  * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18
  19 #define SBPROF_TB_DEBUG 0
  20
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/slab.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/fs.h>
  29 #include <linux/errno.h>
  30 #include <linux/reboot.h>
  31 #include <linux/smp_lock.h>
  32 #include <linux/wait.h>
  33 #include <asm/uaccess.h>
  34 #include <asm/io.h>
  35 #include <asm/sibyte/sb1250.h>
  36 #include <asm/sibyte/sb1250_regs.h>
  37 #include <asm/sibyte/sb1250_scd.h>
  38 #include <asm/sibyte/sb1250_int.h>
  39 #include <asm/sibyte/trace_prof.h>
  40
  41 #define DEVNAME "bcm1250_tbprof"
  42
  43 static struct sbprof_tb sbp;
  44
  45 #define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES)
  46
  47 /************************************************************************
  48  * Support for ZBbus sampling using the trace buffer
  49  *
  50  * We use the SCD performance counter interrupt, caused by a Zclk counter
  51  * overflow, to trigger the start of tracing.
  52  *
  53  * We set the trace buffer to sample everything and freeze on
  54  * overflow.
  55  *
  56  * We map the interrupt for trace_buffer_freeze to handle it on CPU 0.
  57  *
  58  ************************************************************************/
  59
  60 static u_int64_t tb_period;
  61
  62 static void arm_tb(void)
  63 {
  64         u_int64_t scdperfcnt;
  65         u_int64_t next = (1ULL << 40) - tb_period;
  66         u_int64_t tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
  67         /* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
  68            trigger start of trace.  XXX vary sampling period */
  69         __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
  70         scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
  71         /* Unfortunately, in Pass 2 we must clear all counters to knock down
  72            a previous interrupt request.  This means that bus profiling
  73            requires ALL of the SCD perf counters. */
  74         __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
  75                                                 // keep counters 0,2,3 as is
  76                      M_SPC_CFG_ENABLE |         // enable counting
  77                      M_SPC_CFG_CLEAR |          // clear all counters
  78                      V_SPC_CFG_SRC1(1),         // counter 1 counts cycles
  79                      IOADDR(A_SCD_PERF_CNT_CFG));
  80         __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
  81         /* Reset the trace buffer */
  82         __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
  83 #if 0 && defined(M_SCD_TRACE_CFG_FORCECNT)
  84         /* XXXKW may want to expose control to the data-collector */
  85         tb_options |= M_SCD_TRACE_CFG_FORCECNT;
  86 #endif
  87         __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG));
  88         sbp.tb_armed = 1;
  89 }
  90
  91 static irqreturn_t sbprof_tb_intr(int irq, void *dev_id)
  92 {
  93         int i;
  94         DBG(printk(DEVNAME ": tb_intr\n"));
  95         if (sbp.next_tb_sample < MAX_TB_SAMPLES) {
  96                 /* XXX should use XKPHYS to make writes bypass L2 */
  97                 u_int64_t *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
  98                 /* Read out trace */
  99                 __raw_writeq(M_SCD_TRACE_CFG_START_READ,
 100                              IOADDR(A_SCD_TRACE_CFG));
 101                 __asm__ __volatile__ ("sync" : : : "memory");
 102                 /* Loop runs backwards because bundles are read out in reverse order */
 103                 for (i = 256 * 6; i > 0; i -= 6) {
 104                         // Subscripts decrease to put bundle in the order
 105                         //   t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi
 106                         p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 107                                                                 // read t2 hi
 108                         p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 109                                                                 // read t2 lo
 110                         p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 111                                                                 // read t1 hi
 112                         p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 113                                                                 // read t1 lo
 114                         p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 115                                                                 // read t0 hi
 116                         p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 117                                                                 // read t0 lo
 118                 }
 119                 if (!sbp.tb_enable) {
 120                         DBG(printk(DEVNAME ": tb_intr shutdown\n"));
 121                         __raw_writeq(M_SCD_TRACE_CFG_RESET,
 122                                      IOADDR(A_SCD_TRACE_CFG));
 123                         sbp.tb_armed = 0;
 124                         wake_up(&sbp.tb_sync);
 125                 } else {
 126                         arm_tb();       // knock down current interrupt and get another one later
 127                 }
 128         } else {
 129                 /* No more trace buffer samples */
 130                 DBG(printk(DEVNAME ": tb_intr full\n"));
 131                 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
 132                 sbp.tb_armed = 0;
 133                 if (!sbp.tb_enable) {
 134                         wake_up(&sbp.tb_sync);
 135                 }
 136                 wake_up(&sbp.tb_read);
 137         }
 138         return IRQ_HANDLED;
 139 }
 140
 141 static irqreturn_t sbprof_pc_intr(int irq, void *dev_id)
 142 {
 143         printk(DEVNAME ": unexpected pc_intr");
 144         return IRQ_NONE;
 145 }
 146
 147 int sbprof_zbprof_start(struct file *filp)
 148 {
 149         u_int64_t scdperfcnt;
 150
 151         if (sbp.tb_enable)
 152                 return -EBUSY;
 153
 154         DBG(printk(DEVNAME ": starting\n"));
 155
 156         sbp.tb_enable = 1;
 157         sbp.next_tb_sample = 0;
 158         filp->f_pos = 0;
 159
 160         if (request_irq
 161             (K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, DEVNAME " trace freeze", &sbp)) {
 162                 return -EBUSY;
 163         }
 164         /* Make sure there isn't a perf-cnt interrupt waiting */
 165         scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
 166         /* Disable and clear counters, override SRC_1 */
 167         __raw_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) |
 168                      M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1),
 169                      IOADDR(A_SCD_PERF_CNT_CFG));
 170
 171         /* We grab this interrupt to prevent others from trying to use
 172            it, even though we don't want to service the interrupts
 173            (they only feed into the trace-on-interrupt mechanism) */
 174         if (request_irq
 175             (K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
 176                 free_irq(K_INT_TRACE_FREEZE, &sbp);
 177                 return -EBUSY;
 178         }
 179
 180         /* I need the core to mask these, but the interrupt mapper to
 181            pass them through.  I am exploiting my knowledge that
 182            cp0_status masks out IP[5]. krw */
 183         __raw_writeq(K_INT_MAP_I3,
 184                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
 185                             (K_INT_PERF_CNT << 3)));
 186
 187         /* Initialize address traps */
 188         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
 189         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1));
 190         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2));
 191         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3));
 192
 193         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0));
 194         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1));
 195         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2));
 196         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3));
 197
 198         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0));
 199         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1));
 200         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2));
 201         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
 202
 203         /* Initialize Trace Event 0-7 */
 204         //                              when interrupt
 205         __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
 206         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
 207         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
 208         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3));
 209         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4));
 210         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5));
 211         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6));
 212         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
 213
 214         /* Initialize Trace Sequence 0-7 */
 215         //                                   Start on event 0 (interrupt)
 216         __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff,
 217                      IOADDR(A_SCD_TRACE_SEQUENCE_0));
 218         //                        dsamp when d used | asamp when a used
 219         __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
 220                      K_SCD_TRSEQ_TRIGGER_ALL,
 221                      IOADDR(A_SCD_TRACE_SEQUENCE_1));
 222         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2));
 223         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3));
 224         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4));
 225         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5));
 226         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6));
 227         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
 228
 229         /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
 230         __raw_writeq(1ULL << K_INT_PERF_CNT,
 231                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
 232
 233         arm_tb();
 234
 235         DBG(printk(DEVNAME ": done starting\n"));
 236
 237         return 0;
 238 }
 239
 240 int sbprof_zbprof_stop(void)
 241 {
 242         DEFINE_WAIT(wait);
 243         DBG(printk(DEVNAME ": stopping\n"));
 244
 245         if (sbp.tb_enable) {
 246                 sbp.tb_enable = 0;
 247                 /* XXXKW there is a window here where the intr handler
 248                    may run, see the disable, and do the wake_up before
 249                    this sleep happens. */
 250                 if (sbp.tb_armed) {
 251                         DBG(printk(DEVNAME ": wait for disarm\n"));
 252                         prepare_to_wait(&sbp.tb_sync, &wait, TASK_INTERRUPTIBLE);
 253                         schedule();
 254                         finish_wait(&sbp.tb_sync, &wait);
 255                         DBG(printk(DEVNAME ": disarm complete\n"));
 256                 }
 257                 free_irq(K_INT_TRACE_FREEZE, &sbp);
 258                 free_irq(K_INT_PERF_CNT, &sbp);
 259         }
 260
 261         DBG(printk(DEVNAME ": done stopping\n"));
 262
 263         return 0;
 264 }
 265
 266 static int sbprof_tb_open(struct inode *inode, struct file *filp)
 267 {
 268         int minor;
 269
 270         minor = iminor(inode);
 271         if (minor != 0) {
 272                 return -ENODEV;
 273         }
 274         if (sbp.open) {
 275                 return -EBUSY;
 276         }
 277
 278         memset(&sbp, 0, sizeof(struct sbprof_tb));
 279         sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES);
 280         if (!sbp.sbprof_tbbuf) {
 281                 return -ENOMEM;
 282         }
 283         memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES);
 284         init_waitqueue_head(&sbp.tb_sync);
 285         init_waitqueue_head(&sbp.tb_read);
 286         sbp.open = 1;
 287
 288         return 0;
 289 }
 290
 291 static int sbprof_tb_release(struct inode *inode, struct file *filp)
 292 {
 293         int minor;
 294
 295         minor = iminor(inode);
 296         if (minor != 0 || !sbp.open) {
 297                 return -ENODEV;
 298         }
 299
 300         if (sbp.tb_armed || sbp.tb_enable) {
 301                 sbprof_zbprof_stop();
 302         }
 303
 304         vfree(sbp.sbprof_tbbuf);
 305         sbp.open = 0;
 306
 307         return 0;
 308 }
 309
 310 static ssize_t sbprof_tb_read(struct file *filp, char *buf,
 311                               size_t size, loff_t *offp)
 312 {
 313         int cur_sample, sample_off, cur_count, sample_left;
 314         char *src;
 315         int   count   =  0;
 316         char *dest    =  buf;
 317         long  cur_off = *offp;
 318
 319         count = 0;
 320         cur_sample = cur_off / TB_SAMPLE_SIZE;
 321         sample_off = cur_off % TB_SAMPLE_SIZE;
 322         sample_left = TB_SAMPLE_SIZE - sample_off;
 323         while (size && (cur_sample < sbp.next_tb_sample)) {
 324                 cur_count = size < sample_left ? size : sample_left;
 325                 src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off);
 326                 copy_to_user(dest, src, cur_count);
 327                 DBG(printk(DEVNAME ": read from sample %d, %d bytes\n",
 328                            cur_sample, cur_count));
 329                 size -= cur_count;
 330                 sample_left -= cur_count;
 331                 if (!sample_left) {
 332                         cur_sample++;
 333                         sample_off = 0;
 334                         sample_left = TB_SAMPLE_SIZE;
 335                 } else {
 336                         sample_off += cur_count;
 337                 }
 338                 cur_off += cur_count;
 339                 dest += cur_count;
 340                 count += cur_count;
 341         }
 342         *offp = cur_off;
 343
 344         return count;
 345 }
 346
 347 static long sbprof_tb_ioctl(struct file *filp,
 348                             unsigned int command,
 349                             unsigned long arg)
 350 {
 351         int error = 0;
 352
 353         lock_kernel();
 354         switch (command) {
 355         case SBPROF_ZBSTART:
 356                 error = sbprof_zbprof_start(filp);
 357                 break;
 358         case SBPROF_ZBSTOP:
 359                 error = sbprof_zbprof_stop();
 360                 break;
 361         case SBPROF_ZBWAITFULL:
 362                 DEFINE_WAIT(wait);
 363                 prepare_to_wait(&sbp.tb_read, &wait, TASK_INTERRUPTIBLE);
 364                 schedule();
 365                 finish_wait(&sbp.tb_read, &wait);
 366                 /* XXXKW check if interrupted? */
 367                 return put_user(TB_FULL, (int *) arg);
 368         default:
 369                 error = -EINVAL;
 370                 break;
 371         }
 372         unlock_kernel();
 373
 374         return error;
 375 }
 376
 377 static struct file_operations sbprof_tb_fops = {
 378         .owner          = THIS_MODULE,
 379         .open           = sbprof_tb_open,
 380         .release        = sbprof_tb_release,
 381         .read           = sbprof_tb_read,
 382         .unlocked_ioctl = sbprof_tb_ioctl,
 383         .compat_ioctl   = sbprof_tb_ioctl,
 384         .mmap           = NULL,
 385 };
 386
 387 static int __init sbprof_tb_init(void)
 388 {
 389         if (register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) {
 390                 printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n",
 391                        SBPROF_TB_MAJOR);
 392                 return -EIO;
 393         }
 394         sbp.open = 0;
 395         tb_period = zbbus_mhz * 10000LL;
 396         printk(KERN_INFO DEVNAME ": initialized - tb_period = %lld\n", tb_period);
 397         return 0;
 398 }
 399
 400 static void __exit sbprof_tb_cleanup(void)
 401 {
 402         unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
 403 }
 404
 405 module_init(sbprof_tb_init);
 406 module_exit(sbprof_tb_cleanup);