2 * linux/arch/mips/tx4938/common/irq.c
4 * Common tx4938 irq handler
5 * Copyright (C) 2000-2001 Toshiba Corporation
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
14 #include <linux/errno.h>
15 #include <linux/init.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/signal.h>
19 #include <linux/sched.h>
20 #include <linux/types.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/timex.h>
24 #include <linux/slab.h>
25 #include <linux/random.h>
26 #include <linux/irq.h>
27 #include <asm/bitops.h>
28 #include <asm/bootinfo.h>
31 #include <asm/mipsregs.h>
32 #include <asm/system.h>
33 #include <asm/wbflush.h>
34 #include <asm/tx4938/rbtx4938.h>
36 /**********************************************************************************/
37 /* Forwad definitions for all pic's */
38 /**********************************************************************************/
40 static void tx4938_irq_cp0_enable(unsigned int irq);
41 static void tx4938_irq_cp0_disable(unsigned int irq);
42 static void tx4938_irq_cp0_end(unsigned int irq);
44 static void tx4938_irq_pic_enable(unsigned int irq);
45 static void tx4938_irq_pic_disable(unsigned int irq);
46 static void tx4938_irq_pic_end(unsigned int irq);
48 /**********************************************************************************/
49 /* Kernel structs for all pic's */
50 /**********************************************************************************/
52 #define TX4938_CP0_NAME "TX4938-CP0"
53 static struct irq_chip tx4938_irq_cp0_type = {
54 .typename = TX4938_CP0_NAME,
55 .ack = tx4938_irq_cp0_disable,
56 .mask = tx4938_irq_cp0_disable,
57 .mask_ack = tx4938_irq_cp0_disable,
58 .unmask = tx4938_irq_cp0_enable,
59 .end = tx4938_irq_cp0_end,
62 #define TX4938_PIC_NAME "TX4938-PIC"
63 static struct irq_chip tx4938_irq_pic_type = {
64 .typename = TX4938_PIC_NAME,
65 .ack = tx4938_irq_pic_disable,
66 .mask = tx4938_irq_pic_disable,
67 .mask_ack = tx4938_irq_pic_disable,
68 .unmask = tx4938_irq_pic_enable,
69 .end = tx4938_irq_pic_end,
72 static struct irqaction tx4938_irq_pic_action = {
75 .mask = CPU_MASK_NONE,
76 .name = TX4938_PIC_NAME
79 /**********************************************************************************/
80 /* Functions for cp0 */
81 /**********************************************************************************/
83 #define tx4938_irq_cp0_mask(irq) ( 1 << ( irq-TX4938_IRQ_CP0_BEG+8 ) )
86 tx4938_irq_cp0_init(void)
90 for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++)
91 set_irq_chip_and_handler(i, &tx4938_irq_cp0_type,
96 tx4938_irq_cp0_enable(unsigned int irq)
98 set_c0_status(tx4938_irq_cp0_mask(irq));
102 tx4938_irq_cp0_disable(unsigned int irq)
104 clear_c0_status(tx4938_irq_cp0_mask(irq));
108 tx4938_irq_cp0_end(unsigned int irq)
110 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
111 tx4938_irq_cp0_enable(irq);
115 /**********************************************************************************/
116 /* Functions for pic */
117 /**********************************************************************************/
120 tx4938_irq_pic_addr(int irq)
122 /* MVMCP -- need to formulize this */
123 irq -= TX4938_IRQ_PIC_BEG;
130 return (TX4938_MKA(TX4938_IRC_IRLVL0));
136 return (TX4938_MKA(TX4938_IRC_IRLVL1));
142 return (TX4938_MKA(TX4938_IRC_IRLVL2));
148 return (TX4938_MKA(TX4938_IRC_IRLVL3));
154 return (TX4938_MKA(TX4938_IRC_IRLVL4));
160 return (TX4938_MKA(TX4938_IRC_IRLVL5));
166 return (TX4938_MKA(TX4938_IRC_IRLVL6));
172 return (TX4938_MKA(TX4938_IRC_IRLVL7));
180 tx4938_irq_pic_mask(int irq)
182 /* MVMCP -- need to formulize this */
183 irq -= TX4938_IRQ_PIC_BEG;
231 tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits)
233 unsigned long val = 0;
235 val = TX4938_RD(pic_reg);
238 TX4938_WR(pic_reg, val);
244 tx4938_irq_pic_init(void)
248 for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++)
249 set_irq_chip_and_handler(i, &tx4938_irq_pic_type,
252 setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action);
254 TX4938_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */
255 TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */
259 tx4938_irq_pic_enable(unsigned int irq)
261 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0,
262 tx4938_irq_pic_mask(irq));
266 tx4938_irq_pic_disable(unsigned int irq)
268 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq),
269 tx4938_irq_pic_mask(irq), 0);
273 tx4938_irq_pic_end(unsigned int irq)
275 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
276 tx4938_irq_pic_enable(irq);
280 /**********************************************************************************/
281 /* Main init functions */
282 /**********************************************************************************/
285 tx4938_irq_init(void)
287 tx4938_irq_cp0_init();
288 tx4938_irq_pic_init();
292 tx4938_irq_nested(void)
297 level2 = TX4938_RD(0xff1ff6a0);
298 if ((level2 & 0x10000) == 0) {
300 sw_irq = TX4938_IRQ_PIC_BEG + level2;
303 extern int toshiba_rbtx4938_irq_nested(int sw_irq);
304 sw_irq = toshiba_rbtx4938_irq_nested(sw_irq);
313 asmlinkage void plat_irq_dispatch(void)
315 unsigned int pending = read_c0_cause() & read_c0_status();
317 if (pending & STATUSF_IP7)
318 do_IRQ(TX4938_IRQ_CPU_TIMER);
319 else if (pending & STATUSF_IP2) {
320 int irq = tx4938_irq_nested();
324 spurious_interrupt();
325 } else if (pending & STATUSF_IP1)
326 do_IRQ(TX4938_IRQ_USER1);
327 else if (pending & STATUSF_IP0)
328 do_IRQ(TX4938_IRQ_USER0);