4 * I2C adapter for the PXA I2C bus access.
6 * Copyright (C) 2002 Intrinsyc Software Inc.
7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * Apr 2002: Initial version [CS]
15 * Jun 2002: Properly seperated algo/adap [FB]
16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20 * Feb 2005: Rework slave mode handling [RMK]
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/i2c-id.h>
26 #include <linux/init.h>
27 #include <linux/time.h>
28 #include <linux/sched.h>
29 #include <linux/delay.h>
30 #include <linux/errno.h>
31 #include <linux/interrupt.h>
32 #include <linux/i2c-pxa.h>
33 #include <linux/platform_device.h>
35 #include <asm/hardware.h>
37 #include <asm/arch/i2c.h>
38 #include <asm/arch/pxa-regs.h>
42 wait_queue_head_t wait;
47 unsigned int slave_addr;
49 struct i2c_adapter adap;
50 #ifdef CONFIG_I2C_PXA_SLAVE
51 struct i2c_slave_client *slave;
54 unsigned int irqlogidx;
60 * I2C Slave mode address
62 #define I2C_PXA_SLAVE_ADDR 0x1
71 #define BIT(m, s, u) { .mask = m, .set = s, .unset = u }
74 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
76 printk("%s %08x: ", prefix, val);
78 const char *str = val & bits->mask ? bits->set : bits->unset;
85 static const struct bits isr_bits[] = {
86 BIT(ISR_RWM, "RX", "TX"),
87 BIT(ISR_ACKNAK, "NAK", "ACK"),
88 BIT(ISR_UB, "Bsy", "Rdy"),
89 BIT(ISR_IBB, "BusBsy", "BusRdy"),
90 BIT(ISR_SSD, "SlaveStop", NULL),
91 BIT(ISR_ALD, "ALD", NULL),
92 BIT(ISR_ITE, "TxEmpty", NULL),
93 BIT(ISR_IRF, "RxFull", NULL),
94 BIT(ISR_GCAD, "GenCall", NULL),
95 BIT(ISR_SAD, "SlaveAddr", NULL),
96 BIT(ISR_BED, "BusErr", NULL),
99 static void decode_ISR(unsigned int val)
101 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
105 static const struct bits icr_bits[] = {
106 BIT(ICR_START, "START", NULL),
107 BIT(ICR_STOP, "STOP", NULL),
108 BIT(ICR_ACKNAK, "ACKNAK", NULL),
109 BIT(ICR_TB, "TB", NULL),
110 BIT(ICR_MA, "MA", NULL),
111 BIT(ICR_SCLE, "SCLE", "scle"),
112 BIT(ICR_IUE, "IUE", "iue"),
113 BIT(ICR_GCD, "GCD", NULL),
114 BIT(ICR_ITEIE, "ITEIE", NULL),
115 BIT(ICR_IRFIE, "IRFIE", NULL),
116 BIT(ICR_BEIE, "BEIE", NULL),
117 BIT(ICR_SSDIE, "SSDIE", NULL),
118 BIT(ICR_ALDIE, "ALDIE", NULL),
119 BIT(ICR_SADIE, "SADIE", NULL),
120 BIT(ICR_UR, "UR", "ur"),
123 static void decode_ICR(unsigned int val)
125 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
129 static unsigned int i2c_debug = DEBUG;
131 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
133 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, ISR, ICR, IBMR);
136 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __FUNCTION__)
140 #define show_state(i2c) do { } while (0)
141 #define decode_ISR(val) do { } while (0)
142 #define decode_ICR(val) do { } while (0)
145 #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0)
147 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
149 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
152 printk("i2c: error: %s\n", why);
153 printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
154 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
155 printk("i2c: ICR: %08x ISR: %08x\n"
156 "i2c: log: ", ICR, ISR);
157 for (i = 0; i < i2c->irqlogidx; i++)
158 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
162 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
164 return !(ICR & ICR_SCLE);
167 static void i2c_pxa_abort(struct pxa_i2c *i2c)
169 unsigned long timeout = jiffies + HZ/4;
171 if (i2c_pxa_is_slavemode(i2c)) {
172 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
176 while (time_before(jiffies, timeout) && (IBMR & 0x1) == 0) {
177 unsigned long icr = ICR;
180 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
189 ICR &= ~(ICR_MA | ICR_START | ICR_STOP);
192 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
194 int timeout = DEF_TIMEOUT;
196 while (timeout-- && ISR & (ISR_IBB | ISR_UB)) {
197 if ((ISR & ISR_SAD) != 0)
207 return timeout <= 0 ? I2C_RETRY : 0;
210 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
212 unsigned long timeout = jiffies + HZ*4;
214 while (time_before(jiffies, timeout)) {
216 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
217 __func__, (long)jiffies, ISR, ICR, IBMR);
221 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
225 /* wait for unit and bus being not busy, and we also do a
226 * quick check of the i2c lines themselves to ensure they've
229 if ((ISR & (ISR_UB | ISR_IBB)) == 0 && IBMR == 3) {
231 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
239 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
244 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
247 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
249 if ((ISR & (ISR_UB | ISR_IBB)) != 0) {
250 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
251 if (!i2c_pxa_wait_master(i2c)) {
252 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
261 #ifdef CONFIG_I2C_PXA_SLAVE
262 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
264 unsigned long timeout = jiffies + HZ*1;
270 while (time_before(jiffies, timeout)) {
272 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
273 __func__, (long)jiffies, ISR, ICR, IBMR);
275 if ((ISR & (ISR_UB|ISR_IBB)) == 0 ||
276 (ISR & ISR_SAD) != 0 ||
277 (ICR & ICR_SCLE) == 0) {
279 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
287 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
292 * clear the hold on the bus, and take of anything else
293 * that has been configured
295 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
300 udelay(100); /* simple delay */
302 /* we need to wait for the stop condition to end */
304 /* if we where in stop, then clear... */
305 if (ICR & ICR_STOP) {
310 if (!i2c_pxa_wait_slave(i2c)) {
311 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
317 ICR &= ~(ICR_STOP|ICR_ACKNAK|ICR_MA);
321 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", ICR, ISR);
326 #define i2c_pxa_set_slave(i2c, err) do { } while (0)
329 static void i2c_pxa_reset(struct pxa_i2c *i2c)
331 pr_debug("Resetting I2C Controller Unit\n");
333 /* abort any transfer currently under way */
336 /* reset according to 9.8 */
341 ISAR = i2c->slave_addr;
343 /* set control register values */
346 #ifdef CONFIG_I2C_PXA_SLAVE
347 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
348 ICR |= ICR_SADIE | ICR_ALDIE | ICR_SSDIE;
351 i2c_pxa_set_slave(i2c, 0);
359 #ifdef CONFIG_I2C_PXA_SLAVE
361 * I2C EEPROM emulation.
363 static struct i2c_eeprom_emu eeprom = {
364 .size = I2C_EEPROM_EMU_SIZE,
365 .watch = LIST_HEAD_INIT(eeprom.watch),
368 struct i2c_eeprom_emu *i2c_pxa_get_eeprom(void)
373 int i2c_eeprom_emu_addwatcher(struct i2c_eeprom_emu *emu, void *data,
374 unsigned int addr, unsigned int size,
375 struct i2c_eeprom_emu_watcher *watcher)
377 struct i2c_eeprom_emu_watch *watch;
380 if (addr + size > emu->size)
383 watch = kmalloc(sizeof(struct i2c_eeprom_emu_watch), GFP_KERNEL);
386 watch->end = addr + size - 1;
387 watch->ops = watcher;
390 local_irq_save(flags);
391 list_add(&watch->node, &emu->watch);
392 local_irq_restore(flags);
395 return watch ? 0 : -ENOMEM;
398 void i2c_eeprom_emu_delwatcher(struct i2c_eeprom_emu *emu, void *data,
399 struct i2c_eeprom_emu_watcher *watcher)
401 struct i2c_eeprom_emu_watch *watch, *n;
404 list_for_each_entry_safe(watch, n, &emu->watch, node) {
405 if (watch->ops == watcher && watch->data == data) {
406 local_irq_save(flags);
407 list_del(&watch->node);
408 local_irq_restore(flags);
414 static void i2c_eeprom_emu_event(void *ptr, i2c_slave_event_t event)
416 struct i2c_eeprom_emu *emu = ptr;
418 eedbg(3, "i2c_eeprom_emu_event: %d\n", event);
421 case I2C_SLAVE_EVENT_START_WRITE:
423 eedbg(2, "i2c_eeprom: write initiated\n");
426 case I2C_SLAVE_EVENT_START_READ:
428 eedbg(2, "i2c_eeprom: read initiated\n");
431 case I2C_SLAVE_EVENT_STOP:
433 eedbg(2, "i2c_eeprom: received stop\n");
437 eedbg(0, "i2c_eeprom: unhandled event\n");
442 static int i2c_eeprom_emu_read(void *ptr)
444 struct i2c_eeprom_emu *emu = ptr;
447 ret = emu->bytes[emu->ptr];
448 emu->ptr = (emu->ptr + 1) % emu->size;
453 static void i2c_eeprom_emu_write(void *ptr, unsigned int val)
455 struct i2c_eeprom_emu *emu = ptr;
456 struct i2c_eeprom_emu_watch *watch;
458 if (emu->seen_start != 0) {
459 eedbg(2, "i2c_eeprom_emu_write: setting ptr %02x\n", val);
465 emu->bytes[emu->ptr] = val;
467 eedbg(1, "i2c_eeprom_emu_write: ptr=0x%02x, val=0x%02x\n",
470 list_for_each_entry(watch, &emu->watch, node) {
471 if (!watch->ops || !watch->ops->write)
473 if (watch->start <= emu->ptr && watch->end >= emu->ptr)
474 watch->ops->write(watch->data, emu->ptr, val);
477 emu->ptr = (emu->ptr + 1) % emu->size;
480 struct i2c_slave_client eeprom_client = {
482 .event = i2c_eeprom_emu_event,
483 .read = i2c_eeprom_emu_read,
484 .write = i2c_eeprom_emu_write
491 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
494 /* what should we do here? */
498 if (i2c->slave != NULL)
499 ret = i2c->slave->read(i2c->slave->data);
502 ICR |= ICR_TB; /* allow next byte */
506 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
508 unsigned int byte = IDBR;
510 if (i2c->slave != NULL)
511 i2c->slave->write(i2c->slave->data, byte);
516 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
521 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
522 (isr & ISR_RWM) ? 'r' : 't');
524 if (i2c->slave != NULL)
525 i2c->slave->event(i2c->slave->data,
526 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
529 * slave could interrupt in the middle of us generating a
530 * start condition... if this happens, we'd better back off
531 * and stop holding the poor thing up
533 ICR &= ~(ICR_START|ICR_STOP);
545 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
553 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
556 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
558 if (i2c->slave != NULL)
559 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
562 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
565 * If we have a master-mode message waiting,
566 * kick it off now that the slave has completed.
569 i2c_pxa_master_complete(i2c, I2C_RETRY);
572 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
575 /* what should we do here? */
582 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
584 ICR |= ICR_TB | ICR_ACKNAK;
587 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
592 * slave could interrupt in the middle of us generating a
593 * start condition... if this happens, we'd better back off
594 * and stop holding the poor thing up
596 ICR &= ~(ICR_START|ICR_STOP);
597 ICR |= ICR_TB | ICR_ACKNAK;
608 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
616 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
619 i2c_pxa_master_complete(i2c, I2C_RETRY);
624 * PXA I2C Master mode
627 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
629 unsigned int addr = (msg->addr & 0x7f) << 1;
631 if (msg->flags & I2C_M_RD)
637 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
642 * Step 1: target slave address into IDBR
644 IDBR = i2c_pxa_addr_byte(i2c->msg);
647 * Step 2: initiate the write.
649 icr = ICR & ~(ICR_STOP | ICR_ALDIE);
650 ICR = icr | ICR_START | ICR_TB;
654 * We are protected by the adapter bus mutex.
656 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
662 * Wait for the bus to become free.
664 ret = i2c_pxa_wait_bus_not_busy(i2c);
666 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
673 ret = i2c_pxa_set_master(i2c);
675 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
679 spin_lock_irq(&i2c->lock);
687 i2c_pxa_start_message(i2c);
689 spin_unlock_irq(&i2c->lock);
692 * The rest of the processing occurs in the interrupt handler.
694 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
697 * We place the return code in i2c->msg_idx.
702 i2c_pxa_scream_blue_murder(i2c, "timeout");
709 * i2c_pxa_master_complete - complete the message and wake up.
711 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
722 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
724 u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
728 * If ISR_ALD is set, we lost arbitration.
732 * Do we need to do anything here? The PXA docs
733 * are vague about what happens.
735 i2c_pxa_scream_blue_murder(i2c, "ALD set");
738 * We ignore this error. We seem to see spurious ALDs
739 * for seemingly no reason. If we handle them as I think
740 * they should, we end up causing an I2C error, which
741 * is painful for some systems.
750 * I2C bus error - either the device NAK'd us, or
751 * something more serious happened. If we were NAK'd
752 * on the initial address phase, we can retry.
754 if (isr & ISR_ACKNAK) {
755 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
760 i2c_pxa_master_complete(i2c, ret);
761 } else if (isr & ISR_RWM) {
763 * Read mode. We have just sent the address byte, and
764 * now we must initiate the transfer.
766 if (i2c->msg_ptr == i2c->msg->len - 1 &&
767 i2c->msg_idx == i2c->msg_num - 1)
768 icr |= ICR_STOP | ICR_ACKNAK;
770 icr |= ICR_ALDIE | ICR_TB;
771 } else if (i2c->msg_ptr < i2c->msg->len) {
773 * Write mode. Write the next data byte.
775 IDBR = i2c->msg->buf[i2c->msg_ptr++];
777 icr |= ICR_ALDIE | ICR_TB;
780 * If this is the last byte of the last message, send
783 if (i2c->msg_ptr == i2c->msg->len &&
784 i2c->msg_idx == i2c->msg_num - 1)
786 } else if (i2c->msg_idx < i2c->msg_num - 1) {
788 * Next segment of the message.
795 * If we aren't doing a repeated start and address,
796 * go back and try to send the next byte. Note that
797 * we do not support switching the R/W direction here.
799 if (i2c->msg->flags & I2C_M_NOSTART)
803 * Write the next address.
805 IDBR = i2c_pxa_addr_byte(i2c->msg);
808 * And trigger a repeated start, and send the byte.
811 icr |= ICR_START | ICR_TB;
813 if (i2c->msg->len == 0) {
815 * Device probes have a message length of zero
816 * and need the bus to be reset before it can
821 i2c_pxa_master_complete(i2c, 0);
824 i2c->icrlog[i2c->irqlogidx-1] = icr;
830 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
832 u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
837 i2c->msg->buf[i2c->msg_ptr++] = IDBR;
839 if (i2c->msg_ptr < i2c->msg->len) {
841 * If this is the last byte of the last
842 * message, send a STOP.
844 if (i2c->msg_ptr == i2c->msg->len - 1)
845 icr |= ICR_STOP | ICR_ACKNAK;
847 icr |= ICR_ALDIE | ICR_TB;
849 i2c_pxa_master_complete(i2c, 0);
852 i2c->icrlog[i2c->irqlogidx-1] = icr;
857 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
859 struct pxa_i2c *i2c = dev_id;
862 if (i2c_debug > 2 && 0) {
863 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
864 __func__, isr, ICR, IBMR);
868 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
869 i2c->isrlog[i2c->irqlogidx++] = isr;
874 * Always clear all pending IRQs.
876 ISR = isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED);
879 i2c_pxa_slave_start(i2c, isr);
881 i2c_pxa_slave_stop(i2c);
883 if (i2c_pxa_is_slavemode(i2c)) {
885 i2c_pxa_slave_txempty(i2c, isr);
887 i2c_pxa_slave_rxfull(i2c, isr);
888 } else if (i2c->msg) {
890 i2c_pxa_irq_txempty(i2c, isr);
892 i2c_pxa_irq_rxfull(i2c, isr);
894 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
901 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
903 struct pxa_i2c *i2c = adap->algo_data;
906 /* If the I2C controller is disabled we need to reset it (probably due
907 to a suspend/resume destroying state). We do this here as we can then
908 avoid worrying about resuming the controller before its users. */
909 if (!(ICR & ICR_IUE))
912 for (i = adap->retries; i >= 0; i--) {
913 ret = i2c_pxa_do_xfer(i2c, msgs, num);
914 if (ret != I2C_RETRY)
918 dev_dbg(&adap->dev, "Retrying transmission\n");
921 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
924 i2c_pxa_set_slave(i2c, ret);
928 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
930 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
933 static const struct i2c_algorithm i2c_pxa_algorithm = {
934 .master_xfer = i2c_pxa_xfer,
935 .functionality = i2c_pxa_functionality,
938 static struct pxa_i2c i2c_pxa = {
939 .lock = SPIN_LOCK_UNLOCKED,
940 .wait = __WAIT_QUEUE_HEAD_INITIALIZER(i2c_pxa.wait),
942 .owner = THIS_MODULE,
943 .algo = &i2c_pxa_algorithm,
944 .name = "pxa2xx-i2c",
949 static int i2c_pxa_probe(struct platform_device *dev)
951 struct pxa_i2c *i2c = &i2c_pxa;
952 #ifdef CONFIG_I2C_PXA_SLAVE
953 struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
958 pxa_gpio_mode(GPIO117_I2CSCL_MD);
959 pxa_gpio_mode(GPIO118_I2CSDA_MD);
963 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
965 #ifdef CONFIG_I2C_PXA_SLAVE
966 i2c->slave = &eeprom_client;
968 i2c->slave_addr = plat->slave_addr;
970 i2c->slave = plat->slave;
974 pxa_set_cken(CKEN14_I2C, 1);
975 ret = request_irq(IRQ_I2C, i2c_pxa_handler, IRQF_DISABLED,
982 i2c->adap.algo_data = i2c;
983 i2c->adap.dev.parent = &dev->dev;
985 ret = i2c_add_adapter(&i2c->adap);
987 printk(KERN_INFO "I2C: Failed to add bus\n");
991 platform_set_drvdata(dev, i2c);
993 #ifdef CONFIG_I2C_PXA_SLAVE
994 printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
995 i2c->adap.dev.bus_id, i2c->slave_addr);
997 printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
998 i2c->adap.dev.bus_id);
1003 free_irq(IRQ_I2C, i2c);
1008 static int i2c_pxa_remove(struct platform_device *dev)
1010 struct pxa_i2c *i2c = platform_get_drvdata(dev);
1012 platform_set_drvdata(dev, NULL);
1014 i2c_del_adapter(&i2c->adap);
1015 free_irq(IRQ_I2C, i2c);
1016 pxa_set_cken(CKEN14_I2C, 0);
1021 static struct platform_driver i2c_pxa_driver = {
1022 .probe = i2c_pxa_probe,
1023 .remove = i2c_pxa_remove,
1025 .name = "pxa2xx-i2c",
1029 static int __init i2c_adap_pxa_init(void)
1031 return platform_driver_register(&i2c_pxa_driver);
1034 static void i2c_adap_pxa_exit(void)
1036 return platform_driver_unregister(&i2c_pxa_driver);
1039 MODULE_LICENSE("GPL");
1041 module_init(i2c_adap_pxa_init);
1042 module_exit(i2c_adap_pxa_exit);