git.oblomov.eu Git - linux-2.6/blob - drivers/net/qlge/qlge_main.c

   1 /*
   2  * QLogic qlge NIC HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  * See LICENSE.qlge for copyright and licensing details.
   5  * Author:     Linux qlge network device driver by
   6  *                      Ron Mercer <ron.mercer@qlogic.com>
   7  */
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/pagemap.h>
  16 #include <linux/sched.h>
  17 #include <linux/slab.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/mempool.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/kthread.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/errno.h>
  24 #include <linux/ioport.h>
  25 #include <linux/in.h>
  26 #include <linux/ip.h>
  27 #include <linux/ipv6.h>
  28 #include <net/ipv6.h>
  29 #include <linux/tcp.h>
  30 #include <linux/udp.h>
  31 #include <linux/if_arp.h>
  32 #include <linux/if_ether.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/rtnetlink.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/delay.h>
  40 #include <linux/mm.h>
  41 #include <linux/vmalloc.h>
  42 #include <net/ip6_checksum.h>
  43
  44 #include "qlge.h"
  45
  46 char qlge_driver_name[] = DRV_NAME;
  47 const char qlge_driver_version[] = DRV_VERSION;
  48
  49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
  50 MODULE_DESCRIPTION(DRV_STRING " ");
  51 MODULE_LICENSE("GPL");
  52 MODULE_VERSION(DRV_VERSION);
  53
  54 static const u32 default_msg =
  55     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
  56 /* NETIF_MSG_TIMER |    */
  57     NETIF_MSG_IFDOWN |
  58     NETIF_MSG_IFUP |
  59     NETIF_MSG_RX_ERR |
  60     NETIF_MSG_TX_ERR |
  61     NETIF_MSG_TX_QUEUED |
  62     NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS |
  63 /* NETIF_MSG_PKTDATA | */
  64     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
  65
  66 static int debug = 0x00007fff;  /* defaults above */
  67 module_param(debug, int, 0);
  68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  69
  70 #define MSIX_IRQ 0
  71 #define MSI_IRQ 1
  72 #define LEG_IRQ 2
  73 static int irq_type = MSIX_IRQ;
  74 module_param(irq_type, int, MSIX_IRQ);
  75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
  76
  77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
  78         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID)},
  79         /* required last entry */
  80         {0,}
  81 };
  82
  83 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
  84
  85 /* This hardware semaphore causes exclusive access to
  86  * resources shared between the NIC driver, MPI firmware,
  87  * FCOE firmware and the FC driver.
  88  */
  89 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
  90 {
  91         u32 sem_bits = 0;
  92
  93         switch (sem_mask) {
  94         case SEM_XGMAC0_MASK:
  95                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
  96                 break;
  97         case SEM_XGMAC1_MASK:
  98                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
  99                 break;
 100         case SEM_ICB_MASK:
 101                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
 102                 break;
 103         case SEM_MAC_ADDR_MASK:
 104                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
 105                 break;
 106         case SEM_FLASH_MASK:
 107                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
 108                 break;
 109         case SEM_PROBE_MASK:
 110                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
 111                 break;
 112         case SEM_RT_IDX_MASK:
 113                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
 114                 break;
 115         case SEM_PROC_REG_MASK:
 116                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
 117                 break;
 118         default:
 119                 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
 120                 return -EINVAL;
 121         }
 122
 123         ql_write32(qdev, SEM, sem_bits | sem_mask);
 124         return !(ql_read32(qdev, SEM) & sem_bits);
 125 }
 126
 127 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
 128 {
 129         unsigned int wait_count = 30;
 130         do {
 131                 if (!ql_sem_trylock(qdev, sem_mask))
 132                         return 0;
 133                 udelay(100);
 134         } while (--wait_count);
 135         return -ETIMEDOUT;
 136 }
 137
 138 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
 139 {
 140         ql_write32(qdev, SEM, sem_mask);
 141         ql_read32(qdev, SEM);   /* flush */
 142 }
 143
 144 /* This function waits for a specific bit to come ready
 145  * in a given register.  It is used mostly by the initialize
 146  * process, but is also used in kernel thread API such as
 147  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
 148  */
 149 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
 150 {
 151         u32 temp;
 152         int count = UDELAY_COUNT;
 153
 154         while (count) {
 155                 temp = ql_read32(qdev, reg);
 156
 157                 /* check for errors */
 158                 if (temp & err_bit) {
 159                         QPRINTK(qdev, PROBE, ALERT,
 160                                 "register 0x%.08x access error, value = 0x%.08x!.\n",
 161                                 reg, temp);
 162                         return -EIO;
 163                 } else if (temp & bit)
 164                         return 0;
 165                 udelay(UDELAY_DELAY);
 166                 count--;
 167         }
 168         QPRINTK(qdev, PROBE, ALERT,
 169                 "Timed out waiting for reg %x to come ready.\n", reg);
 170         return -ETIMEDOUT;
 171 }
 172
 173 /* The CFG register is used to download TX and RX control blocks
 174  * to the chip. This function waits for an operation to complete.
 175  */
 176 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
 177 {
 178         int count = UDELAY_COUNT;
 179         u32 temp;
 180
 181         while (count) {
 182                 temp = ql_read32(qdev, CFG);
 183                 if (temp & CFG_LE)
 184                         return -EIO;
 185                 if (!(temp & bit))
 186                         return 0;
 187                 udelay(UDELAY_DELAY);
 188                 count--;
 189         }
 190         return -ETIMEDOUT;
 191 }
 192
 193
 194 /* Used to issue init control blocks to hw. Maps control block,
 195  * sets address, triggers download, waits for completion.
 196  */
 197 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
 198                  u16 q_id)
 199 {
 200         u64 map;
 201         int status = 0;
 202         int direction;
 203         u32 mask;
 204         u32 value;
 205
 206         direction =
 207             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
 208             PCI_DMA_FROMDEVICE;
 209
 210         map = pci_map_single(qdev->pdev, ptr, size, direction);
 211         if (pci_dma_mapping_error(qdev->pdev, map)) {
 212                 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
 213                 return -ENOMEM;
 214         }
 215
 216         status = ql_wait_cfg(qdev, bit);
 217         if (status) {
 218                 QPRINTK(qdev, IFUP, ERR,
 219                         "Timed out waiting for CFG to come ready.\n");
 220                 goto exit;
 221         }
 222
 223         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
 224         if (status)
 225                 goto exit;
 226         ql_write32(qdev, ICB_L, (u32) map);
 227         ql_write32(qdev, ICB_H, (u32) (map >> 32));
 228         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
 229
 230         mask = CFG_Q_MASK | (bit << 16);
 231         value = bit | (q_id << CFG_Q_SHIFT);
 232         ql_write32(qdev, CFG, (mask | value));
 233
 234         /*
 235          * Wait for the bit to clear after signaling hw.
 236          */
 237         status = ql_wait_cfg(qdev, bit);
 238 exit:
 239         pci_unmap_single(qdev->pdev, map, size, direction);
 240         return status;
 241 }
 242
 243 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
 244 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
 245                         u32 *value)
 246 {
 247         u32 offset = 0;
 248         int status;
 249
 250         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
 251         if (status)
 252                 return status;
 253         switch (type) {
 254         case MAC_ADDR_TYPE_MULTI_MAC:
 255         case MAC_ADDR_TYPE_CAM_MAC:
 256                 {
 257                         status =
 258                             ql_wait_reg_rdy(qdev,
 259                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 260                         if (status)
 261                                 goto exit;
 262                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 263                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 264                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 265                         status =
 266                             ql_wait_reg_rdy(qdev,
 267                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 268                         if (status)
 269                                 goto exit;
 270                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 271                         status =
 272                             ql_wait_reg_rdy(qdev,
 273                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 274                         if (status)
 275                                 goto exit;
 276                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 277                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 278                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 279                         status =
 280                             ql_wait_reg_rdy(qdev,
 281                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 282                         if (status)
 283                                 goto exit;
 284                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 285                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 286                                 status =
 287                                     ql_wait_reg_rdy(qdev,
 288                                         MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 289                                 if (status)
 290                                         goto exit;
 291                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 292                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
 293                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 294                                 status =
 295                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
 296                                                     MAC_ADDR_MR, 0);
 297                                 if (status)
 298                                         goto exit;
 299                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 300                         }
 301                         break;
 302                 }
 303         case MAC_ADDR_TYPE_VLAN:
 304         case MAC_ADDR_TYPE_MULTI_FLTR:
 305         default:
 306                 QPRINTK(qdev, IFUP, CRIT,
 307                         "Address type %d not yet supported.\n", type);
 308                 status = -EPERM;
 309         }
 310 exit:
 311         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
 312         return status;
 313 }
 314
 315 /* Set up a MAC, multicast or VLAN address for the
 316  * inbound frame matching.
 317  */
 318 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
 319                                u16 index)
 320 {
 321         u32 offset = 0;
 322         int status = 0;
 323
 324         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
 325         if (status)
 326                 return status;
 327         switch (type) {
 328         case MAC_ADDR_TYPE_MULTI_MAC:
 329         case MAC_ADDR_TYPE_CAM_MAC:
 330                 {
 331                         u32 cam_output;
 332                         u32 upper = (addr[0] << 8) | addr[1];
 333                         u32 lower =
 334                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
 335                             (addr[5]);
 336
 337                         QPRINTK(qdev, IFUP, INFO,
 338                                 "Adding %s address %pM"
 339                                 " at index %d in the CAM.\n",
 340                                 ((type ==
 341                                   MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
 342                                  "UNICAST"), addr, index);
 343
 344                         status =
 345                             ql_wait_reg_rdy(qdev,
 346                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 347                         if (status)
 348                                 goto exit;
 349                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 350                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 351                                    type);       /* type */
 352                         ql_write32(qdev, MAC_ADDR_DATA, lower);
 353                         status =
 354                             ql_wait_reg_rdy(qdev,
 355                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 356                         if (status)
 357                                 goto exit;
 358                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 359                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 360                                    type);       /* type */
 361                         ql_write32(qdev, MAC_ADDR_DATA, upper);
 362                         status =
 363                             ql_wait_reg_rdy(qdev,
 364                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 365                         if (status)
 366                                 goto exit;
 367                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
 368                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 369                                    type);       /* type */
 370                         /* This field should also include the queue id
 371                            and possibly the function id.  Right now we hardcode
 372                            the route field to NIC core.
 373                          */
 374                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 375                                 cam_output = (CAM_OUT_ROUTE_NIC |
 376                                               (qdev->
 377                                                func << CAM_OUT_FUNC_SHIFT) |
 378                                               (qdev->
 379                                                rss_ring_first_cq_id <<
 380                                                CAM_OUT_CQ_ID_SHIFT));
 381                                 if (qdev->vlgrp)
 382                                         cam_output |= CAM_OUT_RV;
 383                                 /* route to NIC core */
 384                                 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
 385                         }
 386                         break;
 387                 }
 388         case MAC_ADDR_TYPE_VLAN:
 389                 {
 390                         u32 enable_bit = *((u32 *) &addr[0]);
 391                         /* For VLAN, the addr actually holds a bit that
 392                          * either enables or disables the vlan id we are
 393                          * addressing. It's either MAC_ADDR_E on or off.
 394                          * That's bit-27 we're talking about.
 395                          */
 396                         QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
 397                                 (enable_bit ? "Adding" : "Removing"),
 398                                 index, (enable_bit ? "to" : "from"));
 399
 400                         status =
 401                             ql_wait_reg_rdy(qdev,
 402                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 403                         if (status)
 404                                 goto exit;
 405                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
 406                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 407                                    type |       /* type */
 408                                    enable_bit); /* enable/disable */
 409                         break;
 410                 }
 411         case MAC_ADDR_TYPE_MULTI_FLTR:
 412         default:
 413                 QPRINTK(qdev, IFUP, CRIT,
 414                         "Address type %d not yet supported.\n", type);
 415                 status = -EPERM;
 416         }
 417 exit:
 418         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
 419         return status;
 420 }
 421
 422 /* Get a specific frame routing value from the CAM.
 423  * Used for debug and reg dump.
 424  */
 425 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
 426 {
 427         int status = 0;
 428
 429         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
 430         if (status)
 431                 goto exit;
 432
 433         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 434         if (status)
 435                 goto exit;
 436
 437         ql_write32(qdev, RT_IDX,
 438                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
 439         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
 440         if (status)
 441                 goto exit;
 442         *value = ql_read32(qdev, RT_DATA);
 443 exit:
 444         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
 445         return status;
 446 }
 447
 448 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
 449  * to route different frame types to various inbound queues.  We send broadcast/
 450  * multicast/error frames to the default queue for slow handling,
 451  * and CAM hit/RSS frames to the fast handling queues.
 452  */
 453 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
 454                               int enable)
 455 {
 456         int status;
 457         u32 value = 0;
 458
 459         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
 460         if (status)
 461                 return status;
 462
 463         QPRINTK(qdev, IFUP, DEBUG,
 464                 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
 465                 (enable ? "Adding" : "Removing"),
 466                 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
 467                 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
 468                 ((index ==
 469                   RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
 470                 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
 471                 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
 472                 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
 473                 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
 474                 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
 475                 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
 476                 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
 477                 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
 478                 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
 479                 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
 480                 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
 481                 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
 482                 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
 483                 (enable ? "to" : "from"));
 484
 485         switch (mask) {
 486         case RT_IDX_CAM_HIT:
 487                 {
 488                         value = RT_IDX_DST_CAM_Q |      /* dest */
 489                             RT_IDX_TYPE_NICQ |  /* type */
 490                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
 491                         break;
 492                 }
 493         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
 494                 {
 495                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 496                             RT_IDX_TYPE_NICQ |  /* type */
 497                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
 498                         break;
 499                 }
 500         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
 501                 {
 502                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 503                             RT_IDX_TYPE_NICQ |  /* type */
 504                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
 505                         break;
 506                 }
 507         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
 508                 {
 509                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 510                             RT_IDX_TYPE_NICQ |  /* type */
 511                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
 512                         break;
 513                 }
 514         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
 515                 {
 516                         value = RT_IDX_DST_CAM_Q |      /* dest */
 517                             RT_IDX_TYPE_NICQ |  /* type */
 518                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
 519                         break;
 520                 }
 521         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
 522                 {
 523                         value = RT_IDX_DST_CAM_Q |      /* dest */
 524                             RT_IDX_TYPE_NICQ |  /* type */
 525                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 526                         break;
 527                 }
 528         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
 529                 {
 530                         value = RT_IDX_DST_RSS |        /* dest */
 531                             RT_IDX_TYPE_NICQ |  /* type */
 532                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 533                         break;
 534                 }
 535         case 0:         /* Clear the E-bit on an entry. */
 536                 {
 537                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 538                             RT_IDX_TYPE_NICQ |  /* type */
 539                             (index << RT_IDX_IDX_SHIFT);/* index */
 540                         break;
 541                 }
 542         default:
 543                 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
 544                         mask);
 545                 status = -EPERM;
 546                 goto exit;
 547         }
 548
 549         if (value) {
 550                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 551                 if (status)
 552                         goto exit;
 553                 value |= (enable ? RT_IDX_E : 0);
 554                 ql_write32(qdev, RT_IDX, value);
 555                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
 556         }
 557 exit:
 558         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
 559         return status;
 560 }
 561
 562 static void ql_enable_interrupts(struct ql_adapter *qdev)
 563 {
 564         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
 565 }
 566
 567 static void ql_disable_interrupts(struct ql_adapter *qdev)
 568 {
 569         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
 570 }
 571
 572 /* If we're running with multiple MSI-X vectors then we enable on the fly.
 573  * Otherwise, we may have multiple outstanding workers and don't want to
 574  * enable until the last one finishes. In this case, the irq_cnt gets
 575  * incremented everytime we queue a worker and decremented everytime
 576  * a worker finishes.  Once it hits zero we enable the interrupt.
 577  */
 578 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 579 {
 580         u32 var = 0;
 581         unsigned long hw_flags = 0;
 582         struct intr_context *ctx = qdev->intr_context + intr;
 583
 584         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
 585                 /* Always enable if we're MSIX multi interrupts and
 586                  * it's not the default (zeroeth) interrupt.
 587                  */
 588                 ql_write32(qdev, INTR_EN,
 589                            ctx->intr_en_mask);
 590                 var = ql_read32(qdev, STS);
 591                 return var;
 592         }
 593
 594         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 595         if (atomic_dec_and_test(&ctx->irq_cnt)) {
 596                 ql_write32(qdev, INTR_EN,
 597                            ctx->intr_en_mask);
 598                 var = ql_read32(qdev, STS);
 599         }
 600         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 601         return var;
 602 }
 603
 604 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 605 {
 606         u32 var = 0;
 607         unsigned long hw_flags;
 608         struct intr_context *ctx;
 609
 610         /* HW disables for us if we're MSIX multi interrupts and
 611          * it's not the default (zeroeth) interrupt.
 612          */
 613         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
 614                 return 0;
 615
 616         ctx = qdev->intr_context + intr;
 617         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 618         if (!atomic_read(&ctx->irq_cnt)) {
 619                 ql_write32(qdev, INTR_EN,
 620                 ctx->intr_dis_mask);
 621                 var = ql_read32(qdev, STS);
 622         }
 623         atomic_inc(&ctx->irq_cnt);
 624         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 625         return var;
 626 }
 627
 628 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
 629 {
 630         int i;
 631         for (i = 0; i < qdev->intr_count; i++) {
 632                 /* The enable call does a atomic_dec_and_test
 633                  * and enables only if the result is zero.
 634                  * So we precharge it here.
 635                  */
 636                 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
 637                         i == 0))
 638                         atomic_set(&qdev->intr_context[i].irq_cnt, 1);
 639                 ql_enable_completion_interrupt(qdev, i);
 640         }
 641
 642 }
 643
 644 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
 645 {
 646         int status = 0;
 647         /* wait for reg to come ready */
 648         status = ql_wait_reg_rdy(qdev,
 649                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 650         if (status)
 651                 goto exit;
 652         /* set up for reg read */
 653         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
 654         /* wait for reg to come ready */
 655         status = ql_wait_reg_rdy(qdev,
 656                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 657         if (status)
 658                 goto exit;
 659          /* This data is stored on flash as an array of
 660          * __le32.  Since ql_read32() returns cpu endian
 661          * we need to swap it back.
 662          */
 663         *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
 664 exit:
 665         return status;
 666 }
 667
 668 static int ql_get_flash_params(struct ql_adapter *qdev)
 669 {
 670         int i;
 671         int status;
 672         __le32 *p = (__le32 *)&qdev->flash;
 673         u32 offset = 0;
 674
 675         /* Second function's parameters follow the first
 676          * function's.
 677          */
 678         if (qdev->func)
 679                 offset = sizeof(qdev->flash) / sizeof(u32);
 680
 681         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 682                 return -ETIMEDOUT;
 683
 684         for (i = 0; i < sizeof(qdev->flash) / sizeof(u32); i++, p++) {
 685                 status = ql_read_flash_word(qdev, i+offset, p);
 686                 if (status) {
 687                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
 688                         goto exit;
 689                 }
 690
 691         }
 692 exit:
 693         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 694         return status;
 695 }
 696
 697 /* xgmac register are located behind the xgmac_addr and xgmac_data
 698  * register pair.  Each read/write requires us to wait for the ready
 699  * bit before reading/writing the data.
 700  */
 701 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
 702 {
 703         int status;
 704         /* wait for reg to come ready */
 705         status = ql_wait_reg_rdy(qdev,
 706                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 707         if (status)
 708                 return status;
 709         /* write the data to the data reg */
 710         ql_write32(qdev, XGMAC_DATA, data);
 711         /* trigger the write */
 712         ql_write32(qdev, XGMAC_ADDR, reg);
 713         return status;
 714 }
 715
 716 /* xgmac register are located behind the xgmac_addr and xgmac_data
 717  * register pair.  Each read/write requires us to wait for the ready
 718  * bit before reading/writing the data.
 719  */
 720 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
 721 {
 722         int status = 0;
 723         /* wait for reg to come ready */
 724         status = ql_wait_reg_rdy(qdev,
 725                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 726         if (status)
 727                 goto exit;
 728         /* set up for reg read */
 729         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
 730         /* wait for reg to come ready */
 731         status = ql_wait_reg_rdy(qdev,
 732                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 733         if (status)
 734                 goto exit;
 735         /* get the data */
 736         *data = ql_read32(qdev, XGMAC_DATA);
 737 exit:
 738         return status;
 739 }
 740
 741 /* This is used for reading the 64-bit statistics regs. */
 742 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
 743 {
 744         int status = 0;
 745         u32 hi = 0;
 746         u32 lo = 0;
 747
 748         status = ql_read_xgmac_reg(qdev, reg, &lo);
 749         if (status)
 750                 goto exit;
 751
 752         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
 753         if (status)
 754                 goto exit;
 755
 756         *data = (u64) lo | ((u64) hi << 32);
 757
 758 exit:
 759         return status;
 760 }
 761
 762 /* Take the MAC Core out of reset.
 763  * Enable statistics counting.
 764  * Take the transmitter/receiver out of reset.
 765  * This functionality may be done in the MPI firmware at a
 766  * later date.
 767  */
 768 static int ql_port_initialize(struct ql_adapter *qdev)
 769 {
 770         int status = 0;
 771         u32 data;
 772
 773         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
 774                 /* Another function has the semaphore, so
 775                  * wait for the port init bit to come ready.
 776                  */
 777                 QPRINTK(qdev, LINK, INFO,
 778                         "Another function has the semaphore, so wait for the port init bit to come ready.\n");
 779                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
 780                 if (status) {
 781                         QPRINTK(qdev, LINK, CRIT,
 782                                 "Port initialize timed out.\n");
 783                 }
 784                 return status;
 785         }
 786
 787         QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
 788         /* Set the core reset. */
 789         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
 790         if (status)
 791                 goto end;
 792         data |= GLOBAL_CFG_RESET;
 793         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 794         if (status)
 795                 goto end;
 796
 797         /* Clear the core reset and turn on jumbo for receiver. */
 798         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
 799         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
 800         data |= GLOBAL_CFG_TX_STAT_EN;
 801         data |= GLOBAL_CFG_RX_STAT_EN;
 802         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 803         if (status)
 804                 goto end;
 805
 806         /* Enable transmitter, and clear it's reset. */
 807         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
 808         if (status)
 809                 goto end;
 810         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
 811         data |= TX_CFG_EN;      /* Enable the transmitter. */
 812         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
 813         if (status)
 814                 goto end;
 815
 816         /* Enable receiver and clear it's reset. */
 817         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
 818         if (status)
 819                 goto end;
 820         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
 821         data |= RX_CFG_EN;      /* Enable the receiver. */
 822         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
 823         if (status)
 824                 goto end;
 825
 826         /* Turn on jumbo. */
 827         status =
 828             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
 829         if (status)
 830                 goto end;
 831         status =
 832             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
 833         if (status)
 834                 goto end;
 835
 836         /* Signal to the world that the port is enabled.        */
 837         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
 838 end:
 839         ql_sem_unlock(qdev, qdev->xg_sem_mask);
 840         return status;
 841 }
 842
 843 /* Get the next large buffer. */
 844 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
 845 {
 846         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
 847         rx_ring->lbq_curr_idx++;
 848         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
 849                 rx_ring->lbq_curr_idx = 0;
 850         rx_ring->lbq_free_cnt++;
 851         return lbq_desc;
 852 }
 853
 854 /* Get the next small buffer. */
 855 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
 856 {
 857         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
 858         rx_ring->sbq_curr_idx++;
 859         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
 860                 rx_ring->sbq_curr_idx = 0;
 861         rx_ring->sbq_free_cnt++;
 862         return sbq_desc;
 863 }
 864
 865 /* Update an rx ring index. */
 866 static void ql_update_cq(struct rx_ring *rx_ring)
 867 {
 868         rx_ring->cnsmr_idx++;
 869         rx_ring->curr_entry++;
 870         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
 871                 rx_ring->cnsmr_idx = 0;
 872                 rx_ring->curr_entry = rx_ring->cq_base;
 873         }
 874 }
 875
 876 static void ql_write_cq_idx(struct rx_ring *rx_ring)
 877 {
 878         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
 879 }
 880
 881 /* Process (refill) a large buffer queue. */
 882 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 883 {
 884         int clean_idx = rx_ring->lbq_clean_idx;
 885         struct bq_desc *lbq_desc;
 886         u64 map;
 887         int i;
 888
 889         while (rx_ring->lbq_free_cnt > 16) {
 890                 for (i = 0; i < 16; i++) {
 891                         QPRINTK(qdev, RX_STATUS, DEBUG,
 892                                 "lbq: try cleaning clean_idx = %d.\n",
 893                                 clean_idx);
 894                         lbq_desc = &rx_ring->lbq[clean_idx];
 895                         if (lbq_desc->p.lbq_page == NULL) {
 896                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 897                                         "lbq: getting new page for index %d.\n",
 898                                         lbq_desc->index);
 899                                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
 900                                 if (lbq_desc->p.lbq_page == NULL) {
 901                                         QPRINTK(qdev, RX_STATUS, ERR,
 902                                                 "Couldn't get a page.\n");
 903                                         return;
 904                                 }
 905                                 map = pci_map_page(qdev->pdev,
 906                                                    lbq_desc->p.lbq_page,
 907                                                    0, PAGE_SIZE,
 908                                                    PCI_DMA_FROMDEVICE);
 909                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
 910                                         QPRINTK(qdev, RX_STATUS, ERR,
 911                                                 "PCI mapping failed.\n");
 912                                         return;
 913                                 }
 914                                 pci_unmap_addr_set(lbq_desc, mapaddr, map);
 915                                 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
 916                                 *lbq_desc->addr = cpu_to_le64(map);
 917                         }
 918                         clean_idx++;
 919                         if (clean_idx == rx_ring->lbq_len)
 920                                 clean_idx = 0;
 921                 }
 922
 923                 rx_ring->lbq_clean_idx = clean_idx;
 924                 rx_ring->lbq_prod_idx += 16;
 925                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
 926                         rx_ring->lbq_prod_idx = 0;
 927                 QPRINTK(qdev, RX_STATUS, DEBUG,
 928                         "lbq: updating prod idx = %d.\n",
 929                         rx_ring->lbq_prod_idx);
 930                 ql_write_db_reg(rx_ring->lbq_prod_idx,
 931                                 rx_ring->lbq_prod_idx_db_reg);
 932                 rx_ring->lbq_free_cnt -= 16;
 933         }
 934 }
 935
 936 /* Process (refill) a small buffer queue. */
 937 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 938 {
 939         int clean_idx = rx_ring->sbq_clean_idx;
 940         struct bq_desc *sbq_desc;
 941         u64 map;
 942         int i;
 943
 944         while (rx_ring->sbq_free_cnt > 16) {
 945                 for (i = 0; i < 16; i++) {
 946                         sbq_desc = &rx_ring->sbq[clean_idx];
 947                         QPRINTK(qdev, RX_STATUS, DEBUG,
 948                                 "sbq: try cleaning clean_idx = %d.\n",
 949                                 clean_idx);
 950                         if (sbq_desc->p.skb == NULL) {
 951                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 952                                         "sbq: getting new skb for index %d.\n",
 953                                         sbq_desc->index);
 954                                 sbq_desc->p.skb =
 955                                     netdev_alloc_skb(qdev->ndev,
 956                                                      rx_ring->sbq_buf_size);
 957                                 if (sbq_desc->p.skb == NULL) {
 958                                         QPRINTK(qdev, PROBE, ERR,
 959                                                 "Couldn't get an skb.\n");
 960                                         rx_ring->sbq_clean_idx = clean_idx;
 961                                         return;
 962                                 }
 963                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
 964                                 map = pci_map_single(qdev->pdev,
 965                                                      sbq_desc->p.skb->data,
 966                                                      rx_ring->sbq_buf_size /
 967                                                      2, PCI_DMA_FROMDEVICE);
 968                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
 969                                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
 970                                         rx_ring->sbq_clean_idx = clean_idx;
 971                                         return;
 972                                 }
 973                                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
 974                                 pci_unmap_len_set(sbq_desc, maplen,
 975                                                   rx_ring->sbq_buf_size / 2);
 976                                 *sbq_desc->addr = cpu_to_le64(map);
 977                         }
 978
 979                         clean_idx++;
 980                         if (clean_idx == rx_ring->sbq_len)
 981                                 clean_idx = 0;
 982                 }
 983                 rx_ring->sbq_clean_idx = clean_idx;
 984                 rx_ring->sbq_prod_idx += 16;
 985                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
 986                         rx_ring->sbq_prod_idx = 0;
 987                 QPRINTK(qdev, RX_STATUS, DEBUG,
 988                         "sbq: updating prod idx = %d.\n",
 989                         rx_ring->sbq_prod_idx);
 990                 ql_write_db_reg(rx_ring->sbq_prod_idx,
 991                                 rx_ring->sbq_prod_idx_db_reg);
 992
 993                 rx_ring->sbq_free_cnt -= 16;
 994         }
 995 }
 996
 997 static void ql_update_buffer_queues(struct ql_adapter *qdev,
 998                                     struct rx_ring *rx_ring)
 999 {
1000         ql_update_sbq(qdev, rx_ring);
1001         ql_update_lbq(qdev, rx_ring);
1002 }
1003
1004 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
1005  * fails at some stage, or from the interrupt when a tx completes.
1006  */
1007 static void ql_unmap_send(struct ql_adapter *qdev,
1008                           struct tx_ring_desc *tx_ring_desc, int mapped)
1009 {
1010         int i;
1011         for (i = 0; i < mapped; i++) {
1012                 if (i == 0 || (i == 7 && mapped > 7)) {
1013                         /*
1014                          * Unmap the skb->data area, or the
1015                          * external sglist (AKA the Outbound
1016                          * Address List (OAL)).
1017                          * If its the zeroeth element, then it's
1018                          * the skb->data area.  If it's the 7th
1019                          * element and there is more than 6 frags,
1020                          * then its an OAL.
1021                          */
1022                         if (i == 7) {
1023                                 QPRINTK(qdev, TX_DONE, DEBUG,
1024                                         "unmapping OAL area.\n");
1025                         }
1026                         pci_unmap_single(qdev->pdev,
1027                                          pci_unmap_addr(&tx_ring_desc->map[i],
1028                                                         mapaddr),
1029                                          pci_unmap_len(&tx_ring_desc->map[i],
1030                                                        maplen),
1031                                          PCI_DMA_TODEVICE);
1032                 } else {
1033                         QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1034                                 i);
1035                         pci_unmap_page(qdev->pdev,
1036                                        pci_unmap_addr(&tx_ring_desc->map[i],
1037                                                       mapaddr),
1038                                        pci_unmap_len(&tx_ring_desc->map[i],
1039                                                      maplen), PCI_DMA_TODEVICE);
1040                 }
1041         }
1042
1043 }
1044
1045 /* Map the buffers for this transmit.  This will return
1046  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1047  */
1048 static int ql_map_send(struct ql_adapter *qdev,
1049                        struct ob_mac_iocb_req *mac_iocb_ptr,
1050                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1051 {
1052         int len = skb_headlen(skb);
1053         dma_addr_t map;
1054         int frag_idx, err, map_idx = 0;
1055         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1056         int frag_cnt = skb_shinfo(skb)->nr_frags;
1057
1058         if (frag_cnt) {
1059                 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1060         }
1061         /*
1062          * Map the skb buffer first.
1063          */
1064         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1065
1066         err = pci_dma_mapping_error(qdev->pdev, map);
1067         if (err) {
1068                 QPRINTK(qdev, TX_QUEUED, ERR,
1069                         "PCI mapping failed with error: %d\n", err);
1070
1071                 return NETDEV_TX_BUSY;
1072         }
1073
1074         tbd->len = cpu_to_le32(len);
1075         tbd->addr = cpu_to_le64(map);
1076         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1077         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1078         map_idx++;
1079
1080         /*
1081          * This loop fills the remainder of the 8 address descriptors
1082          * in the IOCB.  If there are more than 7 fragments, then the
1083          * eighth address desc will point to an external list (OAL).
1084          * When this happens, the remainder of the frags will be stored
1085          * in this list.
1086          */
1087         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1088                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1089                 tbd++;
1090                 if (frag_idx == 6 && frag_cnt > 7) {
1091                         /* Let's tack on an sglist.
1092                          * Our control block will now
1093                          * look like this:
1094                          * iocb->seg[0] = skb->data
1095                          * iocb->seg[1] = frag[0]
1096                          * iocb->seg[2] = frag[1]
1097                          * iocb->seg[3] = frag[2]
1098                          * iocb->seg[4] = frag[3]
1099                          * iocb->seg[5] = frag[4]
1100                          * iocb->seg[6] = frag[5]
1101                          * iocb->seg[7] = ptr to OAL (external sglist)
1102                          * oal->seg[0] = frag[6]
1103                          * oal->seg[1] = frag[7]
1104                          * oal->seg[2] = frag[8]
1105                          * oal->seg[3] = frag[9]
1106                          * oal->seg[4] = frag[10]
1107                          *      etc...
1108                          */
1109                         /* Tack on the OAL in the eighth segment of IOCB. */
1110                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1111                                              sizeof(struct oal),
1112                                              PCI_DMA_TODEVICE);
1113                         err = pci_dma_mapping_error(qdev->pdev, map);
1114                         if (err) {
1115                                 QPRINTK(qdev, TX_QUEUED, ERR,
1116                                         "PCI mapping outbound address list with error: %d\n",
1117                                         err);
1118                                 goto map_error;
1119                         }
1120
1121                         tbd->addr = cpu_to_le64(map);
1122                         /*
1123                          * The length is the number of fragments
1124                          * that remain to be mapped times the length
1125                          * of our sglist (OAL).
1126                          */
1127                         tbd->len =
1128                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1129                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1130                         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1131                                            map);
1132                         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1133                                           sizeof(struct oal));
1134                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1135                         map_idx++;
1136                 }
1137
1138                 map =
1139                     pci_map_page(qdev->pdev, frag->page,
1140                                  frag->page_offset, frag->size,
1141                                  PCI_DMA_TODEVICE);
1142
1143                 err = pci_dma_mapping_error(qdev->pdev, map);
1144                 if (err) {
1145                         QPRINTK(qdev, TX_QUEUED, ERR,
1146                                 "PCI mapping frags failed with error: %d.\n",
1147                                 err);
1148                         goto map_error;
1149                 }
1150
1151                 tbd->addr = cpu_to_le64(map);
1152                 tbd->len = cpu_to_le32(frag->size);
1153                 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1154                 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1155                                   frag->size);
1156
1157         }
1158         /* Save the number of segments we've mapped. */
1159         tx_ring_desc->map_cnt = map_idx;
1160         /* Terminate the last segment. */
1161         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1162         return NETDEV_TX_OK;
1163
1164 map_error:
1165         /*
1166          * If the first frag mapping failed, then i will be zero.
1167          * This causes the unmap of the skb->data area.  Otherwise
1168          * we pass in the number of frags that mapped successfully
1169          * so they can be umapped.
1170          */
1171         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1172         return NETDEV_TX_BUSY;
1173 }
1174
1175 static void ql_realign_skb(struct sk_buff *skb, int len)
1176 {
1177         void *temp_addr = skb->data;
1178
1179         /* Undo the skb_reserve(skb,32) we did before
1180          * giving to hardware, and realign data on
1181          * a 2-byte boundary.
1182          */
1183         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1184         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1185         skb_copy_to_linear_data(skb, temp_addr,
1186                 (unsigned int)len);
1187 }
1188
1189 /*
1190  * This function builds an skb for the given inbound
1191  * completion.  It will be rewritten for readability in the near
1192  * future, but for not it works well.
1193  */
1194 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1195                                        struct rx_ring *rx_ring,
1196                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1197 {
1198         struct bq_desc *lbq_desc;
1199         struct bq_desc *sbq_desc;
1200         struct sk_buff *skb = NULL;
1201         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1202        u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1203
1204         /*
1205          * Handle the header buffer if present.
1206          */
1207         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1208             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1209                 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1210                 /*
1211                  * Headers fit nicely into a small buffer.
1212                  */
1213                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1214                 pci_unmap_single(qdev->pdev,
1215                                 pci_unmap_addr(sbq_desc, mapaddr),
1216                                 pci_unmap_len(sbq_desc, maplen),
1217                                 PCI_DMA_FROMDEVICE);
1218                 skb = sbq_desc->p.skb;
1219                 ql_realign_skb(skb, hdr_len);
1220                 skb_put(skb, hdr_len);
1221                 sbq_desc->p.skb = NULL;
1222         }
1223
1224         /*
1225          * Handle the data buffer(s).
1226          */
1227         if (unlikely(!length)) {        /* Is there data too? */
1228                 QPRINTK(qdev, RX_STATUS, DEBUG,
1229                         "No Data buffer in this packet.\n");
1230                 return skb;
1231         }
1232
1233         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1234                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1235                         QPRINTK(qdev, RX_STATUS, DEBUG,
1236                                 "Headers in small, data of %d bytes in small, combine them.\n", length);
1237                         /*
1238                          * Data is less than small buffer size so it's
1239                          * stuffed in a small buffer.
1240                          * For this case we append the data
1241                          * from the "data" small buffer to the "header" small
1242                          * buffer.
1243                          */
1244                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1245                         pci_dma_sync_single_for_cpu(qdev->pdev,
1246                                                     pci_unmap_addr
1247                                                     (sbq_desc, mapaddr),
1248                                                     pci_unmap_len
1249                                                     (sbq_desc, maplen),
1250                                                     PCI_DMA_FROMDEVICE);
1251                         memcpy(skb_put(skb, length),
1252                                sbq_desc->p.skb->data, length);
1253                         pci_dma_sync_single_for_device(qdev->pdev,
1254                                                        pci_unmap_addr
1255                                                        (sbq_desc,
1256                                                         mapaddr),
1257                                                        pci_unmap_len
1258                                                        (sbq_desc,
1259                                                         maplen),
1260                                                        PCI_DMA_FROMDEVICE);
1261                 } else {
1262                         QPRINTK(qdev, RX_STATUS, DEBUG,
1263                                 "%d bytes in a single small buffer.\n", length);
1264                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1265                         skb = sbq_desc->p.skb;
1266                         ql_realign_skb(skb, length);
1267                         skb_put(skb, length);
1268                         pci_unmap_single(qdev->pdev,
1269                                          pci_unmap_addr(sbq_desc,
1270                                                         mapaddr),
1271                                          pci_unmap_len(sbq_desc,
1272                                                        maplen),
1273                                          PCI_DMA_FROMDEVICE);
1274                         sbq_desc->p.skb = NULL;
1275                 }
1276         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1277                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1278                         QPRINTK(qdev, RX_STATUS, DEBUG,
1279                                 "Header in small, %d bytes in large. Chain large to small!\n", length);
1280                         /*
1281                          * The data is in a single large buffer.  We
1282                          * chain it to the header buffer's skb and let
1283                          * it rip.
1284                          */
1285                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1286                         pci_unmap_page(qdev->pdev,
1287                                        pci_unmap_addr(lbq_desc,
1288                                                       mapaddr),
1289                                        pci_unmap_len(lbq_desc, maplen),
1290                                        PCI_DMA_FROMDEVICE);
1291                         QPRINTK(qdev, RX_STATUS, DEBUG,
1292                                 "Chaining page to skb.\n");
1293                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1294                                            0, length);
1295                         skb->len += length;
1296                         skb->data_len += length;
1297                         skb->truesize += length;
1298                         lbq_desc->p.lbq_page = NULL;
1299                 } else {
1300                         /*
1301                          * The headers and data are in a single large buffer. We
1302                          * copy it to a new skb and let it go. This can happen with
1303                          * jumbo mtu on a non-TCP/UDP frame.
1304                          */
1305                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1306                         skb = netdev_alloc_skb(qdev->ndev, length);
1307                         if (skb == NULL) {
1308                                 QPRINTK(qdev, PROBE, DEBUG,
1309                                         "No skb available, drop the packet.\n");
1310                                 return NULL;
1311                         }
1312                         pci_unmap_page(qdev->pdev,
1313                                        pci_unmap_addr(lbq_desc,
1314                                                       mapaddr),
1315                                        pci_unmap_len(lbq_desc, maplen),
1316                                        PCI_DMA_FROMDEVICE);
1317                         skb_reserve(skb, NET_IP_ALIGN);
1318                         QPRINTK(qdev, RX_STATUS, DEBUG,
1319                                 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1320                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1321                                            0, length);
1322                         skb->len += length;
1323                         skb->data_len += length;
1324                         skb->truesize += length;
1325                         length -= length;
1326                         lbq_desc->p.lbq_page = NULL;
1327                         __pskb_pull_tail(skb,
1328                                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1329                                 VLAN_ETH_HLEN : ETH_HLEN);
1330                 }
1331         } else {
1332                 /*
1333                  * The data is in a chain of large buffers
1334                  * pointed to by a small buffer.  We loop
1335                  * thru and chain them to the our small header
1336                  * buffer's skb.
1337                  * frags:  There are 18 max frags and our small
1338                  *         buffer will hold 32 of them. The thing is,
1339                  *         we'll use 3 max for our 9000 byte jumbo
1340                  *         frames.  If the MTU goes up we could
1341                  *          eventually be in trouble.
1342                  */
1343                 int size, offset, i = 0;
1344                 __le64 *bq, bq_array[8];
1345                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1346                 pci_unmap_single(qdev->pdev,
1347                                  pci_unmap_addr(sbq_desc, mapaddr),
1348                                  pci_unmap_len(sbq_desc, maplen),
1349                                  PCI_DMA_FROMDEVICE);
1350                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1351                         /*
1352                          * This is an non TCP/UDP IP frame, so
1353                          * the headers aren't split into a small
1354                          * buffer.  We have to use the small buffer
1355                          * that contains our sg list as our skb to
1356                          * send upstairs. Copy the sg list here to
1357                          * a local buffer and use it to find the
1358                          * pages to chain.
1359                          */
1360                         QPRINTK(qdev, RX_STATUS, DEBUG,
1361                                 "%d bytes of headers & data in chain of large.\n", length);
1362                         skb = sbq_desc->p.skb;
1363                         bq = &bq_array[0];
1364                         memcpy(bq, skb->data, sizeof(bq_array));
1365                         sbq_desc->p.skb = NULL;
1366                         skb_reserve(skb, NET_IP_ALIGN);
1367                 } else {
1368                         QPRINTK(qdev, RX_STATUS, DEBUG,
1369                                 "Headers in small, %d bytes of data in chain of large.\n", length);
1370                         bq = (__le64 *)sbq_desc->p.skb->data;
1371                 }
1372                 while (length > 0) {
1373                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1374                         pci_unmap_page(qdev->pdev,
1375                                        pci_unmap_addr(lbq_desc,
1376                                                       mapaddr),
1377                                        pci_unmap_len(lbq_desc,
1378                                                      maplen),
1379                                        PCI_DMA_FROMDEVICE);
1380                         size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1381                         offset = 0;
1382
1383                         QPRINTK(qdev, RX_STATUS, DEBUG,
1384                                 "Adding page %d to skb for %d bytes.\n",
1385                                 i, size);
1386                         skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1387                                            offset, size);
1388                         skb->len += size;
1389                         skb->data_len += size;
1390                         skb->truesize += size;
1391                         length -= size;
1392                         lbq_desc->p.lbq_page = NULL;
1393                         bq++;
1394                         i++;
1395                 }
1396                 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1397                                 VLAN_ETH_HLEN : ETH_HLEN);
1398         }
1399         return skb;
1400 }
1401
1402 /* Process an inbound completion from an rx ring. */
1403 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1404                                    struct rx_ring *rx_ring,
1405                                    struct ib_mac_iocb_rsp *ib_mac_rsp)
1406 {
1407         struct net_device *ndev = qdev->ndev;
1408         struct sk_buff *skb = NULL;
1409
1410         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1411
1412         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1413         if (unlikely(!skb)) {
1414                 QPRINTK(qdev, RX_STATUS, DEBUG,
1415                         "No skb available, drop packet.\n");
1416                 return;
1417         }
1418
1419         prefetch(skb->data);
1420         skb->dev = ndev;
1421         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1422                 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1423                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1424                         IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1425                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1426                         IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1427                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1428                         IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1429         }
1430         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1431                 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1432         }
1433         if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) {
1434                 QPRINTK(qdev, RX_STATUS, ERR,
1435                         "Bad checksum for this %s packet.\n",
1436                         ((ib_mac_rsp->
1437                           flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP"));
1438                 skb->ip_summed = CHECKSUM_NONE;
1439         } else if (qdev->rx_csum &&
1440                    ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ||
1441                     ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1442                      !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) {
1443                 QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n");
1444                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1445         }
1446         qdev->stats.rx_packets++;
1447         qdev->stats.rx_bytes += skb->len;
1448         skb->protocol = eth_type_trans(skb, ndev);
1449         skb_record_rx_queue(skb, rx_ring - &qdev->rx_ring[0]);
1450         if (qdev->vlgrp && (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)) {
1451                 QPRINTK(qdev, RX_STATUS, DEBUG,
1452                         "Passing a VLAN packet upstream.\n");
1453                 vlan_hwaccel_rx(skb, qdev->vlgrp,
1454                                 le16_to_cpu(ib_mac_rsp->vlan_id));
1455         } else {
1456                 QPRINTK(qdev, RX_STATUS, DEBUG,
1457                         "Passing a normal packet upstream.\n");
1458                 netif_rx(skb);
1459         }
1460 }
1461
1462 /* Process an outbound completion from an rx ring. */
1463 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1464                                    struct ob_mac_iocb_rsp *mac_rsp)
1465 {
1466         struct tx_ring *tx_ring;
1467         struct tx_ring_desc *tx_ring_desc;
1468
1469         QL_DUMP_OB_MAC_RSP(mac_rsp);
1470         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1471         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1472         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1473         qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1474         qdev->stats.tx_packets++;
1475         dev_kfree_skb(tx_ring_desc->skb);
1476         tx_ring_desc->skb = NULL;
1477
1478         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1479                                         OB_MAC_IOCB_RSP_S |
1480                                         OB_MAC_IOCB_RSP_L |
1481                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1482                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1483                         QPRINTK(qdev, TX_DONE, WARNING,
1484                                 "Total descriptor length did not match transfer length.\n");
1485                 }
1486                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1487                         QPRINTK(qdev, TX_DONE, WARNING,
1488                                 "Frame too short to be legal, not sent.\n");
1489                 }
1490                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1491                         QPRINTK(qdev, TX_DONE, WARNING,
1492                                 "Frame too long, but sent anyway.\n");
1493                 }
1494                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1495                         QPRINTK(qdev, TX_DONE, WARNING,
1496                                 "PCI backplane error. Frame not sent.\n");
1497                 }
1498         }
1499         atomic_inc(&tx_ring->tx_count);
1500 }
1501
1502 /* Fire up a handler to reset the MPI processor. */
1503 void ql_queue_fw_error(struct ql_adapter *qdev)
1504 {
1505         netif_stop_queue(qdev->ndev);
1506         netif_carrier_off(qdev->ndev);
1507         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1508 }
1509
1510 void ql_queue_asic_error(struct ql_adapter *qdev)
1511 {
1512         netif_stop_queue(qdev->ndev);
1513         netif_carrier_off(qdev->ndev);
1514         ql_disable_interrupts(qdev);
1515         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1516 }
1517
1518 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1519                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
1520 {
1521         switch (ib_ae_rsp->event) {
1522         case MGMT_ERR_EVENT:
1523                 QPRINTK(qdev, RX_ERR, ERR,
1524                         "Management Processor Fatal Error.\n");
1525                 ql_queue_fw_error(qdev);
1526                 return;
1527
1528         case CAM_LOOKUP_ERR_EVENT:
1529                 QPRINTK(qdev, LINK, ERR,
1530                         "Multiple CAM hits lookup occurred.\n");
1531                 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1532                 ql_queue_asic_error(qdev);
1533                 return;
1534
1535         case SOFT_ECC_ERROR_EVENT:
1536                 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1537                 ql_queue_asic_error(qdev);
1538                 break;
1539
1540         case PCI_ERR_ANON_BUF_RD:
1541                 QPRINTK(qdev, RX_ERR, ERR,
1542                         "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1543                         ib_ae_rsp->q_id);
1544                 ql_queue_asic_error(qdev);
1545                 break;
1546
1547         default:
1548                 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1549                         ib_ae_rsp->event);
1550                 ql_queue_asic_error(qdev);
1551                 break;
1552         }
1553 }
1554
1555 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1556 {
1557         struct ql_adapter *qdev = rx_ring->qdev;
1558         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1559         struct ob_mac_iocb_rsp *net_rsp = NULL;
1560         int count = 0;
1561
1562         /* While there are entries in the completion queue. */
1563         while (prod != rx_ring->cnsmr_idx) {
1564
1565                 QPRINTK(qdev, RX_STATUS, DEBUG,
1566                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1567                         prod, rx_ring->cnsmr_idx);
1568
1569                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1570                 rmb();
1571                 switch (net_rsp->opcode) {
1572
1573                 case OPCODE_OB_MAC_TSO_IOCB:
1574                 case OPCODE_OB_MAC_IOCB:
1575                         ql_process_mac_tx_intr(qdev, net_rsp);
1576                         break;
1577                 default:
1578                         QPRINTK(qdev, RX_STATUS, DEBUG,
1579                                 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1580                                 net_rsp->opcode);
1581                 }
1582                 count++;
1583                 ql_update_cq(rx_ring);
1584                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1585         }
1586         ql_write_cq_idx(rx_ring);
1587         if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
1588                 struct tx_ring *tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1589                 if (atomic_read(&tx_ring->queue_stopped) &&
1590                     (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1591                         /*
1592                          * The queue got stopped because the tx_ring was full.
1593                          * Wake it up, because it's now at least 25% empty.
1594                          */
1595                         netif_wake_queue(qdev->ndev);
1596         }
1597
1598         return count;
1599 }
1600
1601 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1602 {
1603         struct ql_adapter *qdev = rx_ring->qdev;
1604         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1605         struct ql_net_rsp_iocb *net_rsp;
1606         int count = 0;
1607
1608         /* While there are entries in the completion queue. */
1609         while (prod != rx_ring->cnsmr_idx) {
1610
1611                 QPRINTK(qdev, RX_STATUS, DEBUG,
1612                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1613                         prod, rx_ring->cnsmr_idx);
1614
1615                 net_rsp = rx_ring->curr_entry;
1616                 rmb();
1617                 switch (net_rsp->opcode) {
1618                 case OPCODE_IB_MAC_IOCB:
1619                         ql_process_mac_rx_intr(qdev, rx_ring,
1620                                                (struct ib_mac_iocb_rsp *)
1621                                                net_rsp);
1622                         break;
1623
1624                 case OPCODE_IB_AE_IOCB:
1625                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1626                                                 net_rsp);
1627                         break;
1628                 default:
1629                         {
1630                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1631                                         "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1632                                         net_rsp->opcode);
1633                         }
1634                 }
1635                 count++;
1636                 ql_update_cq(rx_ring);
1637                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1638                 if (count == budget)
1639                         break;
1640         }
1641         ql_update_buffer_queues(qdev, rx_ring);
1642         ql_write_cq_idx(rx_ring);
1643         return count;
1644 }
1645
1646 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1647 {
1648         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1649         struct ql_adapter *qdev = rx_ring->qdev;
1650         int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1651
1652         QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1653                 rx_ring->cq_id);
1654
1655         if (work_done < budget) {
1656                 __napi_complete(napi);
1657                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1658         }
1659         return work_done;
1660 }
1661
1662 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1663 {
1664         struct ql_adapter *qdev = netdev_priv(ndev);
1665
1666         qdev->vlgrp = grp;
1667         if (grp) {
1668                 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1669                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1670                            NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1671         } else {
1672                 QPRINTK(qdev, IFUP, DEBUG,
1673                         "Turning off VLAN in NIC_RCV_CFG.\n");
1674                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1675         }
1676 }
1677
1678 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1679 {
1680         struct ql_adapter *qdev = netdev_priv(ndev);
1681         u32 enable_bit = MAC_ADDR_E;
1682
1683         spin_lock(&qdev->hw_lock);
1684         if (ql_set_mac_addr_reg
1685             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1686                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1687         }
1688         spin_unlock(&qdev->hw_lock);
1689 }
1690
1691 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1692 {
1693         struct ql_adapter *qdev = netdev_priv(ndev);
1694         u32 enable_bit = 0;
1695
1696         spin_lock(&qdev->hw_lock);
1697         if (ql_set_mac_addr_reg
1698             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1699                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1700         }
1701         spin_unlock(&qdev->hw_lock);
1702
1703 }
1704
1705 /* Worker thread to process a given rx_ring that is dedicated
1706  * to outbound completions.
1707  */
1708 static void ql_tx_clean(struct work_struct *work)
1709 {
1710         struct rx_ring *rx_ring =
1711             container_of(work, struct rx_ring, rx_work.work);
1712         ql_clean_outbound_rx_ring(rx_ring);
1713         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1714
1715 }
1716
1717 /* Worker thread to process a given rx_ring that is dedicated
1718  * to inbound completions.
1719  */
1720 static void ql_rx_clean(struct work_struct *work)
1721 {
1722         struct rx_ring *rx_ring =
1723             container_of(work, struct rx_ring, rx_work.work);
1724         ql_clean_inbound_rx_ring(rx_ring, 64);
1725         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1726 }
1727
1728 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1729 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1730 {
1731         struct rx_ring *rx_ring = dev_id;
1732         queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1733                               &rx_ring->rx_work, 0);
1734         return IRQ_HANDLED;
1735 }
1736
1737 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1738 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1739 {
1740         struct rx_ring *rx_ring = dev_id;
1741         napi_schedule(&rx_ring->napi);
1742         return IRQ_HANDLED;
1743 }
1744
1745 /* This handles a fatal error, MPI activity, and the default
1746  * rx_ring in an MSI-X multiple vector environment.
1747  * In MSI/Legacy environment it also process the rest of
1748  * the rx_rings.
1749  */
1750 static irqreturn_t qlge_isr(int irq, void *dev_id)
1751 {
1752         struct rx_ring *rx_ring = dev_id;
1753         struct ql_adapter *qdev = rx_ring->qdev;
1754         struct intr_context *intr_context = &qdev->intr_context[0];
1755         u32 var;
1756         int i;
1757         int work_done = 0;
1758
1759         spin_lock(&qdev->hw_lock);
1760         if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1761                 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1762                 spin_unlock(&qdev->hw_lock);
1763                 return IRQ_NONE;
1764         }
1765         spin_unlock(&qdev->hw_lock);
1766
1767         var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1768
1769         /*
1770          * Check for fatal error.
1771          */
1772         if (var & STS_FE) {
1773                 ql_queue_asic_error(qdev);
1774                 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1775                 var = ql_read32(qdev, ERR_STS);
1776                 QPRINTK(qdev, INTR, ERR,
1777                         "Resetting chip. Error Status Register = 0x%x\n", var);
1778                 return IRQ_HANDLED;
1779         }
1780
1781         /*
1782          * Check MPI processor activity.
1783          */
1784         if (var & STS_PI) {
1785                 /*
1786                  * We've got an async event or mailbox completion.
1787                  * Handle it and clear the source of the interrupt.
1788                  */
1789                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1790                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1791                 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1792                                       &qdev->mpi_work, 0);
1793                 work_done++;
1794         }
1795
1796         /*
1797          * Check the default queue and wake handler if active.
1798          */
1799         rx_ring = &qdev->rx_ring[0];
1800         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1801                 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1802                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1803                 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1804                                       &rx_ring->rx_work, 0);
1805                 work_done++;
1806         }
1807
1808         if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1809                 /*
1810                  * Start the DPC for each active queue.
1811                  */
1812                 for (i = 1; i < qdev->rx_ring_count; i++) {
1813                         rx_ring = &qdev->rx_ring[i];
1814                         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1815                             rx_ring->cnsmr_idx) {
1816                                 QPRINTK(qdev, INTR, INFO,
1817                                         "Waking handler for rx_ring[%d].\n", i);
1818                                 ql_disable_completion_interrupt(qdev,
1819                                                                 intr_context->
1820                                                                 intr);
1821                                 if (i < qdev->rss_ring_first_cq_id)
1822                                         queue_delayed_work_on(rx_ring->cpu,
1823                                                               qdev->q_workqueue,
1824                                                               &rx_ring->rx_work,
1825                                                               0);
1826                                 else
1827                                         napi_schedule(&rx_ring->napi);
1828                                 work_done++;
1829                         }
1830                 }
1831         }
1832         ql_enable_completion_interrupt(qdev, intr_context->intr);
1833         return work_done ? IRQ_HANDLED : IRQ_NONE;
1834 }
1835
1836 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1837 {
1838
1839         if (skb_is_gso(skb)) {
1840                 int err;
1841                 if (skb_header_cloned(skb)) {
1842                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1843                         if (err)
1844                                 return err;
1845                 }
1846
1847                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1848                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1849                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1850                 mac_iocb_ptr->total_hdrs_len =
1851                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1852                 mac_iocb_ptr->net_trans_offset =
1853                     cpu_to_le16(skb_network_offset(skb) |
1854                                 skb_transport_offset(skb)
1855                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
1856                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1857                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1858                 if (likely(skb->protocol == htons(ETH_P_IP))) {
1859                         struct iphdr *iph = ip_hdr(skb);
1860                         iph->check = 0;
1861                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1862                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1863                                                                  iph->daddr, 0,
1864                                                                  IPPROTO_TCP,
1865                                                                  0);
1866                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1867                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
1868                         tcp_hdr(skb)->check =
1869                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1870                                              &ipv6_hdr(skb)->daddr,
1871                                              0, IPPROTO_TCP, 0);
1872                 }
1873                 return 1;
1874         }
1875         return 0;
1876 }
1877
1878 static void ql_hw_csum_setup(struct sk_buff *skb,
1879                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1880 {
1881         int len;
1882         struct iphdr *iph = ip_hdr(skb);
1883         __sum16 *check;
1884         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1885         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1886         mac_iocb_ptr->net_trans_offset =
1887                 cpu_to_le16(skb_network_offset(skb) |
1888                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
1889
1890         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1891         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
1892         if (likely(iph->protocol == IPPROTO_TCP)) {
1893                 check = &(tcp_hdr(skb)->check);
1894                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
1895                 mac_iocb_ptr->total_hdrs_len =
1896                     cpu_to_le16(skb_transport_offset(skb) +
1897                                 (tcp_hdr(skb)->doff << 2));
1898         } else {
1899                 check = &(udp_hdr(skb)->check);
1900                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
1901                 mac_iocb_ptr->total_hdrs_len =
1902                     cpu_to_le16(skb_transport_offset(skb) +
1903                                 sizeof(struct udphdr));
1904         }
1905         *check = ~csum_tcpudp_magic(iph->saddr,
1906                                     iph->daddr, len, iph->protocol, 0);
1907 }
1908
1909 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
1910 {
1911         struct tx_ring_desc *tx_ring_desc;
1912         struct ob_mac_iocb_req *mac_iocb_ptr;
1913         struct ql_adapter *qdev = netdev_priv(ndev);
1914         int tso;
1915         struct tx_ring *tx_ring;
1916         u32 tx_ring_idx = (u32) QL_TXQ_IDX(qdev, skb);
1917
1918         tx_ring = &qdev->tx_ring[tx_ring_idx];
1919
1920         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
1921                 QPRINTK(qdev, TX_QUEUED, INFO,
1922                         "%s: shutting down tx queue %d du to lack of resources.\n",
1923                         __func__, tx_ring_idx);
1924                 netif_stop_queue(ndev);
1925                 atomic_inc(&tx_ring->queue_stopped);
1926                 return NETDEV_TX_BUSY;
1927         }
1928         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
1929         mac_iocb_ptr = tx_ring_desc->queue_entry;
1930         memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
1931         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) != NETDEV_TX_OK) {
1932                 QPRINTK(qdev, TX_QUEUED, ERR, "Could not map the segments.\n");
1933                 return NETDEV_TX_BUSY;
1934         }
1935
1936         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
1937         mac_iocb_ptr->tid = tx_ring_desc->index;
1938         /* We use the upper 32-bits to store the tx queue for this IO.
1939          * When we get the completion we can use it to establish the context.
1940          */
1941         mac_iocb_ptr->txq_idx = tx_ring_idx;
1942         tx_ring_desc->skb = skb;
1943
1944         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
1945
1946         if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
1947                 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
1948                         vlan_tx_tag_get(skb));
1949                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
1950                 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
1951         }
1952         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1953         if (tso < 0) {
1954                 dev_kfree_skb_any(skb);
1955                 return NETDEV_TX_OK;
1956         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
1957                 ql_hw_csum_setup(skb,
1958                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1959         }
1960         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
1961         tx_ring->prod_idx++;
1962         if (tx_ring->prod_idx == tx_ring->wq_len)
1963                 tx_ring->prod_idx = 0;
1964         wmb();
1965
1966         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
1967         ndev->trans_start = jiffies;
1968         QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
1969                 tx_ring->prod_idx, skb->len);
1970
1971         atomic_dec(&tx_ring->tx_count);
1972         return NETDEV_TX_OK;
1973 }
1974
1975 static void ql_free_shadow_space(struct ql_adapter *qdev)
1976 {
1977         if (qdev->rx_ring_shadow_reg_area) {
1978                 pci_free_consistent(qdev->pdev,
1979                                     PAGE_SIZE,
1980                                     qdev->rx_ring_shadow_reg_area,
1981                                     qdev->rx_ring_shadow_reg_dma);
1982                 qdev->rx_ring_shadow_reg_area = NULL;
1983         }
1984         if (qdev->tx_ring_shadow_reg_area) {
1985                 pci_free_consistent(qdev->pdev,
1986                                     PAGE_SIZE,
1987                                     qdev->tx_ring_shadow_reg_area,
1988                                     qdev->tx_ring_shadow_reg_dma);
1989                 qdev->tx_ring_shadow_reg_area = NULL;
1990         }
1991 }
1992
1993 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
1994 {
1995         qdev->rx_ring_shadow_reg_area =
1996             pci_alloc_consistent(qdev->pdev,
1997                                  PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
1998         if (qdev->rx_ring_shadow_reg_area == NULL) {
1999                 QPRINTK(qdev, IFUP, ERR,
2000                         "Allocation of RX shadow space failed.\n");
2001                 return -ENOMEM;
2002         }
2003         qdev->tx_ring_shadow_reg_area =
2004             pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2005                                  &qdev->tx_ring_shadow_reg_dma);
2006         if (qdev->tx_ring_shadow_reg_area == NULL) {
2007                 QPRINTK(qdev, IFUP, ERR,
2008                         "Allocation of TX shadow space failed.\n");
2009                 goto err_wqp_sh_area;
2010         }
2011         return 0;
2012
2013 err_wqp_sh_area:
2014         pci_free_consistent(qdev->pdev,
2015                             PAGE_SIZE,
2016                             qdev->rx_ring_shadow_reg_area,
2017                             qdev->rx_ring_shadow_reg_dma);
2018         return -ENOMEM;
2019 }
2020
2021 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2022 {
2023         struct tx_ring_desc *tx_ring_desc;
2024         int i;
2025         struct ob_mac_iocb_req *mac_iocb_ptr;
2026
2027         mac_iocb_ptr = tx_ring->wq_base;
2028         tx_ring_desc = tx_ring->q;
2029         for (i = 0; i < tx_ring->wq_len; i++) {
2030                 tx_ring_desc->index = i;
2031                 tx_ring_desc->skb = NULL;
2032                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2033                 mac_iocb_ptr++;
2034                 tx_ring_desc++;
2035         }
2036         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2037         atomic_set(&tx_ring->queue_stopped, 0);
2038 }
2039
2040 static void ql_free_tx_resources(struct ql_adapter *qdev,
2041                                  struct tx_ring *tx_ring)
2042 {
2043         if (tx_ring->wq_base) {
2044                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2045                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2046                 tx_ring->wq_base = NULL;
2047         }
2048         kfree(tx_ring->q);
2049         tx_ring->q = NULL;
2050 }
2051
2052 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2053                                  struct tx_ring *tx_ring)
2054 {
2055         tx_ring->wq_base =
2056             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2057                                  &tx_ring->wq_base_dma);
2058
2059         if ((tx_ring->wq_base == NULL)
2060             || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2061                 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2062                 return -ENOMEM;
2063         }
2064         tx_ring->q =
2065             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2066         if (tx_ring->q == NULL)
2067                 goto err;
2068
2069         return 0;
2070 err:
2071         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2072                             tx_ring->wq_base, tx_ring->wq_base_dma);
2073         return -ENOMEM;
2074 }
2075
2076 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2077 {
2078         int i;
2079         struct bq_desc *lbq_desc;
2080
2081         for (i = 0; i < rx_ring->lbq_len; i++) {
2082                 lbq_desc = &rx_ring->lbq[i];
2083                 if (lbq_desc->p.lbq_page) {
2084                         pci_unmap_page(qdev->pdev,
2085                                        pci_unmap_addr(lbq_desc, mapaddr),
2086                                        pci_unmap_len(lbq_desc, maplen),
2087                                        PCI_DMA_FROMDEVICE);
2088
2089                         put_page(lbq_desc->p.lbq_page);
2090                         lbq_desc->p.lbq_page = NULL;
2091                 }
2092         }
2093 }
2094
2095 /*
2096  * Allocate and map a page for each element of the lbq.
2097  */
2098 static int ql_alloc_lbq_buffers(struct ql_adapter *qdev,
2099                                 struct rx_ring *rx_ring)
2100 {
2101         int i;
2102         struct bq_desc *lbq_desc;
2103         u64 map;
2104         __le64 *bq = rx_ring->lbq_base;
2105
2106         for (i = 0; i < rx_ring->lbq_len; i++) {
2107                 lbq_desc = &rx_ring->lbq[i];
2108                 memset(lbq_desc, 0, sizeof(lbq_desc));
2109                 lbq_desc->addr = bq;
2110                 lbq_desc->index = i;
2111                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
2112                 if (unlikely(!lbq_desc->p.lbq_page)) {
2113                         QPRINTK(qdev, IFUP, ERR, "failed alloc_page().\n");
2114                         goto mem_error;
2115                 } else {
2116                         map = pci_map_page(qdev->pdev,
2117                                            lbq_desc->p.lbq_page,
2118                                            0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
2119                         if (pci_dma_mapping_error(qdev->pdev, map)) {
2120                                 QPRINTK(qdev, IFUP, ERR,
2121                                         "PCI mapping failed.\n");
2122                                 goto mem_error;
2123                         }
2124                         pci_unmap_addr_set(lbq_desc, mapaddr, map);
2125                         pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
2126                         *lbq_desc->addr = cpu_to_le64(map);
2127                 }
2128                 bq++;
2129         }
2130         return 0;
2131 mem_error:
2132         ql_free_lbq_buffers(qdev, rx_ring);
2133         return -ENOMEM;
2134 }
2135
2136 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2137 {
2138         int i;
2139         struct bq_desc *sbq_desc;
2140
2141         for (i = 0; i < rx_ring->sbq_len; i++) {
2142                 sbq_desc = &rx_ring->sbq[i];
2143                 if (sbq_desc == NULL) {
2144                         QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2145                         return;
2146                 }
2147                 if (sbq_desc->p.skb) {
2148                         pci_unmap_single(qdev->pdev,
2149                                          pci_unmap_addr(sbq_desc, mapaddr),
2150                                          pci_unmap_len(sbq_desc, maplen),
2151                                          PCI_DMA_FROMDEVICE);
2152                         dev_kfree_skb(sbq_desc->p.skb);
2153                         sbq_desc->p.skb = NULL;
2154                 }
2155         }
2156 }
2157
2158 /* Allocate and map an skb for each element of the sbq. */
2159 static int ql_alloc_sbq_buffers(struct ql_adapter *qdev,
2160                                 struct rx_ring *rx_ring)
2161 {
2162         int i;
2163         struct bq_desc *sbq_desc;
2164         struct sk_buff *skb;
2165         u64 map;
2166         __le64 *bq = rx_ring->sbq_base;
2167
2168         for (i = 0; i < rx_ring->sbq_len; i++) {
2169                 sbq_desc = &rx_ring->sbq[i];
2170                 memset(sbq_desc, 0, sizeof(sbq_desc));
2171                 sbq_desc->index = i;
2172                 sbq_desc->addr = bq;
2173                 skb = netdev_alloc_skb(qdev->ndev, rx_ring->sbq_buf_size);
2174                 if (unlikely(!skb)) {
2175                         /* Better luck next round */
2176                         QPRINTK(qdev, IFUP, ERR,
2177                                 "small buff alloc failed for %d bytes at index %d.\n",
2178                                 rx_ring->sbq_buf_size, i);
2179                         goto mem_err;
2180                 }
2181                 skb_reserve(skb, QLGE_SB_PAD);
2182                 sbq_desc->p.skb = skb;
2183                 /*
2184                  * Map only half the buffer. Because the
2185                  * other half may get some data copied to it
2186                  * when the completion arrives.
2187                  */
2188                 map = pci_map_single(qdev->pdev,
2189                                      skb->data,
2190                                      rx_ring->sbq_buf_size / 2,
2191                                      PCI_DMA_FROMDEVICE);
2192                 if (pci_dma_mapping_error(qdev->pdev, map)) {
2193                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
2194                         goto mem_err;
2195                 }
2196                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
2197                 pci_unmap_len_set(sbq_desc, maplen, rx_ring->sbq_buf_size / 2);
2198                 *sbq_desc->addr = cpu_to_le64(map);
2199                 bq++;
2200         }
2201         return 0;
2202 mem_err:
2203         ql_free_sbq_buffers(qdev, rx_ring);
2204         return -ENOMEM;
2205 }
2206
2207 static void ql_free_rx_resources(struct ql_adapter *qdev,
2208                                  struct rx_ring *rx_ring)
2209 {
2210         if (rx_ring->sbq_len)
2211                 ql_free_sbq_buffers(qdev, rx_ring);
2212         if (rx_ring->lbq_len)
2213                 ql_free_lbq_buffers(qdev, rx_ring);
2214
2215         /* Free the small buffer queue. */
2216         if (rx_ring->sbq_base) {
2217                 pci_free_consistent(qdev->pdev,
2218                                     rx_ring->sbq_size,
2219                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2220                 rx_ring->sbq_base = NULL;
2221         }
2222
2223         /* Free the small buffer queue control blocks. */
2224         kfree(rx_ring->sbq);
2225         rx_ring->sbq = NULL;
2226
2227         /* Free the large buffer queue. */
2228         if (rx_ring->lbq_base) {
2229                 pci_free_consistent(qdev->pdev,
2230                                     rx_ring->lbq_size,
2231                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2232                 rx_ring->lbq_base = NULL;
2233         }
2234
2235         /* Free the large buffer queue control blocks. */
2236         kfree(rx_ring->lbq);
2237         rx_ring->lbq = NULL;
2238
2239         /* Free the rx queue. */
2240         if (rx_ring->cq_base) {
2241                 pci_free_consistent(qdev->pdev,
2242                                     rx_ring->cq_size,
2243                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2244                 rx_ring->cq_base = NULL;
2245         }
2246 }
2247
2248 /* Allocate queues and buffers for this completions queue based
2249  * on the values in the parameter structure. */
2250 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2251                                  struct rx_ring *rx_ring)
2252 {
2253
2254         /*
2255          * Allocate the completion queue for this rx_ring.
2256          */
2257         rx_ring->cq_base =
2258             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2259                                  &rx_ring->cq_base_dma);
2260
2261         if (rx_ring->cq_base == NULL) {
2262                 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2263                 return -ENOMEM;
2264         }
2265
2266         if (rx_ring->sbq_len) {
2267                 /*
2268                  * Allocate small buffer queue.
2269                  */
2270                 rx_ring->sbq_base =
2271                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2272                                          &rx_ring->sbq_base_dma);
2273
2274                 if (rx_ring->sbq_base == NULL) {
2275                         QPRINTK(qdev, IFUP, ERR,
2276                                 "Small buffer queue allocation failed.\n");
2277                         goto err_mem;
2278                 }
2279
2280                 /*
2281                  * Allocate small buffer queue control blocks.
2282                  */
2283                 rx_ring->sbq =
2284                     kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2285                             GFP_KERNEL);
2286                 if (rx_ring->sbq == NULL) {
2287                         QPRINTK(qdev, IFUP, ERR,
2288                                 "Small buffer queue control block allocation failed.\n");
2289                         goto err_mem;
2290                 }
2291
2292                 if (ql_alloc_sbq_buffers(qdev, rx_ring)) {
2293                         QPRINTK(qdev, IFUP, ERR,
2294                                 "Small buffer allocation failed.\n");
2295                         goto err_mem;
2296                 }
2297         }
2298
2299         if (rx_ring->lbq_len) {
2300                 /*
2301                  * Allocate large buffer queue.
2302                  */
2303                 rx_ring->lbq_base =
2304                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2305                                          &rx_ring->lbq_base_dma);
2306
2307                 if (rx_ring->lbq_base == NULL) {
2308                         QPRINTK(qdev, IFUP, ERR,
2309                                 "Large buffer queue allocation failed.\n");
2310                         goto err_mem;
2311                 }
2312                 /*
2313                  * Allocate large buffer queue control blocks.
2314                  */
2315                 rx_ring->lbq =
2316                     kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2317                             GFP_KERNEL);
2318                 if (rx_ring->lbq == NULL) {
2319                         QPRINTK(qdev, IFUP, ERR,
2320                                 "Large buffer queue control block allocation failed.\n");
2321                         goto err_mem;
2322                 }
2323
2324                 /*
2325                  * Allocate the buffers.
2326                  */
2327                 if (ql_alloc_lbq_buffers(qdev, rx_ring)) {
2328                         QPRINTK(qdev, IFUP, ERR,
2329                                 "Large buffer allocation failed.\n");
2330                         goto err_mem;
2331                 }
2332         }
2333
2334         return 0;
2335
2336 err_mem:
2337         ql_free_rx_resources(qdev, rx_ring);
2338         return -ENOMEM;
2339 }
2340
2341 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2342 {
2343         struct tx_ring *tx_ring;
2344         struct tx_ring_desc *tx_ring_desc;
2345         int i, j;
2346
2347         /*
2348          * Loop through all queues and free
2349          * any resources.
2350          */
2351         for (j = 0; j < qdev->tx_ring_count; j++) {
2352                 tx_ring = &qdev->tx_ring[j];
2353                 for (i = 0; i < tx_ring->wq_len; i++) {
2354                         tx_ring_desc = &tx_ring->q[i];
2355                         if (tx_ring_desc && tx_ring_desc->skb) {
2356                                 QPRINTK(qdev, IFDOWN, ERR,
2357                                 "Freeing lost SKB %p, from queue %d, index %d.\n",
2358                                         tx_ring_desc->skb, j,
2359                                         tx_ring_desc->index);
2360                                 ql_unmap_send(qdev, tx_ring_desc,
2361                                               tx_ring_desc->map_cnt);
2362                                 dev_kfree_skb(tx_ring_desc->skb);
2363                                 tx_ring_desc->skb = NULL;
2364                         }
2365                 }
2366         }
2367 }
2368
2369 static void ql_free_mem_resources(struct ql_adapter *qdev)
2370 {
2371         int i;
2372
2373         for (i = 0; i < qdev->tx_ring_count; i++)
2374                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2375         for (i = 0; i < qdev->rx_ring_count; i++)
2376                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2377         ql_free_shadow_space(qdev);
2378 }
2379
2380 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2381 {
2382         int i;
2383
2384         /* Allocate space for our shadow registers and such. */
2385         if (ql_alloc_shadow_space(qdev))
2386                 return -ENOMEM;
2387
2388         for (i = 0; i < qdev->rx_ring_count; i++) {
2389                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2390                         QPRINTK(qdev, IFUP, ERR,
2391                                 "RX resource allocation failed.\n");
2392                         goto err_mem;
2393                 }
2394         }
2395         /* Allocate tx queue resources */
2396         for (i = 0; i < qdev->tx_ring_count; i++) {
2397                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2398                         QPRINTK(qdev, IFUP, ERR,
2399                                 "TX resource allocation failed.\n");
2400                         goto err_mem;
2401                 }
2402         }
2403         return 0;
2404
2405 err_mem:
2406         ql_free_mem_resources(qdev);
2407         return -ENOMEM;
2408 }
2409
2410 /* Set up the rx ring control block and pass it to the chip.
2411  * The control block is defined as
2412  * "Completion Queue Initialization Control Block", or cqicb.
2413  */
2414 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2415 {
2416         struct cqicb *cqicb = &rx_ring->cqicb;
2417         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2418             (rx_ring->cq_id * sizeof(u64) * 4);
2419         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2420             (rx_ring->cq_id * sizeof(u64) * 4);
2421         void __iomem *doorbell_area =
2422             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2423         int err = 0;
2424         u16 bq_len;
2425
2426         /* Set up the shadow registers for this ring. */
2427         rx_ring->prod_idx_sh_reg = shadow_reg;
2428         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2429         shadow_reg += sizeof(u64);
2430         shadow_reg_dma += sizeof(u64);
2431         rx_ring->lbq_base_indirect = shadow_reg;
2432         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2433         shadow_reg += sizeof(u64);
2434         shadow_reg_dma += sizeof(u64);
2435         rx_ring->sbq_base_indirect = shadow_reg;
2436         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2437
2438         /* PCI doorbell mem area + 0x00 for consumer index register */
2439         rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2440         rx_ring->cnsmr_idx = 0;
2441         rx_ring->curr_entry = rx_ring->cq_base;
2442
2443         /* PCI doorbell mem area + 0x04 for valid register */
2444         rx_ring->valid_db_reg = doorbell_area + 0x04;
2445
2446         /* PCI doorbell mem area + 0x18 for large buffer consumer */
2447         rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2448
2449         /* PCI doorbell mem area + 0x1c */
2450         rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2451
2452         memset((void *)cqicb, 0, sizeof(struct cqicb));
2453         cqicb->msix_vect = rx_ring->irq;
2454
2455         bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2456         cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
2457
2458         cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
2459
2460         cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
2461
2462         /*
2463          * Set up the control block load flags.
2464          */
2465         cqicb->flags = FLAGS_LC |       /* Load queue base address */
2466             FLAGS_LV |          /* Load MSI-X vector */
2467             FLAGS_LI;           /* Load irq delay values */
2468         if (rx_ring->lbq_len) {
2469                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
2470                 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
2471                 cqicb->lbq_addr =
2472                     cpu_to_le64(rx_ring->lbq_base_indirect_dma);
2473                 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2474                         (u16) rx_ring->lbq_buf_size;
2475                 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2476                 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2477                         (u16) rx_ring->lbq_len;
2478                 cqicb->lbq_len = cpu_to_le16(bq_len);
2479                 rx_ring->lbq_prod_idx = rx_ring->lbq_len - 16;
2480                 rx_ring->lbq_curr_idx = 0;
2481                 rx_ring->lbq_clean_idx = rx_ring->lbq_prod_idx;
2482                 rx_ring->lbq_free_cnt = 16;
2483         }
2484         if (rx_ring->sbq_len) {
2485                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
2486                 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
2487                 cqicb->sbq_addr =
2488                     cpu_to_le64(rx_ring->sbq_base_indirect_dma);
2489                 cqicb->sbq_buf_size =
2490                     cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
2491                 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2492                         (u16) rx_ring->sbq_len;
2493                 cqicb->sbq_len = cpu_to_le16(bq_len);
2494                 rx_ring->sbq_prod_idx = rx_ring->sbq_len - 16;
2495                 rx_ring->sbq_curr_idx = 0;
2496                 rx_ring->sbq_clean_idx = rx_ring->sbq_prod_idx;
2497                 rx_ring->sbq_free_cnt = 16;
2498         }
2499         switch (rx_ring->type) {
2500         case TX_Q:
2501                 /* If there's only one interrupt, then we use
2502                  * worker threads to process the outbound
2503                  * completion handling rx_rings. We do this so
2504                  * they can be run on multiple CPUs. There is
2505                  * room to play with this more where we would only
2506                  * run in a worker if there are more than x number
2507                  * of outbound completions on the queue and more
2508                  * than one queue active.  Some threshold that
2509                  * would indicate a benefit in spite of the cost
2510                  * of a context switch.
2511                  * If there's more than one interrupt, then the
2512                  * outbound completions are processed in the ISR.
2513                  */
2514                 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2515                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2516                 else {
2517                         /* With all debug warnings on we see a WARN_ON message
2518                          * when we free the skb in the interrupt context.
2519                          */
2520                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2521                 }
2522                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2523                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2524                 break;
2525         case DEFAULT_Q:
2526                 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2527                 cqicb->irq_delay = 0;
2528                 cqicb->pkt_delay = 0;
2529                 break;
2530         case RX_Q:
2531                 /* Inbound completion handling rx_rings run in
2532                  * separate NAPI contexts.
2533                  */
2534                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2535                                64);
2536                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2537                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2538                 break;
2539         default:
2540                 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2541                         rx_ring->type);
2542         }
2543         QPRINTK(qdev, IFUP, INFO, "Initializing rx work queue.\n");
2544         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2545                            CFG_LCQ, rx_ring->cq_id);
2546         if (err) {
2547                 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2548                 return err;
2549         }
2550         QPRINTK(qdev, IFUP, INFO, "Successfully loaded CQICB.\n");
2551         /*
2552          * Advance the producer index for the buffer queues.
2553          */
2554         wmb();
2555         if (rx_ring->lbq_len)
2556                 ql_write_db_reg(rx_ring->lbq_prod_idx,
2557                                 rx_ring->lbq_prod_idx_db_reg);
2558         if (rx_ring->sbq_len)
2559                 ql_write_db_reg(rx_ring->sbq_prod_idx,
2560                                 rx_ring->sbq_prod_idx_db_reg);
2561         return err;
2562 }
2563
2564 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2565 {
2566         struct wqicb *wqicb = (struct wqicb *)tx_ring;
2567         void __iomem *doorbell_area =
2568             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2569         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2570             (tx_ring->wq_id * sizeof(u64));
2571         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2572             (tx_ring->wq_id * sizeof(u64));
2573         int err = 0;
2574
2575         /*
2576          * Assign doorbell registers for this tx_ring.
2577          */
2578         /* TX PCI doorbell mem area for tx producer index */
2579         tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2580         tx_ring->prod_idx = 0;
2581         /* TX PCI doorbell mem area + 0x04 */
2582         tx_ring->valid_db_reg = doorbell_area + 0x04;
2583
2584         /*
2585          * Assign shadow registers for this tx_ring.
2586          */
2587         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2588         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2589
2590         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2591         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2592                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2593         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2594         wqicb->rid = 0;
2595         wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
2596
2597         wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
2598
2599         ql_init_tx_ring(qdev, tx_ring);
2600
2601         err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2602                            (u16) tx_ring->wq_id);
2603         if (err) {
2604                 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2605                 return err;
2606         }
2607         QPRINTK(qdev, IFUP, INFO, "Successfully loaded WQICB.\n");
2608         return err;
2609 }
2610
2611 static void ql_disable_msix(struct ql_adapter *qdev)
2612 {
2613         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2614                 pci_disable_msix(qdev->pdev);
2615                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2616                 kfree(qdev->msi_x_entry);
2617                 qdev->msi_x_entry = NULL;
2618         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2619                 pci_disable_msi(qdev->pdev);
2620                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2621         }
2622 }
2623
2624 static void ql_enable_msix(struct ql_adapter *qdev)
2625 {
2626         int i;
2627
2628         qdev->intr_count = 1;
2629         /* Get the MSIX vectors. */
2630         if (irq_type == MSIX_IRQ) {
2631                 /* Try to alloc space for the msix struct,
2632                  * if it fails then go to MSI/legacy.
2633                  */
2634                 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2635                                             sizeof(struct msix_entry),
2636                                             GFP_KERNEL);
2637                 if (!qdev->msi_x_entry) {
2638                         irq_type = MSI_IRQ;
2639                         goto msi;
2640                 }
2641
2642                 for (i = 0; i < qdev->rx_ring_count; i++)
2643                         qdev->msi_x_entry[i].entry = i;
2644
2645                 if (!pci_enable_msix
2646                     (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2647                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
2648                         qdev->intr_count = qdev->rx_ring_count;
2649                         QPRINTK(qdev, IFUP, INFO,
2650                                 "MSI-X Enabled, got %d vectors.\n",
2651                                 qdev->intr_count);
2652                         return;
2653                 } else {
2654                         kfree(qdev->msi_x_entry);
2655                         qdev->msi_x_entry = NULL;
2656                         QPRINTK(qdev, IFUP, WARNING,
2657                                 "MSI-X Enable failed, trying MSI.\n");
2658                         irq_type = MSI_IRQ;
2659                 }
2660         }
2661 msi:
2662         if (irq_type == MSI_IRQ) {
2663                 if (!pci_enable_msi(qdev->pdev)) {
2664                         set_bit(QL_MSI_ENABLED, &qdev->flags);
2665                         QPRINTK(qdev, IFUP, INFO,
2666                                 "Running with MSI interrupts.\n");
2667                         return;
2668                 }
2669         }
2670         irq_type = LEG_IRQ;
2671         QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2672 }
2673
2674 /*
2675  * Here we build the intr_context structures based on
2676  * our rx_ring count and intr vector count.
2677  * The intr_context structure is used to hook each vector
2678  * to possibly different handlers.
2679  */
2680 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2681 {
2682         int i = 0;
2683         struct intr_context *intr_context = &qdev->intr_context[0];
2684
2685         ql_enable_msix(qdev);
2686
2687         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2688                 /* Each rx_ring has it's
2689                  * own intr_context since we have separate
2690                  * vectors for each queue.
2691                  * This only true when MSI-X is enabled.
2692                  */
2693                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2694                         qdev->rx_ring[i].irq = i;
2695                         intr_context->intr = i;
2696                         intr_context->qdev = qdev;
2697                         /*
2698                          * We set up each vectors enable/disable/read bits so
2699                          * there's no bit/mask calculations in the critical path.
2700                          */
2701                         intr_context->intr_en_mask =
2702                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2703                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2704                             | i;
2705                         intr_context->intr_dis_mask =
2706                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2707                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2708                             INTR_EN_IHD | i;
2709                         intr_context->intr_read_mask =
2710                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2711                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2712                             i;
2713
2714                         if (i == 0) {
2715                                 /*
2716                                  * Default queue handles bcast/mcast plus
2717                                  * async events.  Needs buffers.
2718                                  */
2719                                 intr_context->handler = qlge_isr;
2720                                 sprintf(intr_context->name, "%s-default-queue",
2721                                         qdev->ndev->name);
2722                         } else if (i < qdev->rss_ring_first_cq_id) {
2723                                 /*
2724                                  * Outbound queue is for outbound completions only.
2725                                  */
2726                                 intr_context->handler = qlge_msix_tx_isr;
2727                                 sprintf(intr_context->name, "%s-tx-%d",
2728                                         qdev->ndev->name, i);
2729                         } else {
2730                                 /*
2731                                  * Inbound queues handle unicast frames only.
2732                                  */
2733                                 intr_context->handler = qlge_msix_rx_isr;
2734                                 sprintf(intr_context->name, "%s-rx-%d",
2735                                         qdev->ndev->name, i);
2736                         }
2737                 }
2738         } else {
2739                 /*
2740                  * All rx_rings use the same intr_context since
2741                  * there is only one vector.
2742                  */
2743                 intr_context->intr = 0;
2744                 intr_context->qdev = qdev;
2745                 /*
2746                  * We set up each vectors enable/disable/read bits so
2747                  * there's no bit/mask calculations in the critical path.
2748                  */
2749                 intr_context->intr_en_mask =
2750                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2751                 intr_context->intr_dis_mask =
2752                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2753                     INTR_EN_TYPE_DISABLE;
2754                 intr_context->intr_read_mask =
2755                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2756                 /*
2757                  * Single interrupt means one handler for all rings.
2758                  */
2759                 intr_context->handler = qlge_isr;
2760                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2761                 for (i = 0; i < qdev->rx_ring_count; i++)
2762                         qdev->rx_ring[i].irq = 0;
2763         }
2764 }
2765
2766 static void ql_free_irq(struct ql_adapter *qdev)
2767 {
2768         int i;
2769         struct intr_context *intr_context = &qdev->intr_context[0];
2770
2771         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2772                 if (intr_context->hooked) {
2773                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2774                                 free_irq(qdev->msi_x_entry[i].vector,
2775                                          &qdev->rx_ring[i]);
2776                                 QPRINTK(qdev, IFDOWN, ERR,
2777                                         "freeing msix interrupt %d.\n", i);
2778                         } else {
2779                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2780                                 QPRINTK(qdev, IFDOWN, ERR,
2781                                         "freeing msi interrupt %d.\n", i);
2782                         }
2783                 }
2784         }
2785         ql_disable_msix(qdev);
2786 }
2787
2788 static int ql_request_irq(struct ql_adapter *qdev)
2789 {
2790         int i;
2791         int status = 0;
2792         struct pci_dev *pdev = qdev->pdev;
2793         struct intr_context *intr_context = &qdev->intr_context[0];
2794
2795         ql_resolve_queues_to_irqs(qdev);
2796
2797         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2798                 atomic_set(&intr_context->irq_cnt, 0);
2799                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2800                         status = request_irq(qdev->msi_x_entry[i].vector,
2801                                              intr_context->handler,
2802                                              0,
2803                                              intr_context->name,
2804                                              &qdev->rx_ring[i]);
2805                         if (status) {
2806                                 QPRINTK(qdev, IFUP, ERR,
2807                                         "Failed request for MSIX interrupt %d.\n",
2808                                         i);
2809                                 goto err_irq;
2810                         } else {
2811                                 QPRINTK(qdev, IFUP, INFO,
2812                                         "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2813                                         i,
2814                                         qdev->rx_ring[i].type ==
2815                                         DEFAULT_Q ? "DEFAULT_Q" : "",
2816                                         qdev->rx_ring[i].type ==
2817                                         TX_Q ? "TX_Q" : "",
2818                                         qdev->rx_ring[i].type ==
2819                                         RX_Q ? "RX_Q" : "", intr_context->name);
2820                         }
2821                 } else {
2822                         QPRINTK(qdev, IFUP, DEBUG,
2823                                 "trying msi or legacy interrupts.\n");
2824                         QPRINTK(qdev, IFUP, DEBUG,
2825                                 "%s: irq = %d.\n", __func__, pdev->irq);
2826                         QPRINTK(qdev, IFUP, DEBUG,
2827                                 "%s: context->name = %s.\n", __func__,
2828                                intr_context->name);
2829                         QPRINTK(qdev, IFUP, DEBUG,
2830                                 "%s: dev_id = 0x%p.\n", __func__,
2831                                &qdev->rx_ring[0]);
2832                         status =
2833                             request_irq(pdev->irq, qlge_isr,
2834                                         test_bit(QL_MSI_ENABLED,
2835                                                  &qdev->
2836                                                  flags) ? 0 : IRQF_SHARED,
2837                                         intr_context->name, &qdev->rx_ring[0]);
2838                         if (status)
2839                                 goto err_irq;
2840
2841                         QPRINTK(qdev, IFUP, ERR,
2842                                 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2843                                 i,
2844                                 qdev->rx_ring[0].type ==
2845                                 DEFAULT_Q ? "DEFAULT_Q" : "",
2846                                 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2847                                 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2848                                 intr_context->name);
2849                 }
2850                 intr_context->hooked = 1;
2851         }
2852         return status;
2853 err_irq:
2854         QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2855         ql_free_irq(qdev);
2856         return status;
2857 }
2858
2859 static int ql_start_rss(struct ql_adapter *qdev)
2860 {
2861         struct ricb *ricb = &qdev->ricb;
2862         int status = 0;
2863         int i;
2864         u8 *hash_id = (u8 *) ricb->hash_cq_id;
2865
2866         memset((void *)ricb, 0, sizeof(ricb));
2867
2868         ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2869         ricb->flags =
2870             (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2871              RSS_RT6);
2872         ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2873
2874         /*
2875          * Fill out the Indirection Table.
2876          */
2877         for (i = 0; i < 32; i++)
2878                 hash_id[i] = i & 1;
2879
2880         /*
2881          * Random values for the IPv6 and IPv4 Hash Keys.
2882          */
2883         get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2884         get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2885
2886         QPRINTK(qdev, IFUP, INFO, "Initializing RSS.\n");
2887
2888         status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2889         if (status) {
2890                 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2891                 return status;
2892         }
2893         QPRINTK(qdev, IFUP, INFO, "Successfully loaded RICB.\n");
2894         return status;
2895 }
2896
2897 /* Initialize the frame-to-queue routing. */
2898 static int ql_route_initialize(struct ql_adapter *qdev)
2899 {
2900         int status = 0;
2901         int i;
2902
2903         /* Clear all the entries in the routing table. */
2904         for (i = 0; i < 16; i++) {
2905                 status = ql_set_routing_reg(qdev, i, 0, 0);
2906                 if (status) {
2907                         QPRINTK(qdev, IFUP, ERR,
2908                                 "Failed to init routing register for CAM packets.\n");
2909                         return status;
2910                 }
2911         }
2912
2913         status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
2914         if (status) {
2915                 QPRINTK(qdev, IFUP, ERR,
2916                         "Failed to init routing register for error packets.\n");
2917                 return status;
2918         }
2919         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
2920         if (status) {
2921                 QPRINTK(qdev, IFUP, ERR,
2922                         "Failed to init routing register for broadcast packets.\n");
2923                 return status;
2924         }
2925         /* If we have more than one inbound queue, then turn on RSS in the
2926          * routing block.
2927          */
2928         if (qdev->rss_ring_count > 1) {
2929                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
2930                                         RT_IDX_RSS_MATCH, 1);
2931                 if (status) {
2932                         QPRINTK(qdev, IFUP, ERR,
2933                                 "Failed to init routing register for MATCH RSS packets.\n");
2934                         return status;
2935                 }
2936         }
2937
2938         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
2939                                     RT_IDX_CAM_HIT, 1);
2940         if (status) {
2941                 QPRINTK(qdev, IFUP, ERR,
2942                         "Failed to init routing register for CAM packets.\n");
2943                 return status;
2944         }
2945         return status;
2946 }
2947
2948 static int ql_adapter_initialize(struct ql_adapter *qdev)
2949 {
2950         u32 value, mask;
2951         int i;
2952         int status = 0;
2953
2954         /*
2955          * Set up the System register to halt on errors.
2956          */
2957         value = SYS_EFE | SYS_FAE;
2958         mask = value << 16;
2959         ql_write32(qdev, SYS, mask | value);
2960
2961         /* Set the default queue. */
2962         value = NIC_RCV_CFG_DFQ;
2963         mask = NIC_RCV_CFG_DFQ_MASK;
2964         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
2965
2966         /* Set the MPI interrupt to enabled. */
2967         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
2968
2969         /* Enable the function, set pagesize, enable error checking. */
2970         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
2971             FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
2972
2973         /* Set/clear header splitting. */
2974         mask = FSC_VM_PAGESIZE_MASK |
2975             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
2976         ql_write32(qdev, FSC, mask | value);
2977
2978         ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
2979                 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
2980
2981         /* Start up the rx queues. */
2982         for (i = 0; i < qdev->rx_ring_count; i++) {
2983                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
2984                 if (status) {
2985                         QPRINTK(qdev, IFUP, ERR,
2986                                 "Failed to start rx ring[%d].\n", i);
2987                         return status;
2988                 }
2989         }
2990
2991         /* If there is more than one inbound completion queue
2992          * then download a RICB to configure RSS.
2993          */
2994         if (qdev->rss_ring_count > 1) {
2995                 status = ql_start_rss(qdev);
2996                 if (status) {
2997                         QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
2998                         return status;
2999                 }
3000         }
3001
3002         /* Start up the tx queues. */
3003         for (i = 0; i < qdev->tx_ring_count; i++) {
3004                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3005                 if (status) {
3006                         QPRINTK(qdev, IFUP, ERR,
3007                                 "Failed to start tx ring[%d].\n", i);
3008                         return status;
3009                 }
3010         }
3011
3012         status = ql_port_initialize(qdev);
3013         if (status) {
3014                 QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3015                 return status;
3016         }
3017
3018         status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3019                                      MAC_ADDR_TYPE_CAM_MAC, qdev->func);
3020         if (status) {
3021                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3022                 return status;
3023         }
3024
3025         status = ql_route_initialize(qdev);
3026         if (status) {
3027                 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3028                 return status;
3029         }
3030
3031         /* Start NAPI for the RSS queues. */
3032         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3033                 QPRINTK(qdev, IFUP, INFO, "Enabling NAPI for rx_ring[%d].\n",
3034                         i);
3035                 napi_enable(&qdev->rx_ring[i].napi);
3036         }
3037
3038         return status;
3039 }
3040
3041 /* Issue soft reset to chip. */
3042 static int ql_adapter_reset(struct ql_adapter *qdev)
3043 {
3044         u32 value;
3045         int max_wait_time;
3046         int status = 0;
3047         int resetCnt = 0;
3048
3049 #define MAX_RESET_CNT   1
3050 issueReset:
3051         resetCnt++;
3052         QPRINTK(qdev, IFDOWN, DEBUG, "Issue soft reset to chip.\n");
3053         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3054         /* Wait for reset to complete. */
3055         max_wait_time = 3;
3056         QPRINTK(qdev, IFDOWN, DEBUG, "Wait %d seconds for reset to complete.\n",
3057                 max_wait_time);
3058         do {
3059                 value = ql_read32(qdev, RST_FO);
3060                 if ((value & RST_FO_FR) == 0)
3061                         break;
3062
3063                 ssleep(1);
3064         } while ((--max_wait_time));
3065         if (value & RST_FO_FR) {
3066                 QPRINTK(qdev, IFDOWN, ERR,
3067                         "Stuck in SoftReset:  FSC_SR:0x%08x\n", value);
3068                 if (resetCnt < MAX_RESET_CNT)
3069                         goto issueReset;
3070         }
3071         if (max_wait_time == 0) {
3072                 status = -ETIMEDOUT;
3073                 QPRINTK(qdev, IFDOWN, ERR,
3074                         "ETIMEOUT!!! errored out of resetting the chip!\n");
3075         }
3076
3077         return status;
3078 }
3079
3080 static void ql_display_dev_info(struct net_device *ndev)
3081 {
3082         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3083
3084         QPRINTK(qdev, PROBE, INFO,
3085                 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3086                 "XG Roll = %d, XG Rev = %d.\n",
3087                 qdev->func,
3088                 qdev->chip_rev_id & 0x0000000f,
3089                 qdev->chip_rev_id >> 4 & 0x0000000f,
3090                 qdev->chip_rev_id >> 8 & 0x0000000f,
3091                 qdev->chip_rev_id >> 12 & 0x0000000f);
3092         QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3093 }
3094
3095 static int ql_adapter_down(struct ql_adapter *qdev)
3096 {
3097         struct net_device *ndev = qdev->ndev;
3098         int i, status = 0;
3099         struct rx_ring *rx_ring;
3100
3101         netif_stop_queue(ndev);
3102         netif_carrier_off(ndev);
3103
3104         cancel_delayed_work_sync(&qdev->asic_reset_work);
3105         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3106         cancel_delayed_work_sync(&qdev->mpi_work);
3107
3108         /* The default queue at index 0 is always processed in
3109          * a workqueue.
3110          */
3111         cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3112
3113         /* The rest of the rx_rings are processed in
3114          * a workqueue only if it's a single interrupt
3115          * environment (MSI/Legacy).
3116          */
3117         for (i = 1; i < qdev->rx_ring_count; i++) {
3118                 rx_ring = &qdev->rx_ring[i];
3119                 /* Only the RSS rings use NAPI on multi irq
3120                  * environment.  Outbound completion processing
3121                  * is done in interrupt context.
3122                  */
3123                 if (i >= qdev->rss_ring_first_cq_id) {
3124                         napi_disable(&rx_ring->napi);
3125                 } else {
3126                         cancel_delayed_work_sync(&rx_ring->rx_work);
3127                 }
3128         }
3129
3130         clear_bit(QL_ADAPTER_UP, &qdev->flags);
3131
3132         ql_disable_interrupts(qdev);
3133
3134         ql_tx_ring_clean(qdev);
3135
3136         spin_lock(&qdev->hw_lock);
3137         status = ql_adapter_reset(qdev);
3138         if (status)
3139                 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3140                         qdev->func);
3141         spin_unlock(&qdev->hw_lock);
3142         return status;
3143 }
3144
3145 static int ql_adapter_up(struct ql_adapter *qdev)
3146 {
3147         int err = 0;
3148
3149         spin_lock(&qdev->hw_lock);
3150         err = ql_adapter_initialize(qdev);
3151         if (err) {
3152                 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3153                 spin_unlock(&qdev->hw_lock);
3154                 goto err_init;
3155         }
3156         spin_unlock(&qdev->hw_lock);
3157         set_bit(QL_ADAPTER_UP, &qdev->flags);
3158         ql_enable_interrupts(qdev);
3159         ql_enable_all_completion_interrupts(qdev);
3160         if ((ql_read32(qdev, STS) & qdev->port_init)) {
3161                 netif_carrier_on(qdev->ndev);
3162                 netif_start_queue(qdev->ndev);
3163         }
3164
3165         return 0;
3166 err_init:
3167         ql_adapter_reset(qdev);
3168         return err;
3169 }
3170
3171 static int ql_cycle_adapter(struct ql_adapter *qdev)
3172 {
3173         int status;
3174
3175         status = ql_adapter_down(qdev);
3176         if (status)
3177                 goto error;
3178
3179         status = ql_adapter_up(qdev);
3180         if (status)
3181                 goto error;
3182
3183         return status;
3184 error:
3185         QPRINTK(qdev, IFUP, ALERT,
3186                 "Driver up/down cycle failed, closing device\n");
3187         rtnl_lock();
3188         dev_close(qdev->ndev);
3189         rtnl_unlock();
3190         return status;
3191 }
3192
3193 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3194 {
3195         ql_free_mem_resources(qdev);
3196         ql_free_irq(qdev);
3197 }
3198
3199 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3200 {
3201         int status = 0;
3202
3203         if (ql_alloc_mem_resources(qdev)) {
3204                 QPRINTK(qdev, IFUP, ERR, "Unable to  allocate memory.\n");
3205                 return -ENOMEM;
3206         }
3207         status = ql_request_irq(qdev);
3208         if (status)
3209                 goto err_irq;
3210         return status;
3211 err_irq:
3212         ql_free_mem_resources(qdev);
3213         return status;
3214 }
3215
3216 static int qlge_close(struct net_device *ndev)
3217 {
3218         struct ql_adapter *qdev = netdev_priv(ndev);
3219
3220         /*
3221          * Wait for device to recover from a reset.
3222          * (Rarely happens, but possible.)
3223          */
3224         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3225                 msleep(1);
3226         ql_adapter_down(qdev);
3227         ql_release_adapter_resources(qdev);
3228         return 0;
3229 }
3230
3231 static int ql_configure_rings(struct ql_adapter *qdev)
3232 {
3233         int i;
3234         struct rx_ring *rx_ring;
3235         struct tx_ring *tx_ring;
3236         int cpu_cnt = num_online_cpus();
3237
3238         /*
3239          * For each processor present we allocate one
3240          * rx_ring for outbound completions, and one
3241          * rx_ring for inbound completions.  Plus there is
3242          * always the one default queue.  For the CPU
3243          * counts we end up with the following rx_rings:
3244          * rx_ring count =
3245          *  one default queue +
3246          *  (CPU count * outbound completion rx_ring) +
3247          *  (CPU count * inbound (RSS) completion rx_ring)
3248          * To keep it simple we limit the total number of
3249          * queues to < 32, so we truncate CPU to 8.
3250          * This limitation can be removed when requested.
3251          */
3252
3253         if (cpu_cnt > MAX_CPUS)
3254                 cpu_cnt = MAX_CPUS;
3255
3256         /*
3257          * rx_ring[0] is always the default queue.
3258          */
3259         /* Allocate outbound completion ring for each CPU. */
3260         qdev->tx_ring_count = cpu_cnt;
3261         /* Allocate inbound completion (RSS) ring for each CPU. */
3262         qdev->rss_ring_count = cpu_cnt;
3263         /* cq_id for the first inbound ring handler. */
3264         qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3265         /*
3266          * qdev->rx_ring_count:
3267          * Total number of rx_rings.  This includes the one
3268          * default queue, a number of outbound completion
3269          * handler rx_rings, and the number of inbound
3270          * completion handler rx_rings.
3271          */
3272         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3273
3274         for (i = 0; i < qdev->tx_ring_count; i++) {
3275                 tx_ring = &qdev->tx_ring[i];
3276                 memset((void *)tx_ring, 0, sizeof(tx_ring));
3277                 tx_ring->qdev = qdev;
3278                 tx_ring->wq_id = i;
3279                 tx_ring->wq_len = qdev->tx_ring_size;
3280                 tx_ring->wq_size =
3281                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3282
3283                 /*
3284                  * The completion queue ID for the tx rings start
3285                  * immediately after the default Q ID, which is zero.
3286                  */
3287                 tx_ring->cq_id = i + 1;
3288         }
3289
3290         for (i = 0; i < qdev->rx_ring_count; i++) {
3291                 rx_ring = &qdev->rx_ring[i];
3292                 memset((void *)rx_ring, 0, sizeof(rx_ring));
3293                 rx_ring->qdev = qdev;
3294                 rx_ring->cq_id = i;
3295                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
3296                 if (i == 0) {   /* Default queue at index 0. */
3297                         /*
3298                          * Default queue handles bcast/mcast plus
3299                          * async events.  Needs buffers.
3300                          */
3301                         rx_ring->cq_len = qdev->rx_ring_size;
3302                         rx_ring->cq_size =
3303                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3304                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3305                         rx_ring->lbq_size =
3306                             rx_ring->lbq_len * sizeof(__le64);
3307                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3308                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3309                         rx_ring->sbq_size =
3310                             rx_ring->sbq_len * sizeof(__le64);
3311                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3312                         rx_ring->type = DEFAULT_Q;
3313                 } else if (i < qdev->rss_ring_first_cq_id) {
3314                         /*
3315                          * Outbound queue handles outbound completions only.
3316                          */
3317                         /* outbound cq is same size as tx_ring it services. */
3318                         rx_ring->cq_len = qdev->tx_ring_size;
3319                         rx_ring->cq_size =
3320                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3321                         rx_ring->lbq_len = 0;
3322                         rx_ring->lbq_size = 0;
3323                         rx_ring->lbq_buf_size = 0;
3324                         rx_ring->sbq_len = 0;
3325                         rx_ring->sbq_size = 0;
3326                         rx_ring->sbq_buf_size = 0;
3327                         rx_ring->type = TX_Q;
3328                 } else {        /* Inbound completions (RSS) queues */
3329                         /*
3330                          * Inbound queues handle unicast frames only.
3331                          */
3332                         rx_ring->cq_len = qdev->rx_ring_size;
3333                         rx_ring->cq_size =
3334                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3335                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3336                         rx_ring->lbq_size =
3337                             rx_ring->lbq_len * sizeof(__le64);
3338                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3339                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3340                         rx_ring->sbq_size =
3341                             rx_ring->sbq_len * sizeof(__le64);
3342                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3343                         rx_ring->type = RX_Q;
3344                 }
3345         }
3346         return 0;
3347 }
3348
3349 static int qlge_open(struct net_device *ndev)
3350 {
3351         int err = 0;
3352         struct ql_adapter *qdev = netdev_priv(ndev);
3353
3354         err = ql_configure_rings(qdev);
3355         if (err)
3356                 return err;
3357
3358         err = ql_get_adapter_resources(qdev);
3359         if (err)
3360                 goto error_up;
3361
3362         err = ql_adapter_up(qdev);
3363         if (err)
3364                 goto error_up;
3365
3366         return err;
3367
3368 error_up:
3369         ql_release_adapter_resources(qdev);
3370         return err;
3371 }
3372
3373 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3374 {
3375         struct ql_adapter *qdev = netdev_priv(ndev);
3376
3377         if (ndev->mtu == 1500 && new_mtu == 9000) {
3378                 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3379         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3380                 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3381         } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3382                    (ndev->mtu == 9000 && new_mtu == 9000)) {
3383                 return 0;
3384         } else
3385                 return -EINVAL;
3386         ndev->mtu = new_mtu;
3387         return 0;
3388 }
3389
3390 static struct net_device_stats *qlge_get_stats(struct net_device
3391                                                *ndev)
3392 {
3393         struct ql_adapter *qdev = netdev_priv(ndev);
3394         return &qdev->stats;
3395 }
3396
3397 static void qlge_set_multicast_list(struct net_device *ndev)
3398 {
3399         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3400         struct dev_mc_list *mc_ptr;
3401         int i;
3402
3403         spin_lock(&qdev->hw_lock);
3404         /*
3405          * Set or clear promiscuous mode if a
3406          * transition is taking place.
3407          */
3408         if (ndev->flags & IFF_PROMISC) {
3409                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3410                         if (ql_set_routing_reg
3411                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3412                                 QPRINTK(qdev, HW, ERR,
3413                                         "Failed to set promiscous mode.\n");
3414                         } else {
3415                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
3416                         }
3417                 }
3418         } else {
3419                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3420                         if (ql_set_routing_reg
3421                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3422                                 QPRINTK(qdev, HW, ERR,
3423                                         "Failed to clear promiscous mode.\n");
3424                         } else {
3425                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3426                         }
3427                 }
3428         }
3429
3430         /*
3431          * Set or clear all multicast mode if a
3432          * transition is taking place.
3433          */
3434         if ((ndev->flags & IFF_ALLMULTI) ||
3435             (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3436                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3437                         if (ql_set_routing_reg
3438                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3439                                 QPRINTK(qdev, HW, ERR,
3440                                         "Failed to set all-multi mode.\n");
3441                         } else {
3442                                 set_bit(QL_ALLMULTI, &qdev->flags);
3443                         }
3444                 }
3445         } else {
3446                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3447                         if (ql_set_routing_reg
3448                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3449                                 QPRINTK(qdev, HW, ERR,
3450                                         "Failed to clear all-multi mode.\n");
3451                         } else {
3452                                 clear_bit(QL_ALLMULTI, &qdev->flags);
3453                         }
3454                 }
3455         }
3456
3457         if (ndev->mc_count) {
3458                 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3459                      i++, mc_ptr = mc_ptr->next)
3460                         if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3461                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3462                                 QPRINTK(qdev, HW, ERR,
3463                                         "Failed to loadmulticast address.\n");
3464                                 goto exit;
3465                         }
3466                 if (ql_set_routing_reg
3467                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3468                         QPRINTK(qdev, HW, ERR,
3469                                 "Failed to set multicast match mode.\n");
3470                 } else {
3471                         set_bit(QL_ALLMULTI, &qdev->flags);
3472                 }
3473         }
3474 exit:
3475         spin_unlock(&qdev->hw_lock);
3476 }
3477
3478 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3479 {
3480         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3481         struct sockaddr *addr = p;
3482         int ret = 0;
3483
3484         if (netif_running(ndev))
3485                 return -EBUSY;
3486
3487         if (!is_valid_ether_addr(addr->sa_data))
3488                 return -EADDRNOTAVAIL;
3489         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3490
3491         spin_lock(&qdev->hw_lock);
3492         if (ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3493                         MAC_ADDR_TYPE_CAM_MAC, qdev->func)) {/* Unicast */
3494                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3495                 ret = -1;
3496         }
3497         spin_unlock(&qdev->hw_lock);
3498
3499         return ret;
3500 }
3501
3502 static void qlge_tx_timeout(struct net_device *ndev)
3503 {
3504         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3505         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
3506 }
3507
3508 static void ql_asic_reset_work(struct work_struct *work)
3509 {
3510         struct ql_adapter *qdev =
3511             container_of(work, struct ql_adapter, asic_reset_work.work);
3512         ql_cycle_adapter(qdev);
3513 }
3514
3515 static void ql_get_board_info(struct ql_adapter *qdev)
3516 {
3517         qdev->func =
3518             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3519         if (qdev->func) {
3520                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3521                 qdev->port_link_up = STS_PL1;
3522                 qdev->port_init = STS_PI1;
3523                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3524                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3525         } else {
3526                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3527                 qdev->port_link_up = STS_PL0;
3528                 qdev->port_init = STS_PI0;
3529                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3530                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3531         }
3532         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3533 }
3534
3535 static void ql_release_all(struct pci_dev *pdev)
3536 {
3537         struct net_device *ndev = pci_get_drvdata(pdev);
3538         struct ql_adapter *qdev = netdev_priv(ndev);
3539
3540         if (qdev->workqueue) {
3541                 destroy_workqueue(qdev->workqueue);
3542                 qdev->workqueue = NULL;
3543         }
3544         if (qdev->q_workqueue) {
3545                 destroy_workqueue(qdev->q_workqueue);
3546                 qdev->q_workqueue = NULL;
3547         }
3548         if (qdev->reg_base)
3549                 iounmap(qdev->reg_base);
3550         if (qdev->doorbell_area)
3551                 iounmap(qdev->doorbell_area);
3552         pci_release_regions(pdev);
3553         pci_set_drvdata(pdev, NULL);
3554 }
3555
3556 static int __devinit ql_init_device(struct pci_dev *pdev,
3557                                     struct net_device *ndev, int cards_found)
3558 {
3559         struct ql_adapter *qdev = netdev_priv(ndev);
3560         int pos, err = 0;
3561         u16 val16;
3562
3563         memset((void *)qdev, 0, sizeof(qdev));
3564         err = pci_enable_device(pdev);
3565         if (err) {
3566                 dev_err(&pdev->dev, "PCI device enable failed.\n");
3567                 return err;
3568         }
3569
3570         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3571         if (pos <= 0) {
3572                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3573                         "aborting.\n");
3574                 goto err_out;
3575         } else {
3576                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3577                 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3578                 val16 |= (PCI_EXP_DEVCTL_CERE |
3579                           PCI_EXP_DEVCTL_NFERE |
3580                           PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3581                 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3582         }
3583
3584         err = pci_request_regions(pdev, DRV_NAME);
3585         if (err) {
3586                 dev_err(&pdev->dev, "PCI region request failed.\n");
3587                 goto err_out;
3588         }
3589
3590         pci_set_master(pdev);
3591         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3592                 set_bit(QL_DMA64, &qdev->flags);
3593                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3594         } else {
3595                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3596                 if (!err)
3597                        err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3598         }
3599
3600         if (err) {
3601                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3602                 goto err_out;
3603         }
3604
3605         pci_set_drvdata(pdev, ndev);
3606         qdev->reg_base =
3607             ioremap_nocache(pci_resource_start(pdev, 1),
3608                             pci_resource_len(pdev, 1));
3609         if (!qdev->reg_base) {
3610                 dev_err(&pdev->dev, "Register mapping failed.\n");
3611                 err = -ENOMEM;
3612                 goto err_out;
3613         }
3614
3615         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3616         qdev->doorbell_area =
3617             ioremap_nocache(pci_resource_start(pdev, 3),
3618                             pci_resource_len(pdev, 3));
3619         if (!qdev->doorbell_area) {
3620                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3621                 err = -ENOMEM;
3622                 goto err_out;
3623         }
3624
3625         ql_get_board_info(qdev);
3626         qdev->ndev = ndev;
3627         qdev->pdev = pdev;
3628         qdev->msg_enable = netif_msg_init(debug, default_msg);
3629         spin_lock_init(&qdev->hw_lock);
3630         spin_lock_init(&qdev->stats_lock);
3631
3632         /* make sure the EEPROM is good */
3633         err = ql_get_flash_params(qdev);
3634         if (err) {
3635                 dev_err(&pdev->dev, "Invalid FLASH.\n");
3636                 goto err_out;
3637         }
3638
3639         if (!is_valid_ether_addr(qdev->flash.mac_addr))
3640                 goto err_out;
3641
3642         memcpy(ndev->dev_addr, qdev->flash.mac_addr, ndev->addr_len);
3643         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3644
3645         /* Set up the default ring sizes. */
3646         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3647         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3648
3649         /* Set up the coalescing parameters. */
3650         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3651         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3652         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3653         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3654
3655         /*
3656          * Set up the operating parameters.
3657          */
3658         qdev->rx_csum = 1;
3659
3660         qdev->q_workqueue = create_workqueue(ndev->name);
3661         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3662         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3663         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3664         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3665
3666         if (!cards_found) {
3667                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3668                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3669                          DRV_NAME, DRV_VERSION);
3670         }
3671         return 0;
3672 err_out:
3673         ql_release_all(pdev);
3674         pci_disable_device(pdev);
3675         return err;
3676 }
3677
3678
3679 static const struct net_device_ops qlge_netdev_ops = {
3680         .ndo_open               = qlge_open,
3681         .ndo_stop               = qlge_close,
3682         .ndo_start_xmit         = qlge_send,
3683         .ndo_change_mtu         = qlge_change_mtu,
3684         .ndo_get_stats          = qlge_get_stats,
3685         .ndo_set_multicast_list = qlge_set_multicast_list,
3686         .ndo_set_mac_address    = qlge_set_mac_address,
3687         .ndo_validate_addr      = eth_validate_addr,
3688         .ndo_tx_timeout         = qlge_tx_timeout,
3689         .ndo_vlan_rx_register   = ql_vlan_rx_register,
3690         .ndo_vlan_rx_add_vid    = ql_vlan_rx_add_vid,
3691         .ndo_vlan_rx_kill_vid   = ql_vlan_rx_kill_vid,
3692 };
3693
3694 static int __devinit qlge_probe(struct pci_dev *pdev,
3695                                 const struct pci_device_id *pci_entry)
3696 {
3697         struct net_device *ndev = NULL;
3698         struct ql_adapter *qdev = NULL;
3699         static int cards_found = 0;
3700         int err = 0;
3701
3702         ndev = alloc_etherdev(sizeof(struct ql_adapter));
3703         if (!ndev)
3704                 return -ENOMEM;
3705
3706         err = ql_init_device(pdev, ndev, cards_found);
3707         if (err < 0) {
3708                 free_netdev(ndev);
3709                 return err;
3710         }
3711
3712         qdev = netdev_priv(ndev);
3713         SET_NETDEV_DEV(ndev, &pdev->dev);
3714         ndev->features = (0
3715                           | NETIF_F_IP_CSUM
3716                           | NETIF_F_SG
3717                           | NETIF_F_TSO
3718                           | NETIF_F_TSO6
3719                           | NETIF_F_TSO_ECN
3720                           | NETIF_F_HW_VLAN_TX
3721                           | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3722
3723         if (test_bit(QL_DMA64, &qdev->flags))
3724                 ndev->features |= NETIF_F_HIGHDMA;
3725
3726         /*
3727          * Set up net_device structure.
3728          */
3729         ndev->tx_queue_len = qdev->tx_ring_size;
3730         ndev->irq = pdev->irq;
3731
3732         ndev->netdev_ops = &qlge_netdev_ops;
3733         SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3734         ndev->watchdog_timeo = 10 * HZ;
3735
3736         err = register_netdev(ndev);
3737         if (err) {
3738                 dev_err(&pdev->dev, "net device registration failed.\n");
3739                 ql_release_all(pdev);
3740                 pci_disable_device(pdev);
3741                 return err;
3742         }
3743         netif_carrier_off(ndev);
3744         netif_stop_queue(ndev);
3745         ql_display_dev_info(ndev);
3746         cards_found++;
3747         return 0;
3748 }
3749
3750 static void __devexit qlge_remove(struct pci_dev *pdev)
3751 {
3752         struct net_device *ndev = pci_get_drvdata(pdev);
3753         unregister_netdev(ndev);
3754         ql_release_all(pdev);
3755         pci_disable_device(pdev);
3756         free_netdev(ndev);
3757 }
3758
3759 /*
3760  * This callback is called by the PCI subsystem whenever
3761  * a PCI bus error is detected.
3762  */
3763 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3764                                                enum pci_channel_state state)
3765 {
3766         struct net_device *ndev = pci_get_drvdata(pdev);
3767         struct ql_adapter *qdev = netdev_priv(ndev);
3768
3769         if (netif_running(ndev))
3770                 ql_adapter_down(qdev);
3771
3772         pci_disable_device(pdev);
3773
3774         /* Request a slot reset. */
3775         return PCI_ERS_RESULT_NEED_RESET;
3776 }
3777
3778 /*
3779  * This callback is called after the PCI buss has been reset.
3780  * Basically, this tries to restart the card from scratch.
3781  * This is a shortened version of the device probe/discovery code,
3782  * it resembles the first-half of the () routine.
3783  */
3784 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3785 {
3786         struct net_device *ndev = pci_get_drvdata(pdev);
3787         struct ql_adapter *qdev = netdev_priv(ndev);
3788
3789         if (pci_enable_device(pdev)) {
3790                 QPRINTK(qdev, IFUP, ERR,
3791                         "Cannot re-enable PCI device after reset.\n");
3792                 return PCI_ERS_RESULT_DISCONNECT;
3793         }
3794
3795         pci_set_master(pdev);
3796
3797         netif_carrier_off(ndev);
3798         netif_stop_queue(ndev);
3799         ql_adapter_reset(qdev);
3800
3801         /* Make sure the EEPROM is good */
3802         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3803
3804         if (!is_valid_ether_addr(ndev->perm_addr)) {
3805                 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3806                 return PCI_ERS_RESULT_DISCONNECT;
3807         }
3808
3809         return PCI_ERS_RESULT_RECOVERED;
3810 }
3811
3812 static void qlge_io_resume(struct pci_dev *pdev)
3813 {
3814         struct net_device *ndev = pci_get_drvdata(pdev);
3815         struct ql_adapter *qdev = netdev_priv(ndev);
3816
3817         pci_set_master(pdev);
3818
3819         if (netif_running(ndev)) {
3820                 if (ql_adapter_up(qdev)) {
3821                         QPRINTK(qdev, IFUP, ERR,
3822                                 "Device initialization failed after reset.\n");
3823                         return;
3824                 }
3825         }
3826
3827         netif_device_attach(ndev);
3828 }
3829
3830 static struct pci_error_handlers qlge_err_handler = {
3831         .error_detected = qlge_io_error_detected,
3832         .slot_reset = qlge_io_slot_reset,
3833         .resume = qlge_io_resume,
3834 };
3835
3836 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3837 {
3838         struct net_device *ndev = pci_get_drvdata(pdev);
3839         struct ql_adapter *qdev = netdev_priv(ndev);
3840         int err, i;
3841
3842         netif_device_detach(ndev);
3843
3844         if (netif_running(ndev)) {
3845                 err = ql_adapter_down(qdev);
3846                 if (!err)
3847                         return err;
3848         }
3849
3850         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
3851                 netif_napi_del(&qdev->rx_ring[i].napi);
3852
3853         err = pci_save_state(pdev);
3854         if (err)
3855                 return err;
3856
3857         pci_disable_device(pdev);
3858
3859         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3860
3861         return 0;
3862 }
3863
3864 #ifdef CONFIG_PM
3865 static int qlge_resume(struct pci_dev *pdev)
3866 {
3867         struct net_device *ndev = pci_get_drvdata(pdev);
3868         struct ql_adapter *qdev = netdev_priv(ndev);
3869         int err;
3870
3871         pci_set_power_state(pdev, PCI_D0);
3872         pci_restore_state(pdev);
3873         err = pci_enable_device(pdev);
3874         if (err) {
3875                 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
3876                 return err;
3877         }
3878         pci_set_master(pdev);
3879
3880         pci_enable_wake(pdev, PCI_D3hot, 0);
3881         pci_enable_wake(pdev, PCI_D3cold, 0);
3882
3883         if (netif_running(ndev)) {
3884                 err = ql_adapter_up(qdev);
3885                 if (err)
3886                         return err;
3887         }
3888
3889         netif_device_attach(ndev);
3890
3891         return 0;
3892 }
3893 #endif /* CONFIG_PM */
3894
3895 static void qlge_shutdown(struct pci_dev *pdev)
3896 {
3897         qlge_suspend(pdev, PMSG_SUSPEND);
3898 }
3899
3900 static struct pci_driver qlge_driver = {
3901         .name = DRV_NAME,
3902         .id_table = qlge_pci_tbl,
3903         .probe = qlge_probe,
3904         .remove = __devexit_p(qlge_remove),
3905 #ifdef CONFIG_PM
3906         .suspend = qlge_suspend,
3907         .resume = qlge_resume,
3908 #endif
3909         .shutdown = qlge_shutdown,
3910         .err_handler = &qlge_err_handler
3911 };
3912
3913 static int __init qlge_init_module(void)
3914 {
3915         return pci_register_driver(&qlge_driver);
3916 }
3917
3918 static void __exit qlge_exit(void)
3919 {
3920         pci_unregister_driver(&qlge_driver);
3921 }
3922
3923 module_init(qlge_init_module);
3924 module_exit(qlge_exit);