2 * include/linux/spi/spidev.h
4 * Copyright (C) 2006 SWAPP
5 * Andrea Paterniani <a.paterniani@swapp-eng.it>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 /* User space versions of kernel symbols for SPI clocking modes,
27 * matching <linux/spi/spi.h>
33 #define SPI_MODE_0 (0|0)
34 #define SPI_MODE_1 (0|SPI_CPHA)
35 #define SPI_MODE_2 (SPI_CPOL|0)
36 #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
38 #define SPI_CS_HIGH 0x04
39 #define SPI_LSB_FIRST 0x08
40 #define SPI_3WIRE 0x10
43 /*---------------------------------------------------------------------------*/
47 #define SPI_IOC_MAGIC 'k'
50 * struct spi_ioc_transfer - describes a single SPI transfer
51 * @tx_buf: Holds pointer to userspace buffer with transmit data, or null.
52 * If no data is provided, zeroes are shifted out.
53 * @rx_buf: Holds pointer to userspace buffer for receive data, or null.
54 * @len: Length of tx and rx buffers, in bytes.
55 * @speed_hz: Temporary override of the device's bitrate.
56 * @bits_per_word: Temporary override of the device's wordsize.
57 * @delay_usecs: If nonzero, how long to delay after the last bit transfer
58 * before optionally deselecting the device before the next transfer.
59 * @cs_change: True to deselect device before starting the next transfer.
61 * This structure is mapped directly to the kernel spi_transfer structure;
62 * the fields have the same meanings, except of course that the pointers
63 * are in a different address space (and may be of different sizes in some
64 * cases, such as 32-bit i386 userspace over a 64-bit x86_64 kernel).
65 * Zero-initialize the structure, including currently unused fields, to
66 * accomodate potential future updates.
68 * SPI_IOC_MESSAGE gives userspace the equivalent of kernel spi_sync().
69 * Pass it an array of related transfers, they'll execute together.
70 * Each transfer may be half duplex (either direction) or full duplex.
72 * struct spi_ioc_transfer mesg[4];
74 * status = ioctl(fd, SPI_IOC_MESSAGE(4), mesg);
76 * So for example one transfer might send a nine bit command (right aligned
77 * in a 16-bit word), the next could read a block of 8-bit data before
78 * terminating that command by temporarily deselecting the chip; the next
79 * could send a different nine bit command (re-selecting the chip), and the
80 * last transfer might write some register values.
82 struct spi_ioc_transfer {
94 /* If the contents of 'struct spi_ioc_transfer' ever change
95 * incompatibly, then the ioctl number (currently 0) must change;
96 * ioctls with constant size fields get a bit more in the way of
97 * error checking than ones (like this) where that field varies.
99 * NOTE: struct layout is the same in 64bit and 32bit userspace.
103 /* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */
104 #define SPI_MSGSIZE(N) \
105 ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \
106 ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0)
107 #define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)])
110 /* Read / Write of SPI mode (SPI_MODE_0..SPI_MODE_3) */
111 #define SPI_IOC_RD_MODE _IOR(SPI_IOC_MAGIC, 1, __u8)
112 #define SPI_IOC_WR_MODE _IOW(SPI_IOC_MAGIC, 1, __u8)
114 /* Read / Write SPI bit justification */
115 #define SPI_IOC_RD_LSB_FIRST _IOR(SPI_IOC_MAGIC, 2, __u8)
116 #define SPI_IOC_WR_LSB_FIRST _IOW(SPI_IOC_MAGIC, 2, __u8)
118 /* Read / Write SPI device word length (1..N) */
119 #define SPI_IOC_RD_BITS_PER_WORD _IOR(SPI_IOC_MAGIC, 3, __u8)
120 #define SPI_IOC_WR_BITS_PER_WORD _IOW(SPI_IOC_MAGIC, 3, __u8)
122 /* Read / Write SPI device default max speed hz */
123 #define SPI_IOC_RD_MAX_SPEED_HZ _IOR(SPI_IOC_MAGIC, 4, __u32)
124 #define SPI_IOC_WR_MAX_SPEED_HZ _IOW(SPI_IOC_MAGIC, 4, __u32)
128 #endif /* SPIDEV_H */