[netdrvr forcedeth] phy address scan range
[linux-2.6] / drivers / net / forcedeth.c
1 /*
2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3  *
4  * Note: This driver is a cleanroom reimplementation based on reverse
5  *      engineered documentation written by Carl-Daniel Hailfinger
6  *      and Andrew de Quincey. It's neither supported nor endorsed
7  *      by NVIDIA Corp. Use at your own risk.
8  *
9  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10  * trademarks of NVIDIA Corporation in the United States and other
11  * countries.
12  *
13  * Copyright (C) 2003,4 Manfred Spraul
14  * Copyright (C) 2004 Andrew de Quincey (wol support)
15  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
17  * Copyright (c) 2004 NVIDIA Corporation
18  *
19  * This program is free software; you can redistribute it and/or modify
20  * it under the terms of the GNU General Public License as published by
21  * the Free Software Foundation; either version 2 of the License, or
22  * (at your option) any later version.
23  *
24  * This program is distributed in the hope that it will be useful,
25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
27  * GNU General Public License for more details.
28  *
29  * You should have received a copy of the GNU General Public License
30  * along with this program; if not, write to the Free Software
31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
32  *
33  * Changelog:
34  *      0.01: 05 Oct 2003: First release that compiles without warnings.
35  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36  *                         Check all PCI BARs for the register window.
37  *                         udelay added to mii_rw.
38  *      0.03: 06 Oct 2003: Initialize dev->irq.
39  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
42  *                         irq mask updated
43  *      0.07: 14 Oct 2003: Further irq mask updates.
44  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45  *                         added into irq handler, NULL check for drain_ring.
46  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47  *                         requested interrupt sources.
48  *      0.10: 20 Oct 2003: First cleanup for release.
49  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50  *                         MAC Address init fix, set_multicast cleanup.
51  *      0.12: 23 Oct 2003: Cleanups for release.
52  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53  *                         Set link speed correctly. start rx before starting
54  *                         tx (nv_start_rx sets the link speed).
55  *      0.14: 25 Oct 2003: Nic dependant irq mask.
56  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
57  *                         open.
58  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59  *                         increased to 1628 bytes.
60  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
61  *                         the tx length.
62  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64  *                         addresses, really stop rx if already running
65  *                         in nv_start_rx, clean up a bit.
66  *      0.20: 07 Dec 2003: alloc fixes
67  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
69  *                         on close.
70  *      0.23: 26 Jan 2004: various small cleanups
71  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72  *      0.25: 09 Mar 2004: wol support
73  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75  *                         added CK804/MCP04 device IDs, code fixes
76  *                         for registers, link status and other minor fixes.
77  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
79  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80  *                         into nv_close, otherwise reenabling for wol can
81  *                         cause DMA to kfree'd memory.
82  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
83  *                         capabilities.
84  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
85  *      0.33: 16 May 2005: Support for MCP51 added.
86  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
87  *      0.35: 26 Jun 2005: Support for MCP55 added.
88  *      0.36: 28 Jun 2005: Add jumbo frame support.
89  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
90  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
91  *                         per-packet flags.
92  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
93  *      0.40: 19 Jul 2005: Add support for mac address change.
94  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
95  *                         of nv_remove
96  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
97  *                         in the second (and later) nv_open call
98  *      0.43: 10 Aug 2005: Add support for tx checksum.
99  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
100  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
101  *      0.46: 20 Oct 2005: Add irq optimization modes.
102  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
103  *
104  * Known bugs:
105  * We suspect that on some hardware no TX done interrupts are generated.
106  * This means recovery from netif_stop_queue only happens if the hw timer
107  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
108  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
109  * If your hardware reliably generates tx done interrupts, then you can remove
110  * DEV_NEED_TIMERIRQ from the driver_data flags.
111  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
112  * superfluous timer interrupts from the nic.
113  */
114 #define FORCEDETH_VERSION               "0.47"
115 #define DRV_NAME                        "forcedeth"
116
117 #include <linux/module.h>
118 #include <linux/types.h>
119 #include <linux/pci.h>
120 #include <linux/interrupt.h>
121 #include <linux/netdevice.h>
122 #include <linux/etherdevice.h>
123 #include <linux/delay.h>
124 #include <linux/spinlock.h>
125 #include <linux/ethtool.h>
126 #include <linux/timer.h>
127 #include <linux/skbuff.h>
128 #include <linux/mii.h>
129 #include <linux/random.h>
130 #include <linux/init.h>
131 #include <linux/if_vlan.h>
132
133 #include <asm/irq.h>
134 #include <asm/io.h>
135 #include <asm/uaccess.h>
136 #include <asm/system.h>
137
138 #if 0
139 #define dprintk                 printk
140 #else
141 #define dprintk(x...)           do { } while (0)
142 #endif
143
144
145 /*
146  * Hardware access:
147  */
148
149 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
150 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
151 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
152 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
153 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
154
155 enum {
156         NvRegIrqStatus = 0x000,
157 #define NVREG_IRQSTAT_MIIEVENT  0x040
158 #define NVREG_IRQSTAT_MASK              0x1ff
159         NvRegIrqMask = 0x004,
160 #define NVREG_IRQ_RX_ERROR              0x0001
161 #define NVREG_IRQ_RX                    0x0002
162 #define NVREG_IRQ_RX_NOBUF              0x0004
163 #define NVREG_IRQ_TX_ERR                0x0008
164 #define NVREG_IRQ_TX_OK                 0x0010
165 #define NVREG_IRQ_TIMER                 0x0020
166 #define NVREG_IRQ_LINK                  0x0040
167 #define NVREG_IRQ_TX_ERROR              0x0080
168 #define NVREG_IRQ_TX1                   0x0100
169 #define NVREG_IRQMASK_THROUGHPUT        0x00df
170 #define NVREG_IRQMASK_CPU               0x0040
171
172 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
173                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX_ERROR| \
174                                         NVREG_IRQ_TX1))
175
176         NvRegUnknownSetupReg6 = 0x008,
177 #define NVREG_UNKSETUP6_VAL             3
178
179 /*
180  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
181  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
182  */
183         NvRegPollingInterval = 0x00c,
184 #define NVREG_POLL_DEFAULT_THROUGHPUT   970
185 #define NVREG_POLL_DEFAULT_CPU  13
186         NvRegMisc1 = 0x080,
187 #define NVREG_MISC1_HD          0x02
188 #define NVREG_MISC1_FORCE       0x3b0f3c
189
190         NvRegTransmitterControl = 0x084,
191 #define NVREG_XMITCTL_START     0x01
192         NvRegTransmitterStatus = 0x088,
193 #define NVREG_XMITSTAT_BUSY     0x01
194
195         NvRegPacketFilterFlags = 0x8c,
196 #define NVREG_PFF_ALWAYS        0x7F0008
197 #define NVREG_PFF_PROMISC       0x80
198 #define NVREG_PFF_MYADDR        0x20
199
200         NvRegOffloadConfig = 0x90,
201 #define NVREG_OFFLOAD_HOMEPHY   0x601
202 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
203         NvRegReceiverControl = 0x094,
204 #define NVREG_RCVCTL_START      0x01
205         NvRegReceiverStatus = 0x98,
206 #define NVREG_RCVSTAT_BUSY      0x01
207
208         NvRegRandomSeed = 0x9c,
209 #define NVREG_RNDSEED_MASK      0x00ff
210 #define NVREG_RNDSEED_FORCE     0x7f00
211 #define NVREG_RNDSEED_FORCE2    0x2d00
212 #define NVREG_RNDSEED_FORCE3    0x7400
213
214         NvRegUnknownSetupReg1 = 0xA0,
215 #define NVREG_UNKSETUP1_VAL     0x16070f
216         NvRegUnknownSetupReg2 = 0xA4,
217 #define NVREG_UNKSETUP2_VAL     0x16
218         NvRegMacAddrA = 0xA8,
219         NvRegMacAddrB = 0xAC,
220         NvRegMulticastAddrA = 0xB0,
221 #define NVREG_MCASTADDRA_FORCE  0x01
222         NvRegMulticastAddrB = 0xB4,
223         NvRegMulticastMaskA = 0xB8,
224         NvRegMulticastMaskB = 0xBC,
225
226         NvRegPhyInterface = 0xC0,
227 #define PHY_RGMII               0x10000000
228
229         NvRegTxRingPhysAddr = 0x100,
230         NvRegRxRingPhysAddr = 0x104,
231         NvRegRingSizes = 0x108,
232 #define NVREG_RINGSZ_TXSHIFT 0
233 #define NVREG_RINGSZ_RXSHIFT 16
234         NvRegUnknownTransmitterReg = 0x10c,
235         NvRegLinkSpeed = 0x110,
236 #define NVREG_LINKSPEED_FORCE 0x10000
237 #define NVREG_LINKSPEED_10      1000
238 #define NVREG_LINKSPEED_100     100
239 #define NVREG_LINKSPEED_1000    50
240 #define NVREG_LINKSPEED_MASK    (0xFFF)
241         NvRegUnknownSetupReg5 = 0x130,
242 #define NVREG_UNKSETUP5_BIT31   (1<<31)
243         NvRegUnknownSetupReg3 = 0x13c,
244 #define NVREG_UNKSETUP3_VAL1    0x200010
245         NvRegTxRxControl = 0x144,
246 #define NVREG_TXRXCTL_KICK      0x0001
247 #define NVREG_TXRXCTL_BIT1      0x0002
248 #define NVREG_TXRXCTL_BIT2      0x0004
249 #define NVREG_TXRXCTL_IDLE      0x0008
250 #define NVREG_TXRXCTL_RESET     0x0010
251 #define NVREG_TXRXCTL_RXCHECK   0x0400
252 #define NVREG_TXRXCTL_DESC_1    0
253 #define NVREG_TXRXCTL_DESC_2    0x02100
254 #define NVREG_TXRXCTL_DESC_3    0x02200
255         NvRegMIIStatus = 0x180,
256 #define NVREG_MIISTAT_ERROR             0x0001
257 #define NVREG_MIISTAT_LINKCHANGE        0x0008
258 #define NVREG_MIISTAT_MASK              0x000f
259 #define NVREG_MIISTAT_MASK2             0x000f
260         NvRegUnknownSetupReg4 = 0x184,
261 #define NVREG_UNKSETUP4_VAL     8
262
263         NvRegAdapterControl = 0x188,
264 #define NVREG_ADAPTCTL_START    0x02
265 #define NVREG_ADAPTCTL_LINKUP   0x04
266 #define NVREG_ADAPTCTL_PHYVALID 0x40000
267 #define NVREG_ADAPTCTL_RUNNING  0x100000
268 #define NVREG_ADAPTCTL_PHYSHIFT 24
269         NvRegMIISpeed = 0x18c,
270 #define NVREG_MIISPEED_BIT8     (1<<8)
271 #define NVREG_MIIDELAY  5
272         NvRegMIIControl = 0x190,
273 #define NVREG_MIICTL_INUSE      0x08000
274 #define NVREG_MIICTL_WRITE      0x00400
275 #define NVREG_MIICTL_ADDRSHIFT  5
276         NvRegMIIData = 0x194,
277         NvRegWakeUpFlags = 0x200,
278 #define NVREG_WAKEUPFLAGS_VAL           0x7770
279 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
280 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
281 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
282 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
283 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
284 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
285 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
286 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
287 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
288 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
289
290         NvRegPatternCRC = 0x204,
291         NvRegPatternMask = 0x208,
292         NvRegPowerCap = 0x268,
293 #define NVREG_POWERCAP_D3SUPP   (1<<30)
294 #define NVREG_POWERCAP_D2SUPP   (1<<26)
295 #define NVREG_POWERCAP_D1SUPP   (1<<25)
296         NvRegPowerState = 0x26c,
297 #define NVREG_POWERSTATE_POWEREDUP      0x8000
298 #define NVREG_POWERSTATE_VALID          0x0100
299 #define NVREG_POWERSTATE_MASK           0x0003
300 #define NVREG_POWERSTATE_D0             0x0000
301 #define NVREG_POWERSTATE_D1             0x0001
302 #define NVREG_POWERSTATE_D2             0x0002
303 #define NVREG_POWERSTATE_D3             0x0003
304 };
305
306 /* Big endian: should work, but is untested */
307 struct ring_desc {
308         u32 PacketBuffer;
309         u32 FlagLen;
310 };
311
312 struct ring_desc_ex {
313         u32 PacketBufferHigh;
314         u32 PacketBufferLow;
315         u32 Reserved;
316         u32 FlagLen;
317 };
318
319 typedef union _ring_type {
320         struct ring_desc* orig;
321         struct ring_desc_ex* ex;
322 } ring_type;
323
324 #define FLAG_MASK_V1 0xffff0000
325 #define FLAG_MASK_V2 0xffffc000
326 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
327 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
328
329 #define NV_TX_LASTPACKET        (1<<16)
330 #define NV_TX_RETRYERROR        (1<<19)
331 #define NV_TX_FORCED_INTERRUPT  (1<<24)
332 #define NV_TX_DEFERRED          (1<<26)
333 #define NV_TX_CARRIERLOST       (1<<27)
334 #define NV_TX_LATECOLLISION     (1<<28)
335 #define NV_TX_UNDERFLOW         (1<<29)
336 #define NV_TX_ERROR             (1<<30)
337 #define NV_TX_VALID             (1<<31)
338
339 #define NV_TX2_LASTPACKET       (1<<29)
340 #define NV_TX2_RETRYERROR       (1<<18)
341 #define NV_TX2_FORCED_INTERRUPT (1<<30)
342 #define NV_TX2_DEFERRED         (1<<25)
343 #define NV_TX2_CARRIERLOST      (1<<26)
344 #define NV_TX2_LATECOLLISION    (1<<27)
345 #define NV_TX2_UNDERFLOW        (1<<28)
346 /* error and valid are the same for both */
347 #define NV_TX2_ERROR            (1<<30)
348 #define NV_TX2_VALID            (1<<31)
349 #define NV_TX2_TSO              (1<<28)
350 #define NV_TX2_TSO_SHIFT        14
351 #define NV_TX2_CHECKSUM_L3      (1<<27)
352 #define NV_TX2_CHECKSUM_L4      (1<<26)
353
354 #define NV_RX_DESCRIPTORVALID   (1<<16)
355 #define NV_RX_MISSEDFRAME       (1<<17)
356 #define NV_RX_SUBSTRACT1        (1<<18)
357 #define NV_RX_ERROR1            (1<<23)
358 #define NV_RX_ERROR2            (1<<24)
359 #define NV_RX_ERROR3            (1<<25)
360 #define NV_RX_ERROR4            (1<<26)
361 #define NV_RX_CRCERR            (1<<27)
362 #define NV_RX_OVERFLOW          (1<<28)
363 #define NV_RX_FRAMINGERR        (1<<29)
364 #define NV_RX_ERROR             (1<<30)
365 #define NV_RX_AVAIL             (1<<31)
366
367 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
368 #define NV_RX2_CHECKSUMOK1      (0x10000000)
369 #define NV_RX2_CHECKSUMOK2      (0x14000000)
370 #define NV_RX2_CHECKSUMOK3      (0x18000000)
371 #define NV_RX2_DESCRIPTORVALID  (1<<29)
372 #define NV_RX2_SUBSTRACT1       (1<<25)
373 #define NV_RX2_ERROR1           (1<<18)
374 #define NV_RX2_ERROR2           (1<<19)
375 #define NV_RX2_ERROR3           (1<<20)
376 #define NV_RX2_ERROR4           (1<<21)
377 #define NV_RX2_CRCERR           (1<<22)
378 #define NV_RX2_OVERFLOW         (1<<23)
379 #define NV_RX2_FRAMINGERR       (1<<24)
380 /* error and avail are the same for both */
381 #define NV_RX2_ERROR            (1<<30)
382 #define NV_RX2_AVAIL            (1<<31)
383
384 /* Miscelaneous hardware related defines: */
385 #define NV_PCI_REGSZ            0x270
386
387 /* various timeout delays: all in usec */
388 #define NV_TXRX_RESET_DELAY     4
389 #define NV_TXSTOP_DELAY1        10
390 #define NV_TXSTOP_DELAY1MAX     500000
391 #define NV_TXSTOP_DELAY2        100
392 #define NV_RXSTOP_DELAY1        10
393 #define NV_RXSTOP_DELAY1MAX     500000
394 #define NV_RXSTOP_DELAY2        100
395 #define NV_SETUP5_DELAY         5
396 #define NV_SETUP5_DELAYMAX      50000
397 #define NV_POWERUP_DELAY        5
398 #define NV_POWERUP_DELAYMAX     5000
399 #define NV_MIIBUSY_DELAY        50
400 #define NV_MIIPHY_DELAY 10
401 #define NV_MIIPHY_DELAYMAX      10000
402
403 #define NV_WAKEUPPATTERNS       5
404 #define NV_WAKEUPMASKENTRIES    4
405
406 /* General driver defaults */
407 #define NV_WATCHDOG_TIMEO       (5*HZ)
408
409 #define RX_RING         128
410 #define TX_RING         64
411 /* 
412  * If your nic mysteriously hangs then try to reduce the limits
413  * to 1/0: It might be required to set NV_TX_LASTPACKET in the
414  * last valid ring entry. But this would be impossible to
415  * implement - probably a disassembly error.
416  */
417 #define TX_LIMIT_STOP   63
418 #define TX_LIMIT_START  62
419
420 /* rx/tx mac addr + type + vlan + align + slack*/
421 #define NV_RX_HEADERS           (64)
422 /* even more slack. */
423 #define NV_RX_ALLOC_PAD         (64)
424
425 /* maximum mtu size */
426 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
427 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
428
429 #define OOM_REFILL      (1+HZ/20)
430 #define POLL_WAIT       (1+HZ/100)
431 #define LINK_TIMEOUT    (3*HZ)
432
433 /* 
434  * desc_ver values:
435  * The nic supports three different descriptor types:
436  * - DESC_VER_1: Original
437  * - DESC_VER_2: support for jumbo frames.
438  * - DESC_VER_3: 64-bit format.
439  */
440 #define DESC_VER_1      1
441 #define DESC_VER_2      2
442 #define DESC_VER_3      3
443
444 /* PHY defines */
445 #define PHY_OUI_MARVELL 0x5043
446 #define PHY_OUI_CICADA  0x03f1
447 #define PHYID1_OUI_MASK 0x03ff
448 #define PHYID1_OUI_SHFT 6
449 #define PHYID2_OUI_MASK 0xfc00
450 #define PHYID2_OUI_SHFT 10
451 #define PHY_INIT1       0x0f000
452 #define PHY_INIT2       0x0e00
453 #define PHY_INIT3       0x01000
454 #define PHY_INIT4       0x0200
455 #define PHY_INIT5       0x0004
456 #define PHY_INIT6       0x02000
457 #define PHY_GIGABIT     0x0100
458
459 #define PHY_TIMEOUT     0x1
460 #define PHY_ERROR       0x2
461
462 #define PHY_100 0x1
463 #define PHY_1000        0x2
464 #define PHY_HALF        0x100
465
466 /* FIXME: MII defines that should be added to <linux/mii.h> */
467 #define MII_1000BT_CR   0x09
468 #define MII_1000BT_SR   0x0a
469 #define ADVERTISE_1000FULL      0x0200
470 #define ADVERTISE_1000HALF      0x0100
471 #define LPA_1000FULL    0x0800
472 #define LPA_1000HALF    0x0400
473
474
475 /*
476  * SMP locking:
477  * All hardware access under dev->priv->lock, except the performance
478  * critical parts:
479  * - rx is (pseudo-) lockless: it relies on the single-threading provided
480  *      by the arch code for interrupts.
481  * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
482  *      needs dev->priv->lock :-(
483  * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
484  */
485
486 /* in dev: base, irq */
487 struct fe_priv {
488         spinlock_t lock;
489
490         /* General data:
491          * Locking: spin_lock(&np->lock); */
492         struct net_device_stats stats;
493         int in_shutdown;
494         u32 linkspeed;
495         int duplex;
496         int autoneg;
497         int fixed_mode;
498         int phyaddr;
499         int wolenabled;
500         unsigned int phy_oui;
501         u16 gigabit;
502
503         /* General data: RO fields */
504         dma_addr_t ring_addr;
505         struct pci_dev *pci_dev;
506         u32 orig_mac[2];
507         u32 irqmask;
508         u32 desc_ver;
509         u32 txrxctl_bits;
510
511         void __iomem *base;
512
513         /* rx specific fields.
514          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
515          */
516         ring_type rx_ring;
517         unsigned int cur_rx, refill_rx;
518         struct sk_buff *rx_skbuff[RX_RING];
519         dma_addr_t rx_dma[RX_RING];
520         unsigned int rx_buf_sz;
521         unsigned int pkt_limit;
522         struct timer_list oom_kick;
523         struct timer_list nic_poll;
524
525         /* media detection workaround.
526          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
527          */
528         int need_linktimer;
529         unsigned long link_timeout;
530         /*
531          * tx specific fields.
532          */
533         ring_type tx_ring;
534         unsigned int next_tx, nic_tx;
535         struct sk_buff *tx_skbuff[TX_RING];
536         dma_addr_t tx_dma[TX_RING];
537         u32 tx_flags;
538 };
539
540 /*
541  * Maximum number of loops until we assume that a bit in the irq mask
542  * is stuck. Overridable with module param.
543  */
544 static int max_interrupt_work = 5;
545
546 /*
547  * Optimization can be either throuput mode or cpu mode
548  * 
549  * Throughput Mode: Every tx and rx packet will generate an interrupt.
550  * CPU Mode: Interrupts are controlled by a timer.
551  */
552 #define NV_OPTIMIZATION_MODE_THROUGHPUT 0
553 #define NV_OPTIMIZATION_MODE_CPU        1
554 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
555
556 /*
557  * Poll interval for timer irq
558  *
559  * This interval determines how frequent an interrupt is generated.
560  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
561  * Min = 0, and Max = 65535
562  */
563 static int poll_interval = -1;
564
565 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
566 {
567         return netdev_priv(dev);
568 }
569
570 static inline u8 __iomem *get_hwbase(struct net_device *dev)
571 {
572         return ((struct fe_priv *)netdev_priv(dev))->base;
573 }
574
575 static inline void pci_push(u8 __iomem *base)
576 {
577         /* force out pending posted writes */
578         readl(base);
579 }
580
581 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
582 {
583         return le32_to_cpu(prd->FlagLen)
584                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
585 }
586
587 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
588 {
589         return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
590 }
591
592 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
593                                 int delay, int delaymax, const char *msg)
594 {
595         u8 __iomem *base = get_hwbase(dev);
596
597         pci_push(base);
598         do {
599                 udelay(delay);
600                 delaymax -= delay;
601                 if (delaymax < 0) {
602                         if (msg)
603                                 printk(msg);
604                         return 1;
605                 }
606         } while ((readl(base + offset) & mask) != target);
607         return 0;
608 }
609
610 #define MII_READ        (-1)
611 /* mii_rw: read/write a register on the PHY.
612  *
613  * Caller must guarantee serialization
614  */
615 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
616 {
617         u8 __iomem *base = get_hwbase(dev);
618         u32 reg;
619         int retval;
620
621         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
622
623         reg = readl(base + NvRegMIIControl);
624         if (reg & NVREG_MIICTL_INUSE) {
625                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
626                 udelay(NV_MIIBUSY_DELAY);
627         }
628
629         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
630         if (value != MII_READ) {
631                 writel(value, base + NvRegMIIData);
632                 reg |= NVREG_MIICTL_WRITE;
633         }
634         writel(reg, base + NvRegMIIControl);
635
636         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
637                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
638                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
639                                 dev->name, miireg, addr);
640                 retval = -1;
641         } else if (value != MII_READ) {
642                 /* it was a write operation - fewer failures are detectable */
643                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
644                                 dev->name, value, miireg, addr);
645                 retval = 0;
646         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
647                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
648                                 dev->name, miireg, addr);
649                 retval = -1;
650         } else {
651                 retval = readl(base + NvRegMIIData);
652                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
653                                 dev->name, miireg, addr, retval);
654         }
655
656         return retval;
657 }
658
659 static int phy_reset(struct net_device *dev)
660 {
661         struct fe_priv *np = netdev_priv(dev);
662         u32 miicontrol;
663         unsigned int tries = 0;
664
665         miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
666         miicontrol |= BMCR_RESET;
667         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
668                 return -1;
669         }
670
671         /* wait for 500ms */
672         msleep(500);
673
674         /* must wait till reset is deasserted */
675         while (miicontrol & BMCR_RESET) {
676                 msleep(10);
677                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
678                 /* FIXME: 100 tries seem excessive */
679                 if (tries++ > 100)
680                         return -1;
681         }
682         return 0;
683 }
684
685 static int phy_init(struct net_device *dev)
686 {
687         struct fe_priv *np = get_nvpriv(dev);
688         u8 __iomem *base = get_hwbase(dev);
689         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
690
691         /* set advertise register */
692         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
693         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
694         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
695                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
696                 return PHY_ERROR;
697         }
698
699         /* get phy interface type */
700         phyinterface = readl(base + NvRegPhyInterface);
701
702         /* see if gigabit phy */
703         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
704         if (mii_status & PHY_GIGABIT) {
705                 np->gigabit = PHY_GIGABIT;
706                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
707                 mii_control_1000 &= ~ADVERTISE_1000HALF;
708                 if (phyinterface & PHY_RGMII)
709                         mii_control_1000 |= ADVERTISE_1000FULL;
710                 else
711                         mii_control_1000 &= ~ADVERTISE_1000FULL;
712
713                 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
714                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
715                         return PHY_ERROR;
716                 }
717         }
718         else
719                 np->gigabit = 0;
720
721         /* reset the phy */
722         if (phy_reset(dev)) {
723                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
724                 return PHY_ERROR;
725         }
726
727         /* phy vendor specific configuration */
728         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
729                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
730                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
731                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
732                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
733                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
734                         return PHY_ERROR;
735                 }
736                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
737                 phy_reserved |= PHY_INIT5;
738                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
739                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
740                         return PHY_ERROR;
741                 }
742         }
743         if (np->phy_oui == PHY_OUI_CICADA) {
744                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
745                 phy_reserved |= PHY_INIT6;
746                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
747                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
748                         return PHY_ERROR;
749                 }
750         }
751
752         /* restart auto negotiation */
753         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
754         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
755         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
756                 return PHY_ERROR;
757         }
758
759         return 0;
760 }
761
762 static void nv_start_rx(struct net_device *dev)
763 {
764         struct fe_priv *np = netdev_priv(dev);
765         u8 __iomem *base = get_hwbase(dev);
766
767         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
768         /* Already running? Stop it. */
769         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
770                 writel(0, base + NvRegReceiverControl);
771                 pci_push(base);
772         }
773         writel(np->linkspeed, base + NvRegLinkSpeed);
774         pci_push(base);
775         writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
776         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
777                                 dev->name, np->duplex, np->linkspeed);
778         pci_push(base);
779 }
780
781 static void nv_stop_rx(struct net_device *dev)
782 {
783         u8 __iomem *base = get_hwbase(dev);
784
785         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
786         writel(0, base + NvRegReceiverControl);
787         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
788                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
789                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
790
791         udelay(NV_RXSTOP_DELAY2);
792         writel(0, base + NvRegLinkSpeed);
793 }
794
795 static void nv_start_tx(struct net_device *dev)
796 {
797         u8 __iomem *base = get_hwbase(dev);
798
799         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
800         writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
801         pci_push(base);
802 }
803
804 static void nv_stop_tx(struct net_device *dev)
805 {
806         u8 __iomem *base = get_hwbase(dev);
807
808         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
809         writel(0, base + NvRegTransmitterControl);
810         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
811                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
812                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
813
814         udelay(NV_TXSTOP_DELAY2);
815         writel(0, base + NvRegUnknownTransmitterReg);
816 }
817
818 static void nv_txrx_reset(struct net_device *dev)
819 {
820         struct fe_priv *np = netdev_priv(dev);
821         u8 __iomem *base = get_hwbase(dev);
822
823         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
824         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
825         pci_push(base);
826         udelay(NV_TXRX_RESET_DELAY);
827         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
828         pci_push(base);
829 }
830
831 /*
832  * nv_get_stats: dev->get_stats function
833  * Get latest stats value from the nic.
834  * Called with read_lock(&dev_base_lock) held for read -
835  * only synchronized against unregister_netdevice.
836  */
837 static struct net_device_stats *nv_get_stats(struct net_device *dev)
838 {
839         struct fe_priv *np = netdev_priv(dev);
840
841         /* It seems that the nic always generates interrupts and doesn't
842          * accumulate errors internally. Thus the current values in np->stats
843          * are already up to date.
844          */
845         return &np->stats;
846 }
847
848 /*
849  * nv_alloc_rx: fill rx ring entries.
850  * Return 1 if the allocations for the skbs failed and the
851  * rx engine is without Available descriptors
852  */
853 static int nv_alloc_rx(struct net_device *dev)
854 {
855         struct fe_priv *np = netdev_priv(dev);
856         unsigned int refill_rx = np->refill_rx;
857         int nr;
858
859         while (np->cur_rx != refill_rx) {
860                 struct sk_buff *skb;
861
862                 nr = refill_rx % RX_RING;
863                 if (np->rx_skbuff[nr] == NULL) {
864
865                         skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
866                         if (!skb)
867                                 break;
868
869                         skb->dev = dev;
870                         np->rx_skbuff[nr] = skb;
871                 } else {
872                         skb = np->rx_skbuff[nr];
873                 }
874                 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len,
875                                                 PCI_DMA_FROMDEVICE);
876                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
877                         np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
878                         wmb();
879                         np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
880                 } else {
881                         np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
882                         np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
883                         wmb();
884                         np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
885                 }
886                 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
887                                         dev->name, refill_rx);
888                 refill_rx++;
889         }
890         np->refill_rx = refill_rx;
891         if (np->cur_rx - refill_rx == RX_RING)
892                 return 1;
893         return 0;
894 }
895
896 static void nv_do_rx_refill(unsigned long data)
897 {
898         struct net_device *dev = (struct net_device *) data;
899         struct fe_priv *np = netdev_priv(dev);
900
901         disable_irq(dev->irq);
902         if (nv_alloc_rx(dev)) {
903                 spin_lock(&np->lock);
904                 if (!np->in_shutdown)
905                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
906                 spin_unlock(&np->lock);
907         }
908         enable_irq(dev->irq);
909 }
910
911 static void nv_init_rx(struct net_device *dev) 
912 {
913         struct fe_priv *np = netdev_priv(dev);
914         int i;
915
916         np->cur_rx = RX_RING;
917         np->refill_rx = 0;
918         for (i = 0; i < RX_RING; i++)
919                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
920                         np->rx_ring.orig[i].FlagLen = 0;
921                 else
922                         np->rx_ring.ex[i].FlagLen = 0;
923 }
924
925 static void nv_init_tx(struct net_device *dev)
926 {
927         struct fe_priv *np = netdev_priv(dev);
928         int i;
929
930         np->next_tx = np->nic_tx = 0;
931         for (i = 0; i < TX_RING; i++) {
932                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
933                         np->tx_ring.orig[i].FlagLen = 0;
934                 else
935                         np->tx_ring.ex[i].FlagLen = 0;
936                 np->tx_skbuff[i] = NULL;
937         }
938 }
939
940 static int nv_init_ring(struct net_device *dev)
941 {
942         nv_init_tx(dev);
943         nv_init_rx(dev);
944         return nv_alloc_rx(dev);
945 }
946
947 static void nv_release_txskb(struct net_device *dev, unsigned int skbnr)
948 {
949         struct fe_priv *np = netdev_priv(dev);
950         struct sk_buff *skb = np->tx_skbuff[skbnr];
951         unsigned int j, entry, fragments;
952                         
953         dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d, skb %p\n",
954                 dev->name, skbnr, np->tx_skbuff[skbnr]);
955         
956         entry = skbnr;
957         if ((fragments = skb_shinfo(skb)->nr_frags) != 0) {
958                 for (j = fragments; j >= 1; j--) {
959                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j-1];
960                         pci_unmap_page(np->pci_dev, np->tx_dma[entry],
961                                        frag->size,
962                                        PCI_DMA_TODEVICE);
963                         entry = (entry - 1) % TX_RING;
964                 }
965         }
966         pci_unmap_single(np->pci_dev, np->tx_dma[entry],
967                          skb->len - skb->data_len,
968                          PCI_DMA_TODEVICE);
969         dev_kfree_skb_irq(skb);
970         np->tx_skbuff[skbnr] = NULL;
971 }
972
973 static void nv_drain_tx(struct net_device *dev)
974 {
975         struct fe_priv *np = netdev_priv(dev);
976         unsigned int i;
977         
978         for (i = 0; i < TX_RING; i++) {
979                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
980                         np->tx_ring.orig[i].FlagLen = 0;
981                 else
982                         np->tx_ring.ex[i].FlagLen = 0;
983                 if (np->tx_skbuff[i]) {
984                         nv_release_txskb(dev, i);
985                         np->stats.tx_dropped++;
986                 }
987         }
988 }
989
990 static void nv_drain_rx(struct net_device *dev)
991 {
992         struct fe_priv *np = netdev_priv(dev);
993         int i;
994         for (i = 0; i < RX_RING; i++) {
995                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
996                         np->rx_ring.orig[i].FlagLen = 0;
997                 else
998                         np->rx_ring.ex[i].FlagLen = 0;
999                 wmb();
1000                 if (np->rx_skbuff[i]) {
1001                         pci_unmap_single(np->pci_dev, np->rx_dma[i],
1002                                                 np->rx_skbuff[i]->len,
1003                                                 PCI_DMA_FROMDEVICE);
1004                         dev_kfree_skb(np->rx_skbuff[i]);
1005                         np->rx_skbuff[i] = NULL;
1006                 }
1007         }
1008 }
1009
1010 static void drain_ring(struct net_device *dev)
1011 {
1012         nv_drain_tx(dev);
1013         nv_drain_rx(dev);
1014 }
1015
1016 /*
1017  * nv_start_xmit: dev->hard_start_xmit function
1018  * Called with dev->xmit_lock held.
1019  */
1020 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1021 {
1022         struct fe_priv *np = netdev_priv(dev);
1023         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1024         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1025         unsigned int nr = (np->next_tx + fragments) % TX_RING;
1026         unsigned int i;
1027
1028         spin_lock_irq(&np->lock);
1029
1030         if ((np->next_tx - np->nic_tx + fragments) > TX_LIMIT_STOP) {
1031                 spin_unlock_irq(&np->lock);
1032                 netif_stop_queue(dev);
1033                 return NETDEV_TX_BUSY;
1034         }
1035
1036         np->tx_skbuff[nr] = skb;
1037         
1038         if (fragments) {
1039                 dprintk(KERN_DEBUG "%s: nv_start_xmit: buffer contains %d fragments\n", dev->name, fragments);
1040                 /* setup descriptors in reverse order */
1041                 for (i = fragments; i >= 1; i--) {
1042                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i-1];
1043                         np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset, frag->size,
1044                                                         PCI_DMA_TODEVICE);
1045
1046                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1047                                 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1048                                 np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (frag->size-1) | np->tx_flags | tx_flags_extra);
1049                         } else {
1050                                 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1051                                 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1052                                 np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (frag->size-1) | np->tx_flags | tx_flags_extra);
1053                         }
1054                         
1055                         nr = (nr - 1) % TX_RING;
1056
1057                         if (np->desc_ver == DESC_VER_1)
1058                                 tx_flags_extra &= ~NV_TX_LASTPACKET;
1059                         else
1060                                 tx_flags_extra &= ~NV_TX2_LASTPACKET;           
1061                 }
1062         }
1063
1064 #ifdef NETIF_F_TSO
1065         if (skb_shinfo(skb)->tso_size)
1066                 tx_flags_extra |= NV_TX2_TSO | (skb_shinfo(skb)->tso_size << NV_TX2_TSO_SHIFT);
1067         else
1068 #endif
1069         tx_flags_extra |= (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0);
1070
1071         np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len-skb->data_len,
1072                                         PCI_DMA_TODEVICE);
1073         
1074         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1075                 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1076                 np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (skb->len-skb->data_len-1) | np->tx_flags | tx_flags_extra);
1077         } else {
1078                 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1079                 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1080                 np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (skb->len-skb->data_len-1) | np->tx_flags | tx_flags_extra);
1081         }       
1082
1083         dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission. tx_flags_extra: %x\n",
1084                                 dev->name, np->next_tx, tx_flags_extra);
1085         {
1086                 int j;
1087                 for (j=0; j<64; j++) {
1088                         if ((j%16) == 0)
1089                                 dprintk("\n%03x:", j);
1090                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1091                 }
1092                 dprintk("\n");
1093         }
1094
1095         np->next_tx += 1 + fragments;
1096
1097         dev->trans_start = jiffies;
1098         spin_unlock_irq(&np->lock);
1099         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1100         pci_push(get_hwbase(dev));
1101         return NETDEV_TX_OK;
1102 }
1103
1104 /*
1105  * nv_tx_done: check for completed packets, release the skbs.
1106  *
1107  * Caller must own np->lock.
1108  */
1109 static void nv_tx_done(struct net_device *dev)
1110 {
1111         struct fe_priv *np = netdev_priv(dev);
1112         u32 Flags;
1113         unsigned int i;
1114         struct sk_buff *skb;
1115
1116         while (np->nic_tx != np->next_tx) {
1117                 i = np->nic_tx % TX_RING;
1118
1119                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1120                         Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
1121                 else
1122                         Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
1123
1124                 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1125                                         dev->name, np->nic_tx, Flags);
1126                 if (Flags & NV_TX_VALID)
1127                         break;
1128                 if (np->desc_ver == DESC_VER_1) {
1129                         if (Flags & NV_TX_LASTPACKET) {
1130                                 skb = np->tx_skbuff[i];
1131                                 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1132                                              NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1133                                         if (Flags & NV_TX_UNDERFLOW)
1134                                                 np->stats.tx_fifo_errors++;
1135                                         if (Flags & NV_TX_CARRIERLOST)
1136                                                 np->stats.tx_carrier_errors++;
1137                                         np->stats.tx_errors++;
1138                                 } else {
1139                                         np->stats.tx_packets++;
1140                                         np->stats.tx_bytes += skb->len;
1141                                 }
1142                                 nv_release_txskb(dev, i);
1143                         }
1144                 } else {
1145                         if (Flags & NV_TX2_LASTPACKET) {
1146                                 skb = np->tx_skbuff[i];
1147                                 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1148                                              NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1149                                         if (Flags & NV_TX2_UNDERFLOW)
1150                                                 np->stats.tx_fifo_errors++;
1151                                         if (Flags & NV_TX2_CARRIERLOST)
1152                                                 np->stats.tx_carrier_errors++;
1153                                         np->stats.tx_errors++;
1154                                 } else {
1155                                         np->stats.tx_packets++;
1156                                         np->stats.tx_bytes += skb->len;
1157                                 }                               
1158                                 nv_release_txskb(dev, i);
1159                         }
1160                 }
1161                 np->nic_tx++;
1162         }
1163         if (np->next_tx - np->nic_tx < TX_LIMIT_START)
1164                 netif_wake_queue(dev);
1165 }
1166
1167 /*
1168  * nv_tx_timeout: dev->tx_timeout function
1169  * Called with dev->xmit_lock held.
1170  */
1171 static void nv_tx_timeout(struct net_device *dev)
1172 {
1173         struct fe_priv *np = netdev_priv(dev);
1174         u8 __iomem *base = get_hwbase(dev);
1175
1176         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name,
1177                         readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
1178
1179         {
1180                 int i;
1181
1182                 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1183                                 dev->name, (unsigned long)np->ring_addr,
1184                                 np->next_tx, np->nic_tx);
1185                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1186                 for (i=0;i<0x400;i+= 32) {
1187                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1188                                         i,
1189                                         readl(base + i + 0), readl(base + i + 4),
1190                                         readl(base + i + 8), readl(base + i + 12),
1191                                         readl(base + i + 16), readl(base + i + 20),
1192                                         readl(base + i + 24), readl(base + i + 28));
1193                 }
1194                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1195                 for (i=0;i<TX_RING;i+= 4) {
1196                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1197                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1198                                        i, 
1199                                        le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1200                                        le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1201                                        le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
1202                                        le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
1203                                        le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
1204                                        le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
1205                                        le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
1206                                        le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1207                         } else {
1208                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1209                                        i, 
1210                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1211                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1212                                        le32_to_cpu(np->tx_ring.ex[i].FlagLen),
1213                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
1214                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
1215                                        le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
1216                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
1217                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
1218                                        le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
1219                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
1220                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
1221                                        le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
1222                         }
1223                 }
1224         }
1225
1226         spin_lock_irq(&np->lock);
1227
1228         /* 1) stop tx engine */
1229         nv_stop_tx(dev);
1230
1231         /* 2) check that the packets were not sent already: */
1232         nv_tx_done(dev);
1233
1234         /* 3) if there are dead entries: clear everything */
1235         if (np->next_tx != np->nic_tx) {
1236                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1237                 nv_drain_tx(dev);
1238                 np->next_tx = np->nic_tx = 0;
1239                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1240                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1241                 else
1242                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1243                 netif_wake_queue(dev);
1244         }
1245
1246         /* 4) restart tx engine */
1247         nv_start_tx(dev);
1248         spin_unlock_irq(&np->lock);
1249 }
1250
1251 /*
1252  * Called when the nic notices a mismatch between the actual data len on the
1253  * wire and the len indicated in the 802 header
1254  */
1255 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1256 {
1257         int hdrlen;     /* length of the 802 header */
1258         int protolen;   /* length as stored in the proto field */
1259
1260         /* 1) calculate len according to header */
1261         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1262                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1263                 hdrlen = VLAN_HLEN;
1264         } else {
1265                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1266                 hdrlen = ETH_HLEN;
1267         }
1268         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1269                                 dev->name, datalen, protolen, hdrlen);
1270         if (protolen > ETH_DATA_LEN)
1271                 return datalen; /* Value in proto field not a len, no checks possible */
1272
1273         protolen += hdrlen;
1274         /* consistency checks: */
1275         if (datalen > ETH_ZLEN) {
1276                 if (datalen >= protolen) {
1277                         /* more data on wire than in 802 header, trim of
1278                          * additional data.
1279                          */
1280                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1281                                         dev->name, protolen);
1282                         return protolen;
1283                 } else {
1284                         /* less data on wire than mentioned in header.
1285                          * Discard the packet.
1286                          */
1287                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1288                                         dev->name);
1289                         return -1;
1290                 }
1291         } else {
1292                 /* short packet. Accept only if 802 values are also short */
1293                 if (protolen > ETH_ZLEN) {
1294                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1295                                         dev->name);
1296                         return -1;
1297                 }
1298                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1299                                 dev->name, datalen);
1300                 return datalen;
1301         }
1302 }
1303
1304 static void nv_rx_process(struct net_device *dev)
1305 {
1306         struct fe_priv *np = netdev_priv(dev);
1307         u32 Flags;
1308
1309         for (;;) {
1310                 struct sk_buff *skb;
1311                 int len;
1312                 int i;
1313                 if (np->cur_rx - np->refill_rx >= RX_RING)
1314                         break;  /* we scanned the whole ring - do not continue */
1315
1316                 i = np->cur_rx % RX_RING;
1317                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1318                         Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1319                         len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1320                 } else {
1321                         Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1322                         len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1323                 }
1324
1325                 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1326                                         dev->name, np->cur_rx, Flags);
1327
1328                 if (Flags & NV_RX_AVAIL)
1329                         break;  /* still owned by hardware, */
1330
1331                 /*
1332                  * the packet is for us - immediately tear down the pci mapping.
1333                  * TODO: check if a prefetch of the first cacheline improves
1334                  * the performance.
1335                  */
1336                 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1337                                 np->rx_skbuff[i]->len,
1338                                 PCI_DMA_FROMDEVICE);
1339
1340                 {
1341                         int j;
1342                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1343                         for (j=0; j<64; j++) {
1344                                 if ((j%16) == 0)
1345                                         dprintk("\n%03x:", j);
1346                                 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1347                         }
1348                         dprintk("\n");
1349                 }
1350                 /* look at what we actually got: */
1351                 if (np->desc_ver == DESC_VER_1) {
1352                         if (!(Flags & NV_RX_DESCRIPTORVALID))
1353                                 goto next_pkt;
1354
1355                         if (Flags & NV_RX_ERROR) {
1356                                 if (Flags & NV_RX_MISSEDFRAME) {
1357                                         np->stats.rx_missed_errors++;
1358                                         np->stats.rx_errors++;
1359                                         goto next_pkt;
1360                                 }
1361                                 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1362                                         np->stats.rx_errors++;
1363                                         goto next_pkt;
1364                                 }
1365                                 if (Flags & NV_RX_CRCERR) {
1366                                         np->stats.rx_crc_errors++;
1367                                         np->stats.rx_errors++;
1368                                         goto next_pkt;
1369                                 }
1370                                 if (Flags & NV_RX_OVERFLOW) {
1371                                         np->stats.rx_over_errors++;
1372                                         np->stats.rx_errors++;
1373                                         goto next_pkt;
1374                                 }
1375                                 if (Flags & NV_RX_ERROR4) {
1376                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1377                                         if (len < 0) {
1378                                                 np->stats.rx_errors++;
1379                                                 goto next_pkt;
1380                                         }
1381                                 }
1382                                 /* framing errors are soft errors. */
1383                                 if (Flags & NV_RX_FRAMINGERR) {
1384                                         if (Flags & NV_RX_SUBSTRACT1) {
1385                                                 len--;
1386                                         }
1387                                 }
1388                         }
1389                 } else {
1390                         if (!(Flags & NV_RX2_DESCRIPTORVALID))
1391                                 goto next_pkt;
1392
1393                         if (Flags & NV_RX2_ERROR) {
1394                                 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1395                                         np->stats.rx_errors++;
1396                                         goto next_pkt;
1397                                 }
1398                                 if (Flags & NV_RX2_CRCERR) {
1399                                         np->stats.rx_crc_errors++;
1400                                         np->stats.rx_errors++;
1401                                         goto next_pkt;
1402                                 }
1403                                 if (Flags & NV_RX2_OVERFLOW) {
1404                                         np->stats.rx_over_errors++;
1405                                         np->stats.rx_errors++;
1406                                         goto next_pkt;
1407                                 }
1408                                 if (Flags & NV_RX2_ERROR4) {
1409                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1410                                         if (len < 0) {
1411                                                 np->stats.rx_errors++;
1412                                                 goto next_pkt;
1413                                         }
1414                                 }
1415                                 /* framing errors are soft errors */
1416                                 if (Flags & NV_RX2_FRAMINGERR) {
1417                                         if (Flags & NV_RX2_SUBSTRACT1) {
1418                                                 len--;
1419                                         }
1420                                 }
1421                         }
1422                         Flags &= NV_RX2_CHECKSUMMASK;
1423                         if (Flags == NV_RX2_CHECKSUMOK1 ||
1424                                         Flags == NV_RX2_CHECKSUMOK2 ||
1425                                         Flags == NV_RX2_CHECKSUMOK3) {
1426                                 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1427                                 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1428                         } else {
1429                                 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1430                         }
1431                 }
1432                 /* got a valid packet - forward it to the network core */
1433                 skb = np->rx_skbuff[i];
1434                 np->rx_skbuff[i] = NULL;
1435
1436                 skb_put(skb, len);
1437                 skb->protocol = eth_type_trans(skb, dev);
1438                 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1439                                         dev->name, np->cur_rx, len, skb->protocol);
1440                 netif_rx(skb);
1441                 dev->last_rx = jiffies;
1442                 np->stats.rx_packets++;
1443                 np->stats.rx_bytes += len;
1444 next_pkt:
1445                 np->cur_rx++;
1446         }
1447 }
1448
1449 static void set_bufsize(struct net_device *dev)
1450 {
1451         struct fe_priv *np = netdev_priv(dev);
1452
1453         if (dev->mtu <= ETH_DATA_LEN)
1454                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1455         else
1456                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1457 }
1458
1459 /*
1460  * nv_change_mtu: dev->change_mtu function
1461  * Called with dev_base_lock held for read.
1462  */
1463 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1464 {
1465         struct fe_priv *np = netdev_priv(dev);
1466         int old_mtu;
1467
1468         if (new_mtu < 64 || new_mtu > np->pkt_limit)
1469                 return -EINVAL;
1470
1471         old_mtu = dev->mtu;
1472         dev->mtu = new_mtu;
1473
1474         /* return early if the buffer sizes will not change */
1475         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1476                 return 0;
1477         if (old_mtu == new_mtu)
1478                 return 0;
1479
1480         /* synchronized against open : rtnl_lock() held by caller */
1481         if (netif_running(dev)) {
1482                 u8 __iomem *base = get_hwbase(dev);
1483                 /*
1484                  * It seems that the nic preloads valid ring entries into an
1485                  * internal buffer. The procedure for flushing everything is
1486                  * guessed, there is probably a simpler approach.
1487                  * Changing the MTU is a rare event, it shouldn't matter.
1488                  */
1489                 disable_irq(dev->irq);
1490                 spin_lock_bh(&dev->xmit_lock);
1491                 spin_lock(&np->lock);
1492                 /* stop engines */
1493                 nv_stop_rx(dev);
1494                 nv_stop_tx(dev);
1495                 nv_txrx_reset(dev);
1496                 /* drain rx queue */
1497                 nv_drain_rx(dev);
1498                 nv_drain_tx(dev);
1499                 /* reinit driver view of the rx queue */
1500                 nv_init_rx(dev);
1501                 nv_init_tx(dev);
1502                 /* alloc new rx buffers */
1503                 set_bufsize(dev);
1504                 if (nv_alloc_rx(dev)) {
1505                         if (!np->in_shutdown)
1506                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1507                 }
1508                 /* reinit nic view of the rx queue */
1509                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1510                 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1511                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1512                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1513                 else
1514                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1515                 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1516                         base + NvRegRingSizes);
1517                 pci_push(base);
1518                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1519                 pci_push(base);
1520
1521                 /* restart rx engine */
1522                 nv_start_rx(dev);
1523                 nv_start_tx(dev);
1524                 spin_unlock(&np->lock);
1525                 spin_unlock_bh(&dev->xmit_lock);
1526                 enable_irq(dev->irq);
1527         }
1528         return 0;
1529 }
1530
1531 static void nv_copy_mac_to_hw(struct net_device *dev)
1532 {
1533         u8 __iomem *base = get_hwbase(dev);
1534         u32 mac[2];
1535
1536         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1537                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1538         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1539
1540         writel(mac[0], base + NvRegMacAddrA);
1541         writel(mac[1], base + NvRegMacAddrB);
1542 }
1543
1544 /*
1545  * nv_set_mac_address: dev->set_mac_address function
1546  * Called with rtnl_lock() held.
1547  */
1548 static int nv_set_mac_address(struct net_device *dev, void *addr)
1549 {
1550         struct fe_priv *np = netdev_priv(dev);
1551         struct sockaddr *macaddr = (struct sockaddr*)addr;
1552
1553         if(!is_valid_ether_addr(macaddr->sa_data))
1554                 return -EADDRNOTAVAIL;
1555
1556         /* synchronized against open : rtnl_lock() held by caller */
1557         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
1558
1559         if (netif_running(dev)) {
1560                 spin_lock_bh(&dev->xmit_lock);
1561                 spin_lock_irq(&np->lock);
1562
1563                 /* stop rx engine */
1564                 nv_stop_rx(dev);
1565
1566                 /* set mac address */
1567                 nv_copy_mac_to_hw(dev);
1568
1569                 /* restart rx engine */
1570                 nv_start_rx(dev);
1571                 spin_unlock_irq(&np->lock);
1572                 spin_unlock_bh(&dev->xmit_lock);
1573         } else {
1574                 nv_copy_mac_to_hw(dev);
1575         }
1576         return 0;
1577 }
1578
1579 /*
1580  * nv_set_multicast: dev->set_multicast function
1581  * Called with dev->xmit_lock held.
1582  */
1583 static void nv_set_multicast(struct net_device *dev)
1584 {
1585         struct fe_priv *np = netdev_priv(dev);
1586         u8 __iomem *base = get_hwbase(dev);
1587         u32 addr[2];
1588         u32 mask[2];
1589         u32 pff;
1590
1591         memset(addr, 0, sizeof(addr));
1592         memset(mask, 0, sizeof(mask));
1593
1594         if (dev->flags & IFF_PROMISC) {
1595                 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1596                 pff = NVREG_PFF_PROMISC;
1597         } else {
1598                 pff = NVREG_PFF_MYADDR;
1599
1600                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1601                         u32 alwaysOff[2];
1602                         u32 alwaysOn[2];
1603
1604                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1605                         if (dev->flags & IFF_ALLMULTI) {
1606                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1607                         } else {
1608                                 struct dev_mc_list *walk;
1609
1610                                 walk = dev->mc_list;
1611                                 while (walk != NULL) {
1612                                         u32 a, b;
1613                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1614                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1615                                         alwaysOn[0] &= a;
1616                                         alwaysOff[0] &= ~a;
1617                                         alwaysOn[1] &= b;
1618                                         alwaysOff[1] &= ~b;
1619                                         walk = walk->next;
1620                                 }
1621                         }
1622                         addr[0] = alwaysOn[0];
1623                         addr[1] = alwaysOn[1];
1624                         mask[0] = alwaysOn[0] | alwaysOff[0];
1625                         mask[1] = alwaysOn[1] | alwaysOff[1];
1626                 }
1627         }
1628         addr[0] |= NVREG_MCASTADDRA_FORCE;
1629         pff |= NVREG_PFF_ALWAYS;
1630         spin_lock_irq(&np->lock);
1631         nv_stop_rx(dev);
1632         writel(addr[0], base + NvRegMulticastAddrA);
1633         writel(addr[1], base + NvRegMulticastAddrB);
1634         writel(mask[0], base + NvRegMulticastMaskA);
1635         writel(mask[1], base + NvRegMulticastMaskB);
1636         writel(pff, base + NvRegPacketFilterFlags);
1637         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1638                 dev->name);
1639         nv_start_rx(dev);
1640         spin_unlock_irq(&np->lock);
1641 }
1642
1643 /**
1644  * nv_update_linkspeed: Setup the MAC according to the link partner
1645  * @dev: Network device to be configured
1646  *
1647  * The function queries the PHY and checks if there is a link partner.
1648  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
1649  * set to 10 MBit HD.
1650  *
1651  * The function returns 0 if there is no link partner and 1 if there is
1652  * a good link partner.
1653  */
1654 static int nv_update_linkspeed(struct net_device *dev)
1655 {
1656         struct fe_priv *np = netdev_priv(dev);
1657         u8 __iomem *base = get_hwbase(dev);
1658         int adv, lpa;
1659         int newls = np->linkspeed;
1660         int newdup = np->duplex;
1661         int mii_status;
1662         int retval = 0;
1663         u32 control_1000, status_1000, phyreg;
1664
1665         /* BMSR_LSTATUS is latched, read it twice:
1666          * we want the current value.
1667          */
1668         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1669         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1670
1671         if (!(mii_status & BMSR_LSTATUS)) {
1672                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1673                                 dev->name);
1674                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1675                 newdup = 0;
1676                 retval = 0;
1677                 goto set_speed;
1678         }
1679
1680         if (np->autoneg == 0) {
1681                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1682                                 dev->name, np->fixed_mode);
1683                 if (np->fixed_mode & LPA_100FULL) {
1684                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1685                         newdup = 1;
1686                 } else if (np->fixed_mode & LPA_100HALF) {
1687                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1688                         newdup = 0;
1689                 } else if (np->fixed_mode & LPA_10FULL) {
1690                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1691                         newdup = 1;
1692                 } else {
1693                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1694                         newdup = 0;
1695                 }
1696                 retval = 1;
1697                 goto set_speed;
1698         }
1699         /* check auto negotiation is complete */
1700         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
1701                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1702                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1703                 newdup = 0;
1704                 retval = 0;
1705                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
1706                 goto set_speed;
1707         }
1708
1709         retval = 1;
1710         if (np->gigabit == PHY_GIGABIT) {
1711                 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1712                 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
1713
1714                 if ((control_1000 & ADVERTISE_1000FULL) &&
1715                         (status_1000 & LPA_1000FULL)) {
1716                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
1717                                 dev->name);
1718                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
1719                         newdup = 1;
1720                         goto set_speed;
1721                 }
1722         }
1723
1724         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1725         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1726         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1727                                 dev->name, adv, lpa);
1728
1729         /* FIXME: handle parallel detection properly */
1730         lpa = lpa & adv;
1731         if (lpa & LPA_100FULL) {
1732                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1733                 newdup = 1;
1734         } else if (lpa & LPA_100HALF) {
1735                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1736                 newdup = 0;
1737         } else if (lpa & LPA_10FULL) {
1738                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1739                 newdup = 1;
1740         } else if (lpa & LPA_10HALF) {
1741                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1742                 newdup = 0;
1743         } else {
1744                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1745                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1746                 newdup = 0;
1747         }
1748
1749 set_speed:
1750         if (np->duplex == newdup && np->linkspeed == newls)
1751                 return retval;
1752
1753         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
1754                         dev->name, np->linkspeed, np->duplex, newls, newdup);
1755
1756         np->duplex = newdup;
1757         np->linkspeed = newls;
1758
1759         if (np->gigabit == PHY_GIGABIT) {
1760                 phyreg = readl(base + NvRegRandomSeed);
1761                 phyreg &= ~(0x3FF00);
1762                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
1763                         phyreg |= NVREG_RNDSEED_FORCE3;
1764                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1765                         phyreg |= NVREG_RNDSEED_FORCE2;
1766                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1767                         phyreg |= NVREG_RNDSEED_FORCE;
1768                 writel(phyreg, base + NvRegRandomSeed);
1769         }
1770
1771         phyreg = readl(base + NvRegPhyInterface);
1772         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
1773         if (np->duplex == 0)
1774                 phyreg |= PHY_HALF;
1775         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
1776                 phyreg |= PHY_100;
1777         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
1778                 phyreg |= PHY_1000;
1779         writel(phyreg, base + NvRegPhyInterface);
1780
1781         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1782                 base + NvRegMisc1);
1783         pci_push(base);
1784         writel(np->linkspeed, base + NvRegLinkSpeed);
1785         pci_push(base);
1786
1787         return retval;
1788 }
1789
1790 static void nv_linkchange(struct net_device *dev)
1791 {
1792         if (nv_update_linkspeed(dev)) {
1793                 if (!netif_carrier_ok(dev)) {
1794                         netif_carrier_on(dev);
1795                         printk(KERN_INFO "%s: link up.\n", dev->name);
1796                         nv_start_rx(dev);
1797                 }
1798         } else {
1799                 if (netif_carrier_ok(dev)) {
1800                         netif_carrier_off(dev);
1801                         printk(KERN_INFO "%s: link down.\n", dev->name);
1802                         nv_stop_rx(dev);
1803                 }
1804         }
1805 }
1806
1807 static void nv_link_irq(struct net_device *dev)
1808 {
1809         u8 __iomem *base = get_hwbase(dev);
1810         u32 miistat;
1811
1812         miistat = readl(base + NvRegMIIStatus);
1813         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1814         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
1815
1816         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
1817                 nv_linkchange(dev);
1818         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
1819 }
1820
1821 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1822 {
1823         struct net_device *dev = (struct net_device *) data;
1824         struct fe_priv *np = netdev_priv(dev);
1825         u8 __iomem *base = get_hwbase(dev);
1826         u32 events;
1827         int i;
1828
1829         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1830
1831         for (i=0; ; i++) {
1832                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1833                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1834                 pci_push(base);
1835                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1836                 if (!(events & np->irqmask))
1837                         break;
1838
1839                 spin_lock(&np->lock);
1840                 nv_tx_done(dev);
1841                 spin_unlock(&np->lock);
1842                 
1843                 nv_rx_process(dev);
1844                 if (nv_alloc_rx(dev)) {
1845                         spin_lock(&np->lock);
1846                         if (!np->in_shutdown)
1847                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1848                         spin_unlock(&np->lock);
1849                 }
1850                 
1851                 if (events & NVREG_IRQ_LINK) {
1852                         spin_lock(&np->lock);
1853                         nv_link_irq(dev);
1854                         spin_unlock(&np->lock);
1855                 }
1856                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
1857                         spin_lock(&np->lock);
1858                         nv_linkchange(dev);
1859                         spin_unlock(&np->lock);
1860                         np->link_timeout = jiffies + LINK_TIMEOUT;
1861                 }
1862                 if (events & (NVREG_IRQ_TX_ERR)) {
1863                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1864                                                 dev->name, events);
1865                 }
1866                 if (events & (NVREG_IRQ_UNKNOWN)) {
1867                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1868                                                 dev->name, events);
1869                 }
1870                 if (i > max_interrupt_work) {
1871                         spin_lock(&np->lock);
1872                         /* disable interrupts on the nic */
1873                         writel(0, base + NvRegIrqMask);
1874                         pci_push(base);
1875
1876                         if (!np->in_shutdown)
1877                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1878                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1879                         spin_unlock(&np->lock);
1880                         break;
1881                 }
1882
1883         }
1884         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1885
1886         return IRQ_RETVAL(i);
1887 }
1888
1889 static void nv_do_nic_poll(unsigned long data)
1890 {
1891         struct net_device *dev = (struct net_device *) data;
1892         struct fe_priv *np = netdev_priv(dev);
1893         u8 __iomem *base = get_hwbase(dev);
1894
1895         disable_irq(dev->irq);
1896         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1897         /*
1898          * reenable interrupts on the nic, we have to do this before calling
1899          * nv_nic_irq because that may decide to do otherwise
1900          */
1901         writel(np->irqmask, base + NvRegIrqMask);
1902         pci_push(base);
1903         nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1904         enable_irq(dev->irq);
1905 }
1906
1907 #ifdef CONFIG_NET_POLL_CONTROLLER
1908 static void nv_poll_controller(struct net_device *dev)
1909 {
1910         nv_do_nic_poll((unsigned long) dev);
1911 }
1912 #endif
1913
1914 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1915 {
1916         struct fe_priv *np = netdev_priv(dev);
1917         strcpy(info->driver, "forcedeth");
1918         strcpy(info->version, FORCEDETH_VERSION);
1919         strcpy(info->bus_info, pci_name(np->pci_dev));
1920 }
1921
1922 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1923 {
1924         struct fe_priv *np = netdev_priv(dev);
1925         wolinfo->supported = WAKE_MAGIC;
1926
1927         spin_lock_irq(&np->lock);
1928         if (np->wolenabled)
1929                 wolinfo->wolopts = WAKE_MAGIC;
1930         spin_unlock_irq(&np->lock);
1931 }
1932
1933 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1934 {
1935         struct fe_priv *np = netdev_priv(dev);
1936         u8 __iomem *base = get_hwbase(dev);
1937
1938         spin_lock_irq(&np->lock);
1939         if (wolinfo->wolopts == 0) {
1940                 writel(0, base + NvRegWakeUpFlags);
1941                 np->wolenabled = 0;
1942         }
1943         if (wolinfo->wolopts & WAKE_MAGIC) {
1944                 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
1945                 np->wolenabled = 1;
1946         }
1947         spin_unlock_irq(&np->lock);
1948         return 0;
1949 }
1950
1951 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1952 {
1953         struct fe_priv *np = netdev_priv(dev);
1954         int adv;
1955
1956         spin_lock_irq(&np->lock);
1957         ecmd->port = PORT_MII;
1958         if (!netif_running(dev)) {
1959                 /* We do not track link speed / duplex setting if the
1960                  * interface is disabled. Force a link check */
1961                 nv_update_linkspeed(dev);
1962         }
1963         switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
1964                 case NVREG_LINKSPEED_10:
1965                         ecmd->speed = SPEED_10;
1966                         break;
1967                 case NVREG_LINKSPEED_100:
1968                         ecmd->speed = SPEED_100;
1969                         break;
1970                 case NVREG_LINKSPEED_1000:
1971                         ecmd->speed = SPEED_1000;
1972                         break;
1973         }
1974         ecmd->duplex = DUPLEX_HALF;
1975         if (np->duplex)
1976                 ecmd->duplex = DUPLEX_FULL;
1977
1978         ecmd->autoneg = np->autoneg;
1979
1980         ecmd->advertising = ADVERTISED_MII;
1981         if (np->autoneg) {
1982                 ecmd->advertising |= ADVERTISED_Autoneg;
1983                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1984         } else {
1985                 adv = np->fixed_mode;
1986         }
1987         if (adv & ADVERTISE_10HALF)
1988                 ecmd->advertising |= ADVERTISED_10baseT_Half;
1989         if (adv & ADVERTISE_10FULL)
1990                 ecmd->advertising |= ADVERTISED_10baseT_Full;
1991         if (adv & ADVERTISE_100HALF)
1992                 ecmd->advertising |= ADVERTISED_100baseT_Half;
1993         if (adv & ADVERTISE_100FULL)
1994                 ecmd->advertising |= ADVERTISED_100baseT_Full;
1995         if (np->autoneg && np->gigabit == PHY_GIGABIT) {
1996                 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1997                 if (adv & ADVERTISE_1000FULL)
1998                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
1999         }
2000
2001         ecmd->supported = (SUPPORTED_Autoneg |
2002                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2003                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2004                 SUPPORTED_MII);
2005         if (np->gigabit == PHY_GIGABIT)
2006                 ecmd->supported |= SUPPORTED_1000baseT_Full;
2007
2008         ecmd->phy_address = np->phyaddr;
2009         ecmd->transceiver = XCVR_EXTERNAL;
2010
2011         /* ignore maxtxpkt, maxrxpkt for now */
2012         spin_unlock_irq(&np->lock);
2013         return 0;
2014 }
2015
2016 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2017 {
2018         struct fe_priv *np = netdev_priv(dev);
2019
2020         if (ecmd->port != PORT_MII)
2021                 return -EINVAL;
2022         if (ecmd->transceiver != XCVR_EXTERNAL)
2023                 return -EINVAL;
2024         if (ecmd->phy_address != np->phyaddr) {
2025                 /* TODO: support switching between multiple phys. Should be
2026                  * trivial, but not enabled due to lack of test hardware. */
2027                 return -EINVAL;
2028         }
2029         if (ecmd->autoneg == AUTONEG_ENABLE) {
2030                 u32 mask;
2031
2032                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2033                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
2034                 if (np->gigabit == PHY_GIGABIT)
2035                         mask |= ADVERTISED_1000baseT_Full;
2036
2037                 if ((ecmd->advertising & mask) == 0)
2038                         return -EINVAL;
2039
2040         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2041                 /* Note: autonegotiation disable, speed 1000 intentionally
2042                  * forbidden - noone should need that. */
2043
2044                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2045                         return -EINVAL;
2046                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2047                         return -EINVAL;
2048         } else {
2049                 return -EINVAL;
2050         }
2051
2052         spin_lock_irq(&np->lock);
2053         if (ecmd->autoneg == AUTONEG_ENABLE) {
2054                 int adv, bmcr;
2055
2056                 np->autoneg = 1;
2057
2058                 /* advertise only what has been requested */
2059                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2060                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2061                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2062                         adv |= ADVERTISE_10HALF;
2063                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2064                         adv |= ADVERTISE_10FULL;
2065                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2066                         adv |= ADVERTISE_100HALF;
2067                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2068                         adv |= ADVERTISE_100FULL;
2069                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2070
2071                 if (np->gigabit == PHY_GIGABIT) {
2072                         adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2073                         adv &= ~ADVERTISE_1000FULL;
2074                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
2075                                 adv |= ADVERTISE_1000FULL;
2076                         mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
2077                 }
2078
2079                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2080                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2081                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2082
2083         } else {
2084                 int adv, bmcr;
2085
2086                 np->autoneg = 0;
2087
2088                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2089                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2090                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
2091                         adv |= ADVERTISE_10HALF;
2092                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
2093                         adv |= ADVERTISE_10FULL;
2094                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
2095                         adv |= ADVERTISE_100HALF;
2096                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
2097                         adv |= ADVERTISE_100FULL;
2098                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2099                 np->fixed_mode = adv;
2100
2101                 if (np->gigabit == PHY_GIGABIT) {
2102                         adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2103                         adv &= ~ADVERTISE_1000FULL;
2104                         mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
2105                 }
2106
2107                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2108                 bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX);
2109                 if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL))
2110                         bmcr |= BMCR_FULLDPLX;
2111                 if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL))
2112                         bmcr |= BMCR_SPEED100;
2113                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2114
2115                 if (netif_running(dev)) {
2116                         /* Wait a bit and then reconfigure the nic. */
2117                         udelay(10);
2118                         nv_linkchange(dev);
2119                 }
2120         }
2121         spin_unlock_irq(&np->lock);
2122
2123         return 0;
2124 }
2125
2126 #define FORCEDETH_REGS_VER      1
2127 #define FORCEDETH_REGS_SIZE     0x400 /* 256 32-bit registers */
2128
2129 static int nv_get_regs_len(struct net_device *dev)
2130 {
2131         return FORCEDETH_REGS_SIZE;
2132 }
2133
2134 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2135 {
2136         struct fe_priv *np = netdev_priv(dev);
2137         u8 __iomem *base = get_hwbase(dev);
2138         u32 *rbuf = buf;
2139         int i;
2140
2141         regs->version = FORCEDETH_REGS_VER;
2142         spin_lock_irq(&np->lock);
2143         for (i=0;i<FORCEDETH_REGS_SIZE/sizeof(u32);i++)
2144                 rbuf[i] = readl(base + i*sizeof(u32));
2145         spin_unlock_irq(&np->lock);
2146 }
2147
2148 static int nv_nway_reset(struct net_device *dev)
2149 {
2150         struct fe_priv *np = netdev_priv(dev);
2151         int ret;
2152
2153         spin_lock_irq(&np->lock);
2154         if (np->autoneg) {
2155                 int bmcr;
2156
2157                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2158                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2159                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2160
2161                 ret = 0;
2162         } else {
2163                 ret = -EINVAL;
2164         }
2165         spin_unlock_irq(&np->lock);
2166
2167         return ret;
2168 }
2169
2170 static struct ethtool_ops ops = {
2171         .get_drvinfo = nv_get_drvinfo,
2172         .get_link = ethtool_op_get_link,
2173         .get_wol = nv_get_wol,
2174         .set_wol = nv_set_wol,
2175         .get_settings = nv_get_settings,
2176         .set_settings = nv_set_settings,
2177         .get_regs_len = nv_get_regs_len,
2178         .get_regs = nv_get_regs,
2179         .nway_reset = nv_nway_reset,
2180         .get_perm_addr = ethtool_op_get_perm_addr,
2181 };
2182
2183 static int nv_open(struct net_device *dev)
2184 {
2185         struct fe_priv *np = netdev_priv(dev);
2186         u8 __iomem *base = get_hwbase(dev);
2187         int ret, oom, i;
2188
2189         dprintk(KERN_DEBUG "nv_open: begin\n");
2190
2191         /* 1) erase previous misconfiguration */
2192         /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
2193         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2194         writel(0, base + NvRegMulticastAddrB);
2195         writel(0, base + NvRegMulticastMaskA);
2196         writel(0, base + NvRegMulticastMaskB);
2197         writel(0, base + NvRegPacketFilterFlags);
2198
2199         writel(0, base + NvRegTransmitterControl);
2200         writel(0, base + NvRegReceiverControl);
2201
2202         writel(0, base + NvRegAdapterControl);
2203
2204         /* 2) initialize descriptor rings */
2205         set_bufsize(dev);
2206         oom = nv_init_ring(dev);
2207
2208         writel(0, base + NvRegLinkSpeed);
2209         writel(0, base + NvRegUnknownTransmitterReg);
2210         nv_txrx_reset(dev);
2211         writel(0, base + NvRegUnknownSetupReg6);
2212
2213         np->in_shutdown = 0;
2214
2215         /* 3) set mac address */
2216         nv_copy_mac_to_hw(dev);
2217
2218         /* 4) give hw rings */
2219         writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
2220         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2221                 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
2222         else
2223                 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
2224         writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
2225                 base + NvRegRingSizes);
2226
2227         /* 5) continue setup */
2228         writel(np->linkspeed, base + NvRegLinkSpeed);
2229         writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
2230         writel(np->txrxctl_bits, base + NvRegTxRxControl);
2231         pci_push(base);
2232         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
2233         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
2234                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
2235                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
2236
2237         writel(0, base + NvRegUnknownSetupReg4);
2238         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2239         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2240
2241         /* 6) continue setup */
2242         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
2243         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
2244         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
2245         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2246
2247         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
2248         get_random_bytes(&i, sizeof(i));
2249         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
2250         writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
2251         writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
2252         if (poll_interval == -1) {
2253                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
2254                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
2255                 else
2256                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
2257         }
2258         else
2259                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
2260         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
2261         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
2262                         base + NvRegAdapterControl);
2263         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
2264         writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
2265         writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
2266
2267         i = readl(base + NvRegPowerState);
2268         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
2269                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
2270
2271         pci_push(base);
2272         udelay(10);
2273         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
2274
2275         writel(0, base + NvRegIrqMask);
2276         pci_push(base);
2277         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2278         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2279         pci_push(base);
2280
2281         ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
2282         if (ret)
2283                 goto out_drain;
2284
2285         /* ask for interrupts */
2286         writel(np->irqmask, base + NvRegIrqMask);
2287
2288         spin_lock_irq(&np->lock);
2289         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2290         writel(0, base + NvRegMulticastAddrB);
2291         writel(0, base + NvRegMulticastMaskA);
2292         writel(0, base + NvRegMulticastMaskB);
2293         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
2294         /* One manual link speed update: Interrupts are enabled, future link
2295          * speed changes cause interrupts and are handled by nv_link_irq().
2296          */
2297         {
2298                 u32 miistat;
2299                 miistat = readl(base + NvRegMIIStatus);
2300                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2301                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
2302         }
2303         /* set linkspeed to invalid value, thus force nv_update_linkspeed
2304          * to init hw */
2305         np->linkspeed = 0;
2306         ret = nv_update_linkspeed(dev);
2307         nv_start_rx(dev);
2308         nv_start_tx(dev);
2309         netif_start_queue(dev);
2310         if (ret) {
2311                 netif_carrier_on(dev);
2312         } else {
2313                 printk("%s: no link during initialization.\n", dev->name);
2314                 netif_carrier_off(dev);
2315         }
2316         if (oom)
2317                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2318         spin_unlock_irq(&np->lock);
2319
2320         return 0;
2321 out_drain:
2322         drain_ring(dev);
2323         return ret;
2324 }
2325
2326 static int nv_close(struct net_device *dev)
2327 {
2328         struct fe_priv *np = netdev_priv(dev);
2329         u8 __iomem *base;
2330
2331         spin_lock_irq(&np->lock);
2332         np->in_shutdown = 1;
2333         spin_unlock_irq(&np->lock);
2334         synchronize_irq(dev->irq);
2335
2336         del_timer_sync(&np->oom_kick);
2337         del_timer_sync(&np->nic_poll);
2338
2339         netif_stop_queue(dev);
2340         spin_lock_irq(&np->lock);
2341         nv_stop_tx(dev);
2342         nv_stop_rx(dev);
2343         nv_txrx_reset(dev);
2344
2345         /* disable interrupts on the nic or we will lock up */
2346         base = get_hwbase(dev);
2347         writel(0, base + NvRegIrqMask);
2348         pci_push(base);
2349         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
2350
2351         spin_unlock_irq(&np->lock);
2352
2353         free_irq(dev->irq, dev);
2354
2355         drain_ring(dev);
2356
2357         if (np->wolenabled)
2358                 nv_start_rx(dev);
2359
2360         /* special op: write back the misordered MAC address - otherwise
2361          * the next nv_probe would see a wrong address.
2362          */
2363         writel(np->orig_mac[0], base + NvRegMacAddrA);
2364         writel(np->orig_mac[1], base + NvRegMacAddrB);
2365
2366         /* FIXME: power down nic */
2367
2368         return 0;
2369 }
2370
2371 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
2372 {
2373         struct net_device *dev;
2374         struct fe_priv *np;
2375         unsigned long addr;
2376         u8 __iomem *base;
2377         int err, i;
2378
2379         dev = alloc_etherdev(sizeof(struct fe_priv));
2380         err = -ENOMEM;
2381         if (!dev)
2382                 goto out;
2383
2384         np = netdev_priv(dev);
2385         np->pci_dev = pci_dev;
2386         spin_lock_init(&np->lock);
2387         SET_MODULE_OWNER(dev);
2388         SET_NETDEV_DEV(dev, &pci_dev->dev);
2389
2390         init_timer(&np->oom_kick);
2391         np->oom_kick.data = (unsigned long) dev;
2392         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
2393         init_timer(&np->nic_poll);
2394         np->nic_poll.data = (unsigned long) dev;
2395         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
2396
2397         err = pci_enable_device(pci_dev);
2398         if (err) {
2399                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
2400                                 err, pci_name(pci_dev));
2401                 goto out_free;
2402         }
2403
2404         pci_set_master(pci_dev);
2405
2406         err = pci_request_regions(pci_dev, DRV_NAME);
2407         if (err < 0)
2408                 goto out_disable;
2409
2410         err = -EINVAL;
2411         addr = 0;
2412         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2413                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
2414                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
2415                                 pci_resource_len(pci_dev, i),
2416                                 pci_resource_flags(pci_dev, i));
2417                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
2418                                 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
2419                         addr = pci_resource_start(pci_dev, i);
2420                         break;
2421                 }
2422         }
2423         if (i == DEVICE_COUNT_RESOURCE) {
2424                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
2425                                         pci_name(pci_dev));
2426                 goto out_relreg;
2427         }
2428
2429         /* handle different descriptor versions */
2430         if (id->driver_data & DEV_HAS_HIGH_DMA) {
2431                 /* packet format 3: supports 40-bit addressing */
2432                 np->desc_ver = DESC_VER_3;
2433                 if (pci_set_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
2434                         printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
2435                                         pci_name(pci_dev));
2436                 } else {
2437                         dev->features |= NETIF_F_HIGHDMA;
2438                 }
2439                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
2440         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
2441                 /* packet format 2: supports jumbo frames */
2442                 np->desc_ver = DESC_VER_2;
2443                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
2444         } else {
2445                 /* original packet format */
2446                 np->desc_ver = DESC_VER_1;
2447                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
2448         }
2449
2450         np->pkt_limit = NV_PKTLIMIT_1;
2451         if (id->driver_data & DEV_HAS_LARGEDESC)
2452                 np->pkt_limit = NV_PKTLIMIT_2;
2453
2454         if (id->driver_data & DEV_HAS_CHECKSUM) {
2455                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
2456                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
2457 #ifdef NETIF_F_TSO
2458                 dev->features |= NETIF_F_TSO;
2459 #endif
2460         }
2461
2462         err = -ENOMEM;
2463         np->base = ioremap(addr, NV_PCI_REGSZ);
2464         if (!np->base)
2465                 goto out_relreg;
2466         dev->base_addr = (unsigned long)np->base;
2467
2468         dev->irq = pci_dev->irq;
2469
2470         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2471                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
2472                                         sizeof(struct ring_desc) * (RX_RING + TX_RING),
2473                                         &np->ring_addr);
2474                 if (!np->rx_ring.orig)
2475                         goto out_unmap;
2476                 np->tx_ring.orig = &np->rx_ring.orig[RX_RING];
2477         } else {
2478                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
2479                                         sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2480                                         &np->ring_addr);
2481                 if (!np->rx_ring.ex)
2482                         goto out_unmap;
2483                 np->tx_ring.ex = &np->rx_ring.ex[RX_RING];
2484         }
2485
2486         dev->open = nv_open;
2487         dev->stop = nv_close;
2488         dev->hard_start_xmit = nv_start_xmit;
2489         dev->get_stats = nv_get_stats;
2490         dev->change_mtu = nv_change_mtu;
2491         dev->set_mac_address = nv_set_mac_address;
2492         dev->set_multicast_list = nv_set_multicast;
2493 #ifdef CONFIG_NET_POLL_CONTROLLER
2494         dev->poll_controller = nv_poll_controller;
2495 #endif
2496         SET_ETHTOOL_OPS(dev, &ops);
2497         dev->tx_timeout = nv_tx_timeout;
2498         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
2499
2500         pci_set_drvdata(pci_dev, dev);
2501
2502         /* read the mac address */
2503         base = get_hwbase(dev);
2504         np->orig_mac[0] = readl(base + NvRegMacAddrA);
2505         np->orig_mac[1] = readl(base + NvRegMacAddrB);
2506
2507         dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
2508         dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
2509         dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
2510         dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
2511         dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
2512         dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
2513         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2514
2515         if (!is_valid_ether_addr(dev->perm_addr)) {
2516                 /*
2517                  * Bad mac address. At least one bios sets the mac address
2518                  * to 01:23:45:67:89:ab
2519                  */
2520                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
2521                         pci_name(pci_dev),
2522                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2523                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2524                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
2525                 dev->dev_addr[0] = 0x00;
2526                 dev->dev_addr[1] = 0x00;
2527                 dev->dev_addr[2] = 0x6c;
2528                 get_random_bytes(&dev->dev_addr[3], 3);
2529         }
2530
2531         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
2532                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2533                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2534
2535         /* disable WOL */
2536         writel(0, base + NvRegWakeUpFlags);
2537         np->wolenabled = 0;
2538
2539         if (np->desc_ver == DESC_VER_1) {
2540                 np->tx_flags = NV_TX_VALID;
2541         } else {
2542                 np->tx_flags = NV_TX2_VALID;
2543         }
2544         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
2545                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
2546         else
2547                 np->irqmask = NVREG_IRQMASK_CPU;
2548
2549         if (id->driver_data & DEV_NEED_TIMERIRQ)
2550                 np->irqmask |= NVREG_IRQ_TIMER;
2551         if (id->driver_data & DEV_NEED_LINKTIMER) {
2552                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
2553                 np->need_linktimer = 1;
2554                 np->link_timeout = jiffies + LINK_TIMEOUT;
2555         } else {
2556                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
2557                 np->need_linktimer = 0;
2558         }
2559
2560         /* find a suitable phy */
2561         for (i = 1; i <= 32; i++) {
2562                 int id1, id2;
2563                 int phyaddr = i & 0x1F;
2564
2565                 spin_lock_irq(&np->lock);
2566                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
2567                 spin_unlock_irq(&np->lock);
2568                 if (id1 < 0 || id1 == 0xffff)
2569                         continue;
2570                 spin_lock_irq(&np->lock);
2571                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
2572                 spin_unlock_irq(&np->lock);
2573                 if (id2 < 0 || id2 == 0xffff)
2574                         continue;
2575
2576                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
2577                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
2578                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
2579                         pci_name(pci_dev), id1, id2, phyaddr);
2580                 np->phyaddr = phyaddr;
2581                 np->phy_oui = id1 | id2;
2582                 break;
2583         }
2584         if (i == 33) {
2585                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
2586                        pci_name(pci_dev));
2587                 goto out_freering;
2588         }
2589         
2590         /* reset it */
2591         phy_init(dev);
2592
2593         /* set default link speed settings */
2594         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2595         np->duplex = 0;
2596         np->autoneg = 1;
2597
2598         err = register_netdev(dev);
2599         if (err) {
2600                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
2601                 goto out_freering;
2602         }
2603         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
2604                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
2605                         pci_name(pci_dev));
2606
2607         return 0;
2608
2609 out_freering:
2610         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2611                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2612                                     np->rx_ring.orig, np->ring_addr);
2613         else
2614                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2615                                     np->rx_ring.ex, np->ring_addr);
2616         pci_set_drvdata(pci_dev, NULL);
2617 out_unmap:
2618         iounmap(get_hwbase(dev));
2619 out_relreg:
2620         pci_release_regions(pci_dev);
2621 out_disable:
2622         pci_disable_device(pci_dev);
2623 out_free:
2624         free_netdev(dev);
2625 out:
2626         return err;
2627 }
2628
2629 static void __devexit nv_remove(struct pci_dev *pci_dev)
2630 {
2631         struct net_device *dev = pci_get_drvdata(pci_dev);
2632         struct fe_priv *np = netdev_priv(dev);
2633
2634         unregister_netdev(dev);
2635
2636         /* free all structures */
2637         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2638                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring.orig, np->ring_addr);
2639         else
2640                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), np->rx_ring.ex, np->ring_addr);
2641         iounmap(get_hwbase(dev));
2642         pci_release_regions(pci_dev);
2643         pci_disable_device(pci_dev);
2644         free_netdev(dev);
2645         pci_set_drvdata(pci_dev, NULL);
2646 }
2647
2648 static struct pci_device_id pci_tbl[] = {
2649         {       /* nForce Ethernet Controller */
2650                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
2651                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2652         },
2653         {       /* nForce2 Ethernet Controller */
2654                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
2655                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2656         },
2657         {       /* nForce3 Ethernet Controller */
2658                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
2659                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2660         },
2661         {       /* nForce3 Ethernet Controller */
2662                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
2663                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2664         },
2665         {       /* nForce3 Ethernet Controller */
2666                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
2667                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2668         },
2669         {       /* nForce3 Ethernet Controller */
2670                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
2671                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2672         },
2673         {       /* nForce3 Ethernet Controller */
2674                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
2675                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2676         },
2677         {       /* CK804 Ethernet Controller */
2678                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
2679                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2680         },
2681         {       /* CK804 Ethernet Controller */
2682                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
2683                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2684         },
2685         {       /* MCP04 Ethernet Controller */
2686                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
2687                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2688         },
2689         {       /* MCP04 Ethernet Controller */
2690                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
2691                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2692         },
2693         {       /* MCP51 Ethernet Controller */
2694                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
2695                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2696         },
2697         {       /* MCP51 Ethernet Controller */
2698                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
2699                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2700         },
2701         {       /* MCP55 Ethernet Controller */
2702                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
2703                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2704         },
2705         {       /* MCP55 Ethernet Controller */
2706                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
2707                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2708         },
2709         {0,},
2710 };
2711
2712 static struct pci_driver driver = {
2713         .name = "forcedeth",
2714         .id_table = pci_tbl,
2715         .probe = nv_probe,
2716         .remove = __devexit_p(nv_remove),
2717 };
2718
2719
2720 static int __init init_nic(void)
2721 {
2722         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
2723         return pci_module_init(&driver);
2724 }
2725
2726 static void __exit exit_nic(void)
2727 {
2728         pci_unregister_driver(&driver);
2729 }
2730
2731 module_param(max_interrupt_work, int, 0);
2732 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
2733 module_param(optimization_mode, int, 0);
2734 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
2735 module_param(poll_interval, int, 0);
2736 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
2737
2738 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2739 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2740 MODULE_LICENSE("GPL");
2741
2742 MODULE_DEVICE_TABLE(pci, pci_tbl);
2743
2744 module_init(init_nic);
2745 module_exit(exit_nic);