Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[linux-2.6] / drivers / net / cassini.c
1 /* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
2  *
3  * Copyright (C) 2004 Sun Microsystems Inc.
4  * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of the
9  * License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
19  * 02111-1307, USA.
20  *
21  * This driver uses the sungem driver (c) David Miller
22  * (davem@redhat.com) as its basis.
23  *
24  * The cassini chip has a number of features that distinguish it from
25  * the gem chip:
26  *  4 transmit descriptor rings that are used for either QoS (VLAN) or
27  *      load balancing (non-VLAN mode)
28  *  batching of multiple packets
29  *  multiple CPU dispatching
30  *  page-based RX descriptor engine with separate completion rings
31  *  Gigabit support (GMII and PCS interface)
32  *  MIF link up/down detection works
33  *
34  * RX is handled by page sized buffers that are attached as fragments to
35  * the skb. here's what's done:
36  *  -- driver allocates pages at a time and keeps reference counts
37  *     on them.
38  *  -- the upper protocol layers assume that the header is in the skb
39  *     itself. as a result, cassini will copy a small amount (64 bytes)
40  *     to make them happy.
41  *  -- driver appends the rest of the data pages as frags to skbuffs
42  *     and increments the reference count
43  *  -- on page reclamation, the driver swaps the page with a spare page.
44  *     if that page is still in use, it frees its reference to that page,
45  *     and allocates a new page for use. otherwise, it just recycles the
46  *     the page.
47  *
48  * NOTE: cassini can parse the header. however, it's not worth it
49  *       as long as the network stack requires a header copy.
50  *
51  * TX has 4 queues. currently these queues are used in a round-robin
52  * fashion for load balancing. They can also be used for QoS. for that
53  * to work, however, QoS information needs to be exposed down to the driver
54  * level so that subqueues get targetted to particular transmit rings.
55  * alternatively, the queues can be configured via use of the all-purpose
56  * ioctl.
57  *
58  * RX DATA: the rx completion ring has all the info, but the rx desc
59  * ring has all of the data. RX can conceivably come in under multiple
60  * interrupts, but the INT# assignment needs to be set up properly by
61  * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
62  * that. also, the two descriptor rings are designed to distinguish between
63  * encrypted and non-encrypted packets, but we use them for buffering
64  * instead.
65  *
66  * by default, the selective clear mask is set up to process rx packets.
67  */
68
69
70 #include <linux/module.h>
71 #include <linux/kernel.h>
72 #include <linux/types.h>
73 #include <linux/compiler.h>
74 #include <linux/slab.h>
75 #include <linux/delay.h>
76 #include <linux/init.h>
77 #include <linux/ioport.h>
78 #include <linux/pci.h>
79 #include <linux/mm.h>
80 #include <linux/highmem.h>
81 #include <linux/list.h>
82 #include <linux/dma-mapping.h>
83
84 #include <linux/netdevice.h>
85 #include <linux/etherdevice.h>
86 #include <linux/skbuff.h>
87 #include <linux/ethtool.h>
88 #include <linux/crc32.h>
89 #include <linux/random.h>
90 #include <linux/mii.h>
91 #include <linux/ip.h>
92 #include <linux/tcp.h>
93 #include <linux/mutex.h>
94
95 #include <net/checksum.h>
96
97 #include <asm/atomic.h>
98 #include <asm/system.h>
99 #include <asm/io.h>
100 #include <asm/byteorder.h>
101 #include <asm/uaccess.h>
102
103 #define cas_page_map(x)      kmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
104 #define cas_page_unmap(x)    kunmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
105 #define CAS_NCPUS            num_online_cpus()
106
107 #if defined(CONFIG_CASSINI_NAPI) && defined(HAVE_NETDEV_POLL)
108 #define USE_NAPI
109 #define cas_skb_release(x)  netif_receive_skb(x)
110 #else
111 #define cas_skb_release(x)  netif_rx(x)
112 #endif
113
114 /* select which firmware to use */
115 #define USE_HP_WORKAROUND
116 #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
117 #define CAS_HP_ALT_FIRMWARE   cas_prog_null /* alternate firmware */
118
119 #include "cassini.h"
120
121 #define USE_TX_COMPWB      /* use completion writeback registers */
122 #define USE_CSMA_CD_PROTO  /* standard CSMA/CD */
123 #define USE_RX_BLANK       /* hw interrupt mitigation */
124 #undef USE_ENTROPY_DEV     /* don't test for entropy device */
125
126 /* NOTE: these aren't useable unless PCI interrupts can be assigned.
127  * also, we need to make cp->lock finer-grained.
128  */
129 #undef  USE_PCI_INTB
130 #undef  USE_PCI_INTC
131 #undef  USE_PCI_INTD
132 #undef  USE_QOS
133
134 #undef  USE_VPD_DEBUG       /* debug vpd information if defined */
135
136 /* rx processing options */
137 #define USE_PAGE_ORDER      /* specify to allocate large rx pages */
138 #define RX_DONT_BATCH  0    /* if 1, don't batch flows */
139 #define RX_COPY_ALWAYS 0    /* if 0, use frags */
140 #define RX_COPY_MIN    64   /* copy a little to make upper layers happy */
141 #undef  RX_COUNT_BUFFERS    /* define to calculate RX buffer stats */
142
143 #define DRV_MODULE_NAME         "cassini"
144 #define PFX DRV_MODULE_NAME     ": "
145 #define DRV_MODULE_VERSION      "1.6"
146 #define DRV_MODULE_RELDATE      "21 May 2008"
147
148 #define CAS_DEF_MSG_ENABLE        \
149         (NETIF_MSG_DRV          | \
150          NETIF_MSG_PROBE        | \
151          NETIF_MSG_LINK         | \
152          NETIF_MSG_TIMER        | \
153          NETIF_MSG_IFDOWN       | \
154          NETIF_MSG_IFUP         | \
155          NETIF_MSG_RX_ERR       | \
156          NETIF_MSG_TX_ERR)
157
158 /* length of time before we decide the hardware is borked,
159  * and dev->tx_timeout() should be called to fix the problem
160  */
161 #define CAS_TX_TIMEOUT                  (HZ)
162 #define CAS_LINK_TIMEOUT                (22*HZ/10)
163 #define CAS_LINK_FAST_TIMEOUT           (1)
164
165 /* timeout values for state changing. these specify the number
166  * of 10us delays to be used before giving up.
167  */
168 #define STOP_TRIES_PHY 1000
169 #define STOP_TRIES     5000
170
171 /* specify a minimum frame size to deal with some fifo issues
172  * max mtu == 2 * page size - ethernet header - 64 - swivel =
173  *            2 * page_size - 0x50
174  */
175 #define CAS_MIN_FRAME                   97
176 #define CAS_1000MB_MIN_FRAME            255
177 #define CAS_MIN_MTU                     60
178 #define CAS_MAX_MTU                     min(((cp->page_size << 1) - 0x50), 9000)
179
180 #if 1
181 /*
182  * Eliminate these and use separate atomic counters for each, to
183  * avoid a race condition.
184  */
185 #else
186 #define CAS_RESET_MTU                   1
187 #define CAS_RESET_ALL                   2
188 #define CAS_RESET_SPARE                 3
189 #endif
190
191 static char version[] __devinitdata =
192         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
193
194 static int cassini_debug = -1;  /* -1 == use CAS_DEF_MSG_ENABLE as value */
195 static int link_mode;
196
197 MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
198 MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
199 MODULE_LICENSE("GPL");
200 module_param(cassini_debug, int, 0);
201 MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
202 module_param(link_mode, int, 0);
203 MODULE_PARM_DESC(link_mode, "default link mode");
204
205 /*
206  * Work around for a PCS bug in which the link goes down due to the chip
207  * being confused and never showing a link status of "up."
208  */
209 #define DEFAULT_LINKDOWN_TIMEOUT 5
210 /*
211  * Value in seconds, for user input.
212  */
213 static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
214 module_param(linkdown_timeout, int, 0);
215 MODULE_PARM_DESC(linkdown_timeout,
216 "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
217
218 /*
219  * value in 'ticks' (units used by jiffies). Set when we init the
220  * module because 'HZ' in actually a function call on some flavors of
221  * Linux.  This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
222  */
223 static int link_transition_timeout;
224
225
226
227 static u16 link_modes[] __devinitdata = {
228         BMCR_ANENABLE,                   /* 0 : autoneg */
229         0,                               /* 1 : 10bt half duplex */
230         BMCR_SPEED100,                   /* 2 : 100bt half duplex */
231         BMCR_FULLDPLX,                   /* 3 : 10bt full duplex */
232         BMCR_SPEED100|BMCR_FULLDPLX,     /* 4 : 100bt full duplex */
233         CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
234 };
235
236 static struct pci_device_id cas_pci_tbl[] __devinitdata = {
237         { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
238           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
239         { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
240           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
241         { 0, }
242 };
243
244 MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
245
246 static void cas_set_link_modes(struct cas *cp);
247
248 static inline void cas_lock_tx(struct cas *cp)
249 {
250         int i;
251
252         for (i = 0; i < N_TX_RINGS; i++)
253                 spin_lock(&cp->tx_lock[i]);
254 }
255
256 static inline void cas_lock_all(struct cas *cp)
257 {
258         spin_lock_irq(&cp->lock);
259         cas_lock_tx(cp);
260 }
261
262 /* WTZ: QA was finding deadlock problems with the previous
263  * versions after long test runs with multiple cards per machine.
264  * See if replacing cas_lock_all with safer versions helps. The
265  * symptoms QA is reporting match those we'd expect if interrupts
266  * aren't being properly restored, and we fixed a previous deadlock
267  * with similar symptoms by using save/restore versions in other
268  * places.
269  */
270 #define cas_lock_all_save(cp, flags) \
271 do { \
272         struct cas *xxxcp = (cp); \
273         spin_lock_irqsave(&xxxcp->lock, flags); \
274         cas_lock_tx(xxxcp); \
275 } while (0)
276
277 static inline void cas_unlock_tx(struct cas *cp)
278 {
279         int i;
280
281         for (i = N_TX_RINGS; i > 0; i--)
282                 spin_unlock(&cp->tx_lock[i - 1]);
283 }
284
285 static inline void cas_unlock_all(struct cas *cp)
286 {
287         cas_unlock_tx(cp);
288         spin_unlock_irq(&cp->lock);
289 }
290
291 #define cas_unlock_all_restore(cp, flags) \
292 do { \
293         struct cas *xxxcp = (cp); \
294         cas_unlock_tx(xxxcp); \
295         spin_unlock_irqrestore(&xxxcp->lock, flags); \
296 } while (0)
297
298 static void cas_disable_irq(struct cas *cp, const int ring)
299 {
300         /* Make sure we won't get any more interrupts */
301         if (ring == 0) {
302                 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
303                 return;
304         }
305
306         /* disable completion interrupts and selectively mask */
307         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
308                 switch (ring) {
309 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
310 #ifdef USE_PCI_INTB
311                 case 1:
312 #endif
313 #ifdef USE_PCI_INTC
314                 case 2:
315 #endif
316 #ifdef USE_PCI_INTD
317                 case 3:
318 #endif
319                         writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
320                                cp->regs + REG_PLUS_INTRN_MASK(ring));
321                         break;
322 #endif
323                 default:
324                         writel(INTRN_MASK_CLEAR_ALL, cp->regs +
325                                REG_PLUS_INTRN_MASK(ring));
326                         break;
327                 }
328         }
329 }
330
331 static inline void cas_mask_intr(struct cas *cp)
332 {
333         int i;
334
335         for (i = 0; i < N_RX_COMP_RINGS; i++)
336                 cas_disable_irq(cp, i);
337 }
338
339 static void cas_enable_irq(struct cas *cp, const int ring)
340 {
341         if (ring == 0) { /* all but TX_DONE */
342                 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
343                 return;
344         }
345
346         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
347                 switch (ring) {
348 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
349 #ifdef USE_PCI_INTB
350                 case 1:
351 #endif
352 #ifdef USE_PCI_INTC
353                 case 2:
354 #endif
355 #ifdef USE_PCI_INTD
356                 case 3:
357 #endif
358                         writel(INTRN_MASK_RX_EN, cp->regs +
359                                REG_PLUS_INTRN_MASK(ring));
360                         break;
361 #endif
362                 default:
363                         break;
364                 }
365         }
366 }
367
368 static inline void cas_unmask_intr(struct cas *cp)
369 {
370         int i;
371
372         for (i = 0; i < N_RX_COMP_RINGS; i++)
373                 cas_enable_irq(cp, i);
374 }
375
376 static inline void cas_entropy_gather(struct cas *cp)
377 {
378 #ifdef USE_ENTROPY_DEV
379         if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
380                 return;
381
382         batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
383                             readl(cp->regs + REG_ENTROPY_IV),
384                             sizeof(uint64_t)*8);
385 #endif
386 }
387
388 static inline void cas_entropy_reset(struct cas *cp)
389 {
390 #ifdef USE_ENTROPY_DEV
391         if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
392                 return;
393
394         writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
395                cp->regs + REG_BIM_LOCAL_DEV_EN);
396         writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
397         writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
398
399         /* if we read back 0x0, we don't have an entropy device */
400         if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
401                 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
402 #endif
403 }
404
405 /* access to the phy. the following assumes that we've initialized the MIF to
406  * be in frame rather than bit-bang mode
407  */
408 static u16 cas_phy_read(struct cas *cp, int reg)
409 {
410         u32 cmd;
411         int limit = STOP_TRIES_PHY;
412
413         cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
414         cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
415         cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
416         cmd |= MIF_FRAME_TURN_AROUND_MSB;
417         writel(cmd, cp->regs + REG_MIF_FRAME);
418
419         /* poll for completion */
420         while (limit-- > 0) {
421                 udelay(10);
422                 cmd = readl(cp->regs + REG_MIF_FRAME);
423                 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
424                         return (cmd & MIF_FRAME_DATA_MASK);
425         }
426         return 0xFFFF; /* -1 */
427 }
428
429 static int cas_phy_write(struct cas *cp, int reg, u16 val)
430 {
431         int limit = STOP_TRIES_PHY;
432         u32 cmd;
433
434         cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
435         cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
436         cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
437         cmd |= MIF_FRAME_TURN_AROUND_MSB;
438         cmd |= val & MIF_FRAME_DATA_MASK;
439         writel(cmd, cp->regs + REG_MIF_FRAME);
440
441         /* poll for completion */
442         while (limit-- > 0) {
443                 udelay(10);
444                 cmd = readl(cp->regs + REG_MIF_FRAME);
445                 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
446                         return 0;
447         }
448         return -1;
449 }
450
451 static void cas_phy_powerup(struct cas *cp)
452 {
453         u16 ctl = cas_phy_read(cp, MII_BMCR);
454
455         if ((ctl & BMCR_PDOWN) == 0)
456                 return;
457         ctl &= ~BMCR_PDOWN;
458         cas_phy_write(cp, MII_BMCR, ctl);
459 }
460
461 static void cas_phy_powerdown(struct cas *cp)
462 {
463         u16 ctl = cas_phy_read(cp, MII_BMCR);
464
465         if (ctl & BMCR_PDOWN)
466                 return;
467         ctl |= BMCR_PDOWN;
468         cas_phy_write(cp, MII_BMCR, ctl);
469 }
470
471 /* cp->lock held. note: the last put_page will free the buffer */
472 static int cas_page_free(struct cas *cp, cas_page_t *page)
473 {
474         pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size,
475                        PCI_DMA_FROMDEVICE);
476         __free_pages(page->buffer, cp->page_order);
477         kfree(page);
478         return 0;
479 }
480
481 #ifdef RX_COUNT_BUFFERS
482 #define RX_USED_ADD(x, y)       ((x)->used += (y))
483 #define RX_USED_SET(x, y)       ((x)->used  = (y))
484 #else
485 #define RX_USED_ADD(x, y)
486 #define RX_USED_SET(x, y)
487 #endif
488
489 /* local page allocation routines for the receive buffers. jumbo pages
490  * require at least 8K contiguous and 8K aligned buffers.
491  */
492 static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
493 {
494         cas_page_t *page;
495
496         page = kmalloc(sizeof(cas_page_t), flags);
497         if (!page)
498                 return NULL;
499
500         INIT_LIST_HEAD(&page->list);
501         RX_USED_SET(page, 0);
502         page->buffer = alloc_pages(flags, cp->page_order);
503         if (!page->buffer)
504                 goto page_err;
505         page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
506                                       cp->page_size, PCI_DMA_FROMDEVICE);
507         return page;
508
509 page_err:
510         kfree(page);
511         return NULL;
512 }
513
514 /* initialize spare pool of rx buffers, but allocate during the open */
515 static void cas_spare_init(struct cas *cp)
516 {
517         spin_lock(&cp->rx_inuse_lock);
518         INIT_LIST_HEAD(&cp->rx_inuse_list);
519         spin_unlock(&cp->rx_inuse_lock);
520
521         spin_lock(&cp->rx_spare_lock);
522         INIT_LIST_HEAD(&cp->rx_spare_list);
523         cp->rx_spares_needed = RX_SPARE_COUNT;
524         spin_unlock(&cp->rx_spare_lock);
525 }
526
527 /* used on close. free all the spare buffers. */
528 static void cas_spare_free(struct cas *cp)
529 {
530         struct list_head list, *elem, *tmp;
531
532         /* free spare buffers */
533         INIT_LIST_HEAD(&list);
534         spin_lock(&cp->rx_spare_lock);
535         list_splice_init(&cp->rx_spare_list, &list);
536         spin_unlock(&cp->rx_spare_lock);
537         list_for_each_safe(elem, tmp, &list) {
538                 cas_page_free(cp, list_entry(elem, cas_page_t, list));
539         }
540
541         INIT_LIST_HEAD(&list);
542 #if 1
543         /*
544          * Looks like Adrian had protected this with a different
545          * lock than used everywhere else to manipulate this list.
546          */
547         spin_lock(&cp->rx_inuse_lock);
548         list_splice_init(&cp->rx_inuse_list, &list);
549         spin_unlock(&cp->rx_inuse_lock);
550 #else
551         spin_lock(&cp->rx_spare_lock);
552         list_splice_init(&cp->rx_inuse_list, &list);
553         spin_unlock(&cp->rx_spare_lock);
554 #endif
555         list_for_each_safe(elem, tmp, &list) {
556                 cas_page_free(cp, list_entry(elem, cas_page_t, list));
557         }
558 }
559
560 /* replenish spares if needed */
561 static void cas_spare_recover(struct cas *cp, const gfp_t flags)
562 {
563         struct list_head list, *elem, *tmp;
564         int needed, i;
565
566         /* check inuse list. if we don't need any more free buffers,
567          * just free it
568          */
569
570         /* make a local copy of the list */
571         INIT_LIST_HEAD(&list);
572         spin_lock(&cp->rx_inuse_lock);
573         list_splice_init(&cp->rx_inuse_list, &list);
574         spin_unlock(&cp->rx_inuse_lock);
575
576         list_for_each_safe(elem, tmp, &list) {
577                 cas_page_t *page = list_entry(elem, cas_page_t, list);
578
579                 /*
580                  * With the lockless pagecache, cassini buffering scheme gets
581                  * slightly less accurate: we might find that a page has an
582                  * elevated reference count here, due to a speculative ref,
583                  * and skip it as in-use. Ideally we would be able to reclaim
584                  * it. However this would be such a rare case, it doesn't
585                  * matter too much as we should pick it up the next time round.
586                  *
587                  * Importantly, if we find that the page has a refcount of 1
588                  * here (our refcount), then we know it is definitely not inuse
589                  * so we can reuse it.
590                  */
591                 if (page_count(page->buffer) > 1)
592                         continue;
593
594                 list_del(elem);
595                 spin_lock(&cp->rx_spare_lock);
596                 if (cp->rx_spares_needed > 0) {
597                         list_add(elem, &cp->rx_spare_list);
598                         cp->rx_spares_needed--;
599                         spin_unlock(&cp->rx_spare_lock);
600                 } else {
601                         spin_unlock(&cp->rx_spare_lock);
602                         cas_page_free(cp, page);
603                 }
604         }
605
606         /* put any inuse buffers back on the list */
607         if (!list_empty(&list)) {
608                 spin_lock(&cp->rx_inuse_lock);
609                 list_splice(&list, &cp->rx_inuse_list);
610                 spin_unlock(&cp->rx_inuse_lock);
611         }
612
613         spin_lock(&cp->rx_spare_lock);
614         needed = cp->rx_spares_needed;
615         spin_unlock(&cp->rx_spare_lock);
616         if (!needed)
617                 return;
618
619         /* we still need spares, so try to allocate some */
620         INIT_LIST_HEAD(&list);
621         i = 0;
622         while (i < needed) {
623                 cas_page_t *spare = cas_page_alloc(cp, flags);
624                 if (!spare)
625                         break;
626                 list_add(&spare->list, &list);
627                 i++;
628         }
629
630         spin_lock(&cp->rx_spare_lock);
631         list_splice(&list, &cp->rx_spare_list);
632         cp->rx_spares_needed -= i;
633         spin_unlock(&cp->rx_spare_lock);
634 }
635
636 /* pull a page from the list. */
637 static cas_page_t *cas_page_dequeue(struct cas *cp)
638 {
639         struct list_head *entry;
640         int recover;
641
642         spin_lock(&cp->rx_spare_lock);
643         if (list_empty(&cp->rx_spare_list)) {
644                 /* try to do a quick recovery */
645                 spin_unlock(&cp->rx_spare_lock);
646                 cas_spare_recover(cp, GFP_ATOMIC);
647                 spin_lock(&cp->rx_spare_lock);
648                 if (list_empty(&cp->rx_spare_list)) {
649                         if (netif_msg_rx_err(cp))
650                                 printk(KERN_ERR "%s: no spare buffers "
651                                        "available.\n", cp->dev->name);
652                         spin_unlock(&cp->rx_spare_lock);
653                         return NULL;
654                 }
655         }
656
657         entry = cp->rx_spare_list.next;
658         list_del(entry);
659         recover = ++cp->rx_spares_needed;
660         spin_unlock(&cp->rx_spare_lock);
661
662         /* trigger the timer to do the recovery */
663         if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
664 #if 1
665                 atomic_inc(&cp->reset_task_pending);
666                 atomic_inc(&cp->reset_task_pending_spare);
667                 schedule_work(&cp->reset_task);
668 #else
669                 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
670                 schedule_work(&cp->reset_task);
671 #endif
672         }
673         return list_entry(entry, cas_page_t, list);
674 }
675
676
677 static void cas_mif_poll(struct cas *cp, const int enable)
678 {
679         u32 cfg;
680
681         cfg  = readl(cp->regs + REG_MIF_CFG);
682         cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
683
684         if (cp->phy_type & CAS_PHY_MII_MDIO1)
685                 cfg |= MIF_CFG_PHY_SELECT;
686
687         /* poll and interrupt on link status change. */
688         if (enable) {
689                 cfg |= MIF_CFG_POLL_EN;
690                 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
691                 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
692         }
693         writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
694                cp->regs + REG_MIF_MASK);
695         writel(cfg, cp->regs + REG_MIF_CFG);
696 }
697
698 /* Must be invoked under cp->lock */
699 static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep)
700 {
701         u16 ctl;
702 #if 1
703         int lcntl;
704         int changed = 0;
705         int oldstate = cp->lstate;
706         int link_was_not_down = !(oldstate == link_down);
707 #endif
708         /* Setup link parameters */
709         if (!ep)
710                 goto start_aneg;
711         lcntl = cp->link_cntl;
712         if (ep->autoneg == AUTONEG_ENABLE)
713                 cp->link_cntl = BMCR_ANENABLE;
714         else {
715                 cp->link_cntl = 0;
716                 if (ep->speed == SPEED_100)
717                         cp->link_cntl |= BMCR_SPEED100;
718                 else if (ep->speed == SPEED_1000)
719                         cp->link_cntl |= CAS_BMCR_SPEED1000;
720                 if (ep->duplex == DUPLEX_FULL)
721                         cp->link_cntl |= BMCR_FULLDPLX;
722         }
723 #if 1
724         changed = (lcntl != cp->link_cntl);
725 #endif
726 start_aneg:
727         if (cp->lstate == link_up) {
728                 printk(KERN_INFO "%s: PCS link down.\n",
729                        cp->dev->name);
730         } else {
731                 if (changed) {
732                         printk(KERN_INFO "%s: link configuration changed\n",
733                                cp->dev->name);
734                 }
735         }
736         cp->lstate = link_down;
737         cp->link_transition = LINK_TRANSITION_LINK_DOWN;
738         if (!cp->hw_running)
739                 return;
740 #if 1
741         /*
742          * WTZ: If the old state was link_up, we turn off the carrier
743          * to replicate everything we do elsewhere on a link-down
744          * event when we were already in a link-up state..
745          */
746         if (oldstate == link_up)
747                 netif_carrier_off(cp->dev);
748         if (changed  && link_was_not_down) {
749                 /*
750                  * WTZ: This branch will simply schedule a full reset after
751                  * we explicitly changed link modes in an ioctl. See if this
752                  * fixes the link-problems we were having for forced mode.
753                  */
754                 atomic_inc(&cp->reset_task_pending);
755                 atomic_inc(&cp->reset_task_pending_all);
756                 schedule_work(&cp->reset_task);
757                 cp->timer_ticks = 0;
758                 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
759                 return;
760         }
761 #endif
762         if (cp->phy_type & CAS_PHY_SERDES) {
763                 u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
764
765                 if (cp->link_cntl & BMCR_ANENABLE) {
766                         val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
767                         cp->lstate = link_aneg;
768                 } else {
769                         if (cp->link_cntl & BMCR_FULLDPLX)
770                                 val |= PCS_MII_CTRL_DUPLEX;
771                         val &= ~PCS_MII_AUTONEG_EN;
772                         cp->lstate = link_force_ok;
773                 }
774                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
775                 writel(val, cp->regs + REG_PCS_MII_CTRL);
776
777         } else {
778                 cas_mif_poll(cp, 0);
779                 ctl = cas_phy_read(cp, MII_BMCR);
780                 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
781                          CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
782                 ctl |= cp->link_cntl;
783                 if (ctl & BMCR_ANENABLE) {
784                         ctl |= BMCR_ANRESTART;
785                         cp->lstate = link_aneg;
786                 } else {
787                         cp->lstate = link_force_ok;
788                 }
789                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
790                 cas_phy_write(cp, MII_BMCR, ctl);
791                 cas_mif_poll(cp, 1);
792         }
793
794         cp->timer_ticks = 0;
795         mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
796 }
797
798 /* Must be invoked under cp->lock. */
799 static int cas_reset_mii_phy(struct cas *cp)
800 {
801         int limit = STOP_TRIES_PHY;
802         u16 val;
803
804         cas_phy_write(cp, MII_BMCR, BMCR_RESET);
805         udelay(100);
806         while (limit--) {
807                 val = cas_phy_read(cp, MII_BMCR);
808                 if ((val & BMCR_RESET) == 0)
809                         break;
810                 udelay(10);
811         }
812         return (limit <= 0);
813 }
814
815 static void cas_saturn_firmware_load(struct cas *cp)
816 {
817         cas_saturn_patch_t *patch = cas_saturn_patch;
818
819         cas_phy_powerdown(cp);
820
821         /* expanded memory access mode */
822         cas_phy_write(cp, DP83065_MII_MEM, 0x0);
823
824         /* pointer configuration for new firmware */
825         cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
826         cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
827         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
828         cas_phy_write(cp, DP83065_MII_REGD, 0x82);
829         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
830         cas_phy_write(cp, DP83065_MII_REGD, 0x0);
831         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
832         cas_phy_write(cp, DP83065_MII_REGD, 0x39);
833
834         /* download new firmware */
835         cas_phy_write(cp, DP83065_MII_MEM, 0x1);
836         cas_phy_write(cp, DP83065_MII_REGE, patch->addr);
837         while (patch->addr) {
838                 cas_phy_write(cp, DP83065_MII_REGD, patch->val);
839                 patch++;
840         }
841
842         /* enable firmware */
843         cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
844         cas_phy_write(cp, DP83065_MII_REGD, 0x1);
845 }
846
847
848 /* phy initialization */
849 static void cas_phy_init(struct cas *cp)
850 {
851         u16 val;
852
853         /* if we're in MII/GMII mode, set up phy */
854         if (CAS_PHY_MII(cp->phy_type)) {
855                 writel(PCS_DATAPATH_MODE_MII,
856                        cp->regs + REG_PCS_DATAPATH_MODE);
857
858                 cas_mif_poll(cp, 0);
859                 cas_reset_mii_phy(cp); /* take out of isolate mode */
860
861                 if (PHY_LUCENT_B0 == cp->phy_id) {
862                         /* workaround link up/down issue with lucent */
863                         cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
864                         cas_phy_write(cp, MII_BMCR, 0x00f1);
865                         cas_phy_write(cp, LUCENT_MII_REG, 0x0);
866
867                 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
868                         /* workarounds for broadcom phy */
869                         cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
870                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
871                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
872                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
873                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
874                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
875                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
876                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
877                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
878                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
879                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
880
881                 } else if (PHY_BROADCOM_5411 == cp->phy_id) {
882                         val = cas_phy_read(cp, BROADCOM_MII_REG4);
883                         val = cas_phy_read(cp, BROADCOM_MII_REG4);
884                         if (val & 0x0080) {
885                                 /* link workaround */
886                                 cas_phy_write(cp, BROADCOM_MII_REG4,
887                                               val & ~0x0080);
888                         }
889
890                 } else if (cp->cas_flags & CAS_FLAG_SATURN) {
891                         writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
892                                SATURN_PCFG_FSI : 0x0,
893                                cp->regs + REG_SATURN_PCFG);
894
895                         /* load firmware to address 10Mbps auto-negotiation
896                          * issue. NOTE: this will need to be changed if the
897                          * default firmware gets fixed.
898                          */
899                         if (PHY_NS_DP83065 == cp->phy_id) {
900                                 cas_saturn_firmware_load(cp);
901                         }
902                         cas_phy_powerup(cp);
903                 }
904
905                 /* advertise capabilities */
906                 val = cas_phy_read(cp, MII_BMCR);
907                 val &= ~BMCR_ANENABLE;
908                 cas_phy_write(cp, MII_BMCR, val);
909                 udelay(10);
910
911                 cas_phy_write(cp, MII_ADVERTISE,
912                               cas_phy_read(cp, MII_ADVERTISE) |
913                               (ADVERTISE_10HALF | ADVERTISE_10FULL |
914                                ADVERTISE_100HALF | ADVERTISE_100FULL |
915                                CAS_ADVERTISE_PAUSE |
916                                CAS_ADVERTISE_ASYM_PAUSE));
917
918                 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
919                         /* make sure that we don't advertise half
920                          * duplex to avoid a chip issue
921                          */
922                         val  = cas_phy_read(cp, CAS_MII_1000_CTRL);
923                         val &= ~CAS_ADVERTISE_1000HALF;
924                         val |= CAS_ADVERTISE_1000FULL;
925                         cas_phy_write(cp, CAS_MII_1000_CTRL, val);
926                 }
927
928         } else {
929                 /* reset pcs for serdes */
930                 u32 val;
931                 int limit;
932
933                 writel(PCS_DATAPATH_MODE_SERDES,
934                        cp->regs + REG_PCS_DATAPATH_MODE);
935
936                 /* enable serdes pins on saturn */
937                 if (cp->cas_flags & CAS_FLAG_SATURN)
938                         writel(0, cp->regs + REG_SATURN_PCFG);
939
940                 /* Reset PCS unit. */
941                 val = readl(cp->regs + REG_PCS_MII_CTRL);
942                 val |= PCS_MII_RESET;
943                 writel(val, cp->regs + REG_PCS_MII_CTRL);
944
945                 limit = STOP_TRIES;
946                 while (limit-- > 0) {
947                         udelay(10);
948                         if ((readl(cp->regs + REG_PCS_MII_CTRL) &
949                              PCS_MII_RESET) == 0)
950                                 break;
951                 }
952                 if (limit <= 0)
953                         printk(KERN_WARNING "%s: PCS reset bit would not "
954                                "clear [%08x].\n", cp->dev->name,
955                                readl(cp->regs + REG_PCS_STATE_MACHINE));
956
957                 /* Make sure PCS is disabled while changing advertisement
958                  * configuration.
959                  */
960                 writel(0x0, cp->regs + REG_PCS_CFG);
961
962                 /* Advertise all capabilities except half-duplex. */
963                 val  = readl(cp->regs + REG_PCS_MII_ADVERT);
964                 val &= ~PCS_MII_ADVERT_HD;
965                 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
966                         PCS_MII_ADVERT_ASYM_PAUSE);
967                 writel(val, cp->regs + REG_PCS_MII_ADVERT);
968
969                 /* enable PCS */
970                 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
971
972                 /* pcs workaround: enable sync detect */
973                 writel(PCS_SERDES_CTRL_SYNCD_EN,
974                        cp->regs + REG_PCS_SERDES_CTRL);
975         }
976 }
977
978
979 static int cas_pcs_link_check(struct cas *cp)
980 {
981         u32 stat, state_machine;
982         int retval = 0;
983
984         /* The link status bit latches on zero, so you must
985          * read it twice in such a case to see a transition
986          * to the link being up.
987          */
988         stat = readl(cp->regs + REG_PCS_MII_STATUS);
989         if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
990                 stat = readl(cp->regs + REG_PCS_MII_STATUS);
991
992         /* The remote-fault indication is only valid
993          * when autoneg has completed.
994          */
995         if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
996                      PCS_MII_STATUS_REMOTE_FAULT)) ==
997             (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT)) {
998                 if (netif_msg_link(cp))
999                         printk(KERN_INFO "%s: PCS RemoteFault\n",
1000                                cp->dev->name);
1001         }
1002
1003         /* work around link detection issue by querying the PCS state
1004          * machine directly.
1005          */
1006         state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
1007         if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
1008                 stat &= ~PCS_MII_STATUS_LINK_STATUS;
1009         } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
1010                 stat |= PCS_MII_STATUS_LINK_STATUS;
1011         }
1012
1013         if (stat & PCS_MII_STATUS_LINK_STATUS) {
1014                 if (cp->lstate != link_up) {
1015                         if (cp->opened) {
1016                                 cp->lstate = link_up;
1017                                 cp->link_transition = LINK_TRANSITION_LINK_UP;
1018
1019                                 cas_set_link_modes(cp);
1020                                 netif_carrier_on(cp->dev);
1021                         }
1022                 }
1023         } else if (cp->lstate == link_up) {
1024                 cp->lstate = link_down;
1025                 if (link_transition_timeout != 0 &&
1026                     cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1027                     !cp->link_transition_jiffies_valid) {
1028                         /*
1029                          * force a reset, as a workaround for the
1030                          * link-failure problem. May want to move this to a
1031                          * point a bit earlier in the sequence. If we had
1032                          * generated a reset a short time ago, we'll wait for
1033                          * the link timer to check the status until a
1034                          * timer expires (link_transistion_jiffies_valid is
1035                          * true when the timer is running.)  Instead of using
1036                          * a system timer, we just do a check whenever the
1037                          * link timer is running - this clears the flag after
1038                          * a suitable delay.
1039                          */
1040                         retval = 1;
1041                         cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1042                         cp->link_transition_jiffies = jiffies;
1043                         cp->link_transition_jiffies_valid = 1;
1044                 } else {
1045                         cp->link_transition = LINK_TRANSITION_ON_FAILURE;
1046                 }
1047                 netif_carrier_off(cp->dev);
1048                 if (cp->opened && netif_msg_link(cp)) {
1049                         printk(KERN_INFO "%s: PCS link down.\n",
1050                                cp->dev->name);
1051                 }
1052
1053                 /* Cassini only: if you force a mode, there can be
1054                  * sync problems on link down. to fix that, the following
1055                  * things need to be checked:
1056                  * 1) read serialink state register
1057                  * 2) read pcs status register to verify link down.
1058                  * 3) if link down and serial link == 0x03, then you need
1059                  *    to global reset the chip.
1060                  */
1061                 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
1062                         /* should check to see if we're in a forced mode */
1063                         stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1064                         if (stat == 0x03)
1065                                 return 1;
1066                 }
1067         } else if (cp->lstate == link_down) {
1068                 if (link_transition_timeout != 0 &&
1069                     cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1070                     !cp->link_transition_jiffies_valid) {
1071                         /* force a reset, as a workaround for the
1072                          * link-failure problem.  May want to move
1073                          * this to a point a bit earlier in the
1074                          * sequence.
1075                          */
1076                         retval = 1;
1077                         cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1078                         cp->link_transition_jiffies = jiffies;
1079                         cp->link_transition_jiffies_valid = 1;
1080                 } else {
1081                         cp->link_transition = LINK_TRANSITION_STILL_FAILED;
1082                 }
1083         }
1084
1085         return retval;
1086 }
1087
1088 static int cas_pcs_interrupt(struct net_device *dev,
1089                              struct cas *cp, u32 status)
1090 {
1091         u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1092
1093         if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1094                 return 0;
1095         return cas_pcs_link_check(cp);
1096 }
1097
1098 static int cas_txmac_interrupt(struct net_device *dev,
1099                                struct cas *cp, u32 status)
1100 {
1101         u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
1102
1103         if (!txmac_stat)
1104                 return 0;
1105
1106         if (netif_msg_intr(cp))
1107                 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
1108                         cp->dev->name, txmac_stat);
1109
1110         /* Defer timer expiration is quite normal,
1111          * don't even log the event.
1112          */
1113         if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
1114             !(txmac_stat & ~MAC_TX_DEFER_TIMER))
1115                 return 0;
1116
1117         spin_lock(&cp->stat_lock[0]);
1118         if (txmac_stat & MAC_TX_UNDERRUN) {
1119                 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
1120                        dev->name);
1121                 cp->net_stats[0].tx_fifo_errors++;
1122         }
1123
1124         if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
1125                 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
1126                        dev->name);
1127                 cp->net_stats[0].tx_errors++;
1128         }
1129
1130         /* The rest are all cases of one of the 16-bit TX
1131          * counters expiring.
1132          */
1133         if (txmac_stat & MAC_TX_COLL_NORMAL)
1134                 cp->net_stats[0].collisions += 0x10000;
1135
1136         if (txmac_stat & MAC_TX_COLL_EXCESS) {
1137                 cp->net_stats[0].tx_aborted_errors += 0x10000;
1138                 cp->net_stats[0].collisions += 0x10000;
1139         }
1140
1141         if (txmac_stat & MAC_TX_COLL_LATE) {
1142                 cp->net_stats[0].tx_aborted_errors += 0x10000;
1143                 cp->net_stats[0].collisions += 0x10000;
1144         }
1145         spin_unlock(&cp->stat_lock[0]);
1146
1147         /* We do not keep track of MAC_TX_COLL_FIRST and
1148          * MAC_TX_PEAK_ATTEMPTS events.
1149          */
1150         return 0;
1151 }
1152
1153 static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware)
1154 {
1155         cas_hp_inst_t *inst;
1156         u32 val;
1157         int i;
1158
1159         i = 0;
1160         while ((inst = firmware) && inst->note) {
1161                 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
1162
1163                 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1164                 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1165                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1166
1167                 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1168                 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1169                 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1170                 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1171                 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1172                 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1173                 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1174                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1175
1176                 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1177                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1178                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1179                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1180                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1181                 ++firmware;
1182                 ++i;
1183         }
1184 }
1185
1186 static void cas_init_rx_dma(struct cas *cp)
1187 {
1188         u64 desc_dma = cp->block_dvma;
1189         u32 val;
1190         int i, size;
1191
1192         /* rx free descriptors */
1193         val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
1194         val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1195         val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1196         if ((N_RX_DESC_RINGS > 1) &&
1197             (cp->cas_flags & CAS_FLAG_REG_PLUS))  /* do desc 2 */
1198                 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1199         writel(val, cp->regs + REG_RX_CFG);
1200
1201         val = (unsigned long) cp->init_rxds[0] -
1202                 (unsigned long) cp->init_block;
1203         writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1204         writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1205         writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
1206
1207         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1208                 /* rx desc 2 is for IPSEC packets. however,
1209                  * we don't it that for that purpose.
1210                  */
1211                 val = (unsigned long) cp->init_rxds[1] -
1212                         (unsigned long) cp->init_block;
1213                 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1214                 writel((desc_dma + val) & 0xffffffff, cp->regs +
1215                        REG_PLUS_RX_DB1_LOW);
1216                 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
1217                        REG_PLUS_RX_KICK1);
1218         }
1219
1220         /* rx completion registers */
1221         val = (unsigned long) cp->init_rxcs[0] -
1222                 (unsigned long) cp->init_block;
1223         writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1224         writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1225
1226         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1227                 /* rx comp 2-4 */
1228                 for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
1229                         val = (unsigned long) cp->init_rxcs[i] -
1230                                 (unsigned long) cp->init_block;
1231                         writel((desc_dma + val) >> 32, cp->regs +
1232                                REG_PLUS_RX_CBN_HI(i));
1233                         writel((desc_dma + val) & 0xffffffff, cp->regs +
1234                                REG_PLUS_RX_CBN_LOW(i));
1235                 }
1236         }
1237
1238         /* read selective clear regs to prevent spurious interrupts
1239          * on reset because complete == kick.
1240          * selective clear set up to prevent interrupts on resets
1241          */
1242         readl(cp->regs + REG_INTR_STATUS_ALIAS);
1243         writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
1244         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1245                 for (i = 1; i < N_RX_COMP_RINGS; i++)
1246                         readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
1247
1248                 /* 2 is different from 3 and 4 */
1249                 if (N_RX_COMP_RINGS > 1)
1250                         writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1,
1251                                cp->regs + REG_PLUS_ALIASN_CLEAR(1));
1252
1253                 for (i = 2; i < N_RX_COMP_RINGS; i++)
1254                         writel(INTR_RX_DONE_ALT,
1255                                cp->regs + REG_PLUS_ALIASN_CLEAR(i));
1256         }
1257
1258         /* set up pause thresholds */
1259         val  = CAS_BASE(RX_PAUSE_THRESH_OFF,
1260                         cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
1261         val |= CAS_BASE(RX_PAUSE_THRESH_ON,
1262                         cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
1263         writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1264
1265         /* zero out dma reassembly buffers */
1266         for (i = 0; i < 64; i++) {
1267                 writel(i, cp->regs + REG_RX_TABLE_ADDR);
1268                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
1269                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
1270                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
1271         }
1272
1273         /* make sure address register is 0 for normal operation */
1274         writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
1275         writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
1276
1277         /* interrupt mitigation */
1278 #ifdef USE_RX_BLANK
1279         val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1280         val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1281         writel(val, cp->regs + REG_RX_BLANK);
1282 #else
1283         writel(0x0, cp->regs + REG_RX_BLANK);
1284 #endif
1285
1286         /* interrupt generation as a function of low water marks for
1287          * free desc and completion entries. these are used to trigger
1288          * housekeeping for rx descs. we don't use the free interrupt
1289          * as it's not very useful
1290          */
1291         /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
1292         val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1293         writel(val, cp->regs + REG_RX_AE_THRESH);
1294         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1295                 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1296                 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1297         }
1298
1299         /* Random early detect registers. useful for congestion avoidance.
1300          * this should be tunable.
1301          */
1302         writel(0x0, cp->regs + REG_RX_RED);
1303
1304         /* receive page sizes. default == 2K (0x800) */
1305         val = 0;
1306         if (cp->page_size == 0x1000)
1307                 val = 0x1;
1308         else if (cp->page_size == 0x2000)
1309                 val = 0x2;
1310         else if (cp->page_size == 0x4000)
1311                 val = 0x3;
1312
1313         /* round mtu + offset. constrain to page size. */
1314         size = cp->dev->mtu + 64;
1315         if (size > cp->page_size)
1316                 size = cp->page_size;
1317
1318         if (size <= 0x400)
1319                 i = 0x0;
1320         else if (size <= 0x800)
1321                 i = 0x1;
1322         else if (size <= 0x1000)
1323                 i = 0x2;
1324         else
1325                 i = 0x3;
1326
1327         cp->mtu_stride = 1 << (i + 10);
1328         val  = CAS_BASE(RX_PAGE_SIZE, val);
1329         val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
1330         val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1331         val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1332         writel(val, cp->regs + REG_RX_PAGE_SIZE);
1333
1334         /* enable the header parser if desired */
1335         if (CAS_HP_FIRMWARE == cas_prog_null)
1336                 return;
1337
1338         val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1339         val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1340         val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1341         writel(val, cp->regs + REG_HP_CFG);
1342 }
1343
1344 static inline void cas_rxc_init(struct cas_rx_comp *rxc)
1345 {
1346         memset(rxc, 0, sizeof(*rxc));
1347         rxc->word4 = cpu_to_le64(RX_COMP4_ZERO);
1348 }
1349
1350 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
1351  * flipping is protected by the fact that the chip will not
1352  * hand back the same page index while it's being processed.
1353  */
1354 static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
1355 {
1356         cas_page_t *page = cp->rx_pages[1][index];
1357         cas_page_t *new;
1358
1359         if (page_count(page->buffer) == 1)
1360                 return page;
1361
1362         new = cas_page_dequeue(cp);
1363         if (new) {
1364                 spin_lock(&cp->rx_inuse_lock);
1365                 list_add(&page->list, &cp->rx_inuse_list);
1366                 spin_unlock(&cp->rx_inuse_lock);
1367         }
1368         return new;
1369 }
1370
1371 /* this needs to be changed if we actually use the ENC RX DESC ring */
1372 static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
1373                                  const int index)
1374 {
1375         cas_page_t **page0 = cp->rx_pages[0];
1376         cas_page_t **page1 = cp->rx_pages[1];
1377
1378         /* swap if buffer is in use */
1379         if (page_count(page0[index]->buffer) > 1) {
1380                 cas_page_t *new = cas_page_spare(cp, index);
1381                 if (new) {
1382                         page1[index] = page0[index];
1383                         page0[index] = new;
1384                 }
1385         }
1386         RX_USED_SET(page0[index], 0);
1387         return page0[index];
1388 }
1389
1390 static void cas_clean_rxds(struct cas *cp)
1391 {
1392         /* only clean ring 0 as ring 1 is used for spare buffers */
1393         struct cas_rx_desc *rxd = cp->init_rxds[0];
1394         int i, size;
1395
1396         /* release all rx flows */
1397         for (i = 0; i < N_RX_FLOWS; i++) {
1398                 struct sk_buff *skb;
1399                 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
1400                         cas_skb_release(skb);
1401                 }
1402         }
1403
1404         /* initialize descriptors */
1405         size = RX_DESC_RINGN_SIZE(0);
1406         for (i = 0; i < size; i++) {
1407                 cas_page_t *page = cas_page_swap(cp, 0, i);
1408                 rxd[i].buffer = cpu_to_le64(page->dma_addr);
1409                 rxd[i].index  = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
1410                                             CAS_BASE(RX_INDEX_RING, 0));
1411         }
1412
1413         cp->rx_old[0]  = RX_DESC_RINGN_SIZE(0) - 4;
1414         cp->rx_last[0] = 0;
1415         cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
1416 }
1417
1418 static void cas_clean_rxcs(struct cas *cp)
1419 {
1420         int i, j;
1421
1422         /* take ownership of rx comp descriptors */
1423         memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
1424         memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
1425         for (i = 0; i < N_RX_COMP_RINGS; i++) {
1426                 struct cas_rx_comp *rxc = cp->init_rxcs[i];
1427                 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
1428                         cas_rxc_init(rxc + j);
1429                 }
1430         }
1431 }
1432
1433 #if 0
1434 /* When we get a RX fifo overflow, the RX unit is probably hung
1435  * so we do the following.
1436  *
1437  * If any part of the reset goes wrong, we return 1 and that causes the
1438  * whole chip to be reset.
1439  */
1440 static int cas_rxmac_reset(struct cas *cp)
1441 {
1442         struct net_device *dev = cp->dev;
1443         int limit;
1444         u32 val;
1445
1446         /* First, reset MAC RX. */
1447         writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1448         for (limit = 0; limit < STOP_TRIES; limit++) {
1449                 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1450                         break;
1451                 udelay(10);
1452         }
1453         if (limit == STOP_TRIES) {
1454                 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
1455                        "chip.\n", dev->name);
1456                 return 1;
1457         }
1458
1459         /* Second, disable RX DMA. */
1460         writel(0, cp->regs + REG_RX_CFG);
1461         for (limit = 0; limit < STOP_TRIES; limit++) {
1462                 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1463                         break;
1464                 udelay(10);
1465         }
1466         if (limit == STOP_TRIES) {
1467                 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
1468                        "chip.\n", dev->name);
1469                 return 1;
1470         }
1471
1472         mdelay(5);
1473
1474         /* Execute RX reset command. */
1475         writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1476         for (limit = 0; limit < STOP_TRIES; limit++) {
1477                 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1478                         break;
1479                 udelay(10);
1480         }
1481         if (limit == STOP_TRIES) {
1482                 printk(KERN_ERR "%s: RX reset command will not execute, "
1483                        "resetting whole chip.\n", dev->name);
1484                 return 1;
1485         }
1486
1487         /* reset driver rx state */
1488         cas_clean_rxds(cp);
1489         cas_clean_rxcs(cp);
1490
1491         /* Now, reprogram the rest of RX unit. */
1492         cas_init_rx_dma(cp);
1493
1494         /* re-enable */
1495         val = readl(cp->regs + REG_RX_CFG);
1496         writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1497         writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1498         val = readl(cp->regs + REG_MAC_RX_CFG);
1499         writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1500         return 0;
1501 }
1502 #endif
1503
1504 static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
1505                                u32 status)
1506 {
1507         u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1508
1509         if (!stat)
1510                 return 0;
1511
1512         if (netif_msg_intr(cp))
1513                 printk(KERN_DEBUG "%s: rxmac interrupt, stat: 0x%x\n",
1514                         cp->dev->name, stat);
1515
1516         /* these are all rollovers */
1517         spin_lock(&cp->stat_lock[0]);
1518         if (stat & MAC_RX_ALIGN_ERR)
1519                 cp->net_stats[0].rx_frame_errors += 0x10000;
1520
1521         if (stat & MAC_RX_CRC_ERR)
1522                 cp->net_stats[0].rx_crc_errors += 0x10000;
1523
1524         if (stat & MAC_RX_LEN_ERR)
1525                 cp->net_stats[0].rx_length_errors += 0x10000;
1526
1527         if (stat & MAC_RX_OVERFLOW) {
1528                 cp->net_stats[0].rx_over_errors++;
1529                 cp->net_stats[0].rx_fifo_errors++;
1530         }
1531
1532         /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
1533          * events.
1534          */
1535         spin_unlock(&cp->stat_lock[0]);
1536         return 0;
1537 }
1538
1539 static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
1540                              u32 status)
1541 {
1542         u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1543
1544         if (!stat)
1545                 return 0;
1546
1547         if (netif_msg_intr(cp))
1548                 printk(KERN_DEBUG "%s: mac interrupt, stat: 0x%x\n",
1549                         cp->dev->name, stat);
1550
1551         /* This interrupt is just for pause frame and pause
1552          * tracking.  It is useful for diagnostics and debug
1553          * but probably by default we will mask these events.
1554          */
1555         if (stat & MAC_CTRL_PAUSE_STATE)
1556                 cp->pause_entered++;
1557
1558         if (stat & MAC_CTRL_PAUSE_RECEIVED)
1559                 cp->pause_last_time_recvd = (stat >> 16);
1560
1561         return 0;
1562 }
1563
1564
1565 /* Must be invoked under cp->lock. */
1566 static inline int cas_mdio_link_not_up(struct cas *cp)
1567 {
1568         u16 val;
1569
1570         switch (cp->lstate) {
1571         case link_force_ret:
1572                 if (netif_msg_link(cp))
1573                         printk(KERN_INFO "%s: Autoneg failed again, keeping"
1574                                 " forced mode\n", cp->dev->name);
1575                 cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
1576                 cp->timer_ticks = 5;
1577                 cp->lstate = link_force_ok;
1578                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1579                 break;
1580
1581         case link_aneg:
1582                 val = cas_phy_read(cp, MII_BMCR);
1583
1584                 /* Try forced modes. we try things in the following order:
1585                  * 1000 full -> 100 full/half -> 10 half
1586                  */
1587                 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1588                 val |= BMCR_FULLDPLX;
1589                 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
1590                         CAS_BMCR_SPEED1000 : BMCR_SPEED100;
1591                 cas_phy_write(cp, MII_BMCR, val);
1592                 cp->timer_ticks = 5;
1593                 cp->lstate = link_force_try;
1594                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1595                 break;
1596
1597         case link_force_try:
1598                 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
1599                 val = cas_phy_read(cp, MII_BMCR);
1600                 cp->timer_ticks = 5;
1601                 if (val & CAS_BMCR_SPEED1000) { /* gigabit */
1602                         val &= ~CAS_BMCR_SPEED1000;
1603                         val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1604                         cas_phy_write(cp, MII_BMCR, val);
1605                         break;
1606                 }
1607
1608                 if (val & BMCR_SPEED100) {
1609                         if (val & BMCR_FULLDPLX) /* fd failed */
1610                                 val &= ~BMCR_FULLDPLX;
1611                         else { /* 100Mbps failed */
1612                                 val &= ~BMCR_SPEED100;
1613                         }
1614                         cas_phy_write(cp, MII_BMCR, val);
1615                         break;
1616                 }
1617         default:
1618                 break;
1619         }
1620         return 0;
1621 }
1622
1623
1624 /* must be invoked with cp->lock held */
1625 static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
1626 {
1627         int restart;
1628
1629         if (bmsr & BMSR_LSTATUS) {
1630                 /* Ok, here we got a link. If we had it due to a forced
1631                  * fallback, and we were configured for autoneg, we
1632                  * retry a short autoneg pass. If you know your hub is
1633                  * broken, use ethtool ;)
1634                  */
1635                 if ((cp->lstate == link_force_try) &&
1636                     (cp->link_cntl & BMCR_ANENABLE)) {
1637                         cp->lstate = link_force_ret;
1638                         cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1639                         cas_mif_poll(cp, 0);
1640                         cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
1641                         cp->timer_ticks = 5;
1642                         if (cp->opened && netif_msg_link(cp))
1643                                 printk(KERN_INFO "%s: Got link after fallback, retrying"
1644                                        " autoneg once...\n", cp->dev->name);
1645                         cas_phy_write(cp, MII_BMCR,
1646                                       cp->link_fcntl | BMCR_ANENABLE |
1647                                       BMCR_ANRESTART);
1648                         cas_mif_poll(cp, 1);
1649
1650                 } else if (cp->lstate != link_up) {
1651                         cp->lstate = link_up;
1652                         cp->link_transition = LINK_TRANSITION_LINK_UP;
1653
1654                         if (cp->opened) {
1655                                 cas_set_link_modes(cp);
1656                                 netif_carrier_on(cp->dev);
1657                         }
1658                 }
1659                 return 0;
1660         }
1661
1662         /* link not up. if the link was previously up, we restart the
1663          * whole process
1664          */
1665         restart = 0;
1666         if (cp->lstate == link_up) {
1667                 cp->lstate = link_down;
1668                 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
1669
1670                 netif_carrier_off(cp->dev);
1671                 if (cp->opened && netif_msg_link(cp))
1672                         printk(KERN_INFO "%s: Link down\n",
1673                                cp->dev->name);
1674                 restart = 1;
1675
1676         } else if (++cp->timer_ticks > 10)
1677                 cas_mdio_link_not_up(cp);
1678
1679         return restart;
1680 }
1681
1682 static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
1683                              u32 status)
1684 {
1685         u32 stat = readl(cp->regs + REG_MIF_STATUS);
1686         u16 bmsr;
1687
1688         /* check for a link change */
1689         if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1690                 return 0;
1691
1692         bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1693         return cas_mii_link_check(cp, bmsr);
1694 }
1695
1696 static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
1697                              u32 status)
1698 {
1699         u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1700
1701         if (!stat)
1702                 return 0;
1703
1704         printk(KERN_ERR "%s: PCI error [%04x:%04x] ", dev->name, stat,
1705                readl(cp->regs + REG_BIM_DIAG));
1706
1707         /* cassini+ has this reserved */
1708         if ((stat & PCI_ERR_BADACK) &&
1709             ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
1710                 printk("<No ACK64# during ABS64 cycle> ");
1711
1712         if (stat & PCI_ERR_DTRTO)
1713                 printk("<Delayed transaction timeout> ");
1714         if (stat & PCI_ERR_OTHER)
1715                 printk("<other> ");
1716         if (stat & PCI_ERR_BIM_DMA_WRITE)
1717                 printk("<BIM DMA 0 write req> ");
1718         if (stat & PCI_ERR_BIM_DMA_READ)
1719                 printk("<BIM DMA 0 read req> ");
1720         printk("\n");
1721
1722         if (stat & PCI_ERR_OTHER) {
1723                 u16 cfg;
1724
1725                 /* Interrogate PCI config space for the
1726                  * true cause.
1727                  */
1728                 pci_read_config_word(cp->pdev, PCI_STATUS, &cfg);
1729                 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
1730                        dev->name, cfg);
1731                 if (cfg & PCI_STATUS_PARITY)
1732                         printk(KERN_ERR "%s: PCI parity error detected.\n",
1733                                dev->name);
1734                 if (cfg & PCI_STATUS_SIG_TARGET_ABORT)
1735                         printk(KERN_ERR "%s: PCI target abort.\n",
1736                                dev->name);
1737                 if (cfg & PCI_STATUS_REC_TARGET_ABORT)
1738                         printk(KERN_ERR "%s: PCI master acks target abort.\n",
1739                                dev->name);
1740                 if (cfg & PCI_STATUS_REC_MASTER_ABORT)
1741                         printk(KERN_ERR "%s: PCI master abort.\n", dev->name);
1742                 if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR)
1743                         printk(KERN_ERR "%s: PCI system error SERR#.\n",
1744                                dev->name);
1745                 if (cfg & PCI_STATUS_DETECTED_PARITY)
1746                         printk(KERN_ERR "%s: PCI parity error.\n",
1747                                dev->name);
1748
1749                 /* Write the error bits back to clear them. */
1750                 cfg &= (PCI_STATUS_PARITY |
1751                         PCI_STATUS_SIG_TARGET_ABORT |
1752                         PCI_STATUS_REC_TARGET_ABORT |
1753                         PCI_STATUS_REC_MASTER_ABORT |
1754                         PCI_STATUS_SIG_SYSTEM_ERROR |
1755                         PCI_STATUS_DETECTED_PARITY);
1756                 pci_write_config_word(cp->pdev, PCI_STATUS, cfg);
1757         }
1758
1759         /* For all PCI errors, we should reset the chip. */
1760         return 1;
1761 }
1762
1763 /* All non-normal interrupt conditions get serviced here.
1764  * Returns non-zero if we should just exit the interrupt
1765  * handler right now (ie. if we reset the card which invalidates
1766  * all of the other original irq status bits).
1767  */
1768 static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
1769                             u32 status)
1770 {
1771         if (status & INTR_RX_TAG_ERROR) {
1772                 /* corrupt RX tag framing */
1773                 if (netif_msg_rx_err(cp))
1774                         printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
1775                                 cp->dev->name);
1776                 spin_lock(&cp->stat_lock[0]);
1777                 cp->net_stats[0].rx_errors++;
1778                 spin_unlock(&cp->stat_lock[0]);
1779                 goto do_reset;
1780         }
1781
1782         if (status & INTR_RX_LEN_MISMATCH) {
1783                 /* length mismatch. */
1784                 if (netif_msg_rx_err(cp))
1785                         printk(KERN_DEBUG "%s: length mismatch for rx frame\n",
1786                                 cp->dev->name);
1787                 spin_lock(&cp->stat_lock[0]);
1788                 cp->net_stats[0].rx_errors++;
1789                 spin_unlock(&cp->stat_lock[0]);
1790                 goto do_reset;
1791         }
1792
1793         if (status & INTR_PCS_STATUS) {
1794                 if (cas_pcs_interrupt(dev, cp, status))
1795                         goto do_reset;
1796         }
1797
1798         if (status & INTR_TX_MAC_STATUS) {
1799                 if (cas_txmac_interrupt(dev, cp, status))
1800                         goto do_reset;
1801         }
1802
1803         if (status & INTR_RX_MAC_STATUS) {
1804                 if (cas_rxmac_interrupt(dev, cp, status))
1805                         goto do_reset;
1806         }
1807
1808         if (status & INTR_MAC_CTRL_STATUS) {
1809                 if (cas_mac_interrupt(dev, cp, status))
1810                         goto do_reset;
1811         }
1812
1813         if (status & INTR_MIF_STATUS) {
1814                 if (cas_mif_interrupt(dev, cp, status))
1815                         goto do_reset;
1816         }
1817
1818         if (status & INTR_PCI_ERROR_STATUS) {
1819                 if (cas_pci_interrupt(dev, cp, status))
1820                         goto do_reset;
1821         }
1822         return 0;
1823
1824 do_reset:
1825 #if 1
1826         atomic_inc(&cp->reset_task_pending);
1827         atomic_inc(&cp->reset_task_pending_all);
1828         printk(KERN_ERR "%s:reset called in cas_abnormal_irq [0x%x]\n",
1829                dev->name, status);
1830         schedule_work(&cp->reset_task);
1831 #else
1832         atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
1833         printk(KERN_ERR "reset called in cas_abnormal_irq\n");
1834         schedule_work(&cp->reset_task);
1835 #endif
1836         return 1;
1837 }
1838
1839 /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
1840  *       determining whether to do a netif_stop/wakeup
1841  */
1842 #define CAS_TABORT(x)      (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1843 #define CAS_ROUND_PAGE(x)  (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1844 static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
1845                                   const int len)
1846 {
1847         unsigned long off = addr + len;
1848
1849         if (CAS_TABORT(cp) == 1)
1850                 return 0;
1851         if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
1852                 return 0;
1853         return TX_TARGET_ABORT_LEN;
1854 }
1855
1856 static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
1857 {
1858         struct cas_tx_desc *txds;
1859         struct sk_buff **skbs;
1860         struct net_device *dev = cp->dev;
1861         int entry, count;
1862
1863         spin_lock(&cp->tx_lock[ring]);
1864         txds = cp->init_txds[ring];
1865         skbs = cp->tx_skbs[ring];
1866         entry = cp->tx_old[ring];
1867
1868         count = TX_BUFF_COUNT(ring, entry, limit);
1869         while (entry != limit) {
1870                 struct sk_buff *skb = skbs[entry];
1871                 dma_addr_t daddr;
1872                 u32 dlen;
1873                 int frag;
1874
1875                 if (!skb) {
1876                         /* this should never occur */
1877                         entry = TX_DESC_NEXT(ring, entry);
1878                         continue;
1879                 }
1880
1881                 /* however, we might get only a partial skb release. */
1882                 count -= skb_shinfo(skb)->nr_frags +
1883                         + cp->tx_tiny_use[ring][entry].nbufs + 1;
1884                 if (count < 0)
1885                         break;
1886
1887                 if (netif_msg_tx_done(cp))
1888                         printk(KERN_DEBUG "%s: tx[%d] done, slot %d\n",
1889                                cp->dev->name, ring, entry);
1890
1891                 skbs[entry] = NULL;
1892                 cp->tx_tiny_use[ring][entry].nbufs = 0;
1893
1894                 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1895                         struct cas_tx_desc *txd = txds + entry;
1896
1897                         daddr = le64_to_cpu(txd->buffer);
1898                         dlen = CAS_VAL(TX_DESC_BUFLEN,
1899                                        le64_to_cpu(txd->control));
1900                         pci_unmap_page(cp->pdev, daddr, dlen,
1901                                        PCI_DMA_TODEVICE);
1902                         entry = TX_DESC_NEXT(ring, entry);
1903
1904                         /* tiny buffer may follow */
1905                         if (cp->tx_tiny_use[ring][entry].used) {
1906                                 cp->tx_tiny_use[ring][entry].used = 0;
1907                                 entry = TX_DESC_NEXT(ring, entry);
1908                         }
1909                 }
1910
1911                 spin_lock(&cp->stat_lock[ring]);
1912                 cp->net_stats[ring].tx_packets++;
1913                 cp->net_stats[ring].tx_bytes += skb->len;
1914                 spin_unlock(&cp->stat_lock[ring]);
1915                 dev_kfree_skb_irq(skb);
1916         }
1917         cp->tx_old[ring] = entry;
1918
1919         /* this is wrong for multiple tx rings. the net device needs
1920          * multiple queues for this to do the right thing.  we wait
1921          * for 2*packets to be available when using tiny buffers
1922          */
1923         if (netif_queue_stopped(dev) &&
1924             (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
1925                 netif_wake_queue(dev);
1926         spin_unlock(&cp->tx_lock[ring]);
1927 }
1928
1929 static void cas_tx(struct net_device *dev, struct cas *cp,
1930                    u32 status)
1931 {
1932         int limit, ring;
1933 #ifdef USE_TX_COMPWB
1934         u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
1935 #endif
1936         if (netif_msg_intr(cp))
1937                 printk(KERN_DEBUG "%s: tx interrupt, status: 0x%x, %llx\n",
1938                         cp->dev->name, status, (unsigned long long)compwb);
1939         /* process all the rings */
1940         for (ring = 0; ring < N_TX_RINGS; ring++) {
1941 #ifdef USE_TX_COMPWB
1942                 /* use the completion writeback registers */
1943                 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
1944                         CAS_VAL(TX_COMPWB_LSB, compwb);
1945                 compwb = TX_COMPWB_NEXT(compwb);
1946 #else
1947                 limit = readl(cp->regs + REG_TX_COMPN(ring));
1948 #endif
1949                 if (cp->tx_old[ring] != limit)
1950                         cas_tx_ringN(cp, ring, limit);
1951         }
1952 }
1953
1954
1955 static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
1956                               int entry, const u64 *words,
1957                               struct sk_buff **skbref)
1958 {
1959         int dlen, hlen, len, i, alloclen;
1960         int off, swivel = RX_SWIVEL_OFF_VAL;
1961         struct cas_page *page;
1962         struct sk_buff *skb;
1963         void *addr, *crcaddr;
1964         __sum16 csum;
1965         char *p;
1966
1967         hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
1968         dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
1969         len  = hlen + dlen;
1970
1971         if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT))
1972                 alloclen = len;
1973         else
1974                 alloclen = max(hlen, RX_COPY_MIN);
1975
1976         skb = dev_alloc_skb(alloclen + swivel + cp->crc_size);
1977         if (skb == NULL)
1978                 return -1;
1979
1980         *skbref = skb;
1981         skb_reserve(skb, swivel);
1982
1983         p = skb->data;
1984         addr = crcaddr = NULL;
1985         if (hlen) { /* always copy header pages */
1986                 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
1987                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
1988                 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 +
1989                         swivel;
1990
1991                 i = hlen;
1992                 if (!dlen) /* attach FCS */
1993                         i += cp->crc_size;
1994                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
1995                                     PCI_DMA_FROMDEVICE);
1996                 addr = cas_page_map(page->buffer);
1997                 memcpy(p, addr + off, i);
1998                 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
1999                                     PCI_DMA_FROMDEVICE);
2000                 cas_page_unmap(addr);
2001                 RX_USED_ADD(page, 0x100);
2002                 p += hlen;
2003                 swivel = 0;
2004         }
2005
2006
2007         if (alloclen < (hlen + dlen)) {
2008                 skb_frag_t *frag = skb_shinfo(skb)->frags;
2009
2010                 /* normal or jumbo packets. we use frags */
2011                 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2012                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2013                 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2014
2015                 hlen = min(cp->page_size - off, dlen);
2016                 if (hlen < 0) {
2017                         if (netif_msg_rx_err(cp)) {
2018                                 printk(KERN_DEBUG "%s: rx page overflow: "
2019                                        "%d\n", cp->dev->name, hlen);
2020                         }
2021                         dev_kfree_skb_irq(skb);
2022                         return -1;
2023                 }
2024                 i = hlen;
2025                 if (i == dlen)  /* attach FCS */
2026                         i += cp->crc_size;
2027                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2028                                     PCI_DMA_FROMDEVICE);
2029
2030                 /* make sure we always copy a header */
2031                 swivel = 0;
2032                 if (p == (char *) skb->data) { /* not split */
2033                         addr = cas_page_map(page->buffer);
2034                         memcpy(p, addr + off, RX_COPY_MIN);
2035                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2036                                         PCI_DMA_FROMDEVICE);
2037                         cas_page_unmap(addr);
2038                         off += RX_COPY_MIN;
2039                         swivel = RX_COPY_MIN;
2040                         RX_USED_ADD(page, cp->mtu_stride);
2041                 } else {
2042                         RX_USED_ADD(page, hlen);
2043                 }
2044                 skb_put(skb, alloclen);
2045
2046                 skb_shinfo(skb)->nr_frags++;
2047                 skb->data_len += hlen - swivel;
2048                 skb->truesize += hlen - swivel;
2049                 skb->len      += hlen - swivel;
2050
2051                 get_page(page->buffer);
2052                 frag->page = page->buffer;
2053                 frag->page_offset = off;
2054                 frag->size = hlen - swivel;
2055
2056                 /* any more data? */
2057                 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2058                         hlen = dlen;
2059                         off = 0;
2060
2061                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2062                         page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2063                         pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2064                                             hlen + cp->crc_size,
2065                                             PCI_DMA_FROMDEVICE);
2066                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2067                                             hlen + cp->crc_size,
2068                                             PCI_DMA_FROMDEVICE);
2069
2070                         skb_shinfo(skb)->nr_frags++;
2071                         skb->data_len += hlen;
2072                         skb->len      += hlen;
2073                         frag++;
2074
2075                         get_page(page->buffer);
2076                         frag->page = page->buffer;
2077                         frag->page_offset = 0;
2078                         frag->size = hlen;
2079                         RX_USED_ADD(page, hlen + cp->crc_size);
2080                 }
2081
2082                 if (cp->crc_size) {
2083                         addr = cas_page_map(page->buffer);
2084                         crcaddr  = addr + off + hlen;
2085                 }
2086
2087         } else {
2088                 /* copying packet */
2089                 if (!dlen)
2090                         goto end_copy_pkt;
2091
2092                 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2093                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2094                 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2095                 hlen = min(cp->page_size - off, dlen);
2096                 if (hlen < 0) {
2097                         if (netif_msg_rx_err(cp)) {
2098                                 printk(KERN_DEBUG "%s: rx page overflow: "
2099                                        "%d\n", cp->dev->name, hlen);
2100                         }
2101                         dev_kfree_skb_irq(skb);
2102                         return -1;
2103                 }
2104                 i = hlen;
2105                 if (i == dlen) /* attach FCS */
2106                         i += cp->crc_size;
2107                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2108                                     PCI_DMA_FROMDEVICE);
2109                 addr = cas_page_map(page->buffer);
2110                 memcpy(p, addr + off, i);
2111                 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2112                                     PCI_DMA_FROMDEVICE);
2113                 cas_page_unmap(addr);
2114                 if (p == (char *) skb->data) /* not split */
2115                         RX_USED_ADD(page, cp->mtu_stride);
2116                 else
2117                         RX_USED_ADD(page, i);
2118
2119                 /* any more data? */
2120                 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2121                         p += hlen;
2122                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2123                         page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2124                         pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2125                                             dlen + cp->crc_size,
2126                                             PCI_DMA_FROMDEVICE);
2127                         addr = cas_page_map(page->buffer);
2128                         memcpy(p, addr, dlen + cp->crc_size);
2129                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2130                                             dlen + cp->crc_size,
2131                                             PCI_DMA_FROMDEVICE);
2132                         cas_page_unmap(addr);
2133                         RX_USED_ADD(page, dlen + cp->crc_size);
2134                 }
2135 end_copy_pkt:
2136                 if (cp->crc_size) {
2137                         addr    = NULL;
2138                         crcaddr = skb->data + alloclen;
2139                 }
2140                 skb_put(skb, alloclen);
2141         }
2142
2143         csum = (__force __sum16)htons(CAS_VAL(RX_COMP4_TCP_CSUM, words[3]));
2144         if (cp->crc_size) {
2145                 /* checksum includes FCS. strip it out. */
2146                 csum = csum_fold(csum_partial(crcaddr, cp->crc_size,
2147                                               csum_unfold(csum)));
2148                 if (addr)
2149                         cas_page_unmap(addr);
2150         }
2151         skb->protocol = eth_type_trans(skb, cp->dev);
2152         if (skb->protocol == htons(ETH_P_IP)) {
2153                 skb->csum = csum_unfold(~csum);
2154                 skb->ip_summed = CHECKSUM_COMPLETE;
2155         } else
2156                 skb->ip_summed = CHECKSUM_NONE;
2157         return len;
2158 }
2159
2160
2161 /* we can handle up to 64 rx flows at a time. we do the same thing
2162  * as nonreassm except that we batch up the buffers.
2163  * NOTE: we currently just treat each flow as a bunch of packets that
2164  *       we pass up. a better way would be to coalesce the packets
2165  *       into a jumbo packet. to do that, we need to do the following:
2166  *       1) the first packet will have a clean split between header and
2167  *          data. save both.
2168  *       2) each time the next flow packet comes in, extend the
2169  *          data length and merge the checksums.
2170  *       3) on flow release, fix up the header.
2171  *       4) make sure the higher layer doesn't care.
2172  * because packets get coalesced, we shouldn't run into fragment count
2173  * issues.
2174  */
2175 static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
2176                                    struct sk_buff *skb)
2177 {
2178         int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
2179         struct sk_buff_head *flow = &cp->rx_flows[flowid];
2180
2181         /* this is protected at a higher layer, so no need to
2182          * do any additional locking here. stick the buffer
2183          * at the end.
2184          */
2185         __skb_insert(skb, flow->prev, (struct sk_buff *) flow, flow);
2186         if (words[0] & RX_COMP1_RELEASE_FLOW) {
2187                 while ((skb = __skb_dequeue(flow))) {
2188                         cas_skb_release(skb);
2189                 }
2190         }
2191 }
2192
2193 /* put rx descriptor back on ring. if a buffer is in use by a higher
2194  * layer, this will need to put in a replacement.
2195  */
2196 static void cas_post_page(struct cas *cp, const int ring, const int index)
2197 {
2198         cas_page_t *new;
2199         int entry;
2200
2201         entry = cp->rx_old[ring];
2202
2203         new = cas_page_swap(cp, ring, index);
2204         cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
2205         cp->init_rxds[ring][entry].index  =
2206                 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
2207                             CAS_BASE(RX_INDEX_RING, ring));
2208
2209         entry = RX_DESC_ENTRY(ring, entry + 1);
2210         cp->rx_old[ring] = entry;
2211
2212         if (entry % 4)
2213                 return;
2214
2215         if (ring == 0)
2216                 writel(entry, cp->regs + REG_RX_KICK);
2217         else if ((N_RX_DESC_RINGS > 1) &&
2218                  (cp->cas_flags & CAS_FLAG_REG_PLUS))
2219                 writel(entry, cp->regs + REG_PLUS_RX_KICK1);
2220 }
2221
2222
2223 /* only when things are bad */
2224 static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
2225 {
2226         unsigned int entry, last, count, released;
2227         int cluster;
2228         cas_page_t **page = cp->rx_pages[ring];
2229
2230         entry = cp->rx_old[ring];
2231
2232         if (netif_msg_intr(cp))
2233                 printk(KERN_DEBUG "%s: rxd[%d] interrupt, done: %d\n",
2234                        cp->dev->name, ring, entry);
2235
2236         cluster = -1;
2237         count = entry & 0x3;
2238         last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
2239         released = 0;
2240         while (entry != last) {
2241                 /* make a new buffer if it's still in use */
2242                 if (page_count(page[entry]->buffer) > 1) {
2243                         cas_page_t *new = cas_page_dequeue(cp);
2244                         if (!new) {
2245                                 /* let the timer know that we need to
2246                                  * do this again
2247                                  */
2248                                 cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
2249                                 if (!timer_pending(&cp->link_timer))
2250                                         mod_timer(&cp->link_timer, jiffies +
2251                                                   CAS_LINK_FAST_TIMEOUT);
2252                                 cp->rx_old[ring]  = entry;
2253                                 cp->rx_last[ring] = num ? num - released : 0;
2254                                 return -ENOMEM;
2255                         }
2256                         spin_lock(&cp->rx_inuse_lock);
2257                         list_add(&page[entry]->list, &cp->rx_inuse_list);
2258                         spin_unlock(&cp->rx_inuse_lock);
2259                         cp->init_rxds[ring][entry].buffer =
2260                                 cpu_to_le64(new->dma_addr);
2261                         page[entry] = new;
2262
2263                 }
2264
2265                 if (++count == 4) {
2266                         cluster = entry;
2267                         count = 0;
2268                 }
2269                 released++;
2270                 entry = RX_DESC_ENTRY(ring, entry + 1);
2271         }
2272         cp->rx_old[ring] = entry;
2273
2274         if (cluster < 0)
2275                 return 0;
2276
2277         if (ring == 0)
2278                 writel(cluster, cp->regs + REG_RX_KICK);
2279         else if ((N_RX_DESC_RINGS > 1) &&
2280                  (cp->cas_flags & CAS_FLAG_REG_PLUS))
2281                 writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
2282         return 0;
2283 }
2284
2285
2286 /* process a completion ring. packets are set up in three basic ways:
2287  * small packets: should be copied header + data in single buffer.
2288  * large packets: header and data in a single buffer.
2289  * split packets: header in a separate buffer from data.
2290  *                data may be in multiple pages. data may be > 256
2291  *                bytes but in a single page.
2292  *
2293  * NOTE: RX page posting is done in this routine as well. while there's
2294  *       the capability of using multiple RX completion rings, it isn't
2295  *       really worthwhile due to the fact that the page posting will
2296  *       force serialization on the single descriptor ring.
2297  */
2298 static int cas_rx_ringN(struct cas *cp, int ring, int budget)
2299 {
2300         struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
2301         int entry, drops;
2302         int npackets = 0;
2303
2304         if (netif_msg_intr(cp))
2305                 printk(KERN_DEBUG "%s: rx[%d] interrupt, done: %d/%d\n",
2306                        cp->dev->name, ring,
2307                        readl(cp->regs + REG_RX_COMP_HEAD),
2308                        cp->rx_new[ring]);
2309
2310         entry = cp->rx_new[ring];
2311         drops = 0;
2312         while (1) {
2313                 struct cas_rx_comp *rxc = rxcs + entry;
2314                 struct sk_buff *skb;
2315                 int type, len;
2316                 u64 words[4];
2317                 int i, dring;
2318
2319                 words[0] = le64_to_cpu(rxc->word1);
2320                 words[1] = le64_to_cpu(rxc->word2);
2321                 words[2] = le64_to_cpu(rxc->word3);
2322                 words[3] = le64_to_cpu(rxc->word4);
2323
2324                 /* don't touch if still owned by hw */
2325                 type = CAS_VAL(RX_COMP1_TYPE, words[0]);
2326                 if (type == 0)
2327                         break;
2328
2329                 /* hw hasn't cleared the zero bit yet */
2330                 if (words[3] & RX_COMP4_ZERO) {
2331                         break;
2332                 }
2333
2334                 /* get info on the packet */
2335                 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
2336                         spin_lock(&cp->stat_lock[ring]);
2337                         cp->net_stats[ring].rx_errors++;
2338                         if (words[3] & RX_COMP4_LEN_MISMATCH)
2339                                 cp->net_stats[ring].rx_length_errors++;
2340                         if (words[3] & RX_COMP4_BAD)
2341                                 cp->net_stats[ring].rx_crc_errors++;
2342                         spin_unlock(&cp->stat_lock[ring]);
2343
2344                         /* We'll just return it to Cassini. */
2345                 drop_it:
2346                         spin_lock(&cp->stat_lock[ring]);
2347                         ++cp->net_stats[ring].rx_dropped;
2348                         spin_unlock(&cp->stat_lock[ring]);
2349                         goto next;
2350                 }
2351
2352                 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
2353                 if (len < 0) {
2354                         ++drops;
2355                         goto drop_it;
2356                 }
2357
2358                 /* see if it's a flow re-assembly or not. the driver
2359                  * itself handles release back up.
2360                  */
2361                 if (RX_DONT_BATCH || (type == 0x2)) {
2362                         /* non-reassm: these always get released */
2363                         cas_skb_release(skb);
2364                 } else {
2365                         cas_rx_flow_pkt(cp, words, skb);
2366                 }
2367
2368                 spin_lock(&cp->stat_lock[ring]);
2369                 cp->net_stats[ring].rx_packets++;
2370                 cp->net_stats[ring].rx_bytes += len;
2371                 spin_unlock(&cp->stat_lock[ring]);
2372                 cp->dev->last_rx = jiffies;
2373
2374         next:
2375                 npackets++;
2376
2377                 /* should it be released? */
2378                 if (words[0] & RX_COMP1_RELEASE_HDR) {
2379                         i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2380                         dring = CAS_VAL(RX_INDEX_RING, i);
2381                         i = CAS_VAL(RX_INDEX_NUM, i);
2382                         cas_post_page(cp, dring, i);
2383                 }
2384
2385                 if (words[0] & RX_COMP1_RELEASE_DATA) {
2386                         i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2387                         dring = CAS_VAL(RX_INDEX_RING, i);
2388                         i = CAS_VAL(RX_INDEX_NUM, i);
2389                         cas_post_page(cp, dring, i);
2390                 }
2391
2392                 if (words[0] & RX_COMP1_RELEASE_NEXT) {
2393                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2394                         dring = CAS_VAL(RX_INDEX_RING, i);
2395                         i = CAS_VAL(RX_INDEX_NUM, i);
2396                         cas_post_page(cp, dring, i);
2397                 }
2398
2399                 /* skip to the next entry */
2400                 entry = RX_COMP_ENTRY(ring, entry + 1 +
2401                                       CAS_VAL(RX_COMP1_SKIP, words[0]));
2402 #ifdef USE_NAPI
2403                 if (budget && (npackets >= budget))
2404                         break;
2405 #endif
2406         }
2407         cp->rx_new[ring] = entry;
2408
2409         if (drops)
2410                 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
2411                        cp->dev->name);
2412         return npackets;
2413 }
2414
2415
2416 /* put completion entries back on the ring */
2417 static void cas_post_rxcs_ringN(struct net_device *dev,
2418                                 struct cas *cp, int ring)
2419 {
2420         struct cas_rx_comp *rxc = cp->init_rxcs[ring];
2421         int last, entry;
2422
2423         last = cp->rx_cur[ring];
2424         entry = cp->rx_new[ring];
2425         if (netif_msg_intr(cp))
2426                 printk(KERN_DEBUG "%s: rxc[%d] interrupt, done: %d/%d\n",
2427                        dev->name, ring, readl(cp->regs + REG_RX_COMP_HEAD),
2428                        entry);
2429
2430         /* zero and re-mark descriptors */
2431         while (last != entry) {
2432                 cas_rxc_init(rxc + last);
2433                 last = RX_COMP_ENTRY(ring, last + 1);
2434         }
2435         cp->rx_cur[ring] = last;
2436
2437         if (ring == 0)
2438                 writel(last, cp->regs + REG_RX_COMP_TAIL);
2439         else if (cp->cas_flags & CAS_FLAG_REG_PLUS)
2440                 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
2441 }
2442
2443
2444
2445 /* cassini can use all four PCI interrupts for the completion ring.
2446  * rings 3 and 4 are identical
2447  */
2448 #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2449 static inline void cas_handle_irqN(struct net_device *dev,
2450                                    struct cas *cp, const u32 status,
2451                                    const int ring)
2452 {
2453         if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT))
2454                 cas_post_rxcs_ringN(dev, cp, ring);
2455 }
2456
2457 static irqreturn_t cas_interruptN(int irq, void *dev_id)
2458 {
2459         struct net_device *dev = dev_id;
2460         struct cas *cp = netdev_priv(dev);
2461         unsigned long flags;
2462         int ring;
2463         u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
2464
2465         /* check for shared irq */
2466         if (status == 0)
2467                 return IRQ_NONE;
2468
2469         ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
2470         spin_lock_irqsave(&cp->lock, flags);
2471         if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2472 #ifdef USE_NAPI
2473                 cas_mask_intr(cp);
2474                 netif_rx_schedule(dev, &cp->napi);
2475 #else
2476                 cas_rx_ringN(cp, ring, 0);
2477 #endif
2478                 status &= ~INTR_RX_DONE_ALT;
2479         }
2480
2481         if (status)
2482                 cas_handle_irqN(dev, cp, status, ring);
2483         spin_unlock_irqrestore(&cp->lock, flags);
2484         return IRQ_HANDLED;
2485 }
2486 #endif
2487
2488 #ifdef USE_PCI_INTB
2489 /* everything but rx packets */
2490 static inline void cas_handle_irq1(struct cas *cp, const u32 status)
2491 {
2492         if (status & INTR_RX_BUF_UNAVAIL_1) {
2493                 /* Frame arrived, no free RX buffers available.
2494                  * NOTE: we can get this on a link transition. */
2495                 cas_post_rxds_ringN(cp, 1, 0);
2496                 spin_lock(&cp->stat_lock[1]);
2497                 cp->net_stats[1].rx_dropped++;
2498                 spin_unlock(&cp->stat_lock[1]);
2499         }
2500
2501         if (status & INTR_RX_BUF_AE_1)
2502                 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) -
2503                                     RX_AE_FREEN_VAL(1));
2504
2505         if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2506                 cas_post_rxcs_ringN(cp, 1);
2507 }
2508
2509 /* ring 2 handles a few more events than 3 and 4 */
2510 static irqreturn_t cas_interrupt1(int irq, void *dev_id)
2511 {
2512         struct net_device *dev = dev_id;
2513         struct cas *cp = netdev_priv(dev);
2514         unsigned long flags;
2515         u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2516
2517         /* check for shared interrupt */
2518         if (status == 0)
2519                 return IRQ_NONE;
2520
2521         spin_lock_irqsave(&cp->lock, flags);
2522         if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2523 #ifdef USE_NAPI
2524                 cas_mask_intr(cp);
2525                 netif_rx_schedule(dev, &cp->napi);
2526 #else
2527                 cas_rx_ringN(cp, 1, 0);
2528 #endif
2529                 status &= ~INTR_RX_DONE_ALT;
2530         }
2531         if (status)
2532                 cas_handle_irq1(cp, status);
2533         spin_unlock_irqrestore(&cp->lock, flags);
2534         return IRQ_HANDLED;
2535 }
2536 #endif
2537
2538 static inline void cas_handle_irq(struct net_device *dev,
2539                                   struct cas *cp, const u32 status)
2540 {
2541         /* housekeeping interrupts */
2542         if (status & INTR_ERROR_MASK)
2543                 cas_abnormal_irq(dev, cp, status);
2544
2545         if (status & INTR_RX_BUF_UNAVAIL) {
2546                 /* Frame arrived, no free RX buffers available.
2547                  * NOTE: we can get this on a link transition.
2548                  */
2549                 cas_post_rxds_ringN(cp, 0, 0);
2550                 spin_lock(&cp->stat_lock[0]);
2551                 cp->net_stats[0].rx_dropped++;
2552                 spin_unlock(&cp->stat_lock[0]);
2553         } else if (status & INTR_RX_BUF_AE) {
2554                 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
2555                                     RX_AE_FREEN_VAL(0));
2556         }
2557
2558         if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2559                 cas_post_rxcs_ringN(dev, cp, 0);
2560 }
2561
2562 static irqreturn_t cas_interrupt(int irq, void *dev_id)
2563 {
2564         struct net_device *dev = dev_id;
2565         struct cas *cp = netdev_priv(dev);
2566         unsigned long flags;
2567         u32 status = readl(cp->regs + REG_INTR_STATUS);
2568
2569         if (status == 0)
2570                 return IRQ_NONE;
2571
2572         spin_lock_irqsave(&cp->lock, flags);
2573         if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
2574                 cas_tx(dev, cp, status);
2575                 status &= ~(INTR_TX_ALL | INTR_TX_INTME);
2576         }
2577
2578         if (status & INTR_RX_DONE) {
2579 #ifdef USE_NAPI
2580                 cas_mask_intr(cp);
2581                 netif_rx_schedule(dev, &cp->napi);
2582 #else
2583                 cas_rx_ringN(cp, 0, 0);
2584 #endif
2585                 status &= ~INTR_RX_DONE;
2586         }
2587
2588         if (status)
2589                 cas_handle_irq(dev, cp, status);
2590         spin_unlock_irqrestore(&cp->lock, flags);
2591         return IRQ_HANDLED;
2592 }
2593
2594
2595 #ifdef USE_NAPI
2596 static int cas_poll(struct napi_struct *napi, int budget)
2597 {
2598         struct cas *cp = container_of(napi, struct cas, napi);
2599         struct net_device *dev = cp->dev;
2600         int i, enable_intr, credits;
2601         u32 status = readl(cp->regs + REG_INTR_STATUS);
2602         unsigned long flags;
2603
2604         spin_lock_irqsave(&cp->lock, flags);
2605         cas_tx(dev, cp, status);
2606         spin_unlock_irqrestore(&cp->lock, flags);
2607
2608         /* NAPI rx packets. we spread the credits across all of the
2609          * rxc rings
2610          *
2611          * to make sure we're fair with the work we loop through each
2612          * ring N_RX_COMP_RING times with a request of
2613          * budget / N_RX_COMP_RINGS
2614          */
2615         enable_intr = 1;
2616         credits = 0;
2617         for (i = 0; i < N_RX_COMP_RINGS; i++) {
2618                 int j;
2619                 for (j = 0; j < N_RX_COMP_RINGS; j++) {
2620                         credits += cas_rx_ringN(cp, j, budget / N_RX_COMP_RINGS);
2621                         if (credits >= budget) {
2622                                 enable_intr = 0;
2623                                 goto rx_comp;
2624                         }
2625                 }
2626         }
2627
2628 rx_comp:
2629         /* final rx completion */
2630         spin_lock_irqsave(&cp->lock, flags);
2631         if (status)
2632                 cas_handle_irq(dev, cp, status);
2633
2634 #ifdef USE_PCI_INTB
2635         if (N_RX_COMP_RINGS > 1) {
2636                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2637                 if (status)
2638                         cas_handle_irq1(dev, cp, status);
2639         }
2640 #endif
2641
2642 #ifdef USE_PCI_INTC
2643         if (N_RX_COMP_RINGS > 2) {
2644                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
2645                 if (status)
2646                         cas_handle_irqN(dev, cp, status, 2);
2647         }
2648 #endif
2649
2650 #ifdef USE_PCI_INTD
2651         if (N_RX_COMP_RINGS > 3) {
2652                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
2653                 if (status)
2654                         cas_handle_irqN(dev, cp, status, 3);
2655         }
2656 #endif
2657         spin_unlock_irqrestore(&cp->lock, flags);
2658         if (enable_intr) {
2659                 netif_rx_complete(dev, napi);
2660                 cas_unmask_intr(cp);
2661         }
2662         return credits;
2663 }
2664 #endif
2665
2666 #ifdef CONFIG_NET_POLL_CONTROLLER
2667 static void cas_netpoll(struct net_device *dev)
2668 {
2669         struct cas *cp = netdev_priv(dev);
2670
2671         cas_disable_irq(cp, 0);
2672         cas_interrupt(cp->pdev->irq, dev);
2673         cas_enable_irq(cp, 0);
2674
2675 #ifdef USE_PCI_INTB
2676         if (N_RX_COMP_RINGS > 1) {
2677                 /* cas_interrupt1(); */
2678         }
2679 #endif
2680 #ifdef USE_PCI_INTC
2681         if (N_RX_COMP_RINGS > 2) {
2682                 /* cas_interruptN(); */
2683         }
2684 #endif
2685 #ifdef USE_PCI_INTD
2686         if (N_RX_COMP_RINGS > 3) {
2687                 /* cas_interruptN(); */
2688         }
2689 #endif
2690 }
2691 #endif
2692
2693 static void cas_tx_timeout(struct net_device *dev)
2694 {
2695         struct cas *cp = netdev_priv(dev);
2696
2697         printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2698         if (!cp->hw_running) {
2699                 printk("%s: hrm.. hw not running!\n", dev->name);
2700                 return;
2701         }
2702
2703         printk(KERN_ERR "%s: MIF_STATE[%08x]\n",
2704                dev->name, readl(cp->regs + REG_MIF_STATE_MACHINE));
2705
2706         printk(KERN_ERR "%s: MAC_STATE[%08x]\n",
2707                dev->name, readl(cp->regs + REG_MAC_STATE_MACHINE));
2708
2709         printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x] "
2710                "FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2711                dev->name,
2712                readl(cp->regs + REG_TX_CFG),
2713                readl(cp->regs + REG_MAC_TX_STATUS),
2714                readl(cp->regs + REG_MAC_TX_CFG),
2715                readl(cp->regs + REG_TX_FIFO_PKT_CNT),
2716                readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
2717                readl(cp->regs + REG_TX_FIFO_READ_PTR),
2718                readl(cp->regs + REG_TX_SM_1),
2719                readl(cp->regs + REG_TX_SM_2));
2720
2721         printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
2722                dev->name,
2723                readl(cp->regs + REG_RX_CFG),
2724                readl(cp->regs + REG_MAC_RX_STATUS),
2725                readl(cp->regs + REG_MAC_RX_CFG));
2726
2727         printk(KERN_ERR "%s: HP_STATE[%08x:%08x:%08x:%08x]\n",
2728                dev->name,
2729                readl(cp->regs + REG_HP_STATE_MACHINE),
2730                readl(cp->regs + REG_HP_STATUS0),
2731                readl(cp->regs + REG_HP_STATUS1),
2732                readl(cp->regs + REG_HP_STATUS2));
2733
2734 #if 1
2735         atomic_inc(&cp->reset_task_pending);
2736         atomic_inc(&cp->reset_task_pending_all);
2737         schedule_work(&cp->reset_task);
2738 #else
2739         atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
2740         schedule_work(&cp->reset_task);
2741 #endif
2742 }
2743
2744 static inline int cas_intme(int ring, int entry)
2745 {
2746         /* Algorithm: IRQ every 1/2 of descriptors. */
2747         if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
2748                 return 1;
2749         return 0;
2750 }
2751
2752
2753 static void cas_write_txd(struct cas *cp, int ring, int entry,
2754                           dma_addr_t mapping, int len, u64 ctrl, int last)
2755 {
2756         struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
2757
2758         ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
2759         if (cas_intme(ring, entry))
2760                 ctrl |= TX_DESC_INTME;
2761         if (last)
2762                 ctrl |= TX_DESC_EOF;
2763         txd->control = cpu_to_le64(ctrl);
2764         txd->buffer = cpu_to_le64(mapping);
2765 }
2766
2767 static inline void *tx_tiny_buf(struct cas *cp, const int ring,
2768                                 const int entry)
2769 {
2770         return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
2771 }
2772
2773 static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring,
2774                                      const int entry, const int tentry)
2775 {
2776         cp->tx_tiny_use[ring][tentry].nbufs++;
2777         cp->tx_tiny_use[ring][entry].used = 1;
2778         return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
2779 }
2780
2781 static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
2782                                     struct sk_buff *skb)
2783 {
2784         struct net_device *dev = cp->dev;
2785         int entry, nr_frags, frag, tabort, tentry;
2786         dma_addr_t mapping;
2787         unsigned long flags;
2788         u64 ctrl;
2789         u32 len;
2790
2791         spin_lock_irqsave(&cp->tx_lock[ring], flags);
2792
2793         /* This is a hard error, log it. */
2794         if (TX_BUFFS_AVAIL(cp, ring) <=
2795             CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
2796                 netif_stop_queue(dev);
2797                 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2798                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
2799                        "queue awake!\n", dev->name);
2800                 return 1;
2801         }
2802
2803         ctrl = 0;
2804         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2805                 const u64 csum_start_off = skb_transport_offset(skb);
2806                 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
2807
2808                 ctrl =  TX_DESC_CSUM_EN |
2809                         CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
2810                         CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
2811         }
2812
2813         entry = cp->tx_new[ring];
2814         cp->tx_skbs[ring][entry] = skb;
2815
2816         nr_frags = skb_shinfo(skb)->nr_frags;
2817         len = skb_headlen(skb);
2818         mapping = pci_map_page(cp->pdev, virt_to_page(skb->data),
2819                                offset_in_page(skb->data), len,
2820                                PCI_DMA_TODEVICE);
2821
2822         tentry = entry;
2823         tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
2824         if (unlikely(tabort)) {
2825                 /* NOTE: len is always >  tabort */
2826                 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2827                               ctrl | TX_DESC_SOF, 0);
2828                 entry = TX_DESC_NEXT(ring, entry);
2829
2830                 skb_copy_from_linear_data_offset(skb, len - tabort,
2831                               tx_tiny_buf(cp, ring, entry), tabort);
2832                 mapping = tx_tiny_map(cp, ring, entry, tentry);
2833                 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
2834                               (nr_frags == 0));
2835         } else {
2836                 cas_write_txd(cp, ring, entry, mapping, len, ctrl |
2837                               TX_DESC_SOF, (nr_frags == 0));
2838         }
2839         entry = TX_DESC_NEXT(ring, entry);
2840
2841         for (frag = 0; frag < nr_frags; frag++) {
2842                 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
2843
2844                 len = fragp->size;
2845                 mapping = pci_map_page(cp->pdev, fragp->page,
2846                                        fragp->page_offset, len,
2847                                        PCI_DMA_TODEVICE);
2848
2849                 tabort = cas_calc_tabort(cp, fragp->page_offset, len);
2850                 if (unlikely(tabort)) {
2851                         void *addr;
2852
2853                         /* NOTE: len is always > tabort */
2854                         cas_write_txd(cp, ring, entry, mapping, len - tabort,
2855                                       ctrl, 0);
2856                         entry = TX_DESC_NEXT(ring, entry);
2857
2858                         addr = cas_page_map(fragp->page);
2859                         memcpy(tx_tiny_buf(cp, ring, entry),
2860                                addr + fragp->page_offset + len - tabort,
2861                                tabort);
2862                         cas_page_unmap(addr);
2863                         mapping = tx_tiny_map(cp, ring, entry, tentry);
2864                         len     = tabort;
2865                 }
2866
2867                 cas_write_txd(cp, ring, entry, mapping, len, ctrl,
2868                               (frag + 1 == nr_frags));
2869                 entry = TX_DESC_NEXT(ring, entry);
2870         }
2871
2872         cp->tx_new[ring] = entry;
2873         if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
2874                 netif_stop_queue(dev);
2875
2876         if (netif_msg_tx_queued(cp))
2877                 printk(KERN_DEBUG "%s: tx[%d] queued, slot %d, skblen %d, "
2878                        "avail %d\n",
2879                        dev->name, ring, entry, skb->len,
2880                        TX_BUFFS_AVAIL(cp, ring));
2881         writel(entry, cp->regs + REG_TX_KICKN(ring));
2882         spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2883         return 0;
2884 }
2885
2886 static int cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
2887 {
2888         struct cas *cp = netdev_priv(dev);
2889
2890         /* this is only used as a load-balancing hint, so it doesn't
2891          * need to be SMP safe
2892          */
2893         static int ring;
2894
2895         if (skb_padto(skb, cp->min_frame_size))
2896                 return 0;
2897
2898         /* XXX: we need some higher-level QoS hooks to steer packets to
2899          *      individual queues.
2900          */
2901         if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
2902                 return 1;
2903         dev->trans_start = jiffies;
2904         return 0;
2905 }
2906
2907 static void cas_init_tx_dma(struct cas *cp)
2908 {
2909         u64 desc_dma = cp->block_dvma;
2910         unsigned long off;
2911         u32 val;
2912         int i;
2913
2914         /* set up tx completion writeback registers. must be 8-byte aligned */
2915 #ifdef USE_TX_COMPWB
2916         off = offsetof(struct cas_init_block, tx_compwb);
2917         writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
2918         writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
2919 #endif
2920
2921         /* enable completion writebacks, enable paced mode,
2922          * disable read pipe, and disable pre-interrupt compwbs
2923          */
2924         val =   TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
2925                 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
2926                 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |
2927                 TX_CFG_INTR_COMPWB_DIS;
2928
2929         /* write out tx ring info and tx desc bases */
2930         for (i = 0; i < MAX_TX_RINGS; i++) {
2931                 off = (unsigned long) cp->init_txds[i] -
2932                         (unsigned long) cp->init_block;
2933
2934                 val |= CAS_TX_RINGN_BASE(i);
2935                 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
2936                 writel((desc_dma + off) & 0xffffffff, cp->regs +
2937                        REG_TX_DBN_LOW(i));
2938                 /* don't zero out the kick register here as the system
2939                  * will wedge
2940                  */
2941         }
2942         writel(val, cp->regs + REG_TX_CFG);
2943
2944         /* program max burst sizes. these numbers should be different
2945          * if doing QoS.
2946          */
2947 #ifdef USE_QOS
2948         writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2949         writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
2950         writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
2951         writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
2952 #else
2953         writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2954         writel(0x800, cp->regs + REG_TX_MAXBURST_1);
2955         writel(0x800, cp->regs + REG_TX_MAXBURST_2);
2956         writel(0x800, cp->regs + REG_TX_MAXBURST_3);
2957 #endif
2958 }
2959
2960 /* Must be invoked under cp->lock. */
2961 static inline void cas_init_dma(struct cas *cp)
2962 {
2963         cas_init_tx_dma(cp);
2964         cas_init_rx_dma(cp);
2965 }
2966
2967 /* Must be invoked under cp->lock. */
2968 static u32 cas_setup_multicast(struct cas *cp)
2969 {
2970         u32 rxcfg = 0;
2971         int i;
2972
2973         if (cp->dev->flags & IFF_PROMISC) {
2974                 rxcfg |= MAC_RX_CFG_PROMISC_EN;
2975
2976         } else if (cp->dev->flags & IFF_ALLMULTI) {
2977                 for (i=0; i < 16; i++)
2978                         writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
2979                 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2980
2981         } else {
2982                 u16 hash_table[16];
2983                 u32 crc;
2984                 struct dev_mc_list *dmi = cp->dev->mc_list;
2985                 int i;
2986
2987                 /* use the alternate mac address registers for the
2988                  * first 15 multicast addresses
2989                  */
2990                 for (i = 1; i <= CAS_MC_EXACT_MATCH_SIZE; i++) {
2991                         if (!dmi) {
2992                                 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 0));
2993                                 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 1));
2994                                 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 2));
2995                                 continue;
2996                         }
2997                         writel((dmi->dmi_addr[4] << 8) | dmi->dmi_addr[5],
2998                                cp->regs + REG_MAC_ADDRN(i*3 + 0));
2999                         writel((dmi->dmi_addr[2] << 8) | dmi->dmi_addr[3],
3000                                cp->regs + REG_MAC_ADDRN(i*3 + 1));
3001                         writel((dmi->dmi_addr[0] << 8) | dmi->dmi_addr[1],
3002                                cp->regs + REG_MAC_ADDRN(i*3 + 2));
3003                         dmi = dmi->next;
3004                 }
3005
3006                 /* use hw hash table for the next series of
3007                  * multicast addresses
3008                  */
3009                 memset(hash_table, 0, sizeof(hash_table));
3010                 while (dmi) {
3011                         crc = ether_crc_le(ETH_ALEN, dmi->dmi_addr);
3012                         crc >>= 24;
3013                         hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
3014                         dmi = dmi->next;
3015                 }
3016                 for (i=0; i < 16; i++)
3017                         writel(hash_table[i], cp->regs +
3018                                REG_MAC_HASH_TABLEN(i));
3019                 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
3020         }
3021
3022         return rxcfg;
3023 }
3024
3025 /* must be invoked under cp->stat_lock[N_TX_RINGS] */
3026 static void cas_clear_mac_err(struct cas *cp)
3027 {
3028         writel(0, cp->regs + REG_MAC_COLL_NORMAL);
3029         writel(0, cp->regs + REG_MAC_COLL_FIRST);
3030         writel(0, cp->regs + REG_MAC_COLL_EXCESS);
3031         writel(0, cp->regs + REG_MAC_COLL_LATE);
3032         writel(0, cp->regs + REG_MAC_TIMER_DEFER);
3033         writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
3034         writel(0, cp->regs + REG_MAC_RECV_FRAME);
3035         writel(0, cp->regs + REG_MAC_LEN_ERR);
3036         writel(0, cp->regs + REG_MAC_ALIGN_ERR);
3037         writel(0, cp->regs + REG_MAC_FCS_ERR);
3038         writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
3039 }
3040
3041
3042 static void cas_mac_reset(struct cas *cp)
3043 {
3044         int i;
3045
3046         /* do both TX and RX reset */
3047         writel(0x1, cp->regs + REG_MAC_TX_RESET);
3048         writel(0x1, cp->regs + REG_MAC_RX_RESET);
3049
3050         /* wait for TX */
3051         i = STOP_TRIES;
3052         while (i-- > 0) {
3053                 if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
3054                         break;
3055                 udelay(10);
3056         }
3057
3058         /* wait for RX */
3059         i = STOP_TRIES;
3060         while (i-- > 0) {
3061                 if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
3062                         break;
3063                 udelay(10);
3064         }
3065
3066         if (readl(cp->regs + REG_MAC_TX_RESET) |
3067             readl(cp->regs + REG_MAC_RX_RESET))
3068                 printk(KERN_ERR "%s: mac tx[%d]/rx[%d] reset failed [%08x]\n",
3069                        cp->dev->name, readl(cp->regs + REG_MAC_TX_RESET),
3070                        readl(cp->regs + REG_MAC_RX_RESET),
3071                        readl(cp->regs + REG_MAC_STATE_MACHINE));
3072 }
3073
3074
3075 /* Must be invoked under cp->lock. */
3076 static void cas_init_mac(struct cas *cp)
3077 {
3078         unsigned char *e = &cp->dev->dev_addr[0];
3079         int i;
3080 #ifdef CONFIG_CASSINI_MULTICAST_REG_WRITE
3081         u32 rxcfg;
3082 #endif
3083         cas_mac_reset(cp);
3084
3085         /* setup core arbitration weight register */
3086         writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
3087
3088         /* XXX Use pci_dma_burst_advice() */
3089 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3090         /* set the infinite burst register for chips that don't have
3091          * pci issues.
3092          */
3093         if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
3094                 writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
3095 #endif
3096
3097         writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
3098
3099         writel(0x00, cp->regs + REG_MAC_IPG0);
3100         writel(0x08, cp->regs + REG_MAC_IPG1);
3101         writel(0x04, cp->regs + REG_MAC_IPG2);
3102
3103         /* change later for 802.3z */
3104         writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3105
3106         /* min frame + FCS */
3107         writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
3108
3109         /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
3110          * specify the maximum frame size to prevent RX tag errors on
3111          * oversized frames.
3112          */
3113         writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
3114                CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
3115                         (CAS_MAX_MTU + ETH_HLEN + 4 + 4)),
3116                cp->regs + REG_MAC_FRAMESIZE_MAX);
3117
3118         /* NOTE: crc_size is used as a surrogate for half-duplex.
3119          * workaround saturn half-duplex issue by increasing preamble
3120          * size to 65 bytes.
3121          */
3122         if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
3123                 writel(0x41, cp->regs + REG_MAC_PA_SIZE);
3124         else
3125                 writel(0x07, cp->regs + REG_MAC_PA_SIZE);
3126         writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
3127         writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
3128         writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
3129
3130         writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
3131
3132         writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
3133         writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
3134         writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
3135         writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
3136         writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
3137
3138         /* setup mac address in perfect filter array */
3139         for (i = 0; i < 45; i++)
3140                 writel(0x0, cp->regs + REG_MAC_ADDRN(i));
3141
3142         writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
3143         writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
3144         writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
3145
3146         writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
3147         writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
3148         writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
3149
3150 #ifndef CONFIG_CASSINI_MULTICAST_REG_WRITE
3151         cp->mac_rx_cfg = cas_setup_multicast(cp);
3152 #else
3153         /* WTZ: Do what Adrian did in cas_set_multicast. Doing
3154          * a writel does not seem to be necessary because Cassini
3155          * seems to preserve the configuration when we do the reset.
3156          * If the chip is in trouble, though, it is not clear if we
3157          * can really count on this behavior. cas_set_multicast uses
3158          * spin_lock_irqsave, but we are called only in cas_init_hw and
3159          * cas_init_hw is protected by cas_lock_all, which calls
3160          * spin_lock_irq (so it doesn't need to save the flags, and
3161          * we should be OK for the writel, as that is the only
3162          * difference).
3163          */
3164         cp->mac_rx_cfg = rxcfg = cas_setup_multicast(cp);
3165         writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
3166 #endif
3167         spin_lock(&cp->stat_lock[N_TX_RINGS]);
3168         cas_clear_mac_err(cp);
3169         spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3170
3171         /* Setup MAC interrupts.  We want to get all of the interesting
3172          * counter expiration events, but we do not want to hear about
3173          * normal rx/tx as the DMA engine tells us that.
3174          */
3175         writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
3176         writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
3177
3178         /* Don't enable even the PAUSE interrupts for now, we
3179          * make no use of those events other than to record them.
3180          */
3181         writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
3182 }
3183
3184 /* Must be invoked under cp->lock. */
3185 static void cas_init_pause_thresholds(struct cas *cp)
3186 {
3187         /* Calculate pause thresholds.  Setting the OFF threshold to the
3188          * full RX fifo size effectively disables PAUSE generation
3189          */
3190         if (cp->rx_fifo_size <= (2 * 1024)) {
3191                 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
3192         } else {
3193                 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
3194                 if (max_frame * 3 > cp->rx_fifo_size) {
3195                         cp->rx_pause_off = 7104;
3196                         cp->rx_pause_on  = 960;
3197                 } else {
3198                         int off = (cp->rx_fifo_size - (max_frame * 2));
3199                         int on = off - max_frame;
3200                         cp->rx_pause_off = off;
3201                         cp->rx_pause_on = on;
3202                 }
3203         }
3204 }
3205
3206 static int cas_vpd_match(const void __iomem *p, const char *str)
3207 {
3208         int len = strlen(str) + 1;
3209         int i;
3210
3211         for (i = 0; i < len; i++) {
3212                 if (readb(p + i) != str[i])
3213                         return 0;
3214         }
3215         return 1;
3216 }
3217
3218
3219 /* get the mac address by reading the vpd information in the rom.
3220  * also get the phy type and determine if there's an entropy generator.
3221  * NOTE: this is a bit convoluted for the following reasons:
3222  *  1) vpd info has order-dependent mac addresses for multinic cards
3223  *  2) the only way to determine the nic order is to use the slot
3224  *     number.
3225  *  3) fiber cards don't have bridges, so their slot numbers don't
3226  *     mean anything.
3227  *  4) we don't actually know we have a fiber card until after
3228  *     the mac addresses are parsed.
3229  */
3230 static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
3231                             const int offset)
3232 {
3233         void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
3234         void __iomem *base, *kstart;
3235         int i, len;
3236         int found = 0;
3237 #define VPD_FOUND_MAC        0x01
3238 #define VPD_FOUND_PHY        0x02
3239
3240         int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
3241         int mac_off  = 0;
3242
3243         /* give us access to the PROM */
3244         writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
3245                cp->regs + REG_BIM_LOCAL_DEV_EN);
3246
3247         /* check for an expansion rom */
3248         if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
3249                 goto use_random_mac_addr;
3250
3251         /* search for beginning of vpd */
3252         base = NULL;
3253         for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
3254                 /* check for PCIR */
3255                 if ((readb(p + i + 0) == 0x50) &&
3256                     (readb(p + i + 1) == 0x43) &&
3257                     (readb(p + i + 2) == 0x49) &&
3258                     (readb(p + i + 3) == 0x52)) {
3259                         base = p + (readb(p + i + 8) |
3260                                     (readb(p + i + 9) << 8));
3261                         break;
3262                 }
3263         }
3264
3265         if (!base || (readb(base) != 0x82))
3266                 goto use_random_mac_addr;
3267
3268         i = (readb(base + 1) | (readb(base + 2) << 8)) + 3;
3269         while (i < EXPANSION_ROM_SIZE) {
3270                 if (readb(base + i) != 0x90) /* no vpd found */
3271                         goto use_random_mac_addr;
3272
3273                 /* found a vpd field */
3274                 len = readb(base + i + 1) | (readb(base + i + 2) << 8);
3275
3276                 /* extract keywords */
3277                 kstart = base + i + 3;
3278                 p = kstart;
3279                 while ((p - kstart) < len) {
3280                         int klen = readb(p + 2);
3281                         int j;
3282                         char type;
3283
3284                         p += 3;
3285
3286                         /* look for the following things:
3287                          * -- correct length == 29
3288                          * 3 (type) + 2 (size) +
3289                          * 18 (strlen("local-mac-address") + 1) +
3290                          * 6 (mac addr)
3291                          * -- VPD Instance 'I'
3292                          * -- VPD Type Bytes 'B'
3293                          * -- VPD data length == 6
3294                          * -- property string == local-mac-address
3295                          *
3296                          * -- correct length == 24
3297                          * 3 (type) + 2 (size) +
3298                          * 12 (strlen("entropy-dev") + 1) +
3299                          * 7 (strlen("vms110") + 1)
3300                          * -- VPD Instance 'I'
3301                          * -- VPD Type String 'B'
3302                          * -- VPD data length == 7
3303                          * -- property string == entropy-dev
3304                          *
3305                          * -- correct length == 18
3306                          * 3 (type) + 2 (size) +
3307                          * 9 (strlen("phy-type") + 1) +
3308                          * 4 (strlen("pcs") + 1)
3309                          * -- VPD Instance 'I'
3310                          * -- VPD Type String 'S'
3311                          * -- VPD data length == 4
3312                          * -- property string == phy-type
3313                          *
3314                          * -- correct length == 23
3315                          * 3 (type) + 2 (size) +
3316                          * 14 (strlen("phy-interface") + 1) +
3317                          * 4 (strlen("pcs") + 1)
3318                          * -- VPD Instance 'I'
3319                          * -- VPD Type String 'S'
3320                          * -- VPD data length == 4
3321                          * -- property string == phy-interface
3322                          */
3323                         if (readb(p) != 'I')
3324                                 goto next;
3325
3326                         /* finally, check string and length */
3327                         type = readb(p + 3);
3328                         if (type == 'B') {
3329                                 if ((klen == 29) && readb(p + 4) == 6 &&
3330                                     cas_vpd_match(p + 5,
3331                                                   "local-mac-address")) {
3332                                         if (mac_off++ > offset)
3333                                                 goto next;
3334
3335                                         /* set mac address */
3336                                         for (j = 0; j < 6; j++)
3337                                                 dev_addr[j] =
3338                                                         readb(p + 23 + j);
3339                                         goto found_mac;
3340                                 }
3341                         }
3342
3343                         if (type != 'S')
3344                                 goto next;
3345
3346 #ifdef USE_ENTROPY_DEV
3347                         if ((klen == 24) &&
3348                             cas_vpd_match(p + 5, "entropy-dev") &&
3349                             cas_vpd_match(p + 17, "vms110")) {
3350                                 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV;
3351                                 goto next;
3352                         }
3353 #endif
3354
3355                         if (found & VPD_FOUND_PHY)
3356                                 goto next;
3357
3358                         if ((klen == 18) && readb(p + 4) == 4 &&
3359                             cas_vpd_match(p + 5, "phy-type")) {
3360                                 if (cas_vpd_match(p + 14, "pcs")) {
3361                                         phy_type = CAS_PHY_SERDES;
3362                                         goto found_phy;
3363                                 }
3364                         }
3365
3366                         if ((klen == 23) && readb(p + 4) == 4 &&
3367                             cas_vpd_match(p + 5, "phy-interface")) {
3368                                 if (cas_vpd_match(p + 19, "pcs")) {
3369                                         phy_type = CAS_PHY_SERDES;
3370                                         goto found_phy;
3371                                 }
3372                         }
3373 found_mac:
3374                         found |= VPD_FOUND_MAC;
3375                         goto next;
3376
3377 found_phy:
3378                         found |= VPD_FOUND_PHY;
3379
3380 next:
3381                         p += klen;
3382                 }
3383                 i += len + 3;
3384         }
3385
3386 use_random_mac_addr:
3387         if (found & VPD_FOUND_MAC)
3388                 goto done;
3389
3390         /* Sun MAC prefix then 3 random bytes. */
3391         printk(PFX "MAC address not found in ROM VPD\n");
3392         dev_addr[0] = 0x08;
3393         dev_addr[1] = 0x00;
3394         dev_addr[2] = 0x20;
3395         get_random_bytes(dev_addr + 3, 3);
3396
3397 done:
3398         writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3399         return phy_type;
3400 }
3401
3402 /* check pci invariants */
3403 static void cas_check_pci_invariants(struct cas *cp)
3404 {
3405         struct pci_dev *pdev = cp->pdev;
3406
3407         cp->cas_flags = 0;
3408         if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
3409             (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
3410                 if (pdev->revision >= CAS_ID_REVPLUS)
3411                         cp->cas_flags |= CAS_FLAG_REG_PLUS;
3412                 if (pdev->revision < CAS_ID_REVPLUS02u)
3413                         cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
3414
3415                 /* Original Cassini supports HW CSUM, but it's not
3416                  * enabled by default as it can trigger TX hangs.
3417                  */
3418                 if (pdev->revision < CAS_ID_REV2)
3419                         cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
3420         } else {
3421                 /* Only sun has original cassini chips.  */
3422                 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3423
3424                 /* We use a flag because the same phy might be externally
3425                  * connected.
3426                  */
3427                 if ((pdev->vendor == PCI_VENDOR_ID_NS) &&
3428                     (pdev->device == PCI_DEVICE_ID_NS_SATURN))
3429                         cp->cas_flags |= CAS_FLAG_SATURN;
3430         }
3431 }
3432
3433
3434 static int cas_check_invariants(struct cas *cp)
3435 {
3436         struct pci_dev *pdev = cp->pdev;
3437         u32 cfg;
3438         int i;
3439
3440         /* get page size for rx buffers. */
3441         cp->page_order = 0;
3442 #ifdef USE_PAGE_ORDER
3443         if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) {
3444                 /* see if we can allocate larger pages */
3445                 struct page *page = alloc_pages(GFP_ATOMIC,
3446                                                 CAS_JUMBO_PAGE_SHIFT -
3447                                                 PAGE_SHIFT);
3448                 if (page) {
3449                         __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT);
3450                         cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT;
3451                 } else {
3452                         printk(PFX "MTU limited to %d bytes\n", CAS_MAX_MTU);
3453                 }
3454         }
3455 #endif
3456         cp->page_size = (PAGE_SIZE << cp->page_order);
3457
3458         /* Fetch the FIFO configurations. */
3459         cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64;
3460         cp->rx_fifo_size = RX_FIFO_SIZE;
3461
3462         /* finish phy determination. MDIO1 takes precedence over MDIO0 if
3463          * they're both connected.
3464          */
3465         cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr,
3466                                         PCI_SLOT(pdev->devfn));
3467         if (cp->phy_type & CAS_PHY_SERDES) {
3468                 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3469                 return 0; /* no more checking needed */
3470         }
3471
3472         /* MII */
3473         cfg = readl(cp->regs + REG_MIF_CFG);
3474         if (cfg & MIF_CFG_MDIO_1) {
3475                 cp->phy_type = CAS_PHY_MII_MDIO1;
3476         } else if (cfg & MIF_CFG_MDIO_0) {
3477                 cp->phy_type = CAS_PHY_MII_MDIO0;
3478         }
3479
3480         cas_mif_poll(cp, 0);
3481         writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3482
3483         for (i = 0; i < 32; i++) {
3484                 u32 phy_id;
3485                 int j;
3486
3487                 for (j = 0; j < 3; j++) {
3488                         cp->phy_addr = i;
3489                         phy_id = cas_phy_read(cp, MII_PHYSID1) << 16;
3490                         phy_id |= cas_phy_read(cp, MII_PHYSID2);
3491                         if (phy_id && (phy_id != 0xFFFFFFFF)) {
3492                                 cp->phy_id = phy_id;
3493                                 goto done;
3494                         }
3495                 }
3496         }
3497         printk(KERN_ERR PFX "MII phy did not respond [%08x]\n",
3498                readl(cp->regs + REG_MIF_STATE_MACHINE));
3499         return -1;
3500
3501 done:
3502         /* see if we can do gigabit */
3503         cfg = cas_phy_read(cp, MII_BMSR);
3504         if ((cfg & CAS_BMSR_1000_EXTEND) &&
3505             cas_phy_read(cp, CAS_MII_1000_EXTEND))
3506                 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3507         return 0;
3508 }
3509
3510 /* Must be invoked under cp->lock. */
3511 static inline void cas_start_dma(struct cas *cp)
3512 {
3513         int i;
3514         u32 val;
3515         int txfailed = 0;
3516
3517         /* enable dma */
3518         val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
3519         writel(val, cp->regs + REG_TX_CFG);
3520         val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
3521         writel(val, cp->regs + REG_RX_CFG);
3522
3523         /* enable the mac */
3524         val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
3525         writel(val, cp->regs + REG_MAC_TX_CFG);
3526         val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
3527         writel(val, cp->regs + REG_MAC_RX_CFG);
3528
3529         i = STOP_TRIES;
3530         while (i-- > 0) {
3531                 val = readl(cp->regs + REG_MAC_TX_CFG);
3532                 if ((val & MAC_TX_CFG_EN))
3533                         break;
3534                 udelay(10);
3535         }
3536         if (i < 0) txfailed = 1;
3537         i = STOP_TRIES;
3538         while (i-- > 0) {
3539                 val = readl(cp->regs + REG_MAC_RX_CFG);
3540                 if ((val & MAC_RX_CFG_EN)) {
3541                         if (txfailed) {
3542                           printk(KERN_ERR
3543                                  "%s: enabling mac failed [tx:%08x:%08x].\n",
3544                                  cp->dev->name,
3545                                  readl(cp->regs + REG_MIF_STATE_MACHINE),
3546                                  readl(cp->regs + REG_MAC_STATE_MACHINE));
3547                         }
3548                         goto enable_rx_done;
3549                 }
3550                 udelay(10);
3551         }
3552         printk(KERN_ERR "%s: enabling mac failed [%s:%08x:%08x].\n",
3553                cp->dev->name,
3554                (txfailed? "tx,rx":"rx"),
3555                readl(cp->regs + REG_MIF_STATE_MACHINE),
3556                readl(cp->regs + REG_MAC_STATE_MACHINE));
3557
3558 enable_rx_done:
3559         cas_unmask_intr(cp); /* enable interrupts */
3560         writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
3561         writel(0, cp->regs + REG_RX_COMP_TAIL);
3562
3563         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
3564                 if (N_RX_DESC_RINGS > 1)
3565                         writel(RX_DESC_RINGN_SIZE(1) - 4,
3566                                cp->regs + REG_PLUS_RX_KICK1);
3567
3568                 for (i = 1; i < N_RX_COMP_RINGS; i++)
3569                         writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i));
3570         }
3571 }
3572
3573 /* Must be invoked under cp->lock. */
3574 static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd,
3575                                    int *pause)
3576 {
3577         u32 val = readl(cp->regs + REG_PCS_MII_LPA);
3578         *fd     = (val & PCS_MII_LPA_FD) ? 1 : 0;
3579         *pause  = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
3580         if (val & PCS_MII_LPA_ASYM_PAUSE)
3581                 *pause |= 0x10;
3582         *spd = 1000;
3583 }
3584
3585 /* Must be invoked under cp->lock. */
3586 static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd,
3587                                    int *pause)
3588 {
3589         u32 val;
3590
3591         *fd = 0;
3592         *spd = 10;
3593         *pause = 0;
3594
3595         /* use GMII registers */
3596         val = cas_phy_read(cp, MII_LPA);
3597         if (val & CAS_LPA_PAUSE)
3598                 *pause = 0x01;
3599
3600         if (val & CAS_LPA_ASYM_PAUSE)
3601                 *pause |= 0x10;
3602
3603         if (val & LPA_DUPLEX)
3604                 *fd = 1;
3605         if (val & LPA_100)
3606                 *spd = 100;
3607
3608         if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
3609                 val = cas_phy_read(cp, CAS_MII_1000_STATUS);
3610                 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
3611                         *spd = 1000;
3612                 if (val & CAS_LPA_1000FULL)
3613                         *fd = 1;
3614         }
3615 }
3616
3617 /* A link-up condition has occurred, initialize and enable the
3618  * rest of the chip.
3619  *
3620  * Must be invoked under cp->lock.
3621  */
3622 static void cas_set_link_modes(struct cas *cp)
3623 {
3624         u32 val;
3625         int full_duplex, speed, pause;
3626
3627         full_duplex = 0;
3628         speed = 10;
3629         pause = 0;
3630
3631         if (CAS_PHY_MII(cp->phy_type)) {
3632                 cas_mif_poll(cp, 0);
3633                 val = cas_phy_read(cp, MII_BMCR);
3634                 if (val & BMCR_ANENABLE) {
3635                         cas_read_mii_link_mode(cp, &full_duplex, &speed,
3636                                                &pause);
3637                 } else {
3638                         if (val & BMCR_FULLDPLX)
3639                                 full_duplex = 1;
3640
3641                         if (val & BMCR_SPEED100)
3642                                 speed = 100;
3643                         else if (val & CAS_BMCR_SPEED1000)
3644                                 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
3645                                         1000 : 100;
3646                 }
3647                 cas_mif_poll(cp, 1);
3648
3649         } else {
3650                 val = readl(cp->regs + REG_PCS_MII_CTRL);
3651                 cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause);
3652                 if ((val & PCS_MII_AUTONEG_EN) == 0) {
3653                         if (val & PCS_MII_CTRL_DUPLEX)
3654                                 full_duplex = 1;
3655                 }
3656         }
3657
3658         if (netif_msg_link(cp))
3659                 printk(KERN_INFO "%s: Link up at %d Mbps, %s-duplex.\n",
3660                        cp->dev->name, speed, (full_duplex ? "full" : "half"));
3661
3662         val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
3663         if (CAS_PHY_MII(cp->phy_type)) {
3664                 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
3665                 if (!full_duplex)
3666                         val |= MAC_XIF_DISABLE_ECHO;
3667         }
3668         if (full_duplex)
3669                 val |= MAC_XIF_FDPLX_LED;
3670         if (speed == 1000)
3671                 val |= MAC_XIF_GMII_MODE;
3672         writel(val, cp->regs + REG_MAC_XIF_CFG);
3673
3674         /* deal with carrier and collision detect. */
3675         val = MAC_TX_CFG_IPG_EN;
3676         if (full_duplex) {
3677                 val |= MAC_TX_CFG_IGNORE_CARRIER;
3678                 val |= MAC_TX_CFG_IGNORE_COLL;
3679         } else {
3680 #ifndef USE_CSMA_CD_PROTO
3681                 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
3682                 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
3683 #endif
3684         }
3685         /* val now set up for REG_MAC_TX_CFG */
3686
3687         /* If gigabit and half-duplex, enable carrier extension
3688          * mode.  increase slot time to 512 bytes as well.
3689          * else, disable it and make sure slot time is 64 bytes.
3690          * also activate checksum bug workaround
3691          */
3692         if ((speed == 1000) && !full_duplex) {
3693                 writel(val | MAC_TX_CFG_CARRIER_EXTEND,
3694                        cp->regs + REG_MAC_TX_CFG);
3695
3696                 val = readl(cp->regs + REG_MAC_RX_CFG);
3697                 val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */
3698                 writel(val | MAC_RX_CFG_CARRIER_EXTEND,
3699                        cp->regs + REG_MAC_RX_CFG);
3700
3701                 writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
3702
3703                 cp->crc_size = 4;
3704                 /* minimum size gigabit frame at half duplex */
3705                 cp->min_frame_size = CAS_1000MB_MIN_FRAME;
3706
3707         } else {
3708                 writel(val, cp->regs + REG_MAC_TX_CFG);
3709
3710                 /* checksum bug workaround. don't strip FCS when in
3711                  * half-duplex mode
3712                  */
3713                 val = readl(cp->regs + REG_MAC_RX_CFG);
3714                 if (full_duplex) {
3715                         val |= MAC_RX_CFG_STRIP_FCS;
3716                         cp->crc_size = 0;
3717                         cp->min_frame_size = CAS_MIN_MTU;
3718                 } else {
3719                         val &= ~MAC_RX_CFG_STRIP_FCS;
3720                         cp->crc_size = 4;
3721                         cp->min_frame_size = CAS_MIN_FRAME;
3722                 }
3723                 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
3724                        cp->regs + REG_MAC_RX_CFG);
3725                 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3726         }
3727
3728         if (netif_msg_link(cp)) {
3729                 if (pause & 0x01) {
3730                         printk(KERN_INFO "%s: Pause is enabled "
3731                                "(rxfifo: %d off: %d on: %d)\n",
3732                                cp->dev->name,
3733                                cp->rx_fifo_size,
3734                                cp->rx_pause_off,
3735                                cp->rx_pause_on);
3736                 } else if (pause & 0x10) {
3737                         printk(KERN_INFO "%s: TX pause enabled\n",
3738                                cp->dev->name);
3739                 } else {
3740                         printk(KERN_INFO "%s: Pause is disabled\n",
3741                                cp->dev->name);
3742                 }
3743         }
3744
3745         val = readl(cp->regs + REG_MAC_CTRL_CFG);
3746         val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
3747         if (pause) { /* symmetric or asymmetric pause */
3748                 val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
3749                 if (pause & 0x01) { /* symmetric pause */
3750                         val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
3751                 }
3752         }
3753         writel(val, cp->regs + REG_MAC_CTRL_CFG);
3754         cas_start_dma(cp);
3755 }
3756
3757 /* Must be invoked under cp->lock. */
3758 static void cas_init_hw(struct cas *cp, int restart_link)
3759 {
3760         if (restart_link)
3761                 cas_phy_init(cp);
3762
3763         cas_init_pause_thresholds(cp);
3764         cas_init_mac(cp);
3765         cas_init_dma(cp);
3766
3767         if (restart_link) {
3768                 /* Default aneg parameters */
3769                 cp->timer_ticks = 0;
3770                 cas_begin_auto_negotiation(cp, NULL);
3771         } else if (cp->lstate == link_up) {
3772                 cas_set_link_modes(cp);
3773                 netif_carrier_on(cp->dev);
3774         }
3775 }
3776
3777 /* Must be invoked under cp->lock. on earlier cassini boards,
3778  * SOFT_0 is tied to PCI reset. we use this to force a pci reset,
3779  * let it settle out, and then restore pci state.
3780  */
3781 static void cas_hard_reset(struct cas *cp)
3782 {
3783         writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3784         udelay(20);
3785         pci_restore_state(cp->pdev);
3786 }
3787
3788
3789 static void cas_global_reset(struct cas *cp, int blkflag)
3790 {
3791         int limit;
3792
3793         /* issue a global reset. don't use RSTOUT. */
3794         if (blkflag && !CAS_PHY_MII(cp->phy_type)) {
3795                 /* For PCS, when the blkflag is set, we should set the
3796                  * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of
3797                  * the last autonegotiation from being cleared.  We'll
3798                  * need some special handling if the chip is set into a
3799                  * loopback mode.
3800                  */
3801                 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),
3802                        cp->regs + REG_SW_RESET);
3803         } else {
3804                 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
3805         }
3806
3807         /* need to wait at least 3ms before polling register */
3808         mdelay(3);
3809
3810         limit = STOP_TRIES;
3811         while (limit-- > 0) {
3812                 u32 val = readl(cp->regs + REG_SW_RESET);
3813                 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
3814                         goto done;
3815                 udelay(10);
3816         }
3817         printk(KERN_ERR "%s: sw reset failed.\n", cp->dev->name);
3818
3819 done:
3820         /* enable various BIM interrupts */
3821         writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |
3822                BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);
3823
3824         /* clear out pci error status mask for handled errors.
3825          * we don't deal with DMA counter overflows as they happen
3826          * all the time.
3827          */
3828         writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |
3829                                PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE |
3830                                PCI_ERR_BIM_DMA_READ), cp->regs +
3831                REG_PCI_ERR_STATUS_MASK);
3832
3833         /* set up for MII by default to address mac rx reset timeout
3834          * issue
3835          */
3836         writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3837 }
3838
3839 static void cas_reset(struct cas *cp, int blkflag)
3840 {
3841         u32 val;
3842
3843         cas_mask_intr(cp);
3844         cas_global_reset(cp, blkflag);
3845         cas_mac_reset(cp);
3846         cas_entropy_reset(cp);
3847
3848         /* disable dma engines. */
3849         val = readl(cp->regs + REG_TX_CFG);
3850         val &= ~TX_CFG_DMA_EN;
3851         writel(val, cp->regs + REG_TX_CFG);
3852
3853         val = readl(cp->regs + REG_RX_CFG);
3854         val &= ~RX_CFG_DMA_EN;
3855         writel(val, cp->regs + REG_RX_CFG);
3856
3857         /* program header parser */
3858         if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) ||
3859             (CAS_HP_ALT_FIRMWARE == cas_prog_null)) {
3860                 cas_load_firmware(cp, CAS_HP_FIRMWARE);
3861         } else {
3862                 cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE);
3863         }
3864
3865         /* clear out error registers */
3866         spin_lock(&cp->stat_lock[N_TX_RINGS]);
3867         cas_clear_mac_err(cp);
3868         spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3869 }
3870
3871 /* Shut down the chip, must be called with pm_mutex held.  */
3872 static void cas_shutdown(struct cas *cp)
3873 {
3874         unsigned long flags;
3875
3876         /* Make us not-running to avoid timers respawning */
3877         cp->hw_running = 0;
3878
3879         del_timer_sync(&cp->link_timer);
3880
3881         /* Stop the reset task */
3882 #if 0
3883         while (atomic_read(&cp->reset_task_pending_mtu) ||
3884                atomic_read(&cp->reset_task_pending_spare) ||
3885                atomic_read(&cp->reset_task_pending_all))
3886                 schedule();
3887
3888 #else
3889         while (atomic_read(&cp->reset_task_pending))
3890                 schedule();
3891 #endif
3892         /* Actually stop the chip */
3893         cas_lock_all_save(cp, flags);
3894         cas_reset(cp, 0);
3895         if (cp->cas_flags & CAS_FLAG_SATURN)
3896                 cas_phy_powerdown(cp);
3897         cas_unlock_all_restore(cp, flags);
3898 }
3899
3900 static int cas_change_mtu(struct net_device *dev, int new_mtu)
3901 {
3902         struct cas *cp = netdev_priv(dev);
3903
3904         if (new_mtu < CAS_MIN_MTU || new_mtu > CAS_MAX_MTU)
3905                 return -EINVAL;
3906
3907         dev->mtu = new_mtu;
3908         if (!netif_running(dev) || !netif_device_present(dev))
3909                 return 0;
3910
3911         /* let the reset task handle it */
3912 #if 1
3913         atomic_inc(&cp->reset_task_pending);
3914         if ((cp->phy_type & CAS_PHY_SERDES)) {
3915                 atomic_inc(&cp->reset_task_pending_all);
3916         } else {
3917                 atomic_inc(&cp->reset_task_pending_mtu);
3918         }
3919         schedule_work(&cp->reset_task);
3920 #else
3921         atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ?
3922                    CAS_RESET_ALL : CAS_RESET_MTU);
3923         printk(KERN_ERR "reset called in cas_change_mtu\n");
3924         schedule_work(&cp->reset_task);
3925 #endif
3926
3927         flush_scheduled_work();
3928         return 0;
3929 }
3930
3931 static void cas_clean_txd(struct cas *cp, int ring)
3932 {
3933         struct cas_tx_desc *txd = cp->init_txds[ring];
3934         struct sk_buff *skb, **skbs = cp->tx_skbs[ring];
3935         u64 daddr, dlen;
3936         int i, size;
3937
3938         size = TX_DESC_RINGN_SIZE(ring);
3939         for (i = 0; i < size; i++) {
3940                 int frag;
3941
3942                 if (skbs[i] == NULL)
3943                         continue;
3944
3945                 skb = skbs[i];
3946                 skbs[i] = NULL;
3947
3948                 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags;  frag++) {
3949                         int ent = i & (size - 1);
3950
3951                         /* first buffer is never a tiny buffer and so
3952                          * needs to be unmapped.
3953                          */
3954                         daddr = le64_to_cpu(txd[ent].buffer);
3955                         dlen  =  CAS_VAL(TX_DESC_BUFLEN,
3956                                          le64_to_cpu(txd[ent].control));
3957                         pci_unmap_page(cp->pdev, daddr, dlen,
3958                                        PCI_DMA_TODEVICE);
3959
3960                         if (frag != skb_shinfo(skb)->nr_frags) {
3961                                 i++;
3962
3963                                 /* next buffer might by a tiny buffer.
3964                                  * skip past it.
3965                                  */
3966                                 ent = i & (size - 1);
3967                                 if (cp->tx_tiny_use[ring][ent].used)
3968                                         i++;
3969                         }
3970                 }
3971                 dev_kfree_skb_any(skb);
3972         }
3973
3974         /* zero out tiny buf usage */
3975         memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring]));
3976 }
3977
3978 /* freed on close */
3979 static inline void cas_free_rx_desc(struct cas *cp, int ring)
3980 {
3981         cas_page_t **page = cp->rx_pages[ring];
3982         int i, size;
3983
3984         size = RX_DESC_RINGN_SIZE(ring);
3985         for (i = 0; i < size; i++) {
3986                 if (page[i]) {
3987                         cas_page_free(cp, page[i]);
3988                         page[i] = NULL;
3989                 }
3990         }
3991 }
3992
3993 static void cas_free_rxds(struct cas *cp)
3994 {
3995         int i;
3996
3997         for (i = 0; i < N_RX_DESC_RINGS; i++)
3998                 cas_free_rx_desc(cp, i);
3999 }
4000
4001 /* Must be invoked under cp->lock. */
4002 static void cas_clean_rings(struct cas *cp)
4003 {
4004         int i;
4005
4006         /* need to clean all tx rings */
4007         memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS);
4008         memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS);
4009         for (i = 0; i < N_TX_RINGS; i++)
4010                 cas_clean_txd(cp, i);
4011
4012         /* zero out init block */
4013         memset(cp->init_block, 0, sizeof(struct cas_init_block));
4014         cas_clean_rxds(cp);
4015         cas_clean_rxcs(cp);
4016 }
4017
4018 /* allocated on open */
4019 static inline int cas_alloc_rx_desc(struct cas *cp, int ring)
4020 {
4021         cas_page_t **page = cp->rx_pages[ring];
4022         int size, i = 0;
4023
4024         size = RX_DESC_RINGN_SIZE(ring);
4025         for (i = 0; i < size; i++) {
4026                 if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL)
4027                         return -1;
4028         }
4029         return 0;
4030 }
4031
4032 static int cas_alloc_rxds(struct cas *cp)
4033 {
4034         int i;
4035
4036         for (i = 0; i < N_RX_DESC_RINGS; i++) {
4037                 if (cas_alloc_rx_desc(cp, i) < 0) {
4038                         cas_free_rxds(cp);
4039                         return -1;
4040                 }
4041         }
4042         return 0;
4043 }
4044
4045 static void cas_reset_task(struct work_struct *work)
4046 {
4047         struct cas *cp = container_of(work, struct cas, reset_task);
4048 #if 0
4049         int pending = atomic_read(&cp->reset_task_pending);
4050 #else
4051         int pending_all = atomic_read(&cp->reset_task_pending_all);
4052         int pending_spare = atomic_read(&cp->reset_task_pending_spare);
4053         int pending_mtu = atomic_read(&cp->reset_task_pending_mtu);
4054
4055         if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) {
4056                 /* We can have more tasks scheduled than actually
4057                  * needed.
4058                  */
4059                 atomic_dec(&cp->reset_task_pending);
4060                 return;
4061         }
4062 #endif
4063         /* The link went down, we reset the ring, but keep
4064          * DMA stopped. Use this function for reset
4065          * on error as well.
4066          */
4067         if (cp->hw_running) {
4068                 unsigned long flags;
4069
4070                 /* Make sure we don't get interrupts or tx packets */
4071                 netif_device_detach(cp->dev);
4072                 cas_lock_all_save(cp, flags);
4073
4074                 if (cp->opened) {
4075                         /* We call cas_spare_recover when we call cas_open.
4076                          * but we do not initialize the lists cas_spare_recover
4077                          * uses until cas_open is called.
4078                          */
4079                         cas_spare_recover(cp, GFP_ATOMIC);
4080                 }
4081 #if 1
4082                 /* test => only pending_spare set */
4083                 if (!pending_all && !pending_mtu)
4084                         goto done;
4085 #else
4086                 if (pending == CAS_RESET_SPARE)
4087                         goto done;
4088 #endif
4089                 /* when pending == CAS_RESET_ALL, the following
4090                  * call to cas_init_hw will restart auto negotiation.
4091                  * Setting the second argument of cas_reset to
4092                  * !(pending == CAS_RESET_ALL) will set this argument
4093                  * to 1 (avoiding reinitializing the PHY for the normal
4094                  * PCS case) when auto negotiation is not restarted.
4095                  */
4096 #if 1
4097                 cas_reset(cp, !(pending_all > 0));
4098                 if (cp->opened)
4099                         cas_clean_rings(cp);
4100                 cas_init_hw(cp, (pending_all > 0));
4101 #else
4102                 cas_reset(cp, !(pending == CAS_RESET_ALL));
4103                 if (cp->opened)
4104                         cas_clean_rings(cp);
4105                 cas_init_hw(cp, pending == CAS_RESET_ALL);
4106 #endif
4107
4108 done:
4109                 cas_unlock_all_restore(cp, flags);
4110                 netif_device_attach(cp->dev);
4111         }
4112 #if 1
4113         atomic_sub(pending_all, &cp->reset_task_pending_all);
4114         atomic_sub(pending_spare, &cp->reset_task_pending_spare);
4115         atomic_sub(pending_mtu, &cp->reset_task_pending_mtu);
4116         atomic_dec(&cp->reset_task_pending);
4117 #else
4118         atomic_set(&cp->reset_task_pending, 0);
4119 #endif
4120 }
4121
4122 static void cas_link_timer(unsigned long data)
4123 {
4124         struct cas *cp = (struct cas *) data;
4125         int mask, pending = 0, reset = 0;
4126         unsigned long flags;
4127
4128         if (link_transition_timeout != 0 &&
4129             cp->link_transition_jiffies_valid &&
4130             ((jiffies - cp->link_transition_jiffies) >
4131               (link_transition_timeout))) {
4132                 /* One-second counter so link-down workaround doesn't
4133                  * cause resets to occur so fast as to fool the switch
4134                  * into thinking the link is down.
4135                  */
4136                 cp->link_transition_jiffies_valid = 0;
4137         }
4138
4139         if (!cp->hw_running)
4140                 return;
4141
4142         spin_lock_irqsave(&cp->lock, flags);
4143         cas_lock_tx(cp);
4144         cas_entropy_gather(cp);
4145
4146         /* If the link task is still pending, we just
4147          * reschedule the link timer
4148          */
4149 #if 1
4150         if (atomic_read(&cp->reset_task_pending_all) ||
4151             atomic_read(&cp->reset_task_pending_spare) ||
4152             atomic_read(&cp->reset_task_pending_mtu))
4153                 goto done;
4154 #else
4155         if (atomic_read(&cp->reset_task_pending))
4156                 goto done;
4157 #endif
4158
4159         /* check for rx cleaning */
4160         if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) {
4161                 int i, rmask;
4162
4163                 for (i = 0; i < MAX_RX_DESC_RINGS; i++) {
4164                         rmask = CAS_FLAG_RXD_POST(i);
4165                         if ((mask & rmask) == 0)
4166                                 continue;
4167
4168                         /* post_rxds will do a mod_timer */
4169                         if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) {
4170                                 pending = 1;
4171                                 continue;
4172                         }
4173                         cp->cas_flags &= ~rmask;
4174                 }
4175         }
4176
4177         if (CAS_PHY_MII(cp->phy_type)) {
4178                 u16 bmsr;
4179                 cas_mif_poll(cp, 0);
4180                 bmsr = cas_phy_read(cp, MII_BMSR);
4181                 /* WTZ: Solaris driver reads this twice, but that
4182                  * may be due to the PCS case and the use of a
4183                  * common implementation. Read it twice here to be
4184                  * safe.
4185                  */
4186                 bmsr = cas_phy_read(cp, MII_BMSR);
4187                 cas_mif_poll(cp, 1);
4188                 readl(cp->regs + REG_MIF_STATUS); /* avoid dups */
4189                 reset = cas_mii_link_check(cp, bmsr);
4190         } else {
4191                 reset = cas_pcs_link_check(cp);
4192         }
4193
4194         if (reset)
4195                 goto done;
4196
4197         /* check for tx state machine confusion */
4198         if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) {
4199                 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
4200                 u32 wptr, rptr;
4201                 int tlm  = CAS_VAL(MAC_SM_TLM, val);
4202
4203                 if (((tlm == 0x5) || (tlm == 0x3)) &&
4204                     (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
4205                         if (netif_msg_tx_err(cp))
4206                                 printk(KERN_DEBUG "%s: tx err: "
4207                                        "MAC_STATE[%08x]\n",
4208                                        cp->dev->name, val);
4209                         reset = 1;
4210                         goto done;
4211                 }
4212
4213                 val  = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
4214                 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
4215                 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR);
4216                 if ((val == 0) && (wptr != rptr)) {
4217                         if (netif_msg_tx_err(cp))
4218                                 printk(KERN_DEBUG "%s: tx err: "
4219                                        "TX_FIFO[%08x:%08x:%08x]\n",
4220                                        cp->dev->name, val, wptr, rptr);
4221                         reset = 1;
4222                 }
4223
4224                 if (reset)
4225                         cas_hard_reset(cp);
4226         }
4227
4228 done:
4229         if (reset) {
4230 #if 1
4231                 atomic_inc(&cp->reset_task_pending);
4232                 atomic_inc(&cp->reset_task_pending_all);
4233                 schedule_work(&cp->reset_task);
4234 #else
4235                 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
4236                 printk(KERN_ERR "reset called in cas_link_timer\n");
4237                 schedule_work(&cp->reset_task);
4238 #endif
4239         }
4240
4241         if (!pending)
4242                 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
4243         cas_unlock_tx(cp);
4244         spin_unlock_irqrestore(&cp->lock, flags);
4245 }
4246
4247 /* tiny buffers are used to avoid target abort issues with
4248  * older cassini's
4249  */
4250 static void cas_tx_tiny_free(struct cas *cp)
4251 {
4252         struct pci_dev *pdev = cp->pdev;
4253         int i;
4254
4255         for (i = 0; i < N_TX_RINGS; i++) {
4256                 if (!cp->tx_tiny_bufs[i])
4257                         continue;
4258
4259                 pci_free_consistent(pdev, TX_TINY_BUF_BLOCK,
4260                                     cp->tx_tiny_bufs[i],
4261                                     cp->tx_tiny_dvma[i]);
4262                 cp->tx_tiny_bufs[i] = NULL;
4263         }
4264 }
4265
4266 static int cas_tx_tiny_alloc(struct cas *cp)
4267 {
4268         struct pci_dev *pdev = cp->pdev;
4269         int i;
4270
4271         for (i = 0; i < N_TX_RINGS; i++) {
4272                 cp->tx_tiny_bufs[i] =
4273                         pci_alloc_consistent(pdev, TX_TINY_BUF_BLOCK,
4274                                              &cp->tx_tiny_dvma[i]);
4275                 if (!cp->tx_tiny_bufs[i]) {
4276                         cas_tx_tiny_free(cp);
4277                         return -1;
4278                 }
4279         }
4280         return 0;
4281 }
4282
4283
4284 static int cas_open(struct net_device *dev)
4285 {
4286         struct cas *cp = netdev_priv(dev);
4287         int hw_was_up, err;
4288         unsigned long flags;
4289
4290         mutex_lock(&cp->pm_mutex);
4291
4292         hw_was_up = cp->hw_running;
4293
4294         /* The power-management mutex protects the hw_running
4295          * etc. state so it is safe to do this bit without cp->lock
4296          */
4297         if (!cp->hw_running) {
4298                 /* Reset the chip */
4299                 cas_lock_all_save(cp, flags);
4300                 /* We set the second arg to cas_reset to zero
4301                  * because cas_init_hw below will have its second
4302                  * argument set to non-zero, which will force
4303                  * autonegotiation to start.
4304                  */
4305                 cas_reset(cp, 0);
4306                 cp->hw_running = 1;
4307                 cas_unlock_all_restore(cp, flags);
4308         }
4309
4310         if (cas_tx_tiny_alloc(cp) < 0)
4311                 return -ENOMEM;
4312
4313         /* alloc rx descriptors */
4314         err = -ENOMEM;
4315         if (cas_alloc_rxds(cp) < 0)
4316                 goto err_tx_tiny;
4317
4318         /* allocate spares */
4319         cas_spare_init(cp);
4320         cas_spare_recover(cp, GFP_KERNEL);
4321
4322         /* We can now request the interrupt as we know it's masked
4323          * on the controller. cassini+ has up to 4 interrupts
4324          * that can be used, but you need to do explicit pci interrupt
4325          * mapping to expose them
4326          */
4327         if (request_irq(cp->pdev->irq, cas_interrupt,
4328                         IRQF_SHARED, dev->name, (void *) dev)) {
4329                 printk(KERN_ERR "%s: failed to request irq !\n",
4330                        cp->dev->name);
4331                 err = -EAGAIN;
4332                 goto err_spare;
4333         }
4334
4335 #ifdef USE_NAPI
4336         napi_enable(&cp->napi);
4337 #endif
4338         /* init hw */
4339         cas_lock_all_save(cp, flags);
4340         cas_clean_rings(cp);
4341         cas_init_hw(cp, !hw_was_up);
4342         cp->opened = 1;
4343         cas_unlock_all_restore(cp, flags);
4344
4345         netif_start_queue(dev);
4346         mutex_unlock(&cp->pm_mutex);
4347         return 0;
4348
4349 err_spare:
4350         cas_spare_free(cp);
4351         cas_free_rxds(cp);
4352 err_tx_tiny:
4353         cas_tx_tiny_free(cp);
4354         mutex_unlock(&cp->pm_mutex);
4355         return err;
4356 }
4357
4358 static int cas_close(struct net_device *dev)
4359 {
4360         unsigned long flags;
4361         struct cas *cp = netdev_priv(dev);
4362
4363 #ifdef USE_NAPI
4364         napi_disable(&cp->napi);
4365 #endif
4366         /* Make sure we don't get distracted by suspend/resume */
4367         mutex_lock(&cp->pm_mutex);
4368
4369         netif_stop_queue(dev);
4370
4371         /* Stop traffic, mark us closed */
4372         cas_lock_all_save(cp, flags);
4373         cp->opened = 0;
4374         cas_reset(cp, 0);
4375         cas_phy_init(cp);
4376         cas_begin_auto_negotiation(cp, NULL);
4377         cas_clean_rings(cp);
4378         cas_unlock_all_restore(cp, flags);
4379
4380         free_irq(cp->pdev->irq, (void *) dev);
4381         cas_spare_free(cp);
4382         cas_free_rxds(cp);
4383         cas_tx_tiny_free(cp);
4384         mutex_unlock(&cp->pm_mutex);
4385         return 0;
4386 }
4387
4388 static struct {
4389         const char name[ETH_GSTRING_LEN];
4390 } ethtool_cassini_statnames[] = {
4391         {"collisions"},
4392         {"rx_bytes"},
4393         {"rx_crc_errors"},
4394         {"rx_dropped"},
4395         {"rx_errors"},
4396         {"rx_fifo_errors"},
4397         {"rx_frame_errors"},
4398         {"rx_length_errors"},
4399         {"rx_over_errors"},
4400         {"rx_packets"},
4401         {"tx_aborted_errors"},
4402         {"tx_bytes"},
4403         {"tx_dropped"},
4404         {"tx_errors"},
4405         {"tx_fifo_errors"},
4406         {"tx_packets"}
4407 };
4408 #define CAS_NUM_STAT_KEYS ARRAY_SIZE(ethtool_cassini_statnames)
4409
4410 static struct {
4411         const int offsets;      /* neg. values for 2nd arg to cas_read_phy */
4412 } ethtool_register_table[] = {
4413         {-MII_BMSR},
4414         {-MII_BMCR},
4415         {REG_CAWR},
4416         {REG_INF_BURST},
4417         {REG_BIM_CFG},
4418         {REG_RX_CFG},
4419         {REG_HP_CFG},
4420         {REG_MAC_TX_CFG},
4421         {REG_MAC_RX_CFG},
4422         {REG_MAC_CTRL_CFG},
4423         {REG_MAC_XIF_CFG},
4424         {REG_MIF_CFG},
4425         {REG_PCS_CFG},
4426         {REG_SATURN_PCFG},
4427         {REG_PCS_MII_STATUS},
4428         {REG_PCS_STATE_MACHINE},
4429         {REG_MAC_COLL_EXCESS},
4430         {REG_MAC_COLL_LATE}
4431 };
4432 #define CAS_REG_LEN     ARRAY_SIZE(ethtool_register_table)
4433 #define CAS_MAX_REGS    (sizeof (u32)*CAS_REG_LEN)
4434
4435 static void cas_read_regs(struct cas *cp, u8 *ptr, int len)
4436 {
4437         u8 *p;
4438         int i;
4439         unsigned long flags;
4440
4441         spin_lock_irqsave(&cp->lock, flags);
4442         for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) {
4443                 u16 hval;
4444                 u32 val;
4445                 if (ethtool_register_table[i].offsets < 0) {
4446                         hval = cas_phy_read(cp,
4447                                     -ethtool_register_table[i].offsets);
4448                         val = hval;
4449                 } else {
4450                         val= readl(cp->regs+ethtool_register_table[i].offsets);
4451                 }
4452                 memcpy(p, (u8 *)&val, sizeof(u32));
4453         }
4454         spin_unlock_irqrestore(&cp->lock, flags);
4455 }
4456
4457 static struct net_device_stats *cas_get_stats(struct net_device *dev)
4458 {
4459         struct cas *cp = netdev_priv(dev);
4460         struct net_device_stats *stats = cp->net_stats;
4461         unsigned long flags;
4462         int i;
4463         unsigned long tmp;
4464
4465         /* we collate all of the stats into net_stats[N_TX_RING] */
4466         if (!cp->hw_running)
4467                 return stats + N_TX_RINGS;
4468
4469         /* collect outstanding stats */
4470         /* WTZ: the Cassini spec gives these as 16 bit counters but
4471          * stored in 32-bit words.  Added a mask of 0xffff to be safe,
4472          * in case the chip somehow puts any garbage in the other bits.
4473          * Also, counter usage didn't seem to mach what Adrian did
4474          * in the parts of the code that set these quantities. Made
4475          * that consistent.
4476          */
4477         spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags);
4478         stats[N_TX_RINGS].rx_crc_errors +=
4479           readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff;
4480         stats[N_TX_RINGS].rx_frame_errors +=
4481                 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff;
4482         stats[N_TX_RINGS].rx_length_errors +=
4483                 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff;
4484 #if 1
4485         tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) +
4486                 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff);
4487         stats[N_TX_RINGS].tx_aborted_errors += tmp;
4488         stats[N_TX_RINGS].collisions +=
4489           tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff);
4490 #else
4491         stats[N_TX_RINGS].tx_aborted_errors +=
4492                 readl(cp->regs + REG_MAC_COLL_EXCESS);
4493         stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) +
4494                 readl(cp->regs + REG_MAC_COLL_LATE);
4495 #endif
4496         cas_clear_mac_err(cp);
4497
4498         /* saved bits that are unique to ring 0 */
4499         spin_lock(&cp->stat_lock[0]);
4500         stats[N_TX_RINGS].collisions        += stats[0].collisions;
4501         stats[N_TX_RINGS].rx_over_errors    += stats[0].rx_over_errors;
4502         stats[N_TX_RINGS].rx_frame_errors   += stats[0].rx_frame_errors;
4503         stats[N_TX_RINGS].rx_fifo_errors    += stats[0].rx_fifo_errors;
4504         stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors;
4505         stats[N_TX_RINGS].tx_fifo_errors    += stats[0].tx_fifo_errors;
4506         spin_unlock(&cp->stat_lock[0]);
4507
4508         for (i = 0; i < N_TX_RINGS; i++) {
4509                 spin_lock(&cp->stat_lock[i]);
4510                 stats[N_TX_RINGS].rx_length_errors +=
4511                         stats[i].rx_length_errors;
4512                 stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors;
4513                 stats[N_TX_RINGS].rx_packets    += stats[i].rx_packets;
4514                 stats[N_TX_RINGS].tx_packets    += stats[i].tx_packets;
4515                 stats[N_TX_RINGS].rx_bytes      += stats[i].rx_bytes;
4516                 stats[N_TX_RINGS].tx_bytes      += stats[i].tx_bytes;
4517                 stats[N_TX_RINGS].rx_errors     += stats[i].rx_errors;
4518                 stats[N_TX_RINGS].tx_errors     += stats[i].tx_errors;
4519                 stats[N_TX_RINGS].rx_dropped    += stats[i].rx_dropped;
4520                 stats[N_TX_RINGS].tx_dropped    += stats[i].tx_dropped;
4521                 memset(stats + i, 0, sizeof(struct net_device_stats));
4522                 spin_unlock(&cp->stat_lock[i]);
4523         }
4524         spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags);
4525         return stats + N_TX_RINGS;
4526 }
4527
4528
4529 static void cas_set_multicast(struct net_device *dev)
4530 {
4531         struct cas *cp = netdev_priv(dev);
4532         u32 rxcfg, rxcfg_new;
4533         unsigned long flags;
4534         int limit = STOP_TRIES;
4535
4536         if (!cp->hw_running)
4537                 return;
4538
4539         spin_lock_irqsave(&cp->lock, flags);
4540         rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
4541
4542         /* disable RX MAC and wait for completion */
4543         writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4544         while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) {
4545                 if (!limit--)
4546                         break;
4547                 udelay(10);
4548         }
4549
4550         /* disable hash filter and wait for completion */
4551         limit = STOP_TRIES;
4552         rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
4553         writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4554         while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) {
4555                 if (!limit--)
4556                         break;
4557                 udelay(10);
4558         }
4559
4560         /* program hash filters */
4561         cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp);
4562         rxcfg |= rxcfg_new;
4563         writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
4564         spin_unlock_irqrestore(&cp->lock, flags);
4565 }
4566
4567 static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4568 {
4569         struct cas *cp = netdev_priv(dev);
4570         strncpy(info->driver, DRV_MODULE_NAME, ETHTOOL_BUSINFO_LEN);
4571         strncpy(info->version, DRV_MODULE_VERSION, ETHTOOL_BUSINFO_LEN);
4572         info->fw_version[0] = '\0';
4573         strncpy(info->bus_info, pci_name(cp->pdev), ETHTOOL_BUSINFO_LEN);
4574         info->regdump_len = cp->casreg_len < CAS_MAX_REGS ?
4575                 cp->casreg_len : CAS_MAX_REGS;
4576         info->n_stats = CAS_NUM_STAT_KEYS;
4577 }
4578
4579 static int cas_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4580 {
4581         struct cas *cp = netdev_priv(dev);
4582         u16 bmcr;
4583         int full_duplex, speed, pause;
4584         unsigned long flags;
4585         enum link_state linkstate = link_up;
4586
4587         cmd->advertising = 0;
4588         cmd->supported = SUPPORTED_Autoneg;
4589         if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
4590                 cmd->supported |= SUPPORTED_1000baseT_Full;
4591                 cmd->advertising |= ADVERTISED_1000baseT_Full;
4592         }
4593
4594         /* Record PHY settings if HW is on. */
4595         spin_lock_irqsave(&cp->lock, flags);
4596         bmcr = 0;
4597         linkstate = cp->lstate;
4598         if (CAS_PHY_MII(cp->phy_type)) {
4599                 cmd->port = PORT_MII;
4600                 cmd->transceiver = (cp->cas_flags & CAS_FLAG_SATURN) ?
4601                         XCVR_INTERNAL : XCVR_EXTERNAL;
4602                 cmd->phy_address = cp->phy_addr;
4603                 cmd->advertising |= ADVERTISED_TP | ADVERTISED_MII |
4604                         ADVERTISED_10baseT_Half |
4605                         ADVERTISED_10baseT_Full |
4606                         ADVERTISED_100baseT_Half |
4607                         ADVERTISED_100baseT_Full;
4608
4609                 cmd->supported |=
4610                         (SUPPORTED_10baseT_Half |
4611                          SUPPORTED_10baseT_Full |
4612                          SUPPORTED_100baseT_Half |
4613                          SUPPORTED_100baseT_Full |
4614                          SUPPORTED_TP | SUPPORTED_MII);
4615
4616                 if (cp->hw_running) {
4617                         cas_mif_poll(cp, 0);
4618                         bmcr = cas_phy_read(cp, MII_BMCR);
4619                         cas_read_mii_link_mode(cp, &full_duplex,
4620                                                &speed, &pause);
4621                         cas_mif_poll(cp, 1);
4622                 }
4623
4624         } else {
4625                 cmd->port = PORT_FIBRE;
4626                 cmd->transceiver = XCVR_INTERNAL;
4627                 cmd->phy_address = 0;
4628                 cmd->supported   |= SUPPORTED_FIBRE;
4629                 cmd->advertising |= ADVERTISED_FIBRE;
4630
4631                 if (cp->hw_running) {
4632                         /* pcs uses the same bits as mii */
4633                         bmcr = readl(cp->regs + REG_PCS_MII_CTRL);
4634                         cas_read_pcs_link_mode(cp, &full_duplex,
4635                                                &speed, &pause);
4636                 }
4637         }
4638         spin_unlock_irqrestore(&cp->lock, flags);
4639
4640         if (bmcr & BMCR_ANENABLE) {
4641                 cmd->advertising |= ADVERTISED_Autoneg;
4642                 cmd->autoneg = AUTONEG_ENABLE;
4643                 cmd->speed = ((speed == 10) ?
4644                               SPEED_10 :
4645                               ((speed == 1000) ?
4646                                SPEED_1000 : SPEED_100));
4647                 cmd->duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
4648         } else {
4649                 cmd->autoneg = AUTONEG_DISABLE;
4650                 cmd->speed =
4651                         (bmcr & CAS_BMCR_SPEED1000) ?
4652                         SPEED_1000 :
4653                         ((bmcr & BMCR_SPEED100) ? SPEED_100:
4654                          SPEED_10);
4655                 cmd->duplex =
4656                         (bmcr & BMCR_FULLDPLX) ?
4657                         DUPLEX_FULL : DUPLEX_HALF;
4658         }
4659         if (linkstate != link_up) {
4660                 /* Force these to "unknown" if the link is not up and
4661                  * autonogotiation in enabled. We can set the link
4662                  * speed to 0, but not cmd->duplex,
4663                  * because its legal values are 0 and 1.  Ethtool will
4664                  * print the value reported in parentheses after the
4665                  * word "Unknown" for unrecognized values.
4666                  *
4667                  * If in forced mode, we report the speed and duplex
4668                  * settings that we configured.
4669                  */
4670                 if (cp->link_cntl & BMCR_ANENABLE) {
4671                         cmd->speed = 0;
4672                         cmd->duplex = 0xff;
4673                 } else {
4674                         cmd->speed = SPEED_10;
4675                         if (cp->link_cntl & BMCR_SPEED100) {
4676                                 cmd->speed = SPEED_100;
4677                         } else if (cp->link_cntl & CAS_BMCR_SPEED1000) {
4678                                 cmd->speed = SPEED_1000;
4679                         }
4680                         cmd->duplex = (cp->link_cntl & BMCR_FULLDPLX)?
4681                                 DUPLEX_FULL : DUPLEX_HALF;
4682                 }
4683         }
4684         return 0;
4685 }
4686
4687 static int cas_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4688 {
4689         struct cas *cp = netdev_priv(dev);
4690         unsigned long flags;
4691
4692         /* Verify the settings we care about. */
4693         if (cmd->autoneg != AUTONEG_ENABLE &&
4694             cmd->autoneg != AUTONEG_DISABLE)
4695                 return -EINVAL;
4696
4697         if (cmd->autoneg == AUTONEG_DISABLE &&
4698             ((cmd->speed != SPEED_1000 &&
4699               cmd->speed != SPEED_100 &&
4700               cmd->speed != SPEED_10) ||
4701              (cmd->duplex != DUPLEX_HALF &&
4702               cmd->duplex != DUPLEX_FULL)))
4703                 return -EINVAL;
4704
4705         /* Apply settings and restart link process. */
4706         spin_lock_irqsave(&cp->lock, flags);
4707         cas_begin_auto_negotiation(cp, cmd);
4708         spin_unlock_irqrestore(&cp->lock, flags);
4709         return 0;
4710 }
4711
4712 static int cas_nway_reset(struct net_device *dev)
4713 {
4714         struct cas *cp = netdev_priv(dev);
4715         unsigned long flags;
4716
4717         if ((cp->link_cntl & BMCR_ANENABLE) == 0)
4718                 return -EINVAL;
4719
4720         /* Restart link process. */
4721         spin_lock_irqsave(&cp->lock, flags);
4722         cas_begin_auto_negotiation(cp, NULL);
4723         spin_unlock_irqrestore(&cp->lock, flags);
4724
4725         return 0;
4726 }
4727
4728 static u32 cas_get_link(struct net_device *dev)
4729 {
4730         struct cas *cp = netdev_priv(dev);
4731         return cp->lstate == link_up;
4732 }
4733
4734 static u32 cas_get_msglevel(struct net_device *dev)
4735 {
4736         struct cas *cp = netdev_priv(dev);
4737         return cp->msg_enable;
4738 }
4739
4740 static void cas_set_msglevel(struct net_device *dev, u32 value)
4741 {
4742         struct cas *cp = netdev_priv(dev);
4743         cp->msg_enable = value;
4744 }
4745
4746 static int cas_get_regs_len(struct net_device *dev)
4747 {
4748         struct cas *cp = netdev_priv(dev);
4749         return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS;
4750 }
4751
4752 static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4753                              void *p)
4754 {
4755         struct cas *cp = netdev_priv(dev);
4756         regs->version = 0;
4757         /* cas_read_regs handles locks (cp->lock).  */
4758         cas_read_regs(cp, p, regs->len / sizeof(u32));
4759 }
4760
4761 static int cas_get_sset_count(struct net_device *dev, int sset)
4762 {
4763         switch (sset) {
4764         case ETH_SS_STATS:
4765                 return CAS_NUM_STAT_KEYS;
4766         default:
4767                 return -EOPNOTSUPP;
4768         }
4769 }
4770
4771 static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4772 {
4773          memcpy(data, &ethtool_cassini_statnames,
4774                                          CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN);
4775 }
4776
4777 static void cas_get_ethtool_stats(struct net_device *dev,
4778                                       struct ethtool_stats *estats, u64 *data)
4779 {
4780         struct cas *cp = netdev_priv(dev);
4781         struct net_device_stats *stats = cas_get_stats(cp->dev);
4782         int i = 0;
4783         data[i++] = stats->collisions;
4784         data[i++] = stats->rx_bytes;
4785         data[i++] = stats->rx_crc_errors;
4786         data[i++] = stats->rx_dropped;
4787         data[i++] = stats->rx_errors;
4788         data[i++] = stats->rx_fifo_errors;
4789         data[i++] = stats->rx_frame_errors;
4790         data[i++] = stats->rx_length_errors;
4791         data[i++] = stats->rx_over_errors;
4792         data[i++] = stats->rx_packets;
4793         data[i++] = stats->tx_aborted_errors;
4794         data[i++] = stats->tx_bytes;
4795         data[i++] = stats->tx_dropped;
4796         data[i++] = stats->tx_errors;
4797         data[i++] = stats->tx_fifo_errors;
4798         data[i++] = stats->tx_packets;
4799         BUG_ON(i != CAS_NUM_STAT_KEYS);
4800 }
4801
4802 static const struct ethtool_ops cas_ethtool_ops = {
4803         .get_drvinfo            = cas_get_drvinfo,
4804         .get_settings           = cas_get_settings,
4805         .set_settings           = cas_set_settings,
4806         .nway_reset             = cas_nway_reset,
4807         .get_link               = cas_get_link,
4808         .get_msglevel           = cas_get_msglevel,
4809         .set_msglevel           = cas_set_msglevel,
4810         .get_regs_len           = cas_get_regs_len,
4811         .get_regs               = cas_get_regs,
4812         .get_sset_count         = cas_get_sset_count,
4813         .get_strings            = cas_get_strings,
4814         .get_ethtool_stats      = cas_get_ethtool_stats,
4815 };
4816
4817 static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4818 {
4819         struct cas *cp = netdev_priv(dev);
4820         struct mii_ioctl_data *data = if_mii(ifr);
4821         unsigned long flags;
4822         int rc = -EOPNOTSUPP;
4823
4824         /* Hold the PM mutex while doing ioctl's or we may collide
4825          * with open/close and power management and oops.
4826          */
4827         mutex_lock(&cp->pm_mutex);
4828         switch (cmd) {
4829         case SIOCGMIIPHY:               /* Get address of MII PHY in use. */
4830                 data->phy_id = cp->phy_addr;
4831                 /* Fallthrough... */
4832
4833         case SIOCGMIIREG:               /* Read MII PHY register. */
4834                 spin_lock_irqsave(&cp->lock, flags);
4835                 cas_mif_poll(cp, 0);
4836                 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);
4837                 cas_mif_poll(cp, 1);
4838                 spin_unlock_irqrestore(&cp->lock, flags);
4839                 rc = 0;
4840                 break;
4841
4842         case SIOCSMIIREG:               /* Write MII PHY register. */
4843                 if (!capable(CAP_NET_ADMIN)) {
4844                         rc = -EPERM;
4845                         break;
4846                 }
4847                 spin_lock_irqsave(&cp->lock, flags);
4848                 cas_mif_poll(cp, 0);
4849                 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);
4850                 cas_mif_poll(cp, 1);
4851                 spin_unlock_irqrestore(&cp->lock, flags);
4852                 break;
4853         default:
4854                 break;
4855         };
4856
4857         mutex_unlock(&cp->pm_mutex);
4858         return rc;
4859 }
4860
4861 /* When this chip sits underneath an Intel 31154 bridge, it is the
4862  * only subordinate device and we can tweak the bridge settings to
4863  * reflect that fact.
4864  */
4865 static void __devinit cas_program_bridge(struct pci_dev *cas_pdev)
4866 {
4867         struct pci_dev *pdev = cas_pdev->bus->self;
4868         u32 val;
4869
4870         if (!pdev)
4871                 return;
4872
4873         if (pdev->vendor != 0x8086 || pdev->device != 0x537c)
4874                 return;
4875
4876         /* Clear bit 10 (Bus Parking Control) in the Secondary
4877          * Arbiter Control/Status Register which lives at offset
4878          * 0x41.  Using a 32-bit word read/modify/write at 0x40
4879          * is much simpler so that's how we do this.
4880          */
4881         pci_read_config_dword(pdev, 0x40, &val);
4882         val &= ~0x00040000;
4883         pci_write_config_dword(pdev, 0x40, val);
4884
4885         /* Max out the Multi-Transaction Timer settings since
4886          * Cassini is the only device present.
4887          *
4888          * The register is 16-bit and lives at 0x50.  When the
4889          * settings are enabled, it extends the GRANT# signal
4890          * for a requestor after a transaction is complete.  This
4891          * allows the next request to run without first needing
4892          * to negotiate the GRANT# signal back.
4893          *
4894          * Bits 12:10 define the grant duration:
4895          *
4896          *      1       --      16 clocks
4897          *      2       --      32 clocks
4898          *      3       --      64 clocks
4899          *      4       --      128 clocks
4900          *      5       --      256 clocks
4901          *
4902          * All other values are illegal.
4903          *
4904          * Bits 09:00 define which REQ/GNT signal pairs get the
4905          * GRANT# signal treatment.  We set them all.
4906          */
4907         pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff);
4908
4909         /* The Read Prefecth Policy register is 16-bit and sits at
4910          * offset 0x52.  It enables a "smart" pre-fetch policy.  We
4911          * enable it and max out all of the settings since only one
4912          * device is sitting underneath and thus bandwidth sharing is
4913          * not an issue.
4914          *
4915          * The register has several 3 bit fields, which indicates a
4916          * multiplier applied to the base amount of prefetching the
4917          * chip would do.  These fields are at:
4918          *
4919          *      15:13   ---     ReRead Primary Bus
4920          *      12:10   ---     FirstRead Primary Bus
4921          *      09:07   ---     ReRead Secondary Bus
4922          *      06:04   ---     FirstRead Secondary Bus
4923          *
4924          * Bits 03:00 control which REQ/GNT pairs the prefetch settings
4925          * get enabled on.  Bit 3 is a grouped enabler which controls
4926          * all of the REQ/GNT pairs from [8:3].  Bits 2 to 0 control
4927          * the individual REQ/GNT pairs [2:0].
4928          */
4929         pci_write_config_word(pdev, 0x52,
4930                               (0x7 << 13) |
4931                               (0x7 << 10) |
4932                               (0x7 <<  7) |
4933                               (0x7 <<  4) |
4934                               (0xf <<  0));
4935
4936         /* Force cacheline size to 0x8 */
4937         pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4938
4939         /* Force latency timer to maximum setting so Cassini can
4940          * sit on the bus as long as it likes.
4941          */
4942         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff);
4943 }
4944
4945 static int __devinit cas_init_one(struct pci_dev *pdev,
4946                                   const struct pci_device_id *ent)
4947 {
4948         static int cas_version_printed = 0;
4949         unsigned long casreg_len;
4950         struct net_device *dev;
4951         struct cas *cp;
4952         int i, err, pci_using_dac;
4953         u16 pci_cmd;
4954         u8 orig_cacheline_size = 0, cas_cacheline_size = 0;
4955         DECLARE_MAC_BUF(mac);
4956
4957         if (cas_version_printed++ == 0)
4958                 printk(KERN_INFO "%s", version);
4959
4960         err = pci_enable_device(pdev);
4961         if (err) {
4962                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
4963                 return err;
4964         }
4965
4966         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4967                 dev_err(&pdev->dev, "Cannot find proper PCI device "
4968                        "base address, aborting.\n");
4969                 err = -ENODEV;
4970                 goto err_out_disable_pdev;
4971         }
4972
4973         dev = alloc_etherdev(sizeof(*cp));
4974         if (!dev) {
4975                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting.\n");
4976                 err = -ENOMEM;
4977                 goto err_out_disable_pdev;
4978         }
4979         SET_NETDEV_DEV(dev, &pdev->dev);
4980
4981         err = pci_request_regions(pdev, dev->name);
4982         if (err) {
4983                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
4984                 goto err_out_free_netdev;
4985         }
4986         pci_set_master(pdev);
4987
4988         /* we must always turn on parity response or else parity
4989          * doesn't get generated properly. disable SERR/PERR as well.
4990          * in addition, we want to turn MWI on.
4991          */
4992         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4993         pci_cmd &= ~PCI_COMMAND_SERR;
4994         pci_cmd |= PCI_COMMAND_PARITY;
4995         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4996         if (pci_try_set_mwi(pdev))
4997                 printk(KERN_WARNING PFX "Could not enable MWI for %s\n",
4998                        pci_name(pdev));
4999
5000         cas_program_bridge(pdev);
5001
5002         /*
5003          * On some architectures, the default cache line size set
5004          * by pci_try_set_mwi reduces perforamnce.  We have to increase
5005          * it for this case.  To start, we'll print some configuration
5006          * data.
5007          */
5008 #if 1
5009         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
5010                              &orig_cacheline_size);
5011         if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) {
5012                 cas_cacheline_size =
5013                         (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ?
5014                         CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES;
5015                 if (pci_write_config_byte(pdev,
5016                                           PCI_CACHE_LINE_SIZE,
5017                                           cas_cacheline_size)) {
5018                         dev_err(&pdev->dev, "Could not set PCI cache "
5019                                "line size\n");
5020                         goto err_write_cacheline;
5021                 }
5022         }
5023 #endif
5024
5025
5026         /* Configure DMA attributes. */
5027         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
5028                 pci_using_dac = 1;
5029                 err = pci_set_consistent_dma_mask(pdev,
5030                                                   DMA_64BIT_MASK);
5031                 if (err < 0) {
5032                         dev_err(&pdev->dev, "Unable to obtain 64-bit DMA "
5033                                "for consistent allocations\n");
5034                         goto err_out_free_res;
5035                 }
5036
5037         } else {
5038                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
5039                 if (err) {
5040                         dev_err(&pdev->dev, "No usable DMA configuration, "
5041                                "aborting.\n");
5042                         goto err_out_free_res;
5043                 }
5044                 pci_using_dac = 0;
5045         }
5046
5047         casreg_len = pci_resource_len(pdev, 0);
5048
5049         cp = netdev_priv(dev);
5050         cp->pdev = pdev;
5051 #if 1
5052         /* A value of 0 indicates we never explicitly set it */
5053         cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0;
5054 #endif
5055         cp->dev = dev;
5056         cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE :
5057           cassini_debug;
5058
5059         cp->link_transition = LINK_TRANSITION_UNKNOWN;
5060         cp->link_transition_jiffies_valid = 0;
5061
5062         spin_lock_init(&cp->lock);
5063         spin_lock_init(&cp->rx_inuse_lock);
5064         spin_lock_init(&cp->rx_spare_lock);
5065         for (i = 0; i < N_TX_RINGS; i++) {
5066                 spin_lock_init(&cp->stat_lock[i]);
5067                 spin_lock_init(&cp->tx_lock[i]);
5068         }
5069         spin_lock_init(&cp->stat_lock[N_TX_RINGS]);
5070         mutex_init(&cp->pm_mutex);
5071
5072         init_timer(&cp->link_timer);
5073         cp->link_timer.function = cas_link_timer;
5074         cp->link_timer.data = (unsigned long) cp;
5075
5076 #if 1
5077         /* Just in case the implementation of atomic operations
5078          * change so that an explicit initialization is necessary.
5079          */
5080         atomic_set(&cp->reset_task_pending, 0);
5081         atomic_set(&cp->reset_task_pending_all, 0);
5082         atomic_set(&cp->reset_task_pending_spare, 0);
5083         atomic_set(&cp->reset_task_pending_mtu, 0);
5084 #endif
5085         INIT_WORK(&cp->reset_task, cas_reset_task);
5086
5087         /* Default link parameters */
5088         if (link_mode >= 0 && link_mode <= 6)
5089                 cp->link_cntl = link_modes[link_mode];
5090         else
5091                 cp->link_cntl = BMCR_ANENABLE;
5092         cp->lstate = link_down;
5093         cp->link_transition = LINK_TRANSITION_LINK_DOWN;
5094         netif_carrier_off(cp->dev);
5095         cp->timer_ticks = 0;
5096
5097         /* give us access to cassini registers */
5098         cp->regs = pci_iomap(pdev, 0, casreg_len);
5099         if (!cp->regs) {
5100                 dev_err(&pdev->dev, "Cannot map device registers, aborting.\n");
5101                 goto err_out_free_res;
5102         }
5103         cp->casreg_len = casreg_len;
5104
5105         pci_save_state(pdev);
5106         cas_check_pci_invariants(cp);
5107         cas_hard_reset(cp);
5108         cas_reset(cp, 0);
5109         if (cas_check_invariants(cp))
5110                 goto err_out_iounmap;
5111
5112         cp->init_block = (struct cas_init_block *)
5113                 pci_alloc_consistent(pdev, sizeof(struct cas_init_block),
5114                                      &cp->block_dvma);
5115         if (!cp->init_block) {
5116                 dev_err(&pdev->dev, "Cannot allocate init block, aborting.\n");
5117                 goto err_out_iounmap;
5118         }
5119
5120         for (i = 0; i < N_TX_RINGS; i++)
5121                 cp->init_txds[i] = cp->init_block->txds[i];
5122
5123         for (i = 0; i < N_RX_DESC_RINGS; i++)
5124                 cp->init_rxds[i] = cp->init_block->rxds[i];
5125
5126         for (i = 0; i < N_RX_COMP_RINGS; i++)
5127                 cp->init_rxcs[i] = cp->init_block->rxcs[i];
5128
5129         for (i = 0; i < N_RX_FLOWS; i++)
5130                 skb_queue_head_init(&cp->rx_flows[i]);
5131
5132         dev->open = cas_open;
5133         dev->stop = cas_close;
5134         dev->hard_start_xmit = cas_start_xmit;
5135         dev->get_stats = cas_get_stats;
5136         dev->set_multicast_list = cas_set_multicast;
5137         dev->do_ioctl = cas_ioctl;
5138         dev->ethtool_ops = &cas_ethtool_ops;
5139         dev->tx_timeout = cas_tx_timeout;
5140         dev->watchdog_timeo = CAS_TX_TIMEOUT;
5141         dev->change_mtu = cas_change_mtu;
5142 #ifdef USE_NAPI
5143         netif_napi_add(dev, &cp->napi, cas_poll, 64);
5144 #endif
5145 #ifdef CONFIG_NET_POLL_CONTROLLER
5146         dev->poll_controller = cas_netpoll;
5147 #endif
5148         dev->irq = pdev->irq;
5149         dev->dma = 0;
5150
5151         /* Cassini features. */
5152         if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0)
5153                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5154
5155         if (pci_using_dac)
5156                 dev->features |= NETIF_F_HIGHDMA;
5157
5158         if (register_netdev(dev)) {
5159                 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
5160                 goto err_out_free_consistent;
5161         }
5162
5163         i = readl(cp->regs + REG_BIM_CFG);
5164         printk(KERN_INFO "%s: Sun Cassini%s (%sbit/%sMHz PCI/%s) "
5165                "Ethernet[%d] %s\n",  dev->name,
5166                (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "",
5167                (i & BIM_CFG_32BIT) ? "32" : "64",
5168                (i & BIM_CFG_66MHZ) ? "66" : "33",
5169                (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq,
5170                print_mac(mac, dev->dev_addr));
5171
5172         pci_set_drvdata(pdev, dev);
5173         cp->hw_running = 1;
5174         cas_entropy_reset(cp);
5175         cas_phy_init(cp);
5176         cas_begin_auto_negotiation(cp, NULL);
5177         return 0;
5178
5179 err_out_free_consistent:
5180         pci_free_consistent(pdev, sizeof(struct cas_init_block),
5181                             cp->init_block, cp->block_dvma);
5182
5183 err_out_iounmap:
5184         mutex_lock(&cp->pm_mutex);
5185         if (cp->hw_running)
5186                 cas_shutdown(cp);
5187         mutex_unlock(&cp->pm_mutex);
5188
5189         pci_iounmap(pdev, cp->regs);
5190
5191
5192 err_out_free_res:
5193         pci_release_regions(pdev);
5194
5195 err_write_cacheline:
5196         /* Try to restore it in case the error occured after we
5197          * set it.
5198          */
5199         pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
5200
5201 err_out_free_netdev:
5202         free_netdev(dev);
5203
5204 err_out_disable_pdev:
5205         pci_disable_device(pdev);
5206         pci_set_drvdata(pdev, NULL);
5207         return -ENODEV;
5208 }
5209
5210 static void __devexit cas_remove_one(struct pci_dev *pdev)
5211 {
5212         struct net_device *dev = pci_get_drvdata(pdev);
5213         struct cas *cp;
5214         if (!dev)
5215                 return;
5216
5217         cp = netdev_priv(dev);
5218         unregister_netdev(dev);
5219
5220         mutex_lock(&cp->pm_mutex);
5221         flush_scheduled_work();
5222         if (cp->hw_running)
5223                 cas_shutdown(cp);
5224         mutex_unlock(&cp->pm_mutex);
5225
5226 #if 1
5227         if (cp->orig_cacheline_size) {
5228                 /* Restore the cache line size if we had modified
5229                  * it.
5230                  */
5231                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
5232                                       cp->orig_cacheline_size);
5233         }
5234 #endif
5235         pci_free_consistent(pdev, sizeof(struct cas_init_block),
5236                             cp->init_block, cp->block_dvma);
5237         pci_iounmap(pdev, cp->regs);
5238         free_netdev(dev);
5239         pci_release_regions(pdev);
5240         pci_disable_device(pdev);
5241         pci_set_drvdata(pdev, NULL);
5242 }
5243
5244 #ifdef CONFIG_PM
5245 static int cas_suspend(struct pci_dev *pdev, pm_message_t state)
5246 {
5247         struct net_device *dev = pci_get_drvdata(pdev);
5248         struct cas *cp = netdev_priv(dev);
5249         unsigned long flags;
5250
5251         mutex_lock(&cp->pm_mutex);
5252
5253         /* If the driver is opened, we stop the DMA */
5254         if (cp->opened) {
5255                 netif_device_detach(dev);
5256
5257                 cas_lock_all_save(cp, flags);
5258
5259                 /* We can set the second arg of cas_reset to 0
5260                  * because on resume, we'll call cas_init_hw with
5261                  * its second arg set so that autonegotiation is
5262                  * restarted.
5263                  */
5264                 cas_reset(cp, 0);
5265                 cas_clean_rings(cp);
5266                 cas_unlock_all_restore(cp, flags);
5267         }
5268
5269         if (cp->hw_running)
5270                 cas_shutdown(cp);
5271         mutex_unlock(&cp->pm_mutex);
5272
5273         return 0;
5274 }
5275
5276 static int cas_resume(struct pci_dev *pdev)
5277 {
5278         struct net_device *dev = pci_get_drvdata(pdev);
5279         struct cas *cp = netdev_priv(dev);
5280
5281         printk(KERN_INFO "%s: resuming\n", dev->name);
5282
5283         mutex_lock(&cp->pm_mutex);
5284         cas_hard_reset(cp);
5285         if (cp->opened) {
5286                 unsigned long flags;
5287                 cas_lock_all_save(cp, flags);
5288                 cas_reset(cp, 0);
5289                 cp->hw_running = 1;
5290                 cas_clean_rings(cp);
5291                 cas_init_hw(cp, 1);
5292                 cas_unlock_all_restore(cp, flags);
5293
5294                 netif_device_attach(dev);
5295         }
5296         mutex_unlock(&cp->pm_mutex);
5297         return 0;
5298 }
5299 #endif /* CONFIG_PM */
5300
5301 static struct pci_driver cas_driver = {
5302         .name           = DRV_MODULE_NAME,
5303         .id_table       = cas_pci_tbl,
5304         .probe          = cas_init_one,
5305         .remove         = __devexit_p(cas_remove_one),
5306 #ifdef CONFIG_PM
5307         .suspend        = cas_suspend,
5308         .resume         = cas_resume
5309 #endif
5310 };
5311
5312 static int __init cas_init(void)
5313 {
5314         if (linkdown_timeout > 0)
5315                 link_transition_timeout = linkdown_timeout * HZ;
5316         else
5317                 link_transition_timeout = 0;
5318
5319         return pci_register_driver(&cas_driver);
5320 }
5321
5322 static void __exit cas_cleanup(void)
5323 {
5324         pci_unregister_driver(&cas_driver);
5325 }
5326
5327 module_init(cas_init);
5328 module_exit(cas_cleanup);