2 * Freescale MPC85xx Memory Controller kenel module
4 * Author: Dave Jiang <djiang@mvista.com>
6 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/interrupt.h>
16 #include <linux/ctype.h>
18 #include <linux/mod_devicetable.h>
19 #include <linux/edac.h>
20 #include <linux/smp.h>
22 #include <linux/of_platform.h>
23 #include <linux/of_device.h>
24 #include "edac_module.h"
25 #include "edac_core.h"
26 #include "mpc85xx_edac.h"
28 static int edac_dev_idx;
29 static int edac_pci_idx;
30 static int edac_mc_idx;
32 static u32 orig_ddr_err_disable;
33 static u32 orig_ddr_err_sbe;
39 static u32 orig_pci_err_cap_dr;
40 static u32 orig_pci_err_en;
43 static u32 orig_l2_err_disable;
44 static u32 orig_hid1[2];
46 /************************ MC SYSFS parts ***********************************/
48 static ssize_t mpc85xx_mc_inject_data_hi_show(struct mem_ctl_info *mci,
51 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
52 return sprintf(data, "0x%08x",
53 in_be32(pdata->mc_vbase +
54 MPC85XX_MC_DATA_ERR_INJECT_HI));
57 static ssize_t mpc85xx_mc_inject_data_lo_show(struct mem_ctl_info *mci,
60 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
61 return sprintf(data, "0x%08x",
62 in_be32(pdata->mc_vbase +
63 MPC85XX_MC_DATA_ERR_INJECT_LO));
66 static ssize_t mpc85xx_mc_inject_ctrl_show(struct mem_ctl_info *mci, char *data)
68 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
69 return sprintf(data, "0x%08x",
70 in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT));
73 static ssize_t mpc85xx_mc_inject_data_hi_store(struct mem_ctl_info *mci,
74 const char *data, size_t count)
76 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
78 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI,
79 simple_strtoul(data, NULL, 0));
85 static ssize_t mpc85xx_mc_inject_data_lo_store(struct mem_ctl_info *mci,
86 const char *data, size_t count)
88 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
90 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO,
91 simple_strtoul(data, NULL, 0));
97 static ssize_t mpc85xx_mc_inject_ctrl_store(struct mem_ctl_info *mci,
98 const char *data, size_t count)
100 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
101 if (isdigit(*data)) {
102 out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT,
103 simple_strtoul(data, NULL, 0));
109 static struct mcidev_sysfs_attribute mpc85xx_mc_sysfs_attributes[] = {
112 .name = "inject_data_hi",
113 .mode = (S_IRUGO | S_IWUSR)
115 .show = mpc85xx_mc_inject_data_hi_show,
116 .store = mpc85xx_mc_inject_data_hi_store},
119 .name = "inject_data_lo",
120 .mode = (S_IRUGO | S_IWUSR)
122 .show = mpc85xx_mc_inject_data_lo_show,
123 .store = mpc85xx_mc_inject_data_lo_store},
126 .name = "inject_ctrl",
127 .mode = (S_IRUGO | S_IWUSR)
129 .show = mpc85xx_mc_inject_ctrl_show,
130 .store = mpc85xx_mc_inject_ctrl_store},
134 .attr = {.name = NULL}
138 static void mpc85xx_set_mc_sysfs_attributes(struct mem_ctl_info *mci)
140 mci->mc_driver_sysfs_attributes = mpc85xx_mc_sysfs_attributes;
143 /**************************** PCI Err device ***************************/
146 static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
148 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
151 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
153 /* master aborts can happen during PCI config cycles */
154 if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
155 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
159 printk(KERN_ERR "PCI error(s) detected\n");
160 printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect);
162 printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n",
163 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
164 printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n",
165 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
166 printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n",
167 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
168 printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n",
169 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
170 printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n",
171 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));
173 /* clear error bits */
174 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
176 if (err_detect & PCI_EDE_PERR_MASK)
177 edac_pci_handle_pe(pci, pci->ctl_name);
179 if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK)
180 edac_pci_handle_npe(pci, pci->ctl_name);
183 static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
185 struct edac_pci_ctl_info *pci = dev_id;
186 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
189 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
194 mpc85xx_pci_check(pci);
199 static int __devinit mpc85xx_pci_err_probe(struct of_device *op,
200 const struct of_device_id *match)
202 struct edac_pci_ctl_info *pci;
203 struct mpc85xx_pci_pdata *pdata;
207 if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL))
210 pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err");
214 pdata = pci->pvt_info;
215 pdata->name = "mpc85xx_pci_err";
217 dev_set_drvdata(&op->dev, pci);
219 pci->mod_name = EDAC_MOD_STR;
220 pci->ctl_name = pdata->name;
221 pci->dev_name = op->dev.bus_id;
223 if (edac_op_state == EDAC_OPSTATE_POLL)
224 pci->edac_check = mpc85xx_pci_check;
226 pdata->edac_idx = edac_pci_idx++;
228 res = of_address_to_resource(op->node, 0, &r);
230 printk(KERN_ERR "%s: Unable to get resource for "
231 "PCI err regs\n", __func__);
235 /* we only need the error registers */
238 if (!devm_request_mem_region(&op->dev, r.start,
239 r.end - r.start + 1, pdata->name)) {
240 printk(KERN_ERR "%s: Error while requesting mem region\n",
246 pdata->pci_vbase = devm_ioremap(&op->dev, r.start,
247 r.end - r.start + 1);
248 if (!pdata->pci_vbase) {
249 printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__);
254 orig_pci_err_cap_dr =
255 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
257 /* PCI master abort is expected during config cycles */
258 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
260 orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
262 /* disable master abort reporting */
263 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
265 /* clear error bits */
266 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
268 if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
269 debugf3("%s(): failed edac_pci_add_device()\n", __func__);
273 if (edac_op_state == EDAC_OPSTATE_INT) {
274 pdata->irq = irq_of_parse_and_map(op->node, 0);
275 res = devm_request_irq(&op->dev, pdata->irq,
276 mpc85xx_pci_isr, IRQF_DISABLED,
277 "[EDAC] PCI err", pci);
280 "%s: Unable to requiest irq %d for "
281 "MPC85xx PCI err\n", __func__, pdata->irq);
282 irq_dispose_mapping(pdata->irq);
287 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n",
291 devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
292 debugf3("%s(): success\n", __func__);
293 printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n");
298 edac_pci_del_device(&op->dev);
300 edac_pci_free_ctl_info(pci);
301 devres_release_group(&op->dev, mpc85xx_pci_err_probe);
305 static int mpc85xx_pci_err_remove(struct of_device *op)
307 struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev);
308 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
310 debugf0("%s()\n", __func__);
312 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR,
313 orig_pci_err_cap_dr);
315 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en);
317 edac_pci_del_device(pci->dev);
319 if (edac_op_state == EDAC_OPSTATE_INT)
320 irq_dispose_mapping(pdata->irq);
322 edac_pci_free_ctl_info(pci);
327 static struct of_device_id mpc85xx_pci_err_of_match[] = {
329 .compatible = "fsl,mpc8540-pcix",
332 .compatible = "fsl,mpc8540-pci",
337 static struct of_platform_driver mpc85xx_pci_err_driver = {
338 .owner = THIS_MODULE,
339 .name = "mpc85xx_pci_err",
340 .match_table = mpc85xx_pci_err_of_match,
341 .probe = mpc85xx_pci_err_probe,
342 .remove = __devexit_p(mpc85xx_pci_err_remove),
344 .name = "mpc85xx_pci_err",
345 .owner = THIS_MODULE,
349 #endif /* CONFIG_PCI */
351 /**************************** L2 Err device ***************************/
353 /************************ L2 SYSFS parts ***********************************/
355 static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info
356 *edac_dev, char *data)
358 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
359 return sprintf(data, "0x%08x",
360 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI));
363 static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info
364 *edac_dev, char *data)
366 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
367 return sprintf(data, "0x%08x",
368 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO));
371 static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info
372 *edac_dev, char *data)
374 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
375 return sprintf(data, "0x%08x",
376 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL));
379 static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info
380 *edac_dev, const char *data,
383 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
384 if (isdigit(*data)) {
385 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI,
386 simple_strtoul(data, NULL, 0));
392 static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info
393 *edac_dev, const char *data,
396 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
397 if (isdigit(*data)) {
398 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO,
399 simple_strtoul(data, NULL, 0));
405 static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info
406 *edac_dev, const char *data,
409 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
410 if (isdigit(*data)) {
411 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL,
412 simple_strtoul(data, NULL, 0));
418 static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = {
421 .name = "inject_data_hi",
422 .mode = (S_IRUGO | S_IWUSR)
424 .show = mpc85xx_l2_inject_data_hi_show,
425 .store = mpc85xx_l2_inject_data_hi_store},
428 .name = "inject_data_lo",
429 .mode = (S_IRUGO | S_IWUSR)
431 .show = mpc85xx_l2_inject_data_lo_show,
432 .store = mpc85xx_l2_inject_data_lo_store},
435 .name = "inject_ctrl",
436 .mode = (S_IRUGO | S_IWUSR)
438 .show = mpc85xx_l2_inject_ctrl_show,
439 .store = mpc85xx_l2_inject_ctrl_store},
443 .attr = {.name = NULL}
447 static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info
450 edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes;
453 /***************************** L2 ops ***********************************/
455 static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev)
457 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
460 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
462 if (!(err_detect & L2_EDE_MASK))
465 printk(KERN_ERR "ECC Error in CPU L2 cache\n");
466 printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect);
467 printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n",
468 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI));
469 printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n",
470 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO));
471 printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n",
472 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC));
473 printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n",
474 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR));
475 printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n",
476 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR));
478 /* clear error detect register */
479 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect);
481 if (err_detect & L2_EDE_CE_MASK)
482 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
484 if (err_detect & L2_EDE_UE_MASK)
485 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
488 static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id)
490 struct edac_device_ctl_info *edac_dev = dev_id;
491 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
494 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
496 if (!(err_detect & L2_EDE_MASK))
499 mpc85xx_l2_check(edac_dev);
504 static int __devinit mpc85xx_l2_err_probe(struct of_device *op,
505 const struct of_device_id *match)
507 struct edac_device_ctl_info *edac_dev;
508 struct mpc85xx_l2_pdata *pdata;
512 if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL))
515 edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata),
516 "cpu", 1, "L", 1, 2, NULL, 0,
519 devres_release_group(&op->dev, mpc85xx_l2_err_probe);
523 pdata = edac_dev->pvt_info;
524 pdata->name = "mpc85xx_l2_err";
526 edac_dev->dev = &op->dev;
527 dev_set_drvdata(edac_dev->dev, edac_dev);
528 edac_dev->ctl_name = pdata->name;
529 edac_dev->dev_name = pdata->name;
531 res = of_address_to_resource(op->node, 0, &r);
533 printk(KERN_ERR "%s: Unable to get resource for "
534 "L2 err regs\n", __func__);
538 /* we only need the error registers */
541 if (!devm_request_mem_region(&op->dev, r.start,
542 r.end - r.start + 1, pdata->name)) {
543 printk(KERN_ERR "%s: Error while requesting mem region\n",
549 pdata->l2_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1);
550 if (!pdata->l2_vbase) {
551 printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__);
556 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0);
558 orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS);
560 /* clear the err_dis */
561 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0);
563 edac_dev->mod_name = EDAC_MOD_STR;
565 if (edac_op_state == EDAC_OPSTATE_POLL)
566 edac_dev->edac_check = mpc85xx_l2_check;
568 mpc85xx_set_l2_sysfs_attributes(edac_dev);
570 pdata->edac_idx = edac_dev_idx++;
572 if (edac_device_add_device(edac_dev) > 0) {
573 debugf3("%s(): failed edac_device_add_device()\n", __func__);
577 if (edac_op_state == EDAC_OPSTATE_INT) {
578 pdata->irq = irq_of_parse_and_map(op->node, 0);
579 res = devm_request_irq(&op->dev, pdata->irq,
580 mpc85xx_l2_isr, IRQF_DISABLED,
581 "[EDAC] L2 err", edac_dev);
584 "%s: Unable to requiest irq %d for "
585 "MPC85xx L2 err\n", __func__, pdata->irq);
586 irq_dispose_mapping(pdata->irq);
591 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n",
594 edac_dev->op_state = OP_RUNNING_INTERRUPT;
596 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK);
599 devres_remove_group(&op->dev, mpc85xx_l2_err_probe);
601 debugf3("%s(): success\n", __func__);
602 printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n");
607 edac_device_del_device(&op->dev);
609 devres_release_group(&op->dev, mpc85xx_l2_err_probe);
610 edac_device_free_ctl_info(edac_dev);
614 static int mpc85xx_l2_err_remove(struct of_device *op)
616 struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev);
617 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
619 debugf0("%s()\n", __func__);
621 if (edac_op_state == EDAC_OPSTATE_INT) {
622 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0);
623 irq_dispose_mapping(pdata->irq);
626 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable);
627 edac_device_del_device(&op->dev);
628 edac_device_free_ctl_info(edac_dev);
632 static struct of_device_id mpc85xx_l2_err_of_match[] = {
634 .compatible = "fsl,8540-l2-cache-controller",
637 .compatible = "fsl,8541-l2-cache-controller",
640 .compatible = "fsl,8544-l2-cache-controller",
643 .compatible = "fsl,8548-l2-cache-controller",
646 .compatible = "fsl,8555-l2-cache-controller",
649 .compatible = "fsl,8568-l2-cache-controller",
652 .compatible = "fsl,mpc8572-l2-cache-controller",
657 static struct of_platform_driver mpc85xx_l2_err_driver = {
658 .owner = THIS_MODULE,
659 .name = "mpc85xx_l2_err",
660 .match_table = mpc85xx_l2_err_of_match,
661 .probe = mpc85xx_l2_err_probe,
662 .remove = mpc85xx_l2_err_remove,
664 .name = "mpc85xx_l2_err",
665 .owner = THIS_MODULE,
669 /**************************** MC Err device ***************************/
671 static void mpc85xx_mc_check(struct mem_ctl_info *mci)
673 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
674 struct csrow_info *csrow;
681 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
685 mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
688 /* no more processing if not ECC bit errors */
689 if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
690 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
694 syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC);
695 err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS);
696 pfn = err_addr >> PAGE_SHIFT;
698 for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
699 csrow = &mci->csrows[row_index];
700 if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page))
704 mpc85xx_mc_printk(mci, KERN_ERR, "Capture Data High: %#8.8x\n",
705 in_be32(pdata->mc_vbase +
706 MPC85XX_MC_CAPTURE_DATA_HI));
707 mpc85xx_mc_printk(mci, KERN_ERR, "Capture Data Low: %#8.8x\n",
708 in_be32(pdata->mc_vbase +
709 MPC85XX_MC_CAPTURE_DATA_LO));
710 mpc85xx_mc_printk(mci, KERN_ERR, "syndrome: %#8.8x\n", syndrome);
711 mpc85xx_mc_printk(mci, KERN_ERR, "err addr: %#8.8x\n", err_addr);
712 mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
714 /* we are out of range */
715 if (row_index == mci->nr_csrows)
716 mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
718 if (err_detect & DDR_EDE_SBE)
719 edac_mc_handle_ce(mci, pfn, err_addr & PAGE_MASK,
720 syndrome, row_index, 0, mci->ctl_name);
722 if (err_detect & DDR_EDE_MBE)
723 edac_mc_handle_ue(mci, pfn, err_addr & PAGE_MASK,
724 row_index, mci->ctl_name);
726 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
729 static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id)
731 struct mem_ctl_info *mci = dev_id;
732 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
735 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
739 mpc85xx_mc_check(mci);
744 static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci)
746 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
747 struct csrow_info *csrow;
754 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
756 sdtype = sdram_ctl & DSC_SDTYPE_MASK;
757 if (sdram_ctl & DSC_RD_EN) {
762 case DSC_SDTYPE_DDR2:
774 case DSC_SDTYPE_DDR2:
783 for (index = 0; index < mci->nr_csrows; index++) {
787 csrow = &mci->csrows[index];
788 cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 +
789 (index * MPC85XX_MC_CS_BNDS_OFS));
790 start = (cs_bnds & 0xfff0000) << 4;
791 end = ((cs_bnds & 0xfff) << 20);
798 continue; /* not populated */
800 csrow->first_page = start >> PAGE_SHIFT;
801 csrow->last_page = end >> PAGE_SHIFT;
802 csrow->nr_pages = csrow->last_page + 1 - csrow->first_page;
804 csrow->mtype = mtype;
805 csrow->dtype = DEV_UNKNOWN;
806 if (sdram_ctl & DSC_X32_EN)
807 csrow->dtype = DEV_X32;
808 csrow->edac_mode = EDAC_SECDED;
812 static int __devinit mpc85xx_mc_err_probe(struct of_device *op,
813 const struct of_device_id *match)
815 struct mem_ctl_info *mci;
816 struct mpc85xx_mc_pdata *pdata;
821 if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL))
824 mci = edac_mc_alloc(sizeof(*pdata), 4, 1, edac_mc_idx);
826 devres_release_group(&op->dev, mpc85xx_mc_err_probe);
830 pdata = mci->pvt_info;
831 pdata->name = "mpc85xx_mc_err";
834 pdata->edac_idx = edac_mc_idx++;
835 dev_set_drvdata(mci->dev, mci);
836 mci->ctl_name = pdata->name;
837 mci->dev_name = pdata->name;
839 res = of_address_to_resource(op->node, 0, &r);
841 printk(KERN_ERR "%s: Unable to get resource for MC err regs\n",
846 if (!devm_request_mem_region(&op->dev, r.start,
847 r.end - r.start + 1, pdata->name)) {
848 printk(KERN_ERR "%s: Error while requesting mem region\n",
854 pdata->mc_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1);
855 if (!pdata->mc_vbase) {
856 printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__);
861 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
862 if (!(sdram_ctl & DSC_ECC_EN)) {
864 printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__);
869 debugf3("%s(): init mci\n", __func__);
870 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 |
871 MEM_FLAG_DDR | MEM_FLAG_DDR2;
872 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
873 mci->edac_cap = EDAC_FLAG_SECDED;
874 mci->mod_name = EDAC_MOD_STR;
875 mci->mod_ver = MPC85XX_REVISION;
877 if (edac_op_state == EDAC_OPSTATE_POLL)
878 mci->edac_check = mpc85xx_mc_check;
880 mci->ctl_page_to_phys = NULL;
882 mci->scrub_mode = SCRUB_SW_SRC;
884 mpc85xx_set_mc_sysfs_attributes(mci);
886 mpc85xx_init_csrows(mci);
888 #ifdef CONFIG_EDAC_DEBUG
889 edac_mc_register_mcidev_debug((struct attribute **)debug_attr);
892 /* store the original error disable bits */
893 orig_ddr_err_disable =
894 in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE);
895 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0);
897 /* clear all error bits */
898 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0);
900 if (edac_mc_add_mc(mci)) {
901 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
905 if (edac_op_state == EDAC_OPSTATE_INT) {
906 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN,
907 DDR_EIE_MBEE | DDR_EIE_SBEE);
909 /* store the original error management threshold */
910 orig_ddr_err_sbe = in_be32(pdata->mc_vbase +
911 MPC85XX_MC_ERR_SBE) & 0xff0000;
913 /* set threshold to 1 error per interrupt */
914 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000);
916 /* register interrupts */
917 pdata->irq = irq_of_parse_and_map(op->node, 0);
918 res = devm_request_irq(&op->dev, pdata->irq,
920 IRQF_DISABLED | IRQF_SHARED,
921 "[EDAC] MC err", mci);
923 printk(KERN_ERR "%s: Unable to request irq %d for "
924 "MPC85xx DRAM ERR\n", __func__, pdata->irq);
925 irq_dispose_mapping(pdata->irq);
930 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n",
934 devres_remove_group(&op->dev, mpc85xx_mc_err_probe);
935 debugf3("%s(): success\n", __func__);
936 printk(KERN_INFO EDAC_MOD_STR " MC err registered\n");
941 edac_mc_del_mc(&op->dev);
943 devres_release_group(&op->dev, mpc85xx_mc_err_probe);
948 static int mpc85xx_mc_err_remove(struct of_device *op)
950 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
951 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
953 debugf0("%s()\n", __func__);
955 if (edac_op_state == EDAC_OPSTATE_INT) {
956 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0);
957 irq_dispose_mapping(pdata->irq);
960 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE,
961 orig_ddr_err_disable);
962 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe);
964 edac_mc_del_mc(&op->dev);
969 static struct of_device_id mpc85xx_mc_err_of_match[] = {
971 .compatible = "fsl,8540-memory-controller",
974 .compatible = "fsl,8541-memory-controller",
977 .compatible = "fsl,8544-memory-controller",
980 .compatible = "fsl,8548-memory-controller",
983 .compatible = "fsl,8555-memory-controller",
986 .compatible = "fsl,8568-memory-controller",
989 .compatible = "fsl,mpc8572-memory-controller",
994 static struct of_platform_driver mpc85xx_mc_err_driver = {
995 .owner = THIS_MODULE,
996 .name = "mpc85xx_mc_err",
997 .match_table = mpc85xx_mc_err_of_match,
998 .probe = mpc85xx_mc_err_probe,
999 .remove = mpc85xx_mc_err_remove,
1001 .name = "mpc85xx_mc_err",
1002 .owner = THIS_MODULE,
1007 static void __init mpc85xx_mc_clear_rfxe(void *data)
1009 orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1);
1010 mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~0x20000));
1014 static int __init mpc85xx_mc_init(void)
1018 printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, "
1019 "(C) 2006 Montavista Software\n");
1021 /* make sure error reporting method is sane */
1022 switch (edac_op_state) {
1023 case EDAC_OPSTATE_POLL:
1024 case EDAC_OPSTATE_INT:
1027 edac_op_state = EDAC_OPSTATE_INT;
1031 res = of_register_platform_driver(&mpc85xx_mc_err_driver);
1033 printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n");
1035 res = of_register_platform_driver(&mpc85xx_l2_err_driver);
1037 printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n");
1040 res = of_register_platform_driver(&mpc85xx_pci_err_driver);
1042 printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n");
1046 * need to clear HID1[RFXE] to disable machine check int
1047 * so we can catch it
1049 if (edac_op_state == EDAC_OPSTATE_INT)
1050 on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
1055 module_init(mpc85xx_mc_init);
1057 static void __exit mpc85xx_mc_restore_hid1(void *data)
1059 mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]);
1062 static void __exit mpc85xx_mc_exit(void)
1064 on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
1066 of_unregister_platform_driver(&mpc85xx_pci_err_driver);
1068 of_unregister_platform_driver(&mpc85xx_l2_err_driver);
1069 of_unregister_platform_driver(&mpc85xx_mc_err_driver);
1072 module_exit(mpc85xx_mc_exit);
1074 MODULE_LICENSE("GPL");
1075 MODULE_AUTHOR("Montavista Software, Inc.");
1076 module_param(edac_op_state, int, 0444);
1077 MODULE_PARM_DESC(edac_op_state,
1078 "EDAC Error Reporting state: 0=Poll, 2=Interrupt");