2 * Copyright (c) 2006 QLogic, Inc. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/spinlock.h>
35 #include <linux/idr.h>
36 #include <linux/pci.h>
37 #include <linux/delay.h>
38 #include <linux/netdevice.h>
39 #include <linux/vmalloc.h>
41 #include "ipath_kernel.h"
42 #include "ipath_verbs.h"
43 #include "ipath_common.h"
45 static void ipath_update_pio_bufs(struct ipath_devdata *);
47 const char *ipath_get_unit_name(int unit)
49 static char iname[16];
50 snprintf(iname, sizeof iname, "infinipath%u", unit);
54 #define DRIVER_LOAD_MSG "QLogic " IPATH_DRV_NAME " loaded: "
55 #define PFX IPATH_DRV_NAME ": "
58 * The size has to be longer than this string, so we can append
59 * board/chip information to it in the init code.
61 const char ib_ipath_version[] = IPATH_IDSTR "\n";
63 static struct idr unit_table;
64 DEFINE_SPINLOCK(ipath_devs_lock);
65 LIST_HEAD(ipath_dev_list);
67 wait_queue_head_t ipath_state_wait;
69 unsigned ipath_debug = __IPATH_INFO;
71 module_param_named(debug, ipath_debug, uint, S_IWUSR | S_IRUGO);
72 MODULE_PARM_DESC(debug, "mask for debug prints");
73 EXPORT_SYMBOL_GPL(ipath_debug);
75 MODULE_LICENSE("GPL");
76 MODULE_AUTHOR("QLogic <support@pathscale.com>");
77 MODULE_DESCRIPTION("QLogic InfiniPath driver");
79 const char *ipath_ibcstatus_str[] = {
86 "LState6", /* unused */
87 "LState7", /* unused */
93 "LState0xD", /* unused */
98 static void __devexit ipath_remove_one(struct pci_dev *);
99 static int __devinit ipath_init_one(struct pci_dev *,
100 const struct pci_device_id *);
102 /* Only needed for registration, nothing else needs this info */
103 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1
104 #define PCI_DEVICE_ID_INFINIPATH_HT 0xd
105 #define PCI_DEVICE_ID_INFINIPATH_PE800 0x10
107 static const struct pci_device_id ipath_pci_tbl[] = {
108 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_HT) },
109 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_PE800) },
113 MODULE_DEVICE_TABLE(pci, ipath_pci_tbl);
115 static struct pci_driver ipath_driver = {
116 .name = IPATH_DRV_NAME,
117 .probe = ipath_init_one,
118 .remove = __devexit_p(ipath_remove_one),
119 .id_table = ipath_pci_tbl,
123 static inline void read_bars(struct ipath_devdata *dd, struct pci_dev *dev,
124 u32 *bar0, u32 *bar1)
128 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
130 ipath_dev_err(dd, "failed to read bar0 before enable: "
133 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, bar1);
135 ipath_dev_err(dd, "failed to read bar1 before enable: "
138 ipath_dbg("Read bar0 %x bar1 %x\n", *bar0, *bar1);
141 static void ipath_free_devdata(struct pci_dev *pdev,
142 struct ipath_devdata *dd)
146 pci_set_drvdata(pdev, NULL);
148 if (dd->ipath_unit != -1) {
149 spin_lock_irqsave(&ipath_devs_lock, flags);
150 idr_remove(&unit_table, dd->ipath_unit);
151 list_del(&dd->ipath_list);
152 spin_unlock_irqrestore(&ipath_devs_lock, flags);
157 static struct ipath_devdata *ipath_alloc_devdata(struct pci_dev *pdev)
160 struct ipath_devdata *dd;
163 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
164 dd = ERR_PTR(-ENOMEM);
168 dd = vmalloc(sizeof(*dd));
170 dd = ERR_PTR(-ENOMEM);
173 memset(dd, 0, sizeof(*dd));
176 spin_lock_irqsave(&ipath_devs_lock, flags);
178 ret = idr_get_new(&unit_table, dd, &dd->ipath_unit);
180 printk(KERN_ERR IPATH_DRV_NAME
181 ": Could not allocate unit ID: error %d\n", -ret);
182 ipath_free_devdata(pdev, dd);
188 pci_set_drvdata(pdev, dd);
190 list_add(&dd->ipath_list, &ipath_dev_list);
193 spin_unlock_irqrestore(&ipath_devs_lock, flags);
199 static inline struct ipath_devdata *__ipath_lookup(int unit)
201 return idr_find(&unit_table, unit);
204 struct ipath_devdata *ipath_lookup(int unit)
206 struct ipath_devdata *dd;
209 spin_lock_irqsave(&ipath_devs_lock, flags);
210 dd = __ipath_lookup(unit);
211 spin_unlock_irqrestore(&ipath_devs_lock, flags);
216 int ipath_count_units(int *npresentp, int *nupp, u32 *maxportsp)
218 int nunits, npresent, nup;
219 struct ipath_devdata *dd;
223 nunits = npresent = nup = maxports = 0;
225 spin_lock_irqsave(&ipath_devs_lock, flags);
227 list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
229 if ((dd->ipath_flags & IPATH_PRESENT) && dd->ipath_kregbase)
232 !(dd->ipath_flags & (IPATH_DISABLED | IPATH_LINKDOWN
235 if (dd->ipath_cfgports > maxports)
236 maxports = dd->ipath_cfgports;
239 spin_unlock_irqrestore(&ipath_devs_lock, flags);
242 *npresentp = npresent;
246 *maxportsp = maxports;
252 * These next two routines are placeholders in case we don't have per-arch
253 * code for controlling write combining. If explicit control of write
254 * combining is not available, performance will probably be awful.
257 int __attribute__((weak)) ipath_enable_wc(struct ipath_devdata *dd)
262 void __attribute__((weak)) ipath_disable_wc(struct ipath_devdata *dd)
266 static int __devinit ipath_init_one(struct pci_dev *pdev,
267 const struct pci_device_id *ent)
270 struct ipath_devdata *dd;
271 unsigned long long addr;
272 u32 bar0 = 0, bar1 = 0;
275 dd = ipath_alloc_devdata(pdev);
278 printk(KERN_ERR IPATH_DRV_NAME
279 ": Could not allocate devdata: error %d\n", -ret);
283 ipath_cdbg(VERBOSE, "initializing unit #%u\n", dd->ipath_unit);
285 read_bars(dd, pdev, &bar0, &bar1);
287 ret = pci_enable_device(pdev);
289 /* This can happen iff:
291 * We did a chip reset, and then failed to reprogram the
292 * BAR, or the chip reset due to an internal error. We then
293 * unloaded the driver and reloaded it.
295 * Both reset cases set the BAR back to initial state. For
296 * the latter case, the AER sticky error bit at offset 0x718
297 * should be set, but the Linux kernel doesn't yet know
298 * about that, it appears. If the original BAR was retained
299 * in the kernel data structures, this may be OK.
301 ipath_dev_err(dd, "enable unit %d failed: error %d\n",
302 dd->ipath_unit, -ret);
305 addr = pci_resource_start(pdev, 0);
306 len = pci_resource_len(pdev, 0);
307 ipath_cdbg(VERBOSE, "regbase (0) %llx len %d pdev->irq %d, vend %x/%x "
308 "driver_data %lx\n", addr, len, pdev->irq, ent->vendor,
309 ent->device, ent->driver_data);
311 read_bars(dd, pdev, &bar0, &bar1);
313 if (!bar1 && !(bar0 & ~0xf)) {
315 dev_info(&pdev->dev, "BAR is 0 (probable RESET), "
316 "rewriting as %llx\n", addr);
317 ret = pci_write_config_dword(
318 pdev, PCI_BASE_ADDRESS_0, addr);
320 ipath_dev_err(dd, "rewrite of BAR0 "
321 "failed: err %d\n", -ret);
324 ret = pci_write_config_dword(
325 pdev, PCI_BASE_ADDRESS_1, addr >> 32);
327 ipath_dev_err(dd, "rewrite of BAR1 "
328 "failed: err %d\n", -ret);
332 ipath_dev_err(dd, "BAR is 0 (probable RESET), "
333 "not usable until reboot\n");
339 ret = pci_request_regions(pdev, IPATH_DRV_NAME);
341 dev_info(&pdev->dev, "pci_request_regions unit %u fails: "
342 "err %d\n", dd->ipath_unit, -ret);
346 ret = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
349 * if the 64 bit setup fails, try 32 bit. Some systems
350 * do not setup 64 bit maps on systems with 2GB or less
353 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
356 "Unable to set DMA mask for unit %u: %d\n",
357 dd->ipath_unit, ret);
361 ipath_dbg("No 64bit DMA mask, used 32 bit mask\n");
362 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
365 "Unable to set DMA consistent mask "
367 dd->ipath_unit, ret);
372 ret = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
375 "Unable to set DMA consistent mask "
377 dd->ipath_unit, ret);
380 pci_set_master(pdev);
383 * Save BARs to rewrite after device reset. Save all 64 bits of
386 dd->ipath_pcibar0 = addr;
387 dd->ipath_pcibar1 = addr >> 32;
388 dd->ipath_deviceid = ent->device; /* save for later use */
389 dd->ipath_vendorid = ent->vendor;
391 /* setup the chip-specific functions, as early as possible. */
392 switch (ent->device) {
394 case PCI_DEVICE_ID_INFINIPATH_HT:
395 ipath_init_iba6110_funcs(dd);
398 #ifdef CONFIG_PCI_MSI
399 case PCI_DEVICE_ID_INFINIPATH_PE800:
400 ipath_init_iba6120_funcs(dd);
404 ipath_dev_err(dd, "Found unknown QLogic deviceid 0x%x, "
405 "failing\n", ent->device);
409 for (j = 0; j < 6; j++) {
410 if (!pdev->resource[j].start)
412 ipath_cdbg(VERBOSE, "BAR %d start %llx, end %llx, len %llx\n",
413 j, (unsigned long long)pdev->resource[j].start,
414 (unsigned long long)pdev->resource[j].end,
415 (unsigned long long)pci_resource_len(pdev, j));
419 ipath_dev_err(dd, "No valid address in BAR 0!\n");
424 dd->ipath_deviceid = ent->device; /* save for later use */
425 dd->ipath_vendorid = ent->vendor;
427 ret = pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
429 ipath_dev_err(dd, "Failed to read PCI revision ID unit "
430 "%u: err %d\n", dd->ipath_unit, -ret);
431 goto bail_regions; /* shouldn't ever happen */
433 dd->ipath_pcirev = rev;
435 #if defined(__powerpc__)
436 /* There isn't a generic way to specify writethrough mappings */
437 dd->ipath_kregbase = __ioremap(addr, len,
438 (_PAGE_NO_CACHE|_PAGE_WRITETHRU));
440 dd->ipath_kregbase = ioremap_nocache(addr, len);
443 if (!dd->ipath_kregbase) {
444 ipath_dbg("Unable to map io addr %llx to kvirt, failing\n",
449 dd->ipath_kregend = (u64 __iomem *)
450 ((void __iomem *)dd->ipath_kregbase + len);
451 dd->ipath_physaddr = addr; /* used for io_remap, etc. */
453 ipath_cdbg(VERBOSE, "mapped io addr %llx to kregbase %p\n",
454 addr, dd->ipath_kregbase);
457 * clear ipath_flags here instead of in ipath_init_chip as it is set
458 * by ipath_setup_htconfig.
461 dd->ipath_lli_counter = 0;
462 dd->ipath_lli_errors = 0;
464 if (dd->ipath_f_bus(dd, pdev))
465 ipath_dev_err(dd, "Failed to setup config space; "
466 "continuing anyway\n");
469 * set up our interrupt handler; IRQF_SHARED probably not needed,
470 * since MSI interrupts shouldn't be shared but won't hurt for now.
471 * check 0 irq after we return from chip-specific bus setup, since
472 * that can affect this due to setup
475 ipath_dev_err(dd, "irq is 0, BIOS error? Interrupts won't "
478 ret = request_irq(dd->ipath_irq, ipath_intr, IRQF_SHARED,
481 ipath_dev_err(dd, "Couldn't setup irq handler, "
482 "irq=%d: %d\n", dd->ipath_irq, ret);
487 ret = ipath_init_chip(dd, 0); /* do the chip-specific init */
491 ret = ipath_enable_wc(dd);
494 ipath_dev_err(dd, "Write combining not enabled "
495 "(err %d): performance may be poor\n",
500 ipath_device_create_group(&pdev->dev, dd);
501 ipathfs_add_device(dd);
504 ipath_register_ib_device(dd);
509 if (pdev->irq) free_irq(pdev->irq, dd);
512 iounmap((volatile void __iomem *) dd->ipath_kregbase);
515 pci_release_regions(pdev);
518 pci_disable_device(pdev);
521 ipath_free_devdata(pdev, dd);
527 static void __devexit cleanup_device(struct ipath_devdata *dd)
531 ipath_shutdown_device(dd);
533 if (*dd->ipath_statusp & IPATH_STATUS_CHIP_PRESENT) {
534 /* can't do anything more with chip; needs re-init */
535 *dd->ipath_statusp &= ~IPATH_STATUS_CHIP_PRESENT;
536 if (dd->ipath_kregbase) {
538 * if we haven't already cleaned up before these are
539 * to ensure any register reads/writes "fail" until
542 dd->ipath_kregbase = NULL;
543 dd->ipath_uregbase = 0;
544 dd->ipath_sregbase = 0;
545 dd->ipath_cregbase = 0;
546 dd->ipath_kregsize = 0;
548 ipath_disable_wc(dd);
551 if (dd->ipath_pioavailregs_dma) {
552 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
553 (void *) dd->ipath_pioavailregs_dma,
554 dd->ipath_pioavailregs_phys);
555 dd->ipath_pioavailregs_dma = NULL;
557 if (dd->ipath_dummy_hdrq) {
558 dma_free_coherent(&dd->pcidev->dev,
559 dd->ipath_pd[0]->port_rcvhdrq_size,
560 dd->ipath_dummy_hdrq, dd->ipath_dummy_hdrq_phys);
561 dd->ipath_dummy_hdrq = NULL;
564 if (dd->ipath_pageshadow) {
565 struct page **tmpp = dd->ipath_pageshadow;
566 dma_addr_t *tmpd = dd->ipath_physshadow;
569 ipath_cdbg(VERBOSE, "Unlocking any expTID pages still "
571 for (port = 0; port < dd->ipath_cfgports; port++) {
572 int port_tidbase = port * dd->ipath_rcvtidcnt;
573 int maxtid = port_tidbase + dd->ipath_rcvtidcnt;
574 for (i = port_tidbase; i < maxtid; i++) {
577 pci_unmap_page(dd->pcidev, tmpd[i],
578 PAGE_SIZE, PCI_DMA_FROMDEVICE);
579 ipath_release_user_pages(&tmpp[i], 1);
585 ipath_stats.sps_pageunlocks += cnt;
586 ipath_cdbg(VERBOSE, "There were still %u expTID "
587 "entries locked\n", cnt);
589 if (ipath_stats.sps_pagelocks ||
590 ipath_stats.sps_pageunlocks)
591 ipath_cdbg(VERBOSE, "%llu pages locked, %llu "
592 "unlocked via ipath_m{un}lock\n",
594 ipath_stats.sps_pagelocks,
596 ipath_stats.sps_pageunlocks);
598 ipath_cdbg(VERBOSE, "Free shadow page tid array at %p\n",
599 dd->ipath_pageshadow);
600 vfree(dd->ipath_pageshadow);
601 dd->ipath_pageshadow = NULL;
605 * free any resources still in use (usually just kernel ports)
606 * at unload; we do for portcnt, not cfgports, because cfgports
607 * could have changed while we were loaded.
609 for (port = 0; port < dd->ipath_portcnt; port++) {
610 struct ipath_portdata *pd = dd->ipath_pd[port];
611 dd->ipath_pd[port] = NULL;
612 ipath_free_pddata(dd, pd);
616 * debuggability, in case some cleanup path tries to use it
622 static void __devexit ipath_remove_one(struct pci_dev *pdev)
624 struct ipath_devdata *dd = pci_get_drvdata(pdev);
626 ipath_cdbg(VERBOSE, "removing, pdev=%p, dd=%p\n", pdev, dd);
629 ipath_unregister_ib_device(dd->verbs_dev);
631 ipath_diag_remove(dd);
632 ipath_user_remove(dd);
633 ipathfs_remove_device(dd);
634 ipath_device_remove_group(&pdev->dev, dd);
636 ipath_cdbg(VERBOSE, "Releasing pci memory regions, dd %p, "
637 "unit %u\n", dd, (u32) dd->ipath_unit);
642 * turn off rcv, send, and interrupts for all ports, all drivers
643 * should also hard reset the chip here?
644 * free up port 0 (kernel) rcvhdr, egr bufs, and eventually tid bufs
645 * for all versions of the driver, if they were allocated
648 ipath_cdbg(VERBOSE, "unit %u free irq %d\n",
649 dd->ipath_unit, dd->ipath_irq);
650 dd->ipath_f_free_irq(dd);
652 ipath_dbg("irq is 0, not doing free_irq "
653 "for unit %u\n", dd->ipath_unit);
655 * we check for NULL here, because it's outside
656 * the kregbase check, and we need to call it
657 * after the free_irq. Thus it's possible that
658 * the function pointers were never initialized.
660 if (dd->ipath_f_cleanup)
661 /* clean up chip-specific stuff */
662 dd->ipath_f_cleanup(dd);
664 ipath_cdbg(VERBOSE, "Unmapping kregbase %p\n", dd->ipath_kregbase);
665 iounmap((volatile void __iomem *) dd->ipath_kregbase);
666 pci_release_regions(pdev);
667 ipath_cdbg(VERBOSE, "calling pci_disable_device\n");
668 pci_disable_device(pdev);
670 ipath_free_devdata(pdev, dd);
673 /* general driver use */
674 DEFINE_MUTEX(ipath_mutex);
676 static DEFINE_SPINLOCK(ipath_pioavail_lock);
679 * ipath_disarm_piobufs - cancel a range of PIO buffers
680 * @dd: the infinipath device
681 * @first: the first PIO buffer to cancel
682 * @cnt: the number of PIO buffers to cancel
684 * cancel a range of PIO buffers, used when they might be armed, but
685 * not triggered. Used at init to ensure buffer state, and also user
686 * process close, in case it died while writing to a PIO buffer
689 void ipath_disarm_piobufs(struct ipath_devdata *dd, unsigned first,
692 unsigned i, last = first + cnt;
693 u64 sendctrl, sendorig;
695 ipath_cdbg(PKT, "disarm %u PIObufs first=%u\n", cnt, first);
696 sendorig = dd->ipath_sendctrl | INFINIPATH_S_DISARM;
697 for (i = first; i < last; i++) {
698 sendctrl = sendorig |
699 (i << INFINIPATH_S_DISARMPIOBUF_SHIFT);
700 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
705 * Write it again with current value, in case ipath_sendctrl changed
706 * while we were looping; no critical bits that would require
709 * Write a 0, and then the original value, reading scratch in
710 * between. This seems to avoid a chip timing race that causes
711 * pioavail updates to memory to stop.
713 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
715 sendorig = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
716 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
721 * ipath_wait_linkstate - wait for an IB link state change to occur
722 * @dd: the infinipath device
723 * @state: the state to wait for
724 * @msecs: the number of milliseconds to wait
726 * wait up to msecs milliseconds for IB link state change to occur for
727 * now, take the easy polling route. Currently used only by
728 * ipath_set_linkstate. Returns 0 if state reached, otherwise
729 * -ETIMEDOUT state can have multiple states set, for any of several
732 static int ipath_wait_linkstate(struct ipath_devdata *dd, u32 state,
735 dd->ipath_state_wanted = state;
736 wait_event_interruptible_timeout(ipath_state_wait,
737 (dd->ipath_flags & state),
738 msecs_to_jiffies(msecs));
739 dd->ipath_state_wanted = 0;
741 if (!(dd->ipath_flags & state)) {
743 ipath_cdbg(VERBOSE, "Didn't reach linkstate %s within %u"
745 /* test INIT ahead of DOWN, both can be set */
746 (state & IPATH_LINKINIT) ? "INIT" :
747 ((state & IPATH_LINKDOWN) ? "DOWN" :
748 ((state & IPATH_LINKARMED) ? "ARM" : "ACTIVE")),
750 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
751 ipath_cdbg(VERBOSE, "ibcc=%llx ibcstatus=%llx (%s)\n",
752 (unsigned long long) ipath_read_kreg64(
753 dd, dd->ipath_kregs->kr_ibcctrl),
754 (unsigned long long) val,
755 ipath_ibcstatus_str[val & 0xf]);
757 return (dd->ipath_flags & state) ? 0 : -ETIMEDOUT;
761 * Decode the error status into strings, deciding whether to always
762 * print * it or not depending on "normal packet errors" vs everything
763 * else. Return 1 if "real" errors, otherwise 0 if only packet
764 * errors, so caller can decide what to print with the string.
766 int ipath_decode_err(char *buf, size_t blen, ipath_err_t err)
770 if (err & INFINIPATH_E_PKTERRS) {
771 if (!(err & ~INFINIPATH_E_PKTERRS))
772 iserr = 0; // if only packet errors.
773 if (ipath_debug & __IPATH_ERRPKTDBG) {
774 if (err & INFINIPATH_E_REBP)
775 strlcat(buf, "EBP ", blen);
776 if (err & INFINIPATH_E_RVCRC)
777 strlcat(buf, "VCRC ", blen);
778 if (err & INFINIPATH_E_RICRC) {
779 strlcat(buf, "CRC ", blen);
780 // clear for check below, so only once
781 err &= INFINIPATH_E_RICRC;
783 if (err & INFINIPATH_E_RSHORTPKTLEN)
784 strlcat(buf, "rshortpktlen ", blen);
785 if (err & INFINIPATH_E_SDROPPEDDATAPKT)
786 strlcat(buf, "sdroppeddatapkt ", blen);
787 if (err & INFINIPATH_E_SPKTLEN)
788 strlcat(buf, "spktlen ", blen);
790 if ((err & INFINIPATH_E_RICRC) &&
791 !(err&(INFINIPATH_E_RVCRC|INFINIPATH_E_REBP)))
792 strlcat(buf, "CRC ", blen);
796 if (err & INFINIPATH_E_RHDRLEN)
797 strlcat(buf, "rhdrlen ", blen);
798 if (err & INFINIPATH_E_RBADTID)
799 strlcat(buf, "rbadtid ", blen);
800 if (err & INFINIPATH_E_RBADVERSION)
801 strlcat(buf, "rbadversion ", blen);
802 if (err & INFINIPATH_E_RHDR)
803 strlcat(buf, "rhdr ", blen);
804 if (err & INFINIPATH_E_RLONGPKTLEN)
805 strlcat(buf, "rlongpktlen ", blen);
806 if (err & INFINIPATH_E_RMAXPKTLEN)
807 strlcat(buf, "rmaxpktlen ", blen);
808 if (err & INFINIPATH_E_RMINPKTLEN)
809 strlcat(buf, "rminpktlen ", blen);
810 if (err & INFINIPATH_E_SMINPKTLEN)
811 strlcat(buf, "sminpktlen ", blen);
812 if (err & INFINIPATH_E_RFORMATERR)
813 strlcat(buf, "rformaterr ", blen);
814 if (err & INFINIPATH_E_RUNSUPVL)
815 strlcat(buf, "runsupvl ", blen);
816 if (err & INFINIPATH_E_RUNEXPCHAR)
817 strlcat(buf, "runexpchar ", blen);
818 if (err & INFINIPATH_E_RIBFLOW)
819 strlcat(buf, "ribflow ", blen);
820 if (err & INFINIPATH_E_SUNDERRUN)
821 strlcat(buf, "sunderrun ", blen);
822 if (err & INFINIPATH_E_SPIOARMLAUNCH)
823 strlcat(buf, "spioarmlaunch ", blen);
824 if (err & INFINIPATH_E_SUNEXPERRPKTNUM)
825 strlcat(buf, "sunexperrpktnum ", blen);
826 if (err & INFINIPATH_E_SDROPPEDSMPPKT)
827 strlcat(buf, "sdroppedsmppkt ", blen);
828 if (err & INFINIPATH_E_SMAXPKTLEN)
829 strlcat(buf, "smaxpktlen ", blen);
830 if (err & INFINIPATH_E_SUNSUPVL)
831 strlcat(buf, "sunsupVL ", blen);
832 if (err & INFINIPATH_E_INVALIDADDR)
833 strlcat(buf, "invalidaddr ", blen);
834 if (err & INFINIPATH_E_RRCVEGRFULL)
835 strlcat(buf, "rcvegrfull ", blen);
836 if (err & INFINIPATH_E_RRCVHDRFULL)
837 strlcat(buf, "rcvhdrfull ", blen);
838 if (err & INFINIPATH_E_IBSTATUSCHANGED)
839 strlcat(buf, "ibcstatuschg ", blen);
840 if (err & INFINIPATH_E_RIBLOSTLINK)
841 strlcat(buf, "riblostlink ", blen);
842 if (err & INFINIPATH_E_HARDWARE)
843 strlcat(buf, "hardware ", blen);
844 if (err & INFINIPATH_E_RESET)
845 strlcat(buf, "reset ", blen);
851 * get_rhf_errstring - decode RHF errors
852 * @err: the err number
853 * @msg: the output buffer
854 * @len: the length of the output buffer
856 * only used one place now, may want more later
858 static void get_rhf_errstring(u32 err, char *msg, size_t len)
860 /* if no errors, and so don't need to check what's first */
863 if (err & INFINIPATH_RHF_H_ICRCERR)
864 strlcat(msg, "icrcerr ", len);
865 if (err & INFINIPATH_RHF_H_VCRCERR)
866 strlcat(msg, "vcrcerr ", len);
867 if (err & INFINIPATH_RHF_H_PARITYERR)
868 strlcat(msg, "parityerr ", len);
869 if (err & INFINIPATH_RHF_H_LENERR)
870 strlcat(msg, "lenerr ", len);
871 if (err & INFINIPATH_RHF_H_MTUERR)
872 strlcat(msg, "mtuerr ", len);
873 if (err & INFINIPATH_RHF_H_IHDRERR)
874 /* infinipath hdr checksum error */
875 strlcat(msg, "ipathhdrerr ", len);
876 if (err & INFINIPATH_RHF_H_TIDERR)
877 strlcat(msg, "tiderr ", len);
878 if (err & INFINIPATH_RHF_H_MKERR)
879 /* bad port, offset, etc. */
880 strlcat(msg, "invalid ipathhdr ", len);
881 if (err & INFINIPATH_RHF_H_IBERR)
882 strlcat(msg, "iberr ", len);
883 if (err & INFINIPATH_RHF_L_SWA)
884 strlcat(msg, "swA ", len);
885 if (err & INFINIPATH_RHF_L_SWB)
886 strlcat(msg, "swB ", len);
890 * ipath_get_egrbuf - get an eager buffer
891 * @dd: the infinipath device
892 * @bufnum: the eager buffer to get
895 * must only be called if ipath_pd[port] is known to be allocated
897 static inline void *ipath_get_egrbuf(struct ipath_devdata *dd, u32 bufnum,
900 return dd->ipath_port0_skbinfo ?
901 (void *) dd->ipath_port0_skbinfo[bufnum].skb->data : NULL;
905 * ipath_alloc_skb - allocate an skb and buffer with possible constraints
906 * @dd: the infinipath device
907 * @gfp_mask: the sk_buff SFP mask
909 struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd,
916 * Only fully supported way to handle this is to allocate lots
917 * extra, align as needed, and then do skb_reserve(). That wastes
918 * a lot of memory... I'll have to hack this into infinipath_copy
923 * We need 2 extra bytes for ipath_ether data sent in the
924 * key header. In order to keep everything dword aligned,
925 * we'll reserve 4 bytes.
927 len = dd->ipath_ibmaxlen + 4;
929 if (dd->ipath_flags & IPATH_4BYTE_TID) {
930 /* We need a 2KB multiple alignment, and there is no way
931 * to do it except to allocate extra and then skb_reserve
932 * enough to bring it up to the right alignment.
937 skb = __dev_alloc_skb(len, gfp_mask);
939 ipath_dev_err(dd, "Failed to allocate skbuff, length %u\n",
946 if (dd->ipath_flags & IPATH_4BYTE_TID) {
947 u32 una = (unsigned long)skb->data & 2047;
949 skb_reserve(skb, 2048 - una);
956 static void ipath_rcv_hdrerr(struct ipath_devdata *dd,
963 struct ipath_message_header *hdr;
965 get_rhf_errstring(eflags, emsg, sizeof emsg);
966 hdr = (struct ipath_message_header *)&rc[1];
967 ipath_cdbg(PKT, "RHFerrs %x hdrqtail=%x typ=%u "
968 "tlen=%x opcode=%x egridx=%x: %s\n",
970 ipath_hdrget_rcv_type((__le32 *) rc),
971 ipath_hdrget_length_in_bytes((__le32 *) rc),
972 be32_to_cpu(hdr->bth[0]) >> 24,
975 /* Count local link integrity errors. */
976 if (eflags & (INFINIPATH_RHF_H_ICRCERR | INFINIPATH_RHF_H_VCRCERR)) {
977 u8 n = (dd->ipath_ibcctrl >>
978 INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT) &
979 INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK;
981 if (++dd->ipath_lli_counter > n) {
982 dd->ipath_lli_counter = 0;
983 dd->ipath_lli_errors++;
989 * ipath_kreceive - receive a packet
990 * @dd: the infinipath device
992 * called from interrupt handler for errors or receive interrupt
994 void ipath_kreceive(struct ipath_devdata *dd)
998 const u32 rsize = dd->ipath_rcvhdrentsize; /* words */
999 const u32 maxcnt = dd->ipath_rcvhdrcnt * rsize; /* words */
1000 u32 etail = -1, l, hdrqtail;
1001 struct ipath_message_header *hdr;
1002 u32 eflags, i, etype, tlen, pkttot = 0, updegr=0, reloop=0;
1003 static u64 totcalls; /* stats, may eventually remove */
1005 if (!dd->ipath_hdrqtailptr) {
1007 "hdrqtailptr not set, can't do receives\n");
1011 /* There is already a thread processing this queue. */
1012 if (test_and_set_bit(0, &dd->ipath_rcv_pending))
1015 l = dd->ipath_port0head;
1016 hdrqtail = (u32) le64_to_cpu(*dd->ipath_hdrqtailptr);
1021 for (i = 0; l != hdrqtail; i++) {
1025 rc = (u64 *) (dd->ipath_pd[0]->port_rcvhdrq + (l << 2));
1026 hdr = (struct ipath_message_header *)&rc[1];
1028 * could make a network order version of IPATH_KD_QP, and
1029 * do the obvious shift before masking to speed this up.
1031 qp = ntohl(hdr->bth[1]) & 0xffffff;
1032 bthbytes = (u8 *) hdr->bth;
1034 eflags = ipath_hdrget_err_flags((__le32 *) rc);
1035 etype = ipath_hdrget_rcv_type((__le32 *) rc);
1037 tlen = ipath_hdrget_length_in_bytes((__le32 *) rc);
1039 if (etype != RCVHQ_RCV_TYPE_EXPECTED) {
1041 * it turns out that the chips uses an eager buffer
1042 * for all non-expected packets, whether it "needs"
1043 * one or not. So always get the index, but don't
1044 * set ebuf (so we try to copy data) unless the
1045 * length requires it.
1047 etail = ipath_hdrget_index((__le32 *) rc);
1048 if (tlen > sizeof(*hdr) ||
1049 etype == RCVHQ_RCV_TYPE_NON_KD)
1050 ebuf = ipath_get_egrbuf(dd, etail, 0);
1054 * both tiderr and ipathhdrerr are set for all plain IB
1055 * packets; only ipathhdrerr should be set.
1058 if (etype != RCVHQ_RCV_TYPE_NON_KD && etype !=
1059 RCVHQ_RCV_TYPE_ERROR && ipath_hdrget_ipath_ver(
1060 hdr->iph.ver_port_tid_offset) !=
1061 IPS_PROTO_VERSION) {
1062 ipath_cdbg(PKT, "Bad InfiniPath protocol version "
1066 if (unlikely(eflags))
1067 ipath_rcv_hdrerr(dd, eflags, l, etail, rc);
1068 else if (etype == RCVHQ_RCV_TYPE_NON_KD) {
1069 ipath_ib_rcv(dd->verbs_dev, rc + 1, ebuf, tlen);
1070 if (dd->ipath_lli_counter)
1071 dd->ipath_lli_counter--;
1072 ipath_cdbg(PKT, "typ %x, opcode %x (eager, "
1073 "qp=%x), len %x; ignored\n",
1074 etype, bthbytes[0], qp, tlen);
1076 else if (etype == RCVHQ_RCV_TYPE_EAGER)
1077 ipath_cdbg(PKT, "typ %x, opcode %x (eager, "
1078 "qp=%x), len %x; ignored\n",
1079 etype, bthbytes[0], qp, tlen);
1080 else if (etype == RCVHQ_RCV_TYPE_EXPECTED)
1081 ipath_dbg("Bug: Expected TID, opcode %x; ignored\n",
1082 be32_to_cpu(hdr->bth[0]) & 0xff);
1085 * error packet, type of error unknown.
1086 * Probably type 3, but we don't know, so don't
1087 * even try to print the opcode, etc.
1089 ipath_dbg("Error Pkt, but no eflags! egrbuf %x, "
1090 "len %x\nhdrq@%lx;hdrq+%x rhf: %llx; "
1091 "hdr %llx %llx %llx %llx %llx\n",
1092 etail, tlen, (unsigned long) rc, l,
1093 (unsigned long long) rc[0],
1094 (unsigned long long) rc[1],
1095 (unsigned long long) rc[2],
1096 (unsigned long long) rc[3],
1097 (unsigned long long) rc[4],
1098 (unsigned long long) rc[5]);
1103 if (etype != RCVHQ_RCV_TYPE_EXPECTED)
1106 * update head regs on last packet, and every 16 packets.
1107 * Reduce bus traffic, while still trying to prevent
1108 * rcvhdrq overflows, for when the queue is nearly full
1110 if (l == hdrqtail || (i && !(i&0xf))) {
1113 /* request IBA6120 interrupt only on last */
1114 lval = dd->ipath_rhdrhead_intr_off | l;
1117 (void)ipath_write_ureg(dd, ur_rcvhdrhead, lval, 0);
1119 (void)ipath_write_ureg(dd, ur_rcvegrindexhead,
1126 if (!dd->ipath_rhdrhead_intr_off && !reloop) {
1127 /* IBA6110 workaround; we can have a race clearing chip
1128 * interrupt with another interrupt about to be delivered,
1129 * and can clear it before it is delivered on the GPIO
1130 * workaround. By doing the extra check here for the
1131 * in-memory tail register updating while we were doing
1132 * earlier packets, we "almost" guarantee we have covered
1135 u32 hqtail = (u32)le64_to_cpu(*dd->ipath_hdrqtailptr);
1136 if (hqtail != hdrqtail) {
1138 reloop = 1; /* loop 1 extra time at most */
1145 dd->ipath_port0head = l;
1147 if (pkttot > ipath_stats.sps_maxpkts_call)
1148 ipath_stats.sps_maxpkts_call = pkttot;
1149 ipath_stats.sps_port0pkts += pkttot;
1150 ipath_stats.sps_avgpkts_call =
1151 ipath_stats.sps_port0pkts / ++totcalls;
1154 clear_bit(0, &dd->ipath_rcv_pending);
1155 smp_mb__after_clear_bit();
1161 * ipath_update_pio_bufs - update shadow copy of the PIO availability map
1162 * @dd: the infinipath device
1164 * called whenever our local copy indicates we have run out of send buffers
1165 * NOTE: This can be called from interrupt context by some code
1166 * and from non-interrupt context by ipath_getpiobuf().
1169 static void ipath_update_pio_bufs(struct ipath_devdata *dd)
1171 unsigned long flags;
1173 const unsigned piobregs = (unsigned)dd->ipath_pioavregs;
1175 /* If the generation (check) bits have changed, then we update the
1176 * busy bit for the corresponding PIO buffer. This algorithm will
1177 * modify positions to the value they already have in some cases
1178 * (i.e., no change), but it's faster than changing only the bits
1179 * that have changed.
1181 * We would like to do this atomicly, to avoid spinlocks in the
1182 * critical send path, but that's not really possible, given the
1183 * type of changes, and that this routine could be called on
1184 * multiple cpu's simultaneously, so we lock in this routine only,
1185 * to avoid conflicting updates; all we change is the shadow, and
1186 * it's a single 64 bit memory location, so by definition the update
1187 * is atomic in terms of what other cpu's can see in testing the
1188 * bits. The spin_lock overhead isn't too bad, since it only
1189 * happens when all buffers are in use, so only cpu overhead, not
1190 * latency or bandwidth is affected.
1192 #define _IPATH_ALL_CHECKBITS 0x5555555555555555ULL
1193 if (!dd->ipath_pioavailregs_dma) {
1194 ipath_dbg("Update shadow pioavail, but regs_dma NULL!\n");
1197 if (ipath_debug & __IPATH_VERBDBG) {
1198 /* only if packet debug and verbose */
1199 volatile __le64 *dma = dd->ipath_pioavailregs_dma;
1200 unsigned long *shadow = dd->ipath_pioavailshadow;
1202 ipath_cdbg(PKT, "Refill avail, dma0=%llx shad0=%lx, "
1203 "d1=%llx s1=%lx, d2=%llx s2=%lx, d3=%llx "
1205 (unsigned long long) le64_to_cpu(dma[0]),
1207 (unsigned long long) le64_to_cpu(dma[1]),
1209 (unsigned long long) le64_to_cpu(dma[2]),
1211 (unsigned long long) le64_to_cpu(dma[3]),
1215 PKT, "2nd group, dma4=%llx shad4=%lx, "
1216 "d5=%llx s5=%lx, d6=%llx s6=%lx, "
1218 (unsigned long long) le64_to_cpu(dma[4]),
1220 (unsigned long long) le64_to_cpu(dma[5]),
1222 (unsigned long long) le64_to_cpu(dma[6]),
1224 (unsigned long long) le64_to_cpu(dma[7]),
1227 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1228 for (i = 0; i < piobregs; i++) {
1229 u64 pchbusy, pchg, piov, pnew;
1231 * Chip Errata: bug 6641; even and odd qwords>3 are swapped
1236 dd->ipath_pioavailregs_dma[i - 1]);
1239 dd->ipath_pioavailregs_dma[i + 1]);
1241 piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i]);
1242 pchg = _IPATH_ALL_CHECKBITS &
1243 ~(dd->ipath_pioavailshadow[i] ^ piov);
1244 pchbusy = pchg << INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT;
1245 if (pchg && (pchbusy & dd->ipath_pioavailshadow[i])) {
1246 pnew = dd->ipath_pioavailshadow[i] & ~pchbusy;
1247 pnew |= piov & pchbusy;
1248 dd->ipath_pioavailshadow[i] = pnew;
1251 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1255 * ipath_setrcvhdrsize - set the receive header size
1256 * @dd: the infinipath device
1257 * @rhdrsize: the receive header size
1259 * called from user init code, and also layered driver init
1261 int ipath_setrcvhdrsize(struct ipath_devdata *dd, unsigned rhdrsize)
1265 if (dd->ipath_flags & IPATH_RCVHDRSZ_SET) {
1266 if (dd->ipath_rcvhdrsize != rhdrsize) {
1267 dev_info(&dd->pcidev->dev,
1268 "Error: can't set protocol header "
1269 "size %u, already %u\n",
1270 rhdrsize, dd->ipath_rcvhdrsize);
1273 ipath_cdbg(VERBOSE, "Reuse same protocol header "
1274 "size %u\n", dd->ipath_rcvhdrsize);
1275 } else if (rhdrsize > (dd->ipath_rcvhdrentsize -
1276 (sizeof(u64) / sizeof(u32)))) {
1277 ipath_dbg("Error: can't set protocol header size %u "
1278 "(> max %u)\n", rhdrsize,
1279 dd->ipath_rcvhdrentsize -
1280 (u32) (sizeof(u64) / sizeof(u32)));
1283 dd->ipath_flags |= IPATH_RCVHDRSZ_SET;
1284 dd->ipath_rcvhdrsize = rhdrsize;
1285 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
1286 dd->ipath_rcvhdrsize);
1287 ipath_cdbg(VERBOSE, "Set protocol header size to %u\n",
1288 dd->ipath_rcvhdrsize);
1294 * ipath_getpiobuf - find an available pio buffer
1295 * @dd: the infinipath device
1296 * @pbufnum: the buffer number is placed here
1298 * do appropriate marking as busy, etc.
1299 * returns buffer number if one found (>=0), negative number is error.
1300 * Used by ipath_layer_send
1302 u32 __iomem *ipath_getpiobuf(struct ipath_devdata *dd, u32 * pbufnum)
1304 int i, j, starti, updated = 0;
1305 unsigned piobcnt, iter;
1306 unsigned long flags;
1307 unsigned long *shadow = dd->ipath_pioavailshadow;
1310 piobcnt = (unsigned)(dd->ipath_piobcnt2k
1311 + dd->ipath_piobcnt4k);
1312 starti = dd->ipath_lastport_piobuf;
1313 iter = piobcnt - starti;
1314 if (dd->ipath_upd_pio_shadow) {
1316 * Minor optimization. If we had no buffers on last call,
1317 * start out by doing the update; continue and do scan even
1318 * if no buffers were updated, to be paranoid
1320 ipath_update_pio_bufs(dd);
1321 /* we scanned here, don't do it at end of scan */
1325 i = dd->ipath_lastpioindex;
1329 * while test_and_set_bit() is atomic, we do that and then the
1330 * change_bit(), and the pair is not. See if this is the cause
1331 * of the remaining armlaunch errors.
1333 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1334 for (j = 0; j < iter; j++, i++) {
1338 * To avoid bus lock overhead, we first find a candidate
1339 * buffer, then do the test and set, and continue if that
1342 if (test_bit((2 * i) + 1, shadow) ||
1343 test_and_set_bit((2 * i) + 1, shadow))
1345 /* flip generation bit */
1346 change_bit(2 * i, shadow);
1349 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1352 volatile __le64 *dma = dd->ipath_pioavailregs_dma;
1355 * first time through; shadow exhausted, but may be real
1356 * buffers available, so go see; if any updated, rescan
1360 ipath_update_pio_bufs(dd);
1365 dd->ipath_upd_pio_shadow = 1;
1367 * not atomic, but if we lose one once in a while, that's OK
1369 ipath_stats.sps_nopiobufs++;
1370 if (!(++dd->ipath_consec_nopiobuf % 100000)) {
1372 "%u pio sends with no bufavail; dmacopy: "
1373 "%llx %llx %llx %llx; shadow: "
1374 "%lx %lx %lx %lx\n",
1375 dd->ipath_consec_nopiobuf,
1376 (unsigned long long) le64_to_cpu(dma[0]),
1377 (unsigned long long) le64_to_cpu(dma[1]),
1378 (unsigned long long) le64_to_cpu(dma[2]),
1379 (unsigned long long) le64_to_cpu(dma[3]),
1380 shadow[0], shadow[1], shadow[2],
1383 * 4 buffers per byte, 4 registers above, cover rest
1386 if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) >
1387 (sizeof(shadow[0]) * 4 * 4))
1388 ipath_dbg("2nd group: dmacopy: %llx %llx "
1389 "%llx %llx; shadow: %lx %lx "
1391 (unsigned long long)
1392 le64_to_cpu(dma[4]),
1393 (unsigned long long)
1394 le64_to_cpu(dma[5]),
1395 (unsigned long long)
1396 le64_to_cpu(dma[6]),
1397 (unsigned long long)
1398 le64_to_cpu(dma[7]),
1399 shadow[4], shadow[5],
1400 shadow[6], shadow[7]);
1407 * set next starting place. Since it's just an optimization,
1408 * it doesn't matter who wins on this, so no locking
1410 dd->ipath_lastpioindex = i + 1;
1411 if (dd->ipath_upd_pio_shadow)
1412 dd->ipath_upd_pio_shadow = 0;
1413 if (dd->ipath_consec_nopiobuf)
1414 dd->ipath_consec_nopiobuf = 0;
1415 if (i < dd->ipath_piobcnt2k)
1416 buf = (u32 __iomem *) (dd->ipath_pio2kbase +
1417 i * dd->ipath_palign);
1419 buf = (u32 __iomem *)
1420 (dd->ipath_pio4kbase +
1421 (i - dd->ipath_piobcnt2k) * dd->ipath_4kalign);
1422 ipath_cdbg(VERBOSE, "Return piobuf%u %uk @ %p\n",
1423 i, (i < dd->ipath_piobcnt2k) ? 2 : 4, buf);
1432 * ipath_create_rcvhdrq - create a receive header queue
1433 * @dd: the infinipath device
1434 * @pd: the port data
1436 * this must be contiguous memory (from an i/o perspective), and must be
1437 * DMA'able (which means for some systems, it will go through an IOMMU,
1438 * or be forced into a low address range).
1440 int ipath_create_rcvhdrq(struct ipath_devdata *dd,
1441 struct ipath_portdata *pd)
1445 if (!pd->port_rcvhdrq) {
1446 dma_addr_t phys_hdrqtail;
1447 gfp_t gfp_flags = GFP_USER | __GFP_COMP;
1448 int amt = ALIGN(dd->ipath_rcvhdrcnt * dd->ipath_rcvhdrentsize *
1449 sizeof(u32), PAGE_SIZE);
1451 pd->port_rcvhdrq = dma_alloc_coherent(
1452 &dd->pcidev->dev, amt, &pd->port_rcvhdrq_phys,
1455 if (!pd->port_rcvhdrq) {
1456 ipath_dev_err(dd, "attempt to allocate %d bytes "
1457 "for port %u rcvhdrq failed\n",
1458 amt, pd->port_port);
1462 pd->port_rcvhdrtail_kvaddr = dma_alloc_coherent(
1463 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail, GFP_KERNEL);
1464 if (!pd->port_rcvhdrtail_kvaddr) {
1465 ipath_dev_err(dd, "attempt to allocate 1 page "
1466 "for port %u rcvhdrqtailaddr failed\n",
1469 dma_free_coherent(&dd->pcidev->dev, amt,
1470 pd->port_rcvhdrq, pd->port_rcvhdrq_phys);
1471 pd->port_rcvhdrq = NULL;
1474 pd->port_rcvhdrqtailaddr_phys = phys_hdrqtail;
1476 pd->port_rcvhdrq_size = amt;
1478 ipath_cdbg(VERBOSE, "%d pages at %p (phys %lx) size=%lu "
1479 "for port %u rcvhdr Q\n",
1480 amt >> PAGE_SHIFT, pd->port_rcvhdrq,
1481 (unsigned long) pd->port_rcvhdrq_phys,
1482 (unsigned long) pd->port_rcvhdrq_size,
1485 ipath_cdbg(VERBOSE, "port %d hdrtailaddr, %llx physical\n",
1487 (unsigned long long) phys_hdrqtail);
1490 ipath_cdbg(VERBOSE, "reuse port %d rcvhdrq @%p %llx phys; "
1491 "hdrtailaddr@%p %llx physical\n",
1492 pd->port_port, pd->port_rcvhdrq,
1493 (unsigned long long) pd->port_rcvhdrq_phys,
1494 pd->port_rcvhdrtail_kvaddr, (unsigned long long)
1495 pd->port_rcvhdrqtailaddr_phys);
1497 /* clear for security and sanity on each use */
1498 memset(pd->port_rcvhdrq, 0, pd->port_rcvhdrq_size);
1499 memset(pd->port_rcvhdrtail_kvaddr, 0, PAGE_SIZE);
1502 * tell chip each time we init it, even if we are re-using previous
1503 * memory (we zero the register at process close)
1505 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdrtailaddr,
1506 pd->port_port, pd->port_rcvhdrqtailaddr_phys);
1507 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdraddr,
1508 pd->port_port, pd->port_rcvhdrq_phys);
1515 int ipath_waitfor_complete(struct ipath_devdata *dd, ipath_kreg reg_id,
1516 u64 bits_to_wait_for, u64 * valp)
1518 unsigned long timeout;
1522 lastval = ipath_read_kreg64(dd, reg_id);
1523 /* wait a ridiculously long time */
1524 timeout = jiffies + msecs_to_jiffies(5);
1526 val = ipath_read_kreg64(dd, reg_id);
1527 /* set so they have something, even on failures. */
1529 if ((val & bits_to_wait_for) == bits_to_wait_for) {
1534 ipath_cdbg(VERBOSE, "Changed from %llx to %llx, "
1535 "waiting for %llx bits\n",
1536 (unsigned long long) lastval,
1537 (unsigned long long) val,
1538 (unsigned long long) bits_to_wait_for);
1540 if (time_after(jiffies, timeout)) {
1541 ipath_dbg("Didn't get bits %llx in register 0x%x, "
1543 (unsigned long long) bits_to_wait_for,
1544 reg_id, (unsigned long long) *valp);
1554 * ipath_waitfor_mdio_cmdready - wait for last command to complete
1555 * @dd: the infinipath device
1557 * Like ipath_waitfor_complete(), but we wait for the CMDVALID bit to go
1558 * away indicating the last command has completed. It doesn't return data
1560 int ipath_waitfor_mdio_cmdready(struct ipath_devdata *dd)
1562 unsigned long timeout;
1566 /* wait a ridiculously long time */
1567 timeout = jiffies + msecs_to_jiffies(5);
1569 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_mdio);
1570 if (!(val & IPATH_MDIO_CMDVALID)) {
1575 if (time_after(jiffies, timeout)) {
1576 ipath_dbg("CMDVALID stuck in mdio reg? (%llx)\n",
1577 (unsigned long long) val);
1586 static void ipath_set_ib_lstate(struct ipath_devdata *dd, int which)
1588 static const char *what[4] = {
1590 [INFINIPATH_IBCC_LINKCMD_INIT] = "INIT",
1591 [INFINIPATH_IBCC_LINKCMD_ARMED] = "ARMED",
1592 [INFINIPATH_IBCC_LINKCMD_ACTIVE] = "ACTIVE"
1594 int linkcmd = (which >> INFINIPATH_IBCC_LINKCMD_SHIFT) &
1595 INFINIPATH_IBCC_LINKCMD_MASK;
1597 ipath_cdbg(VERBOSE, "Trying to move unit %u to %s, current ltstate "
1598 "is %s\n", dd->ipath_unit,
1600 ipath_ibcstatus_str[
1602 (dd, dd->ipath_kregs->kr_ibcstatus) >>
1603 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
1604 INFINIPATH_IBCS_LINKTRAININGSTATE_MASK]);
1605 /* flush all queued sends when going to DOWN or INIT, to be sure that
1606 * they don't block MAD packets */
1607 if (!linkcmd || linkcmd == INFINIPATH_IBCC_LINKCMD_INIT) {
1608 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1609 INFINIPATH_S_ABORT);
1610 ipath_disarm_piobufs(dd, dd->ipath_lastport_piobuf,
1611 (unsigned)(dd->ipath_piobcnt2k +
1612 dd->ipath_piobcnt4k) -
1613 dd->ipath_lastport_piobuf);
1616 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1617 dd->ipath_ibcctrl | which);
1620 int ipath_set_linkstate(struct ipath_devdata *dd, u8 newstate)
1626 case IPATH_IB_LINKDOWN:
1627 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKINITCMD_POLL <<
1628 INFINIPATH_IBCC_LINKINITCMD_SHIFT);
1633 case IPATH_IB_LINKDOWN_SLEEP:
1634 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKINITCMD_SLEEP <<
1635 INFINIPATH_IBCC_LINKINITCMD_SHIFT);
1640 case IPATH_IB_LINKDOWN_DISABLE:
1641 ipath_set_ib_lstate(dd,
1642 INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
1643 INFINIPATH_IBCC_LINKINITCMD_SHIFT);
1648 case IPATH_IB_LINKINIT:
1649 if (dd->ipath_flags & IPATH_LINKINIT) {
1653 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_INIT <<
1654 INFINIPATH_IBCC_LINKCMD_SHIFT);
1655 lstate = IPATH_LINKINIT;
1658 case IPATH_IB_LINKARM:
1659 if (dd->ipath_flags & IPATH_LINKARMED) {
1663 if (!(dd->ipath_flags &
1664 (IPATH_LINKINIT | IPATH_LINKACTIVE))) {
1668 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ARMED <<
1669 INFINIPATH_IBCC_LINKCMD_SHIFT);
1671 * Since the port can transition to ACTIVE by receiving
1672 * a non VL 15 packet, wait for either state.
1674 lstate = IPATH_LINKARMED | IPATH_LINKACTIVE;
1677 case IPATH_IB_LINKACTIVE:
1678 if (dd->ipath_flags & IPATH_LINKACTIVE) {
1682 if (!(dd->ipath_flags & IPATH_LINKARMED)) {
1686 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ACTIVE <<
1687 INFINIPATH_IBCC_LINKCMD_SHIFT);
1688 lstate = IPATH_LINKACTIVE;
1691 case IPATH_IB_LINK_LOOPBACK:
1692 dev_info(&dd->pcidev->dev, "Enabling IB local loopback\n");
1693 dd->ipath_ibcctrl |= INFINIPATH_IBCC_LOOPBACK;
1694 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1697 goto bail; // no state change to wait for
1699 case IPATH_IB_LINK_EXTERNAL:
1700 dev_info(&dd->pcidev->dev, "Disabling IB local loopback (normal)\n");
1701 dd->ipath_ibcctrl &= ~INFINIPATH_IBCC_LOOPBACK;
1702 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1705 goto bail; // no state change to wait for
1708 ipath_dbg("Invalid linkstate 0x%x requested\n", newstate);
1712 ret = ipath_wait_linkstate(dd, lstate, 2000);
1719 * ipath_set_mtu - set the MTU
1720 * @dd: the infinipath device
1723 * we can handle "any" incoming size, the issue here is whether we
1724 * need to restrict our outgoing size. For now, we don't do any
1725 * sanity checking on this, and we don't deal with what happens to
1726 * programs that are already running when the size changes.
1727 * NOTE: changing the MTU will usually cause the IBC to go back to
1728 * link initialize (IPATH_IBSTATE_INIT) state...
1730 int ipath_set_mtu(struct ipath_devdata *dd, u16 arg)
1737 * mtu is IB data payload max. It's the largest power of 2 less
1738 * than piosize (or even larger, since it only really controls the
1739 * largest we can receive; we can send the max of the mtu and
1740 * piosize). We check that it's one of the valid IB sizes.
1742 if (arg != 256 && arg != 512 && arg != 1024 && arg != 2048 &&
1744 ipath_dbg("Trying to set invalid mtu %u, failing\n", arg);
1748 if (dd->ipath_ibmtu == arg) {
1749 ret = 0; /* same as current */
1753 piosize = dd->ipath_ibmaxlen;
1754 dd->ipath_ibmtu = arg;
1756 if (arg >= (piosize - IPATH_PIO_MAXIBHDR)) {
1757 /* Only if it's not the initial value (or reset to it) */
1758 if (piosize != dd->ipath_init_ibmaxlen) {
1759 dd->ipath_ibmaxlen = piosize;
1762 } else if ((arg + IPATH_PIO_MAXIBHDR) != dd->ipath_ibmaxlen) {
1763 piosize = arg + IPATH_PIO_MAXIBHDR;
1764 ipath_cdbg(VERBOSE, "ibmaxlen was 0x%x, setting to 0x%x "
1765 "(mtu 0x%x)\n", dd->ipath_ibmaxlen, piosize,
1767 dd->ipath_ibmaxlen = piosize;
1773 * set the IBC maxpktlength to the size of our pio
1776 u64 ibc = dd->ipath_ibcctrl;
1777 ibc &= ~(INFINIPATH_IBCC_MAXPKTLEN_MASK <<
1778 INFINIPATH_IBCC_MAXPKTLEN_SHIFT);
1780 piosize = piosize - 2 * sizeof(u32); /* ignore pbc */
1781 dd->ipath_ibmaxlen = piosize;
1782 piosize /= sizeof(u32); /* in words */
1784 * for ICRC, which we only send in diag test pkt mode, and
1785 * we don't need to worry about that for mtu
1789 ibc |= piosize << INFINIPATH_IBCC_MAXPKTLEN_SHIFT;
1790 dd->ipath_ibcctrl = ibc;
1791 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1793 dd->ipath_f_tidtemplate(dd);
1802 int ipath_set_lid(struct ipath_devdata *dd, u32 arg, u8 lmc)
1804 dd->ipath_lid = arg;
1805 dd->ipath_lmc = lmc;
1812 * ipath_write_kreg_port - write a device's per-port 64-bit kernel register
1813 * @dd: the infinipath device
1814 * @regno: the register number to write
1815 * @port: the port containing the register
1816 * @value: the value to write
1818 * Registers that vary with the chip implementation constants (port)
1821 void ipath_write_kreg_port(const struct ipath_devdata *dd, ipath_kreg regno,
1822 unsigned port, u64 value)
1826 if (port < dd->ipath_portcnt &&
1827 (regno == dd->ipath_kregs->kr_rcvhdraddr ||
1828 regno == dd->ipath_kregs->kr_rcvhdrtailaddr))
1829 where = regno + port;
1833 ipath_write_kreg(dd, where, value);
1837 * ipath_shutdown_device - shut down a device
1838 * @dd: the infinipath device
1840 * This is called to make the device quiet when we are about to
1841 * unload the driver, and also when the device is administratively
1842 * disabled. It does not free any data structures.
1843 * Everything it does has to be setup again by ipath_init_chip(dd,1)
1845 void ipath_shutdown_device(struct ipath_devdata *dd)
1847 ipath_dbg("Shutting down the device\n");
1849 dd->ipath_flags |= IPATH_LINKUNK;
1850 dd->ipath_flags &= ~(IPATH_INITTED | IPATH_LINKDOWN |
1851 IPATH_LINKINIT | IPATH_LINKARMED |
1853 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_CONF |
1854 IPATH_STATUS_IB_READY);
1856 /* mask interrupts, but not errors */
1857 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
1859 dd->ipath_rcvctrl = 0;
1860 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
1864 * gracefully stop all sends allowing any in progress to trickle out
1867 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 0ULL);
1869 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1871 * enough for anything that's going to trickle out to have actually
1877 * abort any armed or launched PIO buffers that didn't go. (self
1878 * clearing). Will cause any packet currently being transmitted to
1879 * go out with an EBP, and may also cause a short packet error on
1882 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1883 INFINIPATH_S_ABORT);
1885 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
1886 INFINIPATH_IBCC_LINKINITCMD_SHIFT);
1889 dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
1890 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
1891 dd->ipath_control | INFINIPATH_C_FREEZEMODE);
1894 * clear SerdesEnable and turn the leds off; do this here because
1895 * we are unloading, so don't count on interrupts to move along
1896 * Turn the LEDs off explictly for the same reason.
1898 dd->ipath_f_quiet_serdes(dd);
1899 dd->ipath_f_setextled(dd, 0, 0);
1901 if (dd->ipath_stats_timer_active) {
1902 del_timer_sync(&dd->ipath_stats_timer);
1903 dd->ipath_stats_timer_active = 0;
1907 * clear all interrupts and errors, so that the next time the driver
1908 * is loaded or device is enabled, we know that whatever is set
1909 * happened while we were unloaded
1911 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1912 ~0ULL & ~INFINIPATH_HWE_MEMBISTFAILED);
1913 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
1914 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
1918 * ipath_free_pddata - free a port's allocated data
1919 * @dd: the infinipath device
1920 * @pd: the portdata structure
1922 * free up any allocated data for a port
1923 * This should not touch anything that would affect a simultaneous
1924 * re-allocation of port data, because it is called after ipath_mutex
1925 * is released (and can be called from reinit as well).
1926 * It should never change any chip state, or global driver state.
1927 * (The only exception to global state is freeing the port0 port0_skbs.)
1929 void ipath_free_pddata(struct ipath_devdata *dd, struct ipath_portdata *pd)
1934 if (pd->port_rcvhdrq) {
1935 ipath_cdbg(VERBOSE, "free closed port %d rcvhdrq @ %p "
1936 "(size=%lu)\n", pd->port_port, pd->port_rcvhdrq,
1937 (unsigned long) pd->port_rcvhdrq_size);
1938 dma_free_coherent(&dd->pcidev->dev, pd->port_rcvhdrq_size,
1939 pd->port_rcvhdrq, pd->port_rcvhdrq_phys);
1940 pd->port_rcvhdrq = NULL;
1941 if (pd->port_rcvhdrtail_kvaddr) {
1942 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
1943 pd->port_rcvhdrtail_kvaddr,
1944 pd->port_rcvhdrqtailaddr_phys);
1945 pd->port_rcvhdrtail_kvaddr = NULL;
1948 if (pd->port_port && pd->port_rcvegrbuf) {
1951 for (e = 0; e < pd->port_rcvegrbuf_chunks; e++) {
1952 void *base = pd->port_rcvegrbuf[e];
1953 size_t size = pd->port_rcvegrbuf_size;
1955 ipath_cdbg(VERBOSE, "egrbuf free(%p, %lu), "
1956 "chunk %u/%u\n", base,
1957 (unsigned long) size,
1958 e, pd->port_rcvegrbuf_chunks);
1959 dma_free_coherent(&dd->pcidev->dev, size,
1960 base, pd->port_rcvegrbuf_phys[e]);
1962 kfree(pd->port_rcvegrbuf);
1963 pd->port_rcvegrbuf = NULL;
1964 kfree(pd->port_rcvegrbuf_phys);
1965 pd->port_rcvegrbuf_phys = NULL;
1966 pd->port_rcvegrbuf_chunks = 0;
1967 } else if (pd->port_port == 0 && dd->ipath_port0_skbinfo) {
1969 struct ipath_skbinfo *skbinfo = dd->ipath_port0_skbinfo;
1971 dd->ipath_port0_skbinfo = NULL;
1972 ipath_cdbg(VERBOSE, "free closed port %d "
1973 "ipath_port0_skbinfo @ %p\n", pd->port_port,
1975 for (e = 0; e < dd->ipath_rcvegrcnt; e++)
1976 if (skbinfo[e].skb) {
1977 pci_unmap_single(dd->pcidev, skbinfo[e].phys,
1979 PCI_DMA_FROMDEVICE);
1980 dev_kfree_skb(skbinfo[e].skb);
1984 kfree(pd->port_tid_pg_list);
1985 vfree(pd->subport_uregbase);
1986 vfree(pd->subport_rcvegrbuf);
1987 vfree(pd->subport_rcvhdr_base);
1991 static int __init infinipath_init(void)
1995 if (ipath_debug & __IPATH_DBG)
1996 printk(KERN_INFO DRIVER_LOAD_MSG "%s", ib_ipath_version);
1999 * These must be called before the driver is registered with
2000 * the PCI subsystem.
2002 idr_init(&unit_table);
2003 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
2008 ret = pci_register_driver(&ipath_driver);
2010 printk(KERN_ERR IPATH_DRV_NAME
2011 ": Unable to register driver: error %d\n", -ret);
2015 ret = ipath_driver_create_group(&ipath_driver.driver);
2017 printk(KERN_ERR IPATH_DRV_NAME ": Unable to create driver "
2018 "sysfs entries: error %d\n", -ret);
2022 ret = ipath_init_ipathfs();
2024 printk(KERN_ERR IPATH_DRV_NAME ": Unable to create "
2025 "ipathfs: error %d\n", -ret);
2032 ipath_driver_remove_group(&ipath_driver.driver);
2035 pci_unregister_driver(&ipath_driver);
2038 idr_destroy(&unit_table);
2044 static void __exit infinipath_cleanup(void)
2046 ipath_exit_ipathfs();
2048 ipath_driver_remove_group(&ipath_driver.driver);
2050 ipath_cdbg(VERBOSE, "Unregistering pci driver\n");
2051 pci_unregister_driver(&ipath_driver);
2053 idr_destroy(&unit_table);
2057 * ipath_reset_device - reset the chip if possible
2058 * @unit: the device to reset
2060 * Whether or not reset is successful, we attempt to re-initialize the chip
2061 * (that is, much like a driver unload/reload). We clear the INITTED flag
2062 * so that the various entry points will fail until we reinitialize. For
2063 * now, we only allow this if no user ports are open that use chip resources
2065 int ipath_reset_device(int unit)
2068 struct ipath_devdata *dd = ipath_lookup(unit);
2075 dev_info(&dd->pcidev->dev, "Reset on unit %u requested\n", unit);
2077 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) {
2078 dev_info(&dd->pcidev->dev, "Invalid unit number %u or "
2079 "not initialized or not present\n", unit);
2085 for (i = 1; i < dd->ipath_cfgports; i++) {
2086 if (dd->ipath_pd[i] && dd->ipath_pd[i]->port_cnt) {
2087 ipath_dbg("unit %u port %d is in use "
2088 "(PID %u cmd %s), can't reset\n",
2090 dd->ipath_pd[i]->port_pid,
2091 dd->ipath_pd[i]->port_comm);
2097 dd->ipath_flags &= ~IPATH_INITTED;
2098 ret = dd->ipath_f_reset(dd);
2100 ipath_dbg("reset was not successful\n");
2101 ipath_dbg("Trying to reinitialize unit %u after reset attempt\n",
2103 ret = ipath_init_chip(dd, 1);
2105 ipath_dev_err(dd, "Reinitialize unit %u after "
2106 "reset failed with %d\n", unit, ret);
2108 dev_info(&dd->pcidev->dev, "Reinitialized unit %u after "
2109 "resetting\n", unit);
2115 int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv)
2118 if ( new_pol_inv > INFINIPATH_XGXS_RX_POL_MASK ) {
2121 if ( dd->ipath_rx_pol_inv != new_pol_inv ) {
2122 dd->ipath_rx_pol_inv = new_pol_inv;
2123 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
2124 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
2125 INFINIPATH_XGXS_RX_POL_SHIFT);
2126 val |= ((u64)dd->ipath_rx_pol_inv) <<
2127 INFINIPATH_XGXS_RX_POL_SHIFT;
2128 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
2132 module_init(infinipath_init);
2133 module_exit(infinipath_cleanup);