git.oblomov.eu Git - linux-2.6/blob - drivers/char/watchdog/ibmasr.c

   1 /*
   2  * IBM Automatic Server Restart driver.
   3  *
   4  * Copyright (c) 2005 Andrey Panin <pazke@donpac.ru>
   5  *
   6  * Based on driver written by Pete Reynolds.
   7  * Copyright (c) IBM Corporation, 1998-2004.
   8  *
   9  * This software may be used and distributed according to the terms
  10  * of the GNU Public License, incorporated herein by reference.
  11  */
  12
  13 #include <linux/config.h>
  14 #include <linux/fs.h>
  15 #include <linux/kernel.h>
  16 #include <linux/slab.h>
  17 #include <linux/module.h>
  18 #include <linux/pci.h>
  19 #include <linux/timer.h>
  20 #include <linux/miscdevice.h>
  21 #include <linux/watchdog.h>
  22 #include <linux/dmi.h>
  23
  24 #include <asm/io.h>
  25 #include <asm/uaccess.h>
  26
  27
  28 enum {
  29         ASMTYPE_UNKNOWN,
  30         ASMTYPE_TOPAZ,
  31         ASMTYPE_JASPER,
  32         ASMTYPE_PEARL,
  33         ASMTYPE_JUNIPER,
  34         ASMTYPE_SPRUCE,
  35 };
  36
  37 #define PFX "ibmasr: "
  38
  39 #define TOPAZ_ASR_REG_OFFSET    4
  40 #define TOPAZ_ASR_TOGGLE        0x40
  41 #define TOPAZ_ASR_DISABLE       0x80
  42
  43 /* PEARL ASR S/W REGISTER SUPERIO PORT ADDRESSES */
  44 #define PEARL_BASE      0xe04
  45 #define PEARL_WRITE     0xe06
  46 #define PEARL_READ      0xe07
  47
  48 #define PEARL_ASR_DISABLE_MASK  0x80    /* bit 7: disable = 1, enable = 0 */
  49 #define PEARL_ASR_TOGGLE_MASK   0x40    /* bit 6: 0, then 1, then 0 */
  50
  51 /* JASPER OFFSET FROM SIO BASE ADDR TO ASR S/W REGISTERS. */
  52 #define JASPER_ASR_REG_OFFSET   0x38
  53
  54 #define JASPER_ASR_DISABLE_MASK 0x01    /* bit 0: disable = 1, enable = 0 */
  55 #define JASPER_ASR_TOGGLE_MASK  0x02    /* bit 1: 0, then 1, then 0 */
  56
  57 #define JUNIPER_BASE_ADDRESS    0x54b   /* Base address of Juniper ASR */
  58 #define JUNIPER_ASR_DISABLE_MASK 0x01   /* bit 0: disable = 1 enable = 0 */
  59 #define JUNIPER_ASR_TOGGLE_MASK 0x02    /* bit 1: 0, then 1, then 0 */
  60
  61 #define SPRUCE_BASE_ADDRESS     0x118e  /* Base address of Spruce ASR */
  62 #define SPRUCE_ASR_DISABLE_MASK 0x01    /* bit 1: disable = 1 enable = 0 */
  63 #define SPRUCE_ASR_TOGGLE_MASK  0x02    /* bit 0: 0, then 1, then 0 */
  64
  65
  66 static int nowayout = WATCHDOG_NOWAYOUT;
  67
  68 static unsigned long asr_is_open;
  69 static char asr_expect_close;
  70
  71 static unsigned int asr_type, asr_base, asr_length;
  72 static unsigned int asr_read_addr, asr_write_addr;
  73 static unsigned char asr_toggle_mask, asr_disable_mask;
  74
  75 static void asr_toggle(void)
  76 {
  77         unsigned char reg = inb(asr_read_addr);
  78
  79         outb(reg & ~asr_toggle_mask, asr_write_addr);
  80         reg = inb(asr_read_addr);
  81
  82         outb(reg | asr_toggle_mask, asr_write_addr);
  83         reg = inb(asr_read_addr);
  84
  85         outb(reg & ~asr_toggle_mask, asr_write_addr);
  86         reg = inb(asr_read_addr);
  87 }
  88
  89 static void asr_enable(void)
  90 {
  91         unsigned char reg;
  92
  93         if (asr_type == ASMTYPE_TOPAZ) {
  94                 /* asr_write_addr == asr_read_addr */
  95                 reg = inb(asr_read_addr);
  96                 outb(reg & ~(TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE),
  97                      asr_read_addr);
  98         } else {
  99                 /*
 100                  * First make sure the hardware timer is reset by toggling
 101                  * ASR hardware timer line.
 102                  */
 103                 asr_toggle();
 104
 105                 reg = inb(asr_read_addr);
 106                 outb(reg & ~asr_disable_mask, asr_write_addr);
 107         }
 108         reg = inb(asr_read_addr);
 109 }
 110
 111 static void asr_disable(void)
 112 {
 113         unsigned char reg = inb(asr_read_addr);
 114
 115         if (asr_type == ASMTYPE_TOPAZ)
 116                 /* asr_write_addr == asr_read_addr */
 117                 outb(reg | TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE,
 118                      asr_read_addr);
 119         else {
 120                 outb(reg | asr_toggle_mask, asr_write_addr);
 121                 reg = inb(asr_read_addr);
 122
 123                 outb(reg | asr_disable_mask, asr_write_addr);
 124         }
 125         reg = inb(asr_read_addr);
 126 }
 127
 128 static int __init asr_get_base_address(void)
 129 {
 130         unsigned char low, high;
 131         const char *type = "";
 132
 133         asr_length = 1;
 134
 135         switch (asr_type) {
 136         case ASMTYPE_TOPAZ:
 137                 /* SELECT SuperIO CHIP FOR QUERYING (WRITE 0x07 TO BOTH 0x2E and 0x2F) */
 138                 outb(0x07, 0x2e);
 139                 outb(0x07, 0x2f);
 140
 141                 /* SELECT AND READ THE HIGH-NIBBLE OF THE GPIO BASE ADDRESS */
 142                 outb(0x60, 0x2e);
 143                 high = inb(0x2f);
 144
 145                 /* SELECT AND READ THE LOW-NIBBLE OF THE GPIO BASE ADDRESS */
 146                 outb(0x61, 0x2e);
 147                 low = inb(0x2f);
 148
 149                 asr_base = (high << 16) | low;
 150                 asr_read_addr = asr_write_addr =
 151                         asr_base + TOPAZ_ASR_REG_OFFSET;
 152                 asr_length = 5;
 153
 154                 break;
 155
 156         case ASMTYPE_JASPER:
 157                 type = "Jaspers ";
 158
 159                 /* FIXME: need to use pci_config_lock here, but it's not exported */
 160
 161 /*              spin_lock_irqsave(&pci_config_lock, flags);*/
 162
 163                 /* Select the SuperIO chip in the PCI I/O port register */
 164                 outl(0x8000f858, 0xcf8);
 165
 166                 /*
 167                  * Read the base address for the SuperIO chip.
 168                  * Only the lower 16 bits are valid, but the address is word
 169                  * aligned so the last bit must be masked off.
 170                  */
 171                 asr_base = inl(0xcfc) & 0xfffe;
 172
 173 /*              spin_unlock_irqrestore(&pci_config_lock, flags);*/
 174
 175                 asr_read_addr = asr_write_addr =
 176                         asr_base + JASPER_ASR_REG_OFFSET;
 177                 asr_toggle_mask = JASPER_ASR_TOGGLE_MASK;
 178                 asr_disable_mask = JASPER_ASR_DISABLE_MASK;
 179                 asr_length = JASPER_ASR_REG_OFFSET + 1;
 180
 181                 break;
 182
 183         case ASMTYPE_PEARL:
 184                 type = "Pearls ";
 185                 asr_base = PEARL_BASE;
 186                 asr_read_addr = PEARL_READ;
 187                 asr_write_addr = PEARL_WRITE;
 188                 asr_toggle_mask = PEARL_ASR_TOGGLE_MASK;
 189                 asr_disable_mask = PEARL_ASR_DISABLE_MASK;
 190                 asr_length = 4;
 191                 break;
 192
 193         case ASMTYPE_JUNIPER:
 194                 type = "Junipers ";
 195                 asr_base = JUNIPER_BASE_ADDRESS;
 196                 asr_read_addr = asr_write_addr = asr_base;
 197                 asr_toggle_mask = JUNIPER_ASR_TOGGLE_MASK;
 198                 asr_disable_mask = JUNIPER_ASR_DISABLE_MASK;
 199                 break;
 200
 201         case ASMTYPE_SPRUCE:
 202                 type = "Spruce's ";
 203                 asr_base = SPRUCE_BASE_ADDRESS;
 204                 asr_read_addr = asr_write_addr = asr_base;
 205                 asr_toggle_mask = SPRUCE_ASR_TOGGLE_MASK;
 206                 asr_disable_mask = SPRUCE_ASR_DISABLE_MASK;
 207                 break;
 208         }
 209
 210         if (!request_region(asr_base, asr_length, "ibmasr")) {
 211                 printk(KERN_ERR PFX "address %#x already in use\n",
 212                         asr_base);
 213                 return -EBUSY;
 214         }
 215
 216         printk(KERN_INFO PFX "found %sASR @ addr %#x\n", type, asr_base);
 217
 218         return 0;
 219 }
 220
 221
 222 static ssize_t asr_write(struct file *file, const char __user *buf,
 223                          size_t count, loff_t *ppos)
 224 {
 225         if (count) {
 226                 if (!nowayout) {
 227                         size_t i;
 228
 229                         /* In case it was set long ago */
 230                         asr_expect_close = 0;
 231
 232                         for (i = 0; i != count; i++) {
 233                                 char c;
 234                                 if (get_user(c, buf + i))
 235                                         return -EFAULT;
 236                                 if (c == 'V')
 237                                         asr_expect_close = 42;
 238                         }
 239                 }
 240                 asr_toggle();
 241         }
 242         return count;
 243 }
 244
 245 static int asr_ioctl(struct inode *inode, struct file *file,
 246                      unsigned int cmd, unsigned long arg)
 247 {
 248         static const struct watchdog_info ident = {
 249                 .options =      WDIOF_KEEPALIVEPING |
 250                                 WDIOF_MAGICCLOSE,
 251                 .identity =     "IBM ASR"
 252         };
 253         void __user *argp = (void __user *)arg;
 254         int __user *p = argp;
 255         int heartbeat;
 256
 257         switch (cmd) {
 258                 case WDIOC_GETSUPPORT:
 259                         return copy_to_user(argp, &ident, sizeof(ident)) ?
 260                                 -EFAULT : 0;
 261
 262                 case WDIOC_GETSTATUS:
 263                 case WDIOC_GETBOOTSTATUS:
 264                         return put_user(0, p);
 265
 266                 case WDIOC_KEEPALIVE:
 267                         asr_toggle();
 268                         return 0;
 269
 270                 /*
 271                  * The hardware has a fixed timeout value, so no WDIOC_SETTIMEOUT
 272                  * and WDIOC_GETTIMEOUT always returns 256.
 273                  */
 274                 case WDIOC_GETTIMEOUT:
 275                         heartbeat = 256;
 276                         return put_user(heartbeat, p);
 277
 278                 case WDIOC_SETOPTIONS: {
 279                         int new_options, retval = -EINVAL;
 280
 281                         if (get_user(new_options, p))
 282                                 return -EFAULT;
 283
 284                         if (new_options & WDIOS_DISABLECARD) {
 285                                 asr_disable();
 286                                 retval = 0;
 287                         }
 288
 289                         if (new_options & WDIOS_ENABLECARD) {
 290                                 asr_enable();
 291                                 asr_toggle();
 292                                 retval = 0;
 293                         }
 294
 295                         return retval;
 296                 }
 297         }
 298
 299         return -ENOIOCTLCMD;
 300 }
 301
 302 static int asr_open(struct inode *inode, struct file *file)
 303 {
 304         if(test_and_set_bit(0, &asr_is_open))
 305                 return -EBUSY;
 306
 307         asr_toggle();
 308         asr_enable();
 309
 310         return nonseekable_open(inode, file);
 311 }
 312
 313 static int asr_release(struct inode *inode, struct file *file)
 314 {
 315         if (asr_expect_close == 42)
 316                 asr_disable();
 317         else {
 318                 printk(KERN_CRIT PFX "unexpected close, not stopping watchdog!\n");
 319                 asr_toggle();
 320         }
 321         clear_bit(0, &asr_is_open);
 322         asr_expect_close = 0;
 323         return 0;
 324 }
 325
 326 static struct file_operations asr_fops = {
 327         .owner =        THIS_MODULE,
 328         .llseek =       no_llseek,
 329         .write =        asr_write,
 330         .ioctl =        asr_ioctl,
 331         .open =         asr_open,
 332         .release =      asr_release,
 333 };
 334
 335 static struct miscdevice asr_miscdev = {
 336         .minor =        WATCHDOG_MINOR,
 337         .name =         "watchdog",
 338         .fops =         &asr_fops,
 339 };
 340
 341
 342 struct ibmasr_id {
 343         const char *desc;
 344         int type;
 345 };
 346
 347 static struct ibmasr_id __initdata ibmasr_id_table[] = {
 348         { "IBM Automatic Server Restart - eserver xSeries 220", ASMTYPE_TOPAZ },
 349         { "IBM Automatic Server Restart - Machine Type 8673", ASMTYPE_PEARL },
 350         { "IBM Automatic Server Restart - Machine Type 8480", ASMTYPE_JASPER },
 351         { "IBM Automatic Server Restart - Machine Type 8482", ASMTYPE_JUNIPER },
 352         { "IBM Automatic Server Restart - Machine Type 8648", ASMTYPE_SPRUCE },
 353         { NULL }
 354 };
 355
 356 static int __init ibmasr_init(void)
 357 {
 358         struct ibmasr_id *id;
 359         int rc;
 360
 361         for (id = ibmasr_id_table; id->desc; id++) {
 362                 if (dmi_find_device(DMI_DEV_TYPE_OTHER, id->desc, NULL)) {
 363                         asr_type = id->type;
 364                         break;
 365                 }
 366         }
 367
 368         if (!asr_type)
 369                 return -ENODEV;
 370
 371         rc = misc_register(&asr_miscdev);
 372         if (rc < 0) {
 373                 printk(KERN_ERR PFX "failed to register misc device\n");
 374                 return rc;
 375         }
 376
 377         rc = asr_get_base_address();
 378         if (rc) {
 379                 misc_deregister(&asr_miscdev);
 380                 return rc;
 381         }
 382
 383         return 0;
 384 }
 385
 386 static void __exit ibmasr_exit(void)
 387 {
 388         if (!nowayout)
 389                 asr_disable();
 390
 391         misc_deregister(&asr_miscdev);
 392
 393         release_region(asr_base, asr_length);
 394 }
 395
 396 module_init(ibmasr_init);
 397 module_exit(ibmasr_exit);
 398
 399 module_param(nowayout, int, 0);
 400 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 401
 402 MODULE_DESCRIPTION("IBM Automatic Server Restart driver");
 403 MODULE_AUTHOR("Andrey Panin");
 404 MODULE_LICENSE("GPL");
 405 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);