git.oblomov.eu Git - linux-2.6/blob - drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/log2.h>
  34
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_pack.h>
  37
  38 #include <linux/mlx4/qp.h>
  39
  40 #include "mlx4_ib.h"
  41 #include "user.h"
  42
  43 enum {
  44         MLX4_IB_ACK_REQ_FREQ    = 8,
  45 };
  46
  47 enum {
  48         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  49         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f
  50 };
  51
  52 enum {
  53         /*
  54          * Largest possible UD header: send with GRH and immediate data.
  55          */
  56         MLX4_IB_UD_HEADER_SIZE          = 72
  57 };
  58
  59 struct mlx4_ib_sqp {
  60         struct mlx4_ib_qp       qp;
  61         int                     pkey_index;
  62         u32                     qkey;
  63         u32                     send_psn;
  64         struct ib_ud_header     ud_header;
  65         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  66 };
  67
  68 enum {
  69         MLX4_IB_MIN_SQ_STRIDE = 6
  70 };
  71
  72 static const __be32 mlx4_ib_opcode[] = {
  73         [IB_WR_SEND]                    = __constant_cpu_to_be32(MLX4_OPCODE_SEND),
  74         [IB_WR_LSO]                     = __constant_cpu_to_be32(MLX4_OPCODE_LSO),
  75         [IB_WR_SEND_WITH_IMM]           = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM),
  76         [IB_WR_RDMA_WRITE]              = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
  77         [IB_WR_RDMA_WRITE_WITH_IMM]     = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
  78         [IB_WR_RDMA_READ]               = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_READ),
  79         [IB_WR_ATOMIC_CMP_AND_SWP]      = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
  80         [IB_WR_ATOMIC_FETCH_AND_ADD]    = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
  81 };
  82
  83 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
  84 {
  85         return container_of(mqp, struct mlx4_ib_sqp, qp);
  86 }
  87
  88 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
  89 {
  90         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
  91                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
  92 }
  93
  94 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
  95 {
  96         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
  97                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
  98 }
  99
 100 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 101 {
 102         return mlx4_buf_offset(&qp->buf, offset);
 103 }
 104
 105 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 106 {
 107         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 108 }
 109
 110 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 111 {
 112         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 113 }
 114
 115 /*
 116  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 117  * first four bytes of every 64 byte chunk with
 118  *     0x7FFFFFF | (invalid_ownership_value << 31).
 119  *
 120  * When the max work request size is less than or equal to the WQE
 121  * basic block size, as an optimization, we can stamp all WQEs with
 122  * 0xffffffff, and skip the very first chunk of each WQE.
 123  */
 124 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 125 {
 126         __be32 *wqe;
 127         int i;
 128         int s;
 129         int ind;
 130         void *buf;
 131         __be32 stamp;
 132         struct mlx4_wqe_ctrl_seg *ctrl;
 133
 134         if (qp->sq_max_wqes_per_wr > 1) {
 135                 s = roundup(size, 1U << qp->sq.wqe_shift);
 136                 for (i = 0; i < s; i += 64) {
 137                         ind = (i >> qp->sq.wqe_shift) + n;
 138                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 139                                                        cpu_to_be32(0xffffffff);
 140                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 141                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 142                         *wqe = stamp;
 143                 }
 144         } else {
 145                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 146                 s = (ctrl->fence_size & 0x3f) << 4;
 147                 for (i = 64; i < s; i += 64) {
 148                         wqe = buf + i;
 149                         *wqe = cpu_to_be32(0xffffffff);
 150                 }
 151         }
 152 }
 153
 154 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 155 {
 156         struct mlx4_wqe_ctrl_seg *ctrl;
 157         struct mlx4_wqe_inline_seg *inl;
 158         void *wqe;
 159         int s;
 160
 161         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 162         s = sizeof(struct mlx4_wqe_ctrl_seg);
 163
 164         if (qp->ibqp.qp_type == IB_QPT_UD) {
 165                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 166                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 167                 memset(dgram, 0, sizeof *dgram);
 168                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 169                 s += sizeof(struct mlx4_wqe_datagram_seg);
 170         }
 171
 172         /* Pad the remainder of the WQE with an inline data segment. */
 173         if (size > s) {
 174                 inl = wqe + s;
 175                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 176         }
 177         ctrl->srcrb_flags = 0;
 178         ctrl->fence_size = size / 16;
 179         /*
 180          * Make sure descriptor is fully written before setting ownership bit
 181          * (because HW can start executing as soon as we do).
 182          */
 183         wmb();
 184
 185         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 186                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 187
 188         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 189 }
 190
 191 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 192 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 193 {
 194         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 195         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 196                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 197                 ind += s;
 198         }
 199         return ind;
 200 }
 201
 202 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 203 {
 204         struct ib_event event;
 205         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 206
 207         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 208                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 209
 210         if (ibqp->event_handler) {
 211                 event.device     = ibqp->device;
 212                 event.element.qp = ibqp;
 213                 switch (type) {
 214                 case MLX4_EVENT_TYPE_PATH_MIG:
 215                         event.event = IB_EVENT_PATH_MIG;
 216                         break;
 217                 case MLX4_EVENT_TYPE_COMM_EST:
 218                         event.event = IB_EVENT_COMM_EST;
 219                         break;
 220                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 221                         event.event = IB_EVENT_SQ_DRAINED;
 222                         break;
 223                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 224                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 225                         break;
 226                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 227                         event.event = IB_EVENT_QP_FATAL;
 228                         break;
 229                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 230                         event.event = IB_EVENT_PATH_MIG_ERR;
 231                         break;
 232                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 233                         event.event = IB_EVENT_QP_REQ_ERR;
 234                         break;
 235                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 236                         event.event = IB_EVENT_QP_ACCESS_ERR;
 237                         break;
 238                 default:
 239                         printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
 240                                "on QP %06x\n", type, qp->qpn);
 241                         return;
 242                 }
 243
 244                 ibqp->event_handler(&event, ibqp->qp_context);
 245         }
 246 }
 247
 248 static int send_wqe_overhead(enum ib_qp_type type, u32 flags)
 249 {
 250         /*
 251          * UD WQEs must have a datagram segment.
 252          * RC and UC WQEs might have a remote address segment.
 253          * MLX WQEs need two extra inline data segments (for the UD
 254          * header and space for the ICRC).
 255          */
 256         switch (type) {
 257         case IB_QPT_UD:
 258                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 259                         sizeof (struct mlx4_wqe_datagram_seg) +
 260                         ((flags & MLX4_IB_QP_LSO) ? 64 : 0);
 261         case IB_QPT_UC:
 262                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 263                         sizeof (struct mlx4_wqe_raddr_seg);
 264         case IB_QPT_RC:
 265                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 266                         sizeof (struct mlx4_wqe_atomic_seg) +
 267                         sizeof (struct mlx4_wqe_raddr_seg);
 268         case IB_QPT_SMI:
 269         case IB_QPT_GSI:
 270                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 271                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 272                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 273                                            MLX4_INLINE_ALIGN) *
 274                               sizeof (struct mlx4_wqe_inline_seg),
 275                               sizeof (struct mlx4_wqe_data_seg)) +
 276                         ALIGN(4 +
 277                               sizeof (struct mlx4_wqe_inline_seg),
 278                               sizeof (struct mlx4_wqe_data_seg));
 279         default:
 280                 return sizeof (struct mlx4_wqe_ctrl_seg);
 281         }
 282 }
 283
 284 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 285                        int is_user, int has_srq, struct mlx4_ib_qp *qp)
 286 {
 287         /* Sanity check RQ size before proceeding */
 288         if (cap->max_recv_wr  > dev->dev->caps.max_wqes  ||
 289             cap->max_recv_sge > dev->dev->caps.max_rq_sg)
 290                 return -EINVAL;
 291
 292         if (has_srq) {
 293                 /* QPs attached to an SRQ should have no RQ */
 294                 if (cap->max_recv_wr)
 295                         return -EINVAL;
 296
 297                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 298         } else {
 299                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 300                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 301                         return -EINVAL;
 302
 303                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 304                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 305                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 306         }
 307
 308         cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 309         cap->max_recv_sge = qp->rq.max_gs;
 310
 311         return 0;
 312 }
 313
 314 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 315                               enum ib_qp_type type, struct mlx4_ib_qp *qp)
 316 {
 317         int s;
 318
 319         /* Sanity check SQ size before proceeding */
 320         if (cap->max_send_wr     > dev->dev->caps.max_wqes  ||
 321             cap->max_send_sge    > dev->dev->caps.max_sq_sg ||
 322             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 323             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 324                 return -EINVAL;
 325
 326         /*
 327          * For MLX transport we need 2 extra S/G entries:
 328          * one for the header and one for the checksum at the end
 329          */
 330         if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
 331             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 332                 return -EINVAL;
 333
 334         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 335                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 336                 send_wqe_overhead(type, qp->flags);
 337
 338         if (s > dev->dev->caps.max_sq_desc_sz)
 339                 return -EINVAL;
 340
 341         /*
 342          * Hermon supports shrinking WQEs, such that a single work
 343          * request can include multiple units of 1 << wqe_shift.  This
 344          * way, work requests can differ in size, and do not have to
 345          * be a power of 2 in size, saving memory and speeding up send
 346          * WR posting.  Unfortunately, if we do this then the
 347          * wqe_index field in CQEs can't be used to look up the WR ID
 348          * anymore, so we do this only if selective signaling is off.
 349          *
 350          * Further, on 32-bit platforms, we can't use vmap() to make
 351          * the QP buffer virtually contigious.  Thus we have to use
 352          * constant-sized WRs to make sure a WR is always fully within
 353          * a single page-sized chunk.
 354          *
 355          * Finally, we use NOP work requests to pad the end of the
 356          * work queue, to avoid wrap-around in the middle of WR.  We
 357          * set NEC bit to avoid getting completions with error for
 358          * these NOP WRs, but since NEC is only supported starting
 359          * with firmware 2.2.232, we use constant-sized WRs for older
 360          * firmware.
 361          *
 362          * And, since MLX QPs only support SEND, we use constant-sized
 363          * WRs in this case.
 364          *
 365          * We look for the smallest value of wqe_shift such that the
 366          * resulting number of wqes does not exceed device
 367          * capabilities.
 368          *
 369          * We set WQE size to at least 64 bytes, this way stamping
 370          * invalidates each WQE.
 371          */
 372         if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 373             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 374             type != IB_QPT_SMI && type != IB_QPT_GSI)
 375                 qp->sq.wqe_shift = ilog2(64);
 376         else
 377                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 378
 379         for (;;) {
 380                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 381
 382                 /*
 383                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 384                  * allow HW to prefetch.
 385                  */
 386                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 387                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 388                                                     qp->sq_max_wqes_per_wr +
 389                                                     qp->sq_spare_wqes);
 390
 391                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 392                         break;
 393
 394                 if (qp->sq_max_wqes_per_wr <= 1)
 395                         return -EINVAL;
 396
 397                 ++qp->sq.wqe_shift;
 398         }
 399
 400         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 401                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 402                          send_wqe_overhead(type, qp->flags)) /
 403                 sizeof (struct mlx4_wqe_data_seg);
 404
 405         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 406                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 407         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 408                 qp->rq.offset = 0;
 409                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 410         } else {
 411                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 412                 qp->sq.offset = 0;
 413         }
 414
 415         cap->max_send_wr  = qp->sq.max_post =
 416                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 417         cap->max_send_sge = min(qp->sq.max_gs,
 418                                 min(dev->dev->caps.max_sq_sg,
 419                                     dev->dev->caps.max_rq_sg));
 420         /* We don't support inline sends for kernel QPs (yet) */
 421         cap->max_inline_data = 0;
 422
 423         return 0;
 424 }
 425
 426 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 427                             struct mlx4_ib_qp *qp,
 428                             struct mlx4_ib_create_qp *ucmd)
 429 {
 430         /* Sanity check SQ size before proceeding */
 431         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 432             ucmd->log_sq_stride >
 433                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 434             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 435                 return -EINVAL;
 436
 437         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 438         qp->sq.wqe_shift = ucmd->log_sq_stride;
 439
 440         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 441                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 442
 443         return 0;
 444 }
 445
 446 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 447                             struct ib_qp_init_attr *init_attr,
 448                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
 449 {
 450         int err;
 451
 452         mutex_init(&qp->mutex);
 453         spin_lock_init(&qp->sq.lock);
 454         spin_lock_init(&qp->rq.lock);
 455
 456         qp->state        = IB_QPS_RESET;
 457         qp->atomic_rd_en = 0;
 458         qp->resp_depth   = 0;
 459
 460         qp->rq.head         = 0;
 461         qp->rq.tail         = 0;
 462         qp->sq.head         = 0;
 463         qp->sq.tail         = 0;
 464         qp->sq_next_wqe     = 0;
 465
 466         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 467                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 468         else
 469                 qp->sq_signal_bits = 0;
 470
 471         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp);
 472         if (err)
 473                 goto err;
 474
 475         if (pd->uobject) {
 476                 struct mlx4_ib_create_qp ucmd;
 477
 478                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 479                         err = -EFAULT;
 480                         goto err;
 481                 }
 482
 483                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 484
 485                 err = set_user_sq_size(dev, qp, &ucmd);
 486                 if (err)
 487                         goto err;
 488
 489                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 490                                        qp->buf_size, 0, 0);
 491                 if (IS_ERR(qp->umem)) {
 492                         err = PTR_ERR(qp->umem);
 493                         goto err;
 494                 }
 495
 496                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 497                                     ilog2(qp->umem->page_size), &qp->mtt);
 498                 if (err)
 499                         goto err_buf;
 500
 501                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 502                 if (err)
 503                         goto err_mtt;
 504
 505                 if (!init_attr->srq) {
 506                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 507                                                   ucmd.db_addr, &qp->db);
 508                         if (err)
 509                                 goto err_mtt;
 510                 }
 511         } else {
 512                 qp->sq_no_prefetch = 0;
 513
 514                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 515                         qp->flags |= MLX4_IB_QP_LSO;
 516
 517                 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
 518                 if (err)
 519                         goto err;
 520
 521                 if (!init_attr->srq) {
 522                         err = mlx4_db_alloc(dev->dev, &qp->db, 0);
 523                         if (err)
 524                                 goto err;
 525
 526                         *qp->db.db = 0;
 527                 }
 528
 529                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
 530                         err = -ENOMEM;
 531                         goto err_db;
 532                 }
 533
 534                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 535                                     &qp->mtt);
 536                 if (err)
 537                         goto err_buf;
 538
 539                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
 540                 if (err)
 541                         goto err_mtt;
 542
 543                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 544                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 545
 546                 if (!qp->sq.wrid || !qp->rq.wrid) {
 547                         err = -ENOMEM;
 548                         goto err_wrid;
 549                 }
 550         }
 551
 552         err = mlx4_qp_alloc(dev->dev, sqpn, &qp->mqp);
 553         if (err)
 554                 goto err_wrid;
 555
 556         /*
 557          * Hardware wants QPN written in big-endian order (after
 558          * shifting) for send doorbell.  Precompute this value to save
 559          * a little bit when posting sends.
 560          */
 561         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 562
 563         qp->mqp.event = mlx4_ib_qp_event;
 564
 565         return 0;
 566
 567 err_wrid:
 568         if (pd->uobject) {
 569                 if (!init_attr->srq)
 570                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context),
 571                                               &qp->db);
 572         } else {
 573                 kfree(qp->sq.wrid);
 574                 kfree(qp->rq.wrid);
 575         }
 576
 577 err_mtt:
 578         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 579
 580 err_buf:
 581         if (pd->uobject)
 582                 ib_umem_release(qp->umem);
 583         else
 584                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 585
 586 err_db:
 587         if (!pd->uobject && !init_attr->srq)
 588                 mlx4_db_free(dev->dev, &qp->db);
 589
 590 err:
 591         return err;
 592 }
 593
 594 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 595 {
 596         switch (state) {
 597         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 598         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 599         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 600         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 601         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 602         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 603         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 604         default:                return -1;
 605         }
 606 }
 607
 608 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 609 {
 610         if (send_cq == recv_cq)
 611                 spin_lock_irq(&send_cq->lock);
 612         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 613                 spin_lock_irq(&send_cq->lock);
 614                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 615         } else {
 616                 spin_lock_irq(&recv_cq->lock);
 617                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 618         }
 619 }
 620
 621 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 622 {
 623         if (send_cq == recv_cq)
 624                 spin_unlock_irq(&send_cq->lock);
 625         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 626                 spin_unlock(&recv_cq->lock);
 627                 spin_unlock_irq(&send_cq->lock);
 628         } else {
 629                 spin_unlock(&send_cq->lock);
 630                 spin_unlock_irq(&recv_cq->lock);
 631         }
 632 }
 633
 634 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 635                               int is_user)
 636 {
 637         struct mlx4_ib_cq *send_cq, *recv_cq;
 638
 639         if (qp->state != IB_QPS_RESET)
 640                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
 641                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
 642                         printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
 643                                qp->mqp.qpn);
 644
 645         send_cq = to_mcq(qp->ibqp.send_cq);
 646         recv_cq = to_mcq(qp->ibqp.recv_cq);
 647
 648         mlx4_ib_lock_cqs(send_cq, recv_cq);
 649
 650         if (!is_user) {
 651                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
 652                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
 653                 if (send_cq != recv_cq)
 654                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
 655         }
 656
 657         mlx4_qp_remove(dev->dev, &qp->mqp);
 658
 659         mlx4_ib_unlock_cqs(send_cq, recv_cq);
 660
 661         mlx4_qp_free(dev->dev, &qp->mqp);
 662         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 663
 664         if (is_user) {
 665                 if (!qp->ibqp.srq)
 666                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
 667                                               &qp->db);
 668                 ib_umem_release(qp->umem);
 669         } else {
 670                 kfree(qp->sq.wrid);
 671                 kfree(qp->rq.wrid);
 672                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 673                 if (!qp->ibqp.srq)
 674                         mlx4_db_free(dev->dev, &qp->db);
 675         }
 676 }
 677
 678 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
 679                                 struct ib_qp_init_attr *init_attr,
 680                                 struct ib_udata *udata)
 681 {
 682         struct mlx4_ib_dev *dev = to_mdev(pd->device);
 683         struct mlx4_ib_sqp *sqp;
 684         struct mlx4_ib_qp *qp;
 685         int err;
 686
 687         /* We only support LSO, and only for kernel UD QPs. */
 688         if (init_attr->create_flags & ~IB_QP_CREATE_IPOIB_UD_LSO)
 689                 return ERR_PTR(-EINVAL);
 690         if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO &&
 691             (pd->uobject || init_attr->qp_type != IB_QPT_UD))
 692                 return ERR_PTR(-EINVAL);
 693
 694         switch (init_attr->qp_type) {
 695         case IB_QPT_RC:
 696         case IB_QPT_UC:
 697         case IB_QPT_UD:
 698         {
 699                 qp = kmalloc(sizeof *qp, GFP_KERNEL);
 700                 if (!qp)
 701                         return ERR_PTR(-ENOMEM);
 702
 703                 err = create_qp_common(dev, pd, init_attr, udata, 0, qp);
 704                 if (err) {
 705                         kfree(qp);
 706                         return ERR_PTR(err);
 707                 }
 708
 709                 qp->ibqp.qp_num = qp->mqp.qpn;
 710
 711                 break;
 712         }
 713         case IB_QPT_SMI:
 714         case IB_QPT_GSI:
 715         {
 716                 /* Userspace is not allowed to create special QPs: */
 717                 if (pd->uobject)
 718                         return ERR_PTR(-EINVAL);
 719
 720                 sqp = kmalloc(sizeof *sqp, GFP_KERNEL);
 721                 if (!sqp)
 722                         return ERR_PTR(-ENOMEM);
 723
 724                 qp = &sqp->qp;
 725
 726                 err = create_qp_common(dev, pd, init_attr, udata,
 727                                        dev->dev->caps.sqp_start +
 728                                        (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
 729                                        init_attr->port_num - 1,
 730                                        qp);
 731                 if (err) {
 732                         kfree(sqp);
 733                         return ERR_PTR(err);
 734                 }
 735
 736                 qp->port        = init_attr->port_num;
 737                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
 738
 739                 break;
 740         }
 741         default:
 742                 /* Don't support raw QPs */
 743                 return ERR_PTR(-EINVAL);
 744         }
 745
 746         return &qp->ibqp;
 747 }
 748
 749 int mlx4_ib_destroy_qp(struct ib_qp *qp)
 750 {
 751         struct mlx4_ib_dev *dev = to_mdev(qp->device);
 752         struct mlx4_ib_qp *mqp = to_mqp(qp);
 753
 754         if (is_qp0(dev, mqp))
 755                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
 756
 757         destroy_qp_common(dev, mqp, !!qp->pd->uobject);
 758
 759         if (is_sqp(dev, mqp))
 760                 kfree(to_msqp(mqp));
 761         else
 762                 kfree(mqp);
 763
 764         return 0;
 765 }
 766
 767 static int to_mlx4_st(enum ib_qp_type type)
 768 {
 769         switch (type) {
 770         case IB_QPT_RC:         return MLX4_QP_ST_RC;
 771         case IB_QPT_UC:         return MLX4_QP_ST_UC;
 772         case IB_QPT_UD:         return MLX4_QP_ST_UD;
 773         case IB_QPT_SMI:
 774         case IB_QPT_GSI:        return MLX4_QP_ST_MLX;
 775         default:                return -1;
 776         }
 777 }
 778
 779 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
 780                                    int attr_mask)
 781 {
 782         u8 dest_rd_atomic;
 783         u32 access_flags;
 784         u32 hw_access_flags = 0;
 785
 786         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 787                 dest_rd_atomic = attr->max_dest_rd_atomic;
 788         else
 789                 dest_rd_atomic = qp->resp_depth;
 790
 791         if (attr_mask & IB_QP_ACCESS_FLAGS)
 792                 access_flags = attr->qp_access_flags;
 793         else
 794                 access_flags = qp->atomic_rd_en;
 795
 796         if (!dest_rd_atomic)
 797                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 798
 799         if (access_flags & IB_ACCESS_REMOTE_READ)
 800                 hw_access_flags |= MLX4_QP_BIT_RRE;
 801         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 802                 hw_access_flags |= MLX4_QP_BIT_RAE;
 803         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 804                 hw_access_flags |= MLX4_QP_BIT_RWE;
 805
 806         return cpu_to_be32(hw_access_flags);
 807 }
 808
 809 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
 810                             int attr_mask)
 811 {
 812         if (attr_mask & IB_QP_PKEY_INDEX)
 813                 sqp->pkey_index = attr->pkey_index;
 814         if (attr_mask & IB_QP_QKEY)
 815                 sqp->qkey = attr->qkey;
 816         if (attr_mask & IB_QP_SQ_PSN)
 817                 sqp->send_psn = attr->sq_psn;
 818 }
 819
 820 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
 821 {
 822         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
 823 }
 824
 825 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
 826                          struct mlx4_qp_path *path, u8 port)
 827 {
 828         path->grh_mylmc     = ah->src_path_bits & 0x7f;
 829         path->rlid          = cpu_to_be16(ah->dlid);
 830         if (ah->static_rate) {
 831                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
 832                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
 833                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
 834                         --path->static_rate;
 835         } else
 836                 path->static_rate = 0;
 837         path->counter_index = 0xff;
 838
 839         if (ah->ah_flags & IB_AH_GRH) {
 840                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
 841                         printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
 842                                ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
 843                         return -1;
 844                 }
 845
 846                 path->grh_mylmc |= 1 << 7;
 847                 path->mgid_index = ah->grh.sgid_index;
 848                 path->hop_limit  = ah->grh.hop_limit;
 849                 path->tclass_flowlabel =
 850                         cpu_to_be32((ah->grh.traffic_class << 20) |
 851                                     (ah->grh.flow_label));
 852                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 853         }
 854
 855         path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
 856                 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
 857
 858         return 0;
 859 }
 860
 861 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
 862                                const struct ib_qp_attr *attr, int attr_mask,
 863                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
 864 {
 865         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
 866         struct mlx4_ib_qp *qp = to_mqp(ibqp);
 867         struct mlx4_qp_context *context;
 868         enum mlx4_qp_optpar optpar = 0;
 869         int sqd_event;
 870         int err = -EINVAL;
 871
 872         context = kzalloc(sizeof *context, GFP_KERNEL);
 873         if (!context)
 874                 return -ENOMEM;
 875
 876         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
 877                                      (to_mlx4_st(ibqp->qp_type) << 16));
 878         context->flags     |= cpu_to_be32(1 << 8); /* DE? */
 879
 880         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 881                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
 882         else {
 883                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
 884                 switch (attr->path_mig_state) {
 885                 case IB_MIG_MIGRATED:
 886                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
 887                         break;
 888                 case IB_MIG_REARM:
 889                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
 890                         break;
 891                 case IB_MIG_ARMED:
 892                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
 893                         break;
 894                 }
 895         }
 896
 897         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
 898                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
 899         else if (ibqp->qp_type == IB_QPT_UD) {
 900                 if (qp->flags & MLX4_IB_QP_LSO)
 901                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
 902                                               ilog2(dev->dev->caps.max_gso_sz);
 903                 else
 904                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
 905         } else if (attr_mask & IB_QP_PATH_MTU) {
 906                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
 907                         printk(KERN_ERR "path MTU (%u) is invalid\n",
 908                                attr->path_mtu);
 909                         goto out;
 910                 }
 911                 context->mtu_msgmax = (attr->path_mtu << 5) |
 912                         ilog2(dev->dev->caps.max_msg_sz);
 913         }
 914
 915         if (qp->rq.wqe_cnt)
 916                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
 917         context->rq_size_stride |= qp->rq.wqe_shift - 4;
 918
 919         if (qp->sq.wqe_cnt)
 920                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
 921         context->sq_size_stride |= qp->sq.wqe_shift - 4;
 922
 923         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
 924                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
 925
 926         if (qp->ibqp.uobject)
 927                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
 928         else
 929                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
 930
 931         if (attr_mask & IB_QP_DEST_QPN)
 932                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 933
 934         if (attr_mask & IB_QP_PORT) {
 935                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
 936                     !(attr_mask & IB_QP_AV)) {
 937                         mlx4_set_sched(&context->pri_path, attr->port_num);
 938                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
 939                 }
 940         }
 941
 942         if (attr_mask & IB_QP_PKEY_INDEX) {
 943                 context->pri_path.pkey_index = attr->pkey_index;
 944                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
 945         }
 946
 947         if (attr_mask & IB_QP_AV) {
 948                 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
 949                                   attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
 950                         goto out;
 951
 952                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
 953                            MLX4_QP_OPTPAR_SCHED_QUEUE);
 954         }
 955
 956         if (attr_mask & IB_QP_TIMEOUT) {
 957                 context->pri_path.ackto = attr->timeout << 3;
 958                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
 959         }
 960
 961         if (attr_mask & IB_QP_ALT_PATH) {
 962                 if (attr->alt_port_num == 0 ||
 963                     attr->alt_port_num > dev->dev->caps.num_ports)
 964                         goto out;
 965
 966                 if (attr->alt_pkey_index >=
 967                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
 968                         goto out;
 969
 970                 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
 971                                   attr->alt_port_num))
 972                         goto out;
 973
 974                 context->alt_path.pkey_index = attr->alt_pkey_index;
 975                 context->alt_path.ackto = attr->alt_timeout << 3;
 976                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
 977         }
 978
 979         context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
 980         context->params1    = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
 981
 982         if (attr_mask & IB_QP_RNR_RETRY) {
 983                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
 984                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
 985         }
 986
 987         if (attr_mask & IB_QP_RETRY_CNT) {
 988                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 989                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
 990         }
 991
 992         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 993                 if (attr->max_rd_atomic)
 994                         context->params1 |=
 995                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 996                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
 997         }
 998
 999         if (attr_mask & IB_QP_SQ_PSN)
1000                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1001
1002         context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn);
1003
1004         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1005                 if (attr->max_dest_rd_atomic)
1006                         context->params2 |=
1007                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1008                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1009         }
1010
1011         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1012                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1013                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1014         }
1015
1016         if (ibqp->srq)
1017                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1018
1019         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1020                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1021                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1022         }
1023         if (attr_mask & IB_QP_RQ_PSN)
1024                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1025
1026         context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn);
1027
1028         if (attr_mask & IB_QP_QKEY) {
1029                 context->qkey = cpu_to_be32(attr->qkey);
1030                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1031         }
1032
1033         if (ibqp->srq)
1034                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1035
1036         if (!ibqp->srq && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1037                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1038
1039         if (cur_state == IB_QPS_INIT &&
1040             new_state == IB_QPS_RTR  &&
1041             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1042              ibqp->qp_type == IB_QPT_UD)) {
1043                 context->pri_path.sched_queue = (qp->port - 1) << 6;
1044                 if (is_qp0(dev, qp))
1045                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1046                 else
1047                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1048         }
1049
1050         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1051             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1052                 sqd_event = 1;
1053         else
1054                 sqd_event = 0;
1055
1056         /*
1057          * Before passing a kernel QP to the HW, make sure that the
1058          * ownership bits of the send queue are set and the SQ
1059          * headroom is stamped so that the hardware doesn't start
1060          * processing stale work requests.
1061          */
1062         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1063                 struct mlx4_wqe_ctrl_seg *ctrl;
1064                 int i;
1065
1066                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1067                         ctrl = get_send_wqe(qp, i);
1068                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
1069                         if (qp->sq_max_wqes_per_wr == 1)
1070                                 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1071
1072                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1073                 }
1074         }
1075
1076         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1077                              to_mlx4_state(new_state), context, optpar,
1078                              sqd_event, &qp->mqp);
1079         if (err)
1080                 goto out;
1081
1082         qp->state = new_state;
1083
1084         if (attr_mask & IB_QP_ACCESS_FLAGS)
1085                 qp->atomic_rd_en = attr->qp_access_flags;
1086         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1087                 qp->resp_depth = attr->max_dest_rd_atomic;
1088         if (attr_mask & IB_QP_PORT)
1089                 qp->port = attr->port_num;
1090         if (attr_mask & IB_QP_ALT_PATH)
1091                 qp->alt_port = attr->alt_port_num;
1092
1093         if (is_sqp(dev, qp))
1094                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1095
1096         /*
1097          * If we moved QP0 to RTR, bring the IB link up; if we moved
1098          * QP0 to RESET or ERROR, bring the link back down.
1099          */
1100         if (is_qp0(dev, qp)) {
1101                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1102                         if (mlx4_INIT_PORT(dev->dev, qp->port))
1103                                 printk(KERN_WARNING "INIT_PORT failed for port %d\n",
1104                                        qp->port);
1105
1106                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1107                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1108                         mlx4_CLOSE_PORT(dev->dev, qp->port);
1109         }
1110
1111         /*
1112          * If we moved a kernel QP to RESET, clean up all old CQ
1113          * entries and reinitialize the QP.
1114          */
1115         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1116                 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn,
1117                                  ibqp->srq ? to_msrq(ibqp->srq): NULL);
1118                 if (ibqp->send_cq != ibqp->recv_cq)
1119                         mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL);
1120
1121                 qp->rq.head = 0;
1122                 qp->rq.tail = 0;
1123                 qp->sq.head = 0;
1124                 qp->sq.tail = 0;
1125                 qp->sq_next_wqe = 0;
1126                 if (!ibqp->srq)
1127                         *qp->db.db  = 0;
1128         }
1129
1130 out:
1131         kfree(context);
1132         return err;
1133 }
1134
1135 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1136                       int attr_mask, struct ib_udata *udata)
1137 {
1138         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1139         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1140         enum ib_qp_state cur_state, new_state;
1141         int err = -EINVAL;
1142
1143         mutex_lock(&qp->mutex);
1144
1145         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1146         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1147
1148         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1149                 goto out;
1150
1151         if ((attr_mask & IB_QP_PORT) &&
1152             (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
1153                 goto out;
1154         }
1155
1156         if (attr_mask & IB_QP_PKEY_INDEX) {
1157                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1158                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p])
1159                         goto out;
1160         }
1161
1162         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1163             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1164                 goto out;
1165         }
1166
1167         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1168             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1169                 goto out;
1170         }
1171
1172         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1173                 err = 0;
1174                 goto out;
1175         }
1176
1177         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1178
1179 out:
1180         mutex_unlock(&qp->mutex);
1181         return err;
1182 }
1183
1184 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1185                             void *wqe, unsigned *mlx_seg_len)
1186 {
1187         struct ib_device *ib_dev = &to_mdev(sqp->qp.ibqp.device)->ib_dev;
1188         struct mlx4_wqe_mlx_seg *mlx = wqe;
1189         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1190         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1191         u16 pkey;
1192         int send_size;
1193         int header_size;
1194         int spc;
1195         int i;
1196
1197         send_size = 0;
1198         for (i = 0; i < wr->num_sge; ++i)
1199                 send_size += wr->sg_list[i].length;
1200
1201         ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), &sqp->ud_header);
1202
1203         sqp->ud_header.lrh.service_level   =
1204                 be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28;
1205         sqp->ud_header.lrh.destination_lid = ah->av.dlid;
1206         sqp->ud_header.lrh.source_lid      = cpu_to_be16(ah->av.g_slid & 0x7f);
1207         if (mlx4_ib_ah_grh_present(ah)) {
1208                 sqp->ud_header.grh.traffic_class =
1209                         (be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff;
1210                 sqp->ud_header.grh.flow_label    =
1211                         ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1212                 sqp->ud_header.grh.hop_limit     = ah->av.hop_limit;
1213                 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.port_pd) >> 24,
1214                                   ah->av.gid_index, &sqp->ud_header.grh.source_gid);
1215                 memcpy(sqp->ud_header.grh.destination_gid.raw,
1216                        ah->av.dgid, 16);
1217         }
1218
1219         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1220         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1221                                   (sqp->ud_header.lrh.destination_lid ==
1222                                    IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1223                                   (sqp->ud_header.lrh.service_level << 8));
1224         mlx->rlid   = sqp->ud_header.lrh.destination_lid;
1225
1226         switch (wr->opcode) {
1227         case IB_WR_SEND:
1228                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
1229                 sqp->ud_header.immediate_present = 0;
1230                 break;
1231         case IB_WR_SEND_WITH_IMM:
1232                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1233                 sqp->ud_header.immediate_present = 1;
1234                 sqp->ud_header.immediate_data    = wr->ex.imm_data;
1235                 break;
1236         default:
1237                 return -EINVAL;
1238         }
1239
1240         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1241         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1242                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1243         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1244         if (!sqp->qp.ibqp.qp_num)
1245                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1246         else
1247                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1248         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1249         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1250         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1251         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1252                                                sqp->qkey : wr->wr.ud.remote_qkey);
1253         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1254
1255         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1256
1257         if (0) {
1258                 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1259                 for (i = 0; i < header_size / 4; ++i) {
1260                         if (i % 8 == 0)
1261                                 printk("  [%02x] ", i * 4);
1262                         printk(" %08x",
1263                                be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1264                         if ((i + 1) % 8 == 0)
1265                                 printk("\n");
1266                 }
1267                 printk("\n");
1268         }
1269
1270         /*
1271          * Inline data segments may not cross a 64 byte boundary.  If
1272          * our UD header is bigger than the space available up to the
1273          * next 64 byte boundary in the WQE, use two inline data
1274          * segments to hold the UD header.
1275          */
1276         spc = MLX4_INLINE_ALIGN -
1277                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1278         if (header_size <= spc) {
1279                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1280                 memcpy(inl + 1, sqp->header_buf, header_size);
1281                 i = 1;
1282         } else {
1283                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1284                 memcpy(inl + 1, sqp->header_buf, spc);
1285
1286                 inl = (void *) (inl + 1) + spc;
1287                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1288                 /*
1289                  * Need a barrier here to make sure all the data is
1290                  * visible before the byte_count field is set.
1291                  * Otherwise the HCA prefetcher could grab the 64-byte
1292                  * chunk with this inline segment and get a valid (!=
1293                  * 0xffffffff) byte count but stale data, and end up
1294                  * generating a packet with bad headers.
1295                  *
1296                  * The first inline segment's byte_count field doesn't
1297                  * need a barrier, because it comes after a
1298                  * control/MLX segment and therefore is at an offset
1299                  * of 16 mod 64.
1300                  */
1301                 wmb();
1302                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1303                 i = 2;
1304         }
1305
1306         *mlx_seg_len =
1307                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1308         return 0;
1309 }
1310
1311 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1312 {
1313         unsigned cur;
1314         struct mlx4_ib_cq *cq;
1315
1316         cur = wq->head - wq->tail;
1317         if (likely(cur + nreq < wq->max_post))
1318                 return 0;
1319
1320         cq = to_mcq(ib_cq);
1321         spin_lock(&cq->lock);
1322         cur = wq->head - wq->tail;
1323         spin_unlock(&cq->lock);
1324
1325         return cur + nreq >= wq->max_post;
1326 }
1327
1328 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
1329                                           u64 remote_addr, u32 rkey)
1330 {
1331         rseg->raddr    = cpu_to_be64(remote_addr);
1332         rseg->rkey     = cpu_to_be32(rkey);
1333         rseg->reserved = 0;
1334 }
1335
1336 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
1337 {
1338         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1339                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1340                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add);
1341         } else {
1342                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1343                 aseg->compare  = 0;
1344         }
1345
1346 }
1347
1348 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
1349                              struct ib_send_wr *wr)
1350 {
1351         memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1352         dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1353         dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1354 }
1355
1356 static void set_mlx_icrc_seg(void *dseg)
1357 {
1358         u32 *t = dseg;
1359         struct mlx4_wqe_inline_seg *iseg = dseg;
1360
1361         t[1] = 0;
1362
1363         /*
1364          * Need a barrier here before writing the byte_count field to
1365          * make sure that all the data is visible before the
1366          * byte_count field is set.  Otherwise, if the segment begins
1367          * a new cacheline, the HCA prefetcher could grab the 64-byte
1368          * chunk and get a valid (!= * 0xffffffff) byte count but
1369          * stale data, and end up sending the wrong data.
1370          */
1371         wmb();
1372
1373         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
1374 }
1375
1376 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1377 {
1378         dseg->lkey       = cpu_to_be32(sg->lkey);
1379         dseg->addr       = cpu_to_be64(sg->addr);
1380
1381         /*
1382          * Need a barrier here before writing the byte_count field to
1383          * make sure that all the data is visible before the
1384          * byte_count field is set.  Otherwise, if the segment begins
1385          * a new cacheline, the HCA prefetcher could grab the 64-byte
1386          * chunk and get a valid (!= * 0xffffffff) byte count but
1387          * stale data, and end up sending the wrong data.
1388          */
1389         wmb();
1390
1391         dseg->byte_count = cpu_to_be32(sg->length);
1392 }
1393
1394 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1395 {
1396         dseg->byte_count = cpu_to_be32(sg->length);
1397         dseg->lkey       = cpu_to_be32(sg->lkey);
1398         dseg->addr       = cpu_to_be64(sg->addr);
1399 }
1400
1401 static int build_lso_seg(struct mlx4_lso_seg *wqe, struct ib_send_wr *wr,
1402                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len)
1403 {
1404         unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
1405
1406         /*
1407          * This is a temporary limitation and will be removed in
1408          * a forthcoming FW release:
1409          */
1410         if (unlikely(halign > 64))
1411                 return -EINVAL;
1412
1413         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
1414                      wr->num_sge > qp->sq.max_gs - (halign >> 4)))
1415                 return -EINVAL;
1416
1417         memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
1418
1419         /* make sure LSO header is written before overwriting stamping */
1420         wmb();
1421
1422         wqe->mss_hdr_size = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
1423                                         wr->wr.ud.hlen);
1424
1425         *lso_seg_len = halign;
1426         return 0;
1427 }
1428
1429 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1430                       struct ib_send_wr **bad_wr)
1431 {
1432         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1433         void *wqe;
1434         struct mlx4_wqe_ctrl_seg *ctrl;
1435         struct mlx4_wqe_data_seg *dseg;
1436         unsigned long flags;
1437         int nreq;
1438         int err = 0;
1439         unsigned ind;
1440         int uninitialized_var(stamp);
1441         int uninitialized_var(size);
1442         unsigned uninitialized_var(seglen);
1443         int i;
1444
1445         spin_lock_irqsave(&qp->sq.lock, flags);
1446
1447         ind = qp->sq_next_wqe;
1448
1449         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1450                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1451                         err = -ENOMEM;
1452                         *bad_wr = wr;
1453                         goto out;
1454                 }
1455
1456                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1457                         err = -EINVAL;
1458                         *bad_wr = wr;
1459                         goto out;
1460                 }
1461
1462                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
1463                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
1464
1465                 ctrl->srcrb_flags =
1466                         (wr->send_flags & IB_SEND_SIGNALED ?
1467                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1468                         (wr->send_flags & IB_SEND_SOLICITED ?
1469                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
1470                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
1471                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
1472                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
1473                         qp->sq_signal_bits;
1474
1475                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1476                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1477                         ctrl->imm = wr->ex.imm_data;
1478                 else
1479                         ctrl->imm = 0;
1480
1481                 wqe += sizeof *ctrl;
1482                 size = sizeof *ctrl / 16;
1483
1484                 switch (ibqp->qp_type) {
1485                 case IB_QPT_RC:
1486                 case IB_QPT_UC:
1487                         switch (wr->opcode) {
1488                         case IB_WR_ATOMIC_CMP_AND_SWP:
1489                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1490                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1491                                               wr->wr.atomic.rkey);
1492                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1493
1494                                 set_atomic_seg(wqe, wr);
1495                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
1496
1497                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1498                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1499
1500                                 break;
1501
1502                         case IB_WR_RDMA_READ:
1503                         case IB_WR_RDMA_WRITE:
1504                         case IB_WR_RDMA_WRITE_WITH_IMM:
1505                                 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1506                                               wr->wr.rdma.rkey);
1507                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1508                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
1509                                 break;
1510
1511                         default:
1512                                 /* No extra segments required for sends */
1513                                 break;
1514                         }
1515                         break;
1516
1517                 case IB_QPT_UD:
1518                         set_datagram_seg(wqe, wr);
1519                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
1520                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
1521
1522                         if (wr->opcode == IB_WR_LSO) {
1523                                 err = build_lso_seg(wqe, wr, qp, &seglen);
1524                                 if (unlikely(err)) {
1525                                         *bad_wr = wr;
1526                                         goto out;
1527                                 }
1528                                 wqe  += seglen;
1529                                 size += seglen / 16;
1530                         }
1531                         break;
1532
1533                 case IB_QPT_SMI:
1534                 case IB_QPT_GSI:
1535                         err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
1536                         if (unlikely(err)) {
1537                                 *bad_wr = wr;
1538                                 goto out;
1539                         }
1540                         wqe  += seglen;
1541                         size += seglen / 16;
1542                         break;
1543
1544                 default:
1545                         break;
1546                 }
1547
1548                 /*
1549                  * Write data segments in reverse order, so as to
1550                  * overwrite cacheline stamp last within each
1551                  * cacheline.  This avoids issues with WQE
1552                  * prefetching.
1553                  */
1554
1555                 dseg = wqe;
1556                 dseg += wr->num_sge - 1;
1557                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
1558
1559                 /* Add one more inline data segment for ICRC for MLX sends */
1560                 if (unlikely(qp->ibqp.qp_type == IB_QPT_SMI ||
1561                              qp->ibqp.qp_type == IB_QPT_GSI)) {
1562                         set_mlx_icrc_seg(dseg + 1);
1563                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
1564                 }
1565
1566                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
1567                         set_data_seg(dseg, wr->sg_list + i);
1568
1569                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1570                                     MLX4_WQE_CTRL_FENCE : 0) | size;
1571
1572                 /*
1573                  * Make sure descriptor is fully written before
1574                  * setting ownership bit (because HW can start
1575                  * executing as soon as we do).
1576                  */
1577                 wmb();
1578
1579                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
1580                         err = -EINVAL;
1581                         goto out;
1582                 }
1583
1584                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
1585                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
1586
1587                 stamp = ind + qp->sq_spare_wqes;
1588                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
1589
1590                 /*
1591                  * We can improve latency by not stamping the last
1592                  * send queue WQE until after ringing the doorbell, so
1593                  * only stamp here if there are still more WQEs to post.
1594                  *
1595                  * Same optimization applies to padding with NOP wqe
1596                  * in case of WQE shrinking (used to prevent wrap-around
1597                  * in the middle of WR).
1598                  */
1599                 if (wr->next) {
1600                         stamp_send_wqe(qp, stamp, size * 16);
1601                         ind = pad_wraparound(qp, ind);
1602                 }
1603
1604         }
1605
1606 out:
1607         if (likely(nreq)) {
1608                 qp->sq.head += nreq;
1609
1610                 /*
1611                  * Make sure that descriptors are written before
1612                  * doorbell record.
1613                  */
1614                 wmb();
1615
1616                 writel(qp->doorbell_qpn,
1617                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1618
1619                 /*
1620                  * Make sure doorbells don't leak out of SQ spinlock
1621                  * and reach the HCA out of order.
1622                  */
1623                 mmiowb();
1624
1625                 stamp_send_wqe(qp, stamp, size * 16);
1626
1627                 ind = pad_wraparound(qp, ind);
1628                 qp->sq_next_wqe = ind;
1629         }
1630
1631         spin_unlock_irqrestore(&qp->sq.lock, flags);
1632
1633         return err;
1634 }
1635
1636 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1637                       struct ib_recv_wr **bad_wr)
1638 {
1639         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1640         struct mlx4_wqe_data_seg *scat;
1641         unsigned long flags;
1642         int err = 0;
1643         int nreq;
1644         int ind;
1645         int i;
1646
1647         spin_lock_irqsave(&qp->rq.lock, flags);
1648
1649         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
1650
1651         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1652                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.send_cq)) {
1653                         err = -ENOMEM;
1654                         *bad_wr = wr;
1655                         goto out;
1656                 }
1657
1658                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1659                         err = -EINVAL;
1660                         *bad_wr = wr;
1661                         goto out;
1662                 }
1663
1664                 scat = get_recv_wqe(qp, ind);
1665
1666                 for (i = 0; i < wr->num_sge; ++i)
1667                         __set_data_seg(scat + i, wr->sg_list + i);
1668
1669                 if (i < qp->rq.max_gs) {
1670                         scat[i].byte_count = 0;
1671                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
1672                         scat[i].addr       = 0;
1673                 }
1674
1675                 qp->rq.wrid[ind] = wr->wr_id;
1676
1677                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
1678         }
1679
1680 out:
1681         if (likely(nreq)) {
1682                 qp->rq.head += nreq;
1683
1684                 /*
1685                  * Make sure that descriptors are written before
1686                  * doorbell record.
1687                  */
1688                 wmb();
1689
1690                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1691         }
1692
1693         spin_unlock_irqrestore(&qp->rq.lock, flags);
1694
1695         return err;
1696 }
1697
1698 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
1699 {
1700         switch (mlx4_state) {
1701         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
1702         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
1703         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
1704         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
1705         case MLX4_QP_STATE_SQ_DRAINING:
1706         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
1707         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
1708         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
1709         default:                     return -1;
1710         }
1711 }
1712
1713 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
1714 {
1715         switch (mlx4_mig_state) {
1716         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
1717         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
1718         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
1719         default: return -1;
1720         }
1721 }
1722
1723 static int to_ib_qp_access_flags(int mlx4_flags)
1724 {
1725         int ib_flags = 0;
1726
1727         if (mlx4_flags & MLX4_QP_BIT_RRE)
1728                 ib_flags |= IB_ACCESS_REMOTE_READ;
1729         if (mlx4_flags & MLX4_QP_BIT_RWE)
1730                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
1731         if (mlx4_flags & MLX4_QP_BIT_RAE)
1732                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
1733
1734         return ib_flags;
1735 }
1736
1737 static void to_ib_ah_attr(struct mlx4_dev *dev, struct ib_ah_attr *ib_ah_attr,
1738                                 struct mlx4_qp_path *path)
1739 {
1740         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
1741         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
1742
1743         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
1744                 return;
1745
1746         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
1747         ib_ah_attr->sl            = (path->sched_queue >> 2) & 0xf;
1748         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
1749         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
1750         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
1751         if (ib_ah_attr->ah_flags) {
1752                 ib_ah_attr->grh.sgid_index = path->mgid_index;
1753                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
1754                 ib_ah_attr->grh.traffic_class =
1755                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
1756                 ib_ah_attr->grh.flow_label =
1757                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
1758                 memcpy(ib_ah_attr->grh.dgid.raw,
1759                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
1760         }
1761 }
1762
1763 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1764                      struct ib_qp_init_attr *qp_init_attr)
1765 {
1766         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1767         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1768         struct mlx4_qp_context context;
1769         int mlx4_state;
1770         int err = 0;
1771
1772         mutex_lock(&qp->mutex);
1773
1774         if (qp->state == IB_QPS_RESET) {
1775                 qp_attr->qp_state = IB_QPS_RESET;
1776                 goto done;
1777         }
1778
1779         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
1780         if (err) {
1781                 err = -EINVAL;
1782                 goto out;
1783         }
1784
1785         mlx4_state = be32_to_cpu(context.flags) >> 28;
1786
1787         qp->state                    = to_ib_qp_state(mlx4_state);
1788         qp_attr->qp_state            = qp->state;
1789         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
1790         qp_attr->path_mig_state      =
1791                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
1792         qp_attr->qkey                = be32_to_cpu(context.qkey);
1793         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
1794         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
1795         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
1796         qp_attr->qp_access_flags     =
1797                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
1798
1799         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
1800                 to_ib_ah_attr(dev->dev, &qp_attr->ah_attr, &context.pri_path);
1801                 to_ib_ah_attr(dev->dev, &qp_attr->alt_ah_attr, &context.alt_path);
1802                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
1803                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
1804         }
1805
1806         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1807         if (qp_attr->qp_state == IB_QPS_INIT)
1808                 qp_attr->port_num = qp->port;
1809         else
1810                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
1811
1812         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
1813         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
1814
1815         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
1816
1817         qp_attr->max_dest_rd_atomic =
1818                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
1819         qp_attr->min_rnr_timer      =
1820                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
1821         qp_attr->timeout            = context.pri_path.ackto >> 3;
1822         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
1823         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
1824         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
1825
1826 done:
1827         qp_attr->cur_qp_state        = qp_attr->qp_state;
1828         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
1829         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
1830
1831         if (!ibqp->uobject) {
1832                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
1833                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
1834         } else {
1835                 qp_attr->cap.max_send_wr  = 0;
1836                 qp_attr->cap.max_send_sge = 0;
1837         }
1838
1839         /*
1840          * We don't support inline sends for kernel QPs (yet), and we
1841          * don't know what userspace's value should be.
1842          */
1843         qp_attr->cap.max_inline_data = 0;
1844
1845         qp_init_attr->cap            = qp_attr->cap;
1846
1847 out:
1848         mutex_unlock(&qp->mutex);
1849         return err;
1850 }
1851