Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6
[linux-2.6] / arch / mips / kernel / cpu-probe.c
1 /*
2  * Processor capabilities determination functions.
3  *
4  * Copyright (C) xxxx  the Anonymous
5  * Copyright (C) 1994 - 2006 Ralf Baechle
6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
7  * Copyright (C) 2001, 2004  MIPS Inc.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * as published by the Free Software Foundation; either version
12  * 2 of the License, or (at your option) any later version.
13  */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/stddef.h>
18
19 #include <asm/bugs.h>
20 #include <asm/cpu.h>
21 #include <asm/fpu.h>
22 #include <asm/mipsregs.h>
23 #include <asm/system.h>
24
25 /*
26  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
27  * the implementation of the "wait" feature differs between CPU families. This
28  * points to the function that implements CPU specific wait.
29  * The wait instruction stops the pipeline and reduces the power consumption of
30  * the CPU very much.
31  */
32 void (*cpu_wait)(void) = NULL;
33
34 static void r3081_wait(void)
35 {
36         unsigned long cfg = read_c0_conf();
37         write_c0_conf(cfg | R30XX_CONF_HALT);
38 }
39
40 static void r39xx_wait(void)
41 {
42         local_irq_disable();
43         if (!need_resched())
44                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
45         local_irq_enable();
46 }
47
48 /*
49  * There is a race when WAIT instruction executed with interrupt
50  * enabled.
51  * But it is implementation-dependent wheter the pipelie restarts when
52  * a non-enabled interrupt is requested.
53  */
54 static void r4k_wait(void)
55 {
56         __asm__("       .set    mips3                   \n"
57                 "       wait                            \n"
58                 "       .set    mips0                   \n");
59 }
60
61 /*
62  * This variant is preferable as it allows testing need_resched and going to
63  * sleep depending on the outcome atomically.  Unfortunately the "It is
64  * implementation-dependent whether the pipeline restarts when a non-enabled
65  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
66  * using this version a gamble.
67  */
68 static void r4k_wait_irqoff(void)
69 {
70         local_irq_disable();
71         if (!need_resched())
72                 __asm__("       .set    mips3           \n"
73                         "       wait                    \n"
74                         "       .set    mips0           \n");
75         local_irq_enable();
76 }
77
78 /*
79  * The RM7000 variant has to handle erratum 38.  The workaround is to not
80  * have any pending stores when the WAIT instruction is executed.
81  */
82 static void rm7k_wait_irqoff(void)
83 {
84         local_irq_disable();
85         if (!need_resched())
86                 __asm__(
87                 "       .set    push                                    \n"
88                 "       .set    mips3                                   \n"
89                 "       .set    noat                                    \n"
90                 "       mfc0    $1, $12                                 \n"
91                 "       sync                                            \n"
92                 "       mtc0    $1, $12         # stalls until W stage  \n"
93                 "       wait                                            \n"
94                 "       mtc0    $1, $12         # stalls until W stage  \n"
95                 "       .set    pop                                     \n");
96         local_irq_enable();
97 }
98
99 /* The Au1xxx wait is available only if using 32khz counter or
100  * external timer source, but specifically not CP0 Counter. */
101 int allow_au1k_wait;
102
103 static void au1k_wait(void)
104 {
105         /* using the wait instruction makes CP0 counter unusable */
106         __asm__("       .set    mips3                   \n"
107                 "       cache   0x14, 0(%0)             \n"
108                 "       cache   0x14, 32(%0)            \n"
109                 "       sync                            \n"
110                 "       nop                             \n"
111                 "       wait                            \n"
112                 "       nop                             \n"
113                 "       nop                             \n"
114                 "       nop                             \n"
115                 "       nop                             \n"
116                 "       .set    mips0                   \n"
117                 : : "r" (au1k_wait));
118 }
119
120 static int __initdata nowait = 0;
121
122 static int __init wait_disable(char *s)
123 {
124         nowait = 1;
125
126         return 1;
127 }
128
129 __setup("nowait", wait_disable);
130
131 static inline void check_wait(void)
132 {
133         struct cpuinfo_mips *c = &current_cpu_data;
134
135         if (nowait) {
136                 printk("Wait instruction disabled.\n");
137                 return;
138         }
139
140         switch (c->cputype) {
141         case CPU_R3081:
142         case CPU_R3081E:
143                 cpu_wait = r3081_wait;
144                 break;
145         case CPU_TX3927:
146                 cpu_wait = r39xx_wait;
147                 break;
148         case CPU_R4200:
149 /*      case CPU_R4300: */
150         case CPU_R4600:
151         case CPU_R4640:
152         case CPU_R4650:
153         case CPU_R4700:
154         case CPU_R5000:
155         case CPU_NEVADA:
156         case CPU_4KC:
157         case CPU_4KEC:
158         case CPU_4KSC:
159         case CPU_5KC:
160         case CPU_25KF:
161         case CPU_PR4450:
162         case CPU_BCM3302:
163                 cpu_wait = r4k_wait;
164                 break;
165
166         case CPU_RM7000:
167                 cpu_wait = rm7k_wait_irqoff;
168                 break;
169
170         case CPU_24K:
171         case CPU_34K:
172         case CPU_1004K:
173                 cpu_wait = r4k_wait;
174                 if (read_c0_config7() & MIPS_CONF7_WII)
175                         cpu_wait = r4k_wait_irqoff;
176                 break;
177
178         case CPU_74K:
179                 cpu_wait = r4k_wait;
180                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
181                         cpu_wait = r4k_wait_irqoff;
182                 break;
183
184         case CPU_TX49XX:
185                 cpu_wait = r4k_wait_irqoff;
186                 break;
187         case CPU_AU1000:
188         case CPU_AU1100:
189         case CPU_AU1500:
190         case CPU_AU1550:
191         case CPU_AU1200:
192         case CPU_AU1210:
193         case CPU_AU1250:
194                 if (allow_au1k_wait)
195                         cpu_wait = au1k_wait;
196                 break;
197         case CPU_20KC:
198                 /*
199                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
200                  * WAIT on Rev2.0 and Rev3.0 has E16.
201                  * Rev3.1 WAIT is nop, why bother
202                  */
203                 if ((c->processor_id & 0xff) <= 0x64)
204                         break;
205
206                 /*
207                  * Another rev is incremeting c0_count at a reduced clock
208                  * rate while in WAIT mode.  So we basically have the choice
209                  * between using the cp0 timer as clocksource or avoiding
210                  * the WAIT instruction.  Until more details are known,
211                  * disable the use of WAIT for 20Kc entirely.
212                    cpu_wait = r4k_wait;
213                  */
214                 break;
215         case CPU_RM9000:
216                 if ((c->processor_id & 0x00ff) >= 0x40)
217                         cpu_wait = r4k_wait;
218                 break;
219         default:
220                 break;
221         }
222 }
223
224 static inline void check_errata(void)
225 {
226         struct cpuinfo_mips *c = &current_cpu_data;
227
228         switch (c->cputype) {
229         case CPU_34K:
230                 /*
231                  * Erratum "RPS May Cause Incorrect Instruction Execution"
232                  * This code only handles VPE0, any SMP/SMTC/RTOS code
233                  * making use of VPE1 will be responsable for that VPE.
234                  */
235                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
236                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
237                 break;
238         default:
239                 break;
240         }
241 }
242
243 void __init check_bugs32(void)
244 {
245         check_wait();
246         check_errata();
247 }
248
249 /*
250  * Probe whether cpu has config register by trying to play with
251  * alternate cache bit and see whether it matters.
252  * It's used by cpu_probe to distinguish between R3000A and R3081.
253  */
254 static inline int cpu_has_confreg(void)
255 {
256 #ifdef CONFIG_CPU_R3000
257         extern unsigned long r3k_cache_size(unsigned long);
258         unsigned long size1, size2;
259         unsigned long cfg = read_c0_conf();
260
261         size1 = r3k_cache_size(ST0_ISC);
262         write_c0_conf(cfg ^ R30XX_CONF_AC);
263         size2 = r3k_cache_size(ST0_ISC);
264         write_c0_conf(cfg);
265         return size1 != size2;
266 #else
267         return 0;
268 #endif
269 }
270
271 /*
272  * Get the FPU Implementation/Revision.
273  */
274 static inline unsigned long cpu_get_fpu_id(void)
275 {
276         unsigned long tmp, fpu_id;
277
278         tmp = read_c0_status();
279         __enable_fpu();
280         fpu_id = read_32bit_cp1_register(CP1_REVISION);
281         write_c0_status(tmp);
282         return fpu_id;
283 }
284
285 /*
286  * Check the CPU has an FPU the official way.
287  */
288 static inline int __cpu_has_fpu(void)
289 {
290         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
291 }
292
293 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
294                 | MIPS_CPU_COUNTER)
295
296 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
297 {
298         switch (c->processor_id & 0xff00) {
299         case PRID_IMP_R2000:
300                 c->cputype = CPU_R2000;
301                 c->isa_level = MIPS_CPU_ISA_I;
302                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
303                              MIPS_CPU_NOFPUEX;
304                 if (__cpu_has_fpu())
305                         c->options |= MIPS_CPU_FPU;
306                 c->tlbsize = 64;
307                 break;
308         case PRID_IMP_R3000:
309                 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
310                         if (cpu_has_confreg())
311                                 c->cputype = CPU_R3081E;
312                         else
313                                 c->cputype = CPU_R3000A;
314                 else
315                         c->cputype = CPU_R3000;
316                 c->isa_level = MIPS_CPU_ISA_I;
317                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
318                              MIPS_CPU_NOFPUEX;
319                 if (__cpu_has_fpu())
320                         c->options |= MIPS_CPU_FPU;
321                 c->tlbsize = 64;
322                 break;
323         case PRID_IMP_R4000:
324                 if (read_c0_config() & CONF_SC) {
325                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
326                                 c->cputype = CPU_R4400PC;
327                         else
328                                 c->cputype = CPU_R4000PC;
329                 } else {
330                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
331                                 c->cputype = CPU_R4400SC;
332                         else
333                                 c->cputype = CPU_R4000SC;
334                 }
335
336                 c->isa_level = MIPS_CPU_ISA_III;
337                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
338                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
339                              MIPS_CPU_LLSC;
340                 c->tlbsize = 48;
341                 break;
342         case PRID_IMP_VR41XX:
343                 switch (c->processor_id & 0xf0) {
344                 case PRID_REV_VR4111:
345                         c->cputype = CPU_VR4111;
346                         break;
347                 case PRID_REV_VR4121:
348                         c->cputype = CPU_VR4121;
349                         break;
350                 case PRID_REV_VR4122:
351                         if ((c->processor_id & 0xf) < 0x3)
352                                 c->cputype = CPU_VR4122;
353                         else
354                                 c->cputype = CPU_VR4181A;
355                         break;
356                 case PRID_REV_VR4130:
357                         if ((c->processor_id & 0xf) < 0x4)
358                                 c->cputype = CPU_VR4131;
359                         else
360                                 c->cputype = CPU_VR4133;
361                         break;
362                 default:
363                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
364                         c->cputype = CPU_VR41XX;
365                         break;
366                 }
367                 c->isa_level = MIPS_CPU_ISA_III;
368                 c->options = R4K_OPTS;
369                 c->tlbsize = 32;
370                 break;
371         case PRID_IMP_R4300:
372                 c->cputype = CPU_R4300;
373                 c->isa_level = MIPS_CPU_ISA_III;
374                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
375                              MIPS_CPU_LLSC;
376                 c->tlbsize = 32;
377                 break;
378         case PRID_IMP_R4600:
379                 c->cputype = CPU_R4600;
380                 c->isa_level = MIPS_CPU_ISA_III;
381                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
382                              MIPS_CPU_LLSC;
383                 c->tlbsize = 48;
384                 break;
385         #if 0
386         case PRID_IMP_R4650:
387                 /*
388                  * This processor doesn't have an MMU, so it's not
389                  * "real easy" to run Linux on it. It is left purely
390                  * for documentation.  Commented out because it shares
391                  * it's c0_prid id number with the TX3900.
392                  */
393                 c->cputype = CPU_R4650;
394                 c->isa_level = MIPS_CPU_ISA_III;
395                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
396                 c->tlbsize = 48;
397                 break;
398         #endif
399         case PRID_IMP_TX39:
400                 c->isa_level = MIPS_CPU_ISA_I;
401                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
402
403                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
404                         c->cputype = CPU_TX3927;
405                         c->tlbsize = 64;
406                 } else {
407                         switch (c->processor_id & 0xff) {
408                         case PRID_REV_TX3912:
409                                 c->cputype = CPU_TX3912;
410                                 c->tlbsize = 32;
411                                 break;
412                         case PRID_REV_TX3922:
413                                 c->cputype = CPU_TX3922;
414                                 c->tlbsize = 64;
415                                 break;
416                         default:
417                                 c->cputype = CPU_UNKNOWN;
418                                 break;
419                         }
420                 }
421                 break;
422         case PRID_IMP_R4700:
423                 c->cputype = CPU_R4700;
424                 c->isa_level = MIPS_CPU_ISA_III;
425                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
426                              MIPS_CPU_LLSC;
427                 c->tlbsize = 48;
428                 break;
429         case PRID_IMP_TX49:
430                 c->cputype = CPU_TX49XX;
431                 c->isa_level = MIPS_CPU_ISA_III;
432                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
433                 if (!(c->processor_id & 0x08))
434                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
435                 c->tlbsize = 48;
436                 break;
437         case PRID_IMP_R5000:
438                 c->cputype = CPU_R5000;
439                 c->isa_level = MIPS_CPU_ISA_IV;
440                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
441                              MIPS_CPU_LLSC;
442                 c->tlbsize = 48;
443                 break;
444         case PRID_IMP_R5432:
445                 c->cputype = CPU_R5432;
446                 c->isa_level = MIPS_CPU_ISA_IV;
447                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
448                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
449                 c->tlbsize = 48;
450                 break;
451         case PRID_IMP_R5500:
452                 c->cputype = CPU_R5500;
453                 c->isa_level = MIPS_CPU_ISA_IV;
454                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
455                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
456                 c->tlbsize = 48;
457                 break;
458         case PRID_IMP_NEVADA:
459                 c->cputype = CPU_NEVADA;
460                 c->isa_level = MIPS_CPU_ISA_IV;
461                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
462                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
463                 c->tlbsize = 48;
464                 break;
465         case PRID_IMP_R6000:
466                 c->cputype = CPU_R6000;
467                 c->isa_level = MIPS_CPU_ISA_II;
468                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
469                              MIPS_CPU_LLSC;
470                 c->tlbsize = 32;
471                 break;
472         case PRID_IMP_R6000A:
473                 c->cputype = CPU_R6000A;
474                 c->isa_level = MIPS_CPU_ISA_II;
475                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
476                              MIPS_CPU_LLSC;
477                 c->tlbsize = 32;
478                 break;
479         case PRID_IMP_RM7000:
480                 c->cputype = CPU_RM7000;
481                 c->isa_level = MIPS_CPU_ISA_IV;
482                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
483                              MIPS_CPU_LLSC;
484                 /*
485                  * Undocumented RM7000:  Bit 29 in the info register of
486                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
487                  * entries.
488                  *
489                  * 29      1 =>    64 entry JTLB
490                  *         0 =>    48 entry JTLB
491                  */
492                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
493                 break;
494         case PRID_IMP_RM9000:
495                 c->cputype = CPU_RM9000;
496                 c->isa_level = MIPS_CPU_ISA_IV;
497                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
498                              MIPS_CPU_LLSC;
499                 /*
500                  * Bit 29 in the info register of the RM9000
501                  * indicates if the TLB has 48 or 64 entries.
502                  *
503                  * 29      1 =>    64 entry JTLB
504                  *         0 =>    48 entry JTLB
505                  */
506                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
507                 break;
508         case PRID_IMP_R8000:
509                 c->cputype = CPU_R8000;
510                 c->isa_level = MIPS_CPU_ISA_IV;
511                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
512                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
513                              MIPS_CPU_LLSC;
514                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
515                 break;
516         case PRID_IMP_R10000:
517                 c->cputype = CPU_R10000;
518                 c->isa_level = MIPS_CPU_ISA_IV;
519                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
520                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
521                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
522                              MIPS_CPU_LLSC;
523                 c->tlbsize = 64;
524                 break;
525         case PRID_IMP_R12000:
526                 c->cputype = CPU_R12000;
527                 c->isa_level = MIPS_CPU_ISA_IV;
528                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
529                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
530                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
531                              MIPS_CPU_LLSC;
532                 c->tlbsize = 64;
533                 break;
534         case PRID_IMP_R14000:
535                 c->cputype = CPU_R14000;
536                 c->isa_level = MIPS_CPU_ISA_IV;
537                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
538                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
539                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
540                              MIPS_CPU_LLSC;
541                 c->tlbsize = 64;
542                 break;
543         case PRID_IMP_LOONGSON2:
544                 c->cputype = CPU_LOONGSON2;
545                 c->isa_level = MIPS_CPU_ISA_III;
546                 c->options = R4K_OPTS |
547                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
548                              MIPS_CPU_32FPR;
549                 c->tlbsize = 64;
550                 break;
551         }
552 }
553
554 static char unknown_isa[] __cpuinitdata = KERN_ERR \
555         "Unsupported ISA type, c0.config0: %d.";
556
557 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
558 {
559         unsigned int config0;
560         int isa;
561
562         config0 = read_c0_config();
563
564         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
565                 c->options |= MIPS_CPU_TLB;
566         isa = (config0 & MIPS_CONF_AT) >> 13;
567         switch (isa) {
568         case 0:
569                 switch ((config0 & MIPS_CONF_AR) >> 10) {
570                 case 0:
571                         c->isa_level = MIPS_CPU_ISA_M32R1;
572                         break;
573                 case 1:
574                         c->isa_level = MIPS_CPU_ISA_M32R2;
575                         break;
576                 default:
577                         goto unknown;
578                 }
579                 break;
580         case 2:
581                 switch ((config0 & MIPS_CONF_AR) >> 10) {
582                 case 0:
583                         c->isa_level = MIPS_CPU_ISA_M64R1;
584                         break;
585                 case 1:
586                         c->isa_level = MIPS_CPU_ISA_M64R2;
587                         break;
588                 default:
589                         goto unknown;
590                 }
591                 break;
592         default:
593                 goto unknown;
594         }
595
596         return config0 & MIPS_CONF_M;
597
598 unknown:
599         panic(unknown_isa, config0);
600 }
601
602 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
603 {
604         unsigned int config1;
605
606         config1 = read_c0_config1();
607
608         if (config1 & MIPS_CONF1_MD)
609                 c->ases |= MIPS_ASE_MDMX;
610         if (config1 & MIPS_CONF1_WR)
611                 c->options |= MIPS_CPU_WATCH;
612         if (config1 & MIPS_CONF1_CA)
613                 c->ases |= MIPS_ASE_MIPS16;
614         if (config1 & MIPS_CONF1_EP)
615                 c->options |= MIPS_CPU_EJTAG;
616         if (config1 & MIPS_CONF1_FP) {
617                 c->options |= MIPS_CPU_FPU;
618                 c->options |= MIPS_CPU_32FPR;
619         }
620         if (cpu_has_tlb)
621                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
622
623         return config1 & MIPS_CONF_M;
624 }
625
626 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
627 {
628         unsigned int config2;
629
630         config2 = read_c0_config2();
631
632         if (config2 & MIPS_CONF2_SL)
633                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
634
635         return config2 & MIPS_CONF_M;
636 }
637
638 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
639 {
640         unsigned int config3;
641
642         config3 = read_c0_config3();
643
644         if (config3 & MIPS_CONF3_SM)
645                 c->ases |= MIPS_ASE_SMARTMIPS;
646         if (config3 & MIPS_CONF3_DSP)
647                 c->ases |= MIPS_ASE_DSP;
648         if (config3 & MIPS_CONF3_VINT)
649                 c->options |= MIPS_CPU_VINT;
650         if (config3 & MIPS_CONF3_VEIC)
651                 c->options |= MIPS_CPU_VEIC;
652         if (config3 & MIPS_CONF3_MT)
653                 c->ases |= MIPS_ASE_MIPSMT;
654         if (config3 & MIPS_CONF3_ULRI)
655                 c->options |= MIPS_CPU_ULRI;
656
657         return config3 & MIPS_CONF_M;
658 }
659
660 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
661 {
662         /* MIPS32 or MIPS64 compliant CPU.  */
663         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
664                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
665
666         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
667
668         /* Read Config registers.  */
669         if (!decode_config0(c))
670                 return;                 /* actually worth a panic() */
671         if (!decode_config1(c))
672                 return;
673         if (!decode_config2(c))
674                 return;
675         if (!decode_config3(c))
676                 return;
677 }
678
679 #ifdef CONFIG_CPU_MIPSR2
680 extern void spram_config(void);
681 #else
682 static inline void spram_config(void) {}
683 #endif
684
685 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
686 {
687         decode_configs(c);
688         switch (c->processor_id & 0xff00) {
689         case PRID_IMP_4KC:
690                 c->cputype = CPU_4KC;
691                 break;
692         case PRID_IMP_4KEC:
693                 c->cputype = CPU_4KEC;
694                 break;
695         case PRID_IMP_4KECR2:
696                 c->cputype = CPU_4KEC;
697                 break;
698         case PRID_IMP_4KSC:
699         case PRID_IMP_4KSD:
700                 c->cputype = CPU_4KSC;
701                 break;
702         case PRID_IMP_5KC:
703                 c->cputype = CPU_5KC;
704                 break;
705         case PRID_IMP_20KC:
706                 c->cputype = CPU_20KC;
707                 break;
708         case PRID_IMP_24K:
709         case PRID_IMP_24KE:
710                 c->cputype = CPU_24K;
711                 break;
712         case PRID_IMP_25KF:
713                 c->cputype = CPU_25KF;
714                 break;
715         case PRID_IMP_34K:
716                 c->cputype = CPU_34K;
717                 break;
718         case PRID_IMP_74K:
719                 c->cputype = CPU_74K;
720                 break;
721         case PRID_IMP_1004K:
722                 c->cputype = CPU_1004K;
723                 break;
724         }
725
726         spram_config();
727 }
728
729 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
730 {
731         decode_configs(c);
732         switch (c->processor_id & 0xff00) {
733         case PRID_IMP_AU1_REV1:
734         case PRID_IMP_AU1_REV2:
735                 switch ((c->processor_id >> 24) & 0xff) {
736                 case 0:
737                         c->cputype = CPU_AU1000;
738                         break;
739                 case 1:
740                         c->cputype = CPU_AU1500;
741                         break;
742                 case 2:
743                         c->cputype = CPU_AU1100;
744                         break;
745                 case 3:
746                         c->cputype = CPU_AU1550;
747                         break;
748                 case 4:
749                         c->cputype = CPU_AU1200;
750                         if (2 == (c->processor_id & 0xff))
751                                 c->cputype = CPU_AU1250;
752                         break;
753                 case 5:
754                         c->cputype = CPU_AU1210;
755                         break;
756                 default:
757                         panic("Unknown Au Core!");
758                         break;
759                 }
760                 break;
761         }
762 }
763
764 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
765 {
766         decode_configs(c);
767
768         switch (c->processor_id & 0xff00) {
769         case PRID_IMP_SB1:
770                 c->cputype = CPU_SB1;
771                 /* FPU in pass1 is known to have issues. */
772                 if ((c->processor_id & 0xff) < 0x02)
773                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
774                 break;
775         case PRID_IMP_SB1A:
776                 c->cputype = CPU_SB1A;
777                 break;
778         }
779 }
780
781 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
782 {
783         decode_configs(c);
784         switch (c->processor_id & 0xff00) {
785         case PRID_IMP_SR71000:
786                 c->cputype = CPU_SR71000;
787                 c->scache.ways = 8;
788                 c->tlbsize = 64;
789                 break;
790         }
791 }
792
793 static inline void cpu_probe_nxp(struct cpuinfo_mips *c)
794 {
795         decode_configs(c);
796         switch (c->processor_id & 0xff00) {
797         case PRID_IMP_PR4450:
798                 c->cputype = CPU_PR4450;
799                 c->isa_level = MIPS_CPU_ISA_M32R1;
800                 break;
801         default:
802                 panic("Unknown NXP Core!"); /* REVISIT: die? */
803                 break;
804         }
805 }
806
807
808 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
809 {
810         decode_configs(c);
811         switch (c->processor_id & 0xff00) {
812         case PRID_IMP_BCM3302:
813                 c->cputype = CPU_BCM3302;
814                 break;
815         case PRID_IMP_BCM4710:
816                 c->cputype = CPU_BCM4710;
817                 break;
818         default:
819                 c->cputype = CPU_UNKNOWN;
820                 break;
821         }
822 }
823
824 const char *__cpu_name[NR_CPUS];
825
826 /*
827  * Name a CPU
828  */
829 static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c)
830 {
831         const char *name = NULL;
832
833         switch (c->cputype) {
834         case CPU_UNKNOWN:       name = "unknown"; break;
835         case CPU_R2000:         name = "R2000"; break;
836         case CPU_R3000:         name = "R3000"; break;
837         case CPU_R3000A:        name = "R3000A"; break;
838         case CPU_R3041:         name = "R3041"; break;
839         case CPU_R3051:         name = "R3051"; break;
840         case CPU_R3052:         name = "R3052"; break;
841         case CPU_R3081:         name = "R3081"; break;
842         case CPU_R3081E:        name = "R3081E"; break;
843         case CPU_R4000PC:       name = "R4000PC"; break;
844         case CPU_R4000SC:       name = "R4000SC"; break;
845         case CPU_R4000MC:       name = "R4000MC"; break;
846         case CPU_R4200:         name = "R4200"; break;
847         case CPU_R4400PC:       name = "R4400PC"; break;
848         case CPU_R4400SC:       name = "R4400SC"; break;
849         case CPU_R4400MC:       name = "R4400MC"; break;
850         case CPU_R4600:         name = "R4600"; break;
851         case CPU_R6000:         name = "R6000"; break;
852         case CPU_R6000A:        name = "R6000A"; break;
853         case CPU_R8000:         name = "R8000"; break;
854         case CPU_R10000:        name = "R10000"; break;
855         case CPU_R12000:        name = "R12000"; break;
856         case CPU_R14000:        name = "R14000"; break;
857         case CPU_R4300:         name = "R4300"; break;
858         case CPU_R4650:         name = "R4650"; break;
859         case CPU_R4700:         name = "R4700"; break;
860         case CPU_R5000:         name = "R5000"; break;
861         case CPU_R5000A:        name = "R5000A"; break;
862         case CPU_R4640:         name = "R4640"; break;
863         case CPU_NEVADA:        name = "Nevada"; break;
864         case CPU_RM7000:        name = "RM7000"; break;
865         case CPU_RM9000:        name = "RM9000"; break;
866         case CPU_R5432:         name = "R5432"; break;
867         case CPU_4KC:           name = "MIPS 4Kc"; break;
868         case CPU_5KC:           name = "MIPS 5Kc"; break;
869         case CPU_R4310:         name = "R4310"; break;
870         case CPU_SB1:           name = "SiByte SB1"; break;
871         case CPU_SB1A:          name = "SiByte SB1A"; break;
872         case CPU_TX3912:        name = "TX3912"; break;
873         case CPU_TX3922:        name = "TX3922"; break;
874         case CPU_TX3927:        name = "TX3927"; break;
875         case CPU_AU1000:        name = "Au1000"; break;
876         case CPU_AU1500:        name = "Au1500"; break;
877         case CPU_AU1100:        name = "Au1100"; break;
878         case CPU_AU1550:        name = "Au1550"; break;
879         case CPU_AU1200:        name = "Au1200"; break;
880         case CPU_AU1210:        name = "Au1210"; break;
881         case CPU_AU1250:        name = "Au1250"; break;
882         case CPU_4KEC:          name = "MIPS 4KEc"; break;
883         case CPU_4KSC:          name = "MIPS 4KSc"; break;
884         case CPU_VR41XX:        name = "NEC Vr41xx"; break;
885         case CPU_R5500:         name = "R5500"; break;
886         case CPU_TX49XX:        name = "TX49xx"; break;
887         case CPU_20KC:          name = "MIPS 20Kc"; break;
888         case CPU_24K:           name = "MIPS 24K"; break;
889         case CPU_25KF:          name = "MIPS 25Kf"; break;
890         case CPU_34K:           name = "MIPS 34K"; break;
891         case CPU_1004K:         name = "MIPS 1004K"; break;
892         case CPU_74K:           name = "MIPS 74K"; break;
893         case CPU_VR4111:        name = "NEC VR4111"; break;
894         case CPU_VR4121:        name = "NEC VR4121"; break;
895         case CPU_VR4122:        name = "NEC VR4122"; break;
896         case CPU_VR4131:        name = "NEC VR4131"; break;
897         case CPU_VR4133:        name = "NEC VR4133"; break;
898         case CPU_VR4181:        name = "NEC VR4181"; break;
899         case CPU_VR4181A:       name = "NEC VR4181A"; break;
900         case CPU_SR71000:       name = "Sandcraft SR71000"; break;
901         case CPU_BCM3302:       name = "Broadcom BCM3302"; break;
902         case CPU_BCM4710:       name = "Broadcom BCM4710"; break;
903         case CPU_PR4450:        name = "Philips PR4450"; break;
904         case CPU_LOONGSON2:     name = "ICT Loongson-2"; break;
905         default:
906                 BUG();
907         }
908
909         return name;
910 }
911
912 __cpuinit void cpu_probe(void)
913 {
914         struct cpuinfo_mips *c = &current_cpu_data;
915         unsigned int cpu = smp_processor_id();
916
917         c->processor_id = PRID_IMP_UNKNOWN;
918         c->fpu_id       = FPIR_IMP_NONE;
919         c->cputype      = CPU_UNKNOWN;
920
921         c->processor_id = read_c0_prid();
922         switch (c->processor_id & 0xff0000) {
923         case PRID_COMP_LEGACY:
924                 cpu_probe_legacy(c);
925                 break;
926         case PRID_COMP_MIPS:
927                 cpu_probe_mips(c);
928                 break;
929         case PRID_COMP_ALCHEMY:
930                 cpu_probe_alchemy(c);
931                 break;
932         case PRID_COMP_SIBYTE:
933                 cpu_probe_sibyte(c);
934                 break;
935         case PRID_COMP_BROADCOM:
936                 cpu_probe_broadcom(c);
937                 break;
938         case PRID_COMP_SANDCRAFT:
939                 cpu_probe_sandcraft(c);
940                 break;
941         case PRID_COMP_NXP:
942                 cpu_probe_nxp(c);
943                 break;
944         default:
945                 c->cputype = CPU_UNKNOWN;
946         }
947
948         /*
949          * Platform code can force the cpu type to optimize code
950          * generation. In that case be sure the cpu type is correctly
951          * manually setup otherwise it could trigger some nasty bugs.
952          */
953         BUG_ON(current_cpu_type() != c->cputype);
954
955         if (c->options & MIPS_CPU_FPU) {
956                 c->fpu_id = cpu_get_fpu_id();
957
958                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
959                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
960                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
961                     c->isa_level == MIPS_CPU_ISA_M64R2) {
962                         if (c->fpu_id & MIPS_FPIR_3D)
963                                 c->ases |= MIPS_ASE_MIPS3D;
964                 }
965         }
966
967         __cpu_name[cpu] = cpu_to_name(c);
968
969         if (cpu_has_mips_r2)
970                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
971         else
972                 c->srsets = 1;
973 }
974
975 __cpuinit void cpu_report(void)
976 {
977         struct cpuinfo_mips *c = &current_cpu_data;
978
979         printk(KERN_INFO "CPU revision is: %08x (%s)\n",
980                c->processor_id, cpu_name_string());
981         if (c->options & MIPS_CPU_FPU)
982                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
983 }