git.oblomov.eu Git - linux-2.6/blob - drivers/ide/pci/pdc202xx_old.c

   1 /*
   2  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   3  *  Copyright (C) 2006-2007             MontaVista Software, Inc.
   4  *  Copyright (C) 2007                  Bartlomiej Zolnierkiewicz
   5  *
   6  *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
   7  *  compiled into the kernel if you have more than one card installed.
   8  *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
   9  *  safe chipset tuning, including this support is harmless
  10  *
  11  *  Promise Ultra66 cards with BIOS v1.11 this
  12  *  compiled into the kernel if you have more than one card installed.
  13  *
  14  *  Promise Ultra100 cards.
  15  *
  16  *  The latest chipset code will support the following ::
  17  *  Three Ultra33 controllers and 12 drives.
  18  *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
  19  *  The 8/4 ratio is a BIOS code limit by promise.
  20  *
  21  *  UNLESS you enable "CONFIG_PDC202XX_BURST"
  22  *
  23  */
  24
  25 /*
  26  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  27  *  Author: Frank Tiernan (frankt@promise.com)
  28  *  Released under terms of General Public License
  29  */
  30
  31 #include <linux/types.h>
  32 #include <linux/module.h>
  33 #include <linux/kernel.h>
  34 #include <linux/delay.h>
  35 #include <linux/blkdev.h>
  36 #include <linux/hdreg.h>
  37 #include <linux/pci.h>
  38 #include <linux/init.h>
  39 #include <linux/ide.h>
  40
  41 #include <asm/io.h>
  42
  43 #define PDC202XX_DEBUG_DRIVE_INFO       0
  44
  45 static const char *pdc_quirk_drives[] = {
  46         "QUANTUM FIREBALLlct08 08",
  47         "QUANTUM FIREBALLP KA6.4",
  48         "QUANTUM FIREBALLP KA9.1",
  49         "QUANTUM FIREBALLP LM20.4",
  50         "QUANTUM FIREBALLP KX13.6",
  51         "QUANTUM FIREBALLP KX20.5",
  52         "QUANTUM FIREBALLP KX27.3",
  53         "QUANTUM FIREBALLP LM20.5",
  54         NULL
  55 };
  56
  57 static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
  58
  59 static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
  60 {
  61         ide_hwif_t *hwif        = HWIF(drive);
  62         struct pci_dev *dev     = to_pci_dev(hwif->dev);
  63         u8 drive_pci            = 0x60 + (drive->dn << 2);
  64
  65         u8                      AP = 0, BP = 0, CP = 0;
  66         u8                      TA = 0, TB = 0, TC = 0;
  67
  68 #if PDC202XX_DEBUG_DRIVE_INFO
  69         u32                     drive_conf = 0;
  70         pci_read_config_dword(dev, drive_pci, &drive_conf);
  71 #endif
  72
  73         /*
  74          * TODO: do this once per channel
  75          */
  76         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
  77                 pdc_old_disable_66MHz_clock(hwif);
  78
  79         pci_read_config_byte(dev, drive_pci,     &AP);
  80         pci_read_config_byte(dev, drive_pci + 1, &BP);
  81         pci_read_config_byte(dev, drive_pci + 2, &CP);
  82
  83         switch(speed) {
  84                 case XFER_UDMA_5:
  85                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
  86                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
  87                 case XFER_UDMA_3:
  88                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
  89                 case XFER_UDMA_0:
  90                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
  91                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
  92                 case XFER_MW_DMA_0:     TB = 0xE0; TC = 0x0F; break;
  93                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
  94                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
  95                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
  96                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
  97                 case XFER_PIO_0:
  98                 default:                TA = 0x09; TB = 0x13; break;
  99         }
 100
 101         if (speed < XFER_SW_DMA_0) {
 102                 /*
 103                  * preserve SYNC_INT / ERDDY_EN bits while clearing
 104                  * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
 105                  */
 106                 AP &= ~0x3f;
 107                 if (drive->id->capability & 4)
 108                         AP |= 0x20;     /* set IORDY_EN bit */
 109                 if (drive->media == ide_disk)
 110                         AP |= 0x10;     /* set Prefetch_EN bit */
 111                 /* clear PB[4:0] bits of register B */
 112                 BP &= ~0x1f;
 113                 pci_write_config_byte(dev, drive_pci,     AP | TA);
 114                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
 115         } else {
 116                 /* clear MB[2:0] bits of register B */
 117                 BP &= ~0xe0;
 118                 /* clear MC[3:0] bits of register C */
 119                 CP &= ~0x0f;
 120                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
 121                 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
 122         }
 123
 124 #if PDC202XX_DEBUG_DRIVE_INFO
 125         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 126                 drive->name, ide_xfer_verbose(speed),
 127                 drive->dn, drive_conf);
 128         pci_read_config_dword(dev, drive_pci, &drive_conf);
 129         printk("0x%08x\n", drive_conf);
 130 #endif
 131 }
 132
 133 static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
 134 {
 135         pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
 136 }
 137
 138 static u8 __devinit pdc2026x_old_cable_detect(ide_hwif_t *hwif)
 139 {
 140         struct pci_dev *dev = to_pci_dev(hwif->dev);
 141         u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
 142
 143         pci_read_config_word(dev, 0x50, &CIS);
 144
 145         return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
 146 }
 147
 148 /*
 149  * Set the control register to use the 66MHz system
 150  * clock for UDMA 3/4/5 mode operation when necessary.
 151  *
 152  * FIXME: this register is shared by both channels, some locking is needed
 153  *
 154  * It may also be possible to leave the 66MHz clock on
 155  * and readjust the timing parameters.
 156  */
 157 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
 158 {
 159         unsigned long clock_reg = hwif->extra_base + 0x01;
 160         u8 clock = inb(clock_reg);
 161
 162         outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
 163 }
 164
 165 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
 166 {
 167         unsigned long clock_reg = hwif->extra_base + 0x01;
 168         u8 clock = inb(clock_reg);
 169
 170         outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
 171 }
 172
 173 static void pdc202xx_quirkproc(ide_drive_t *drive)
 174 {
 175         const char **list, *model = drive->id->model;
 176
 177         for (list = pdc_quirk_drives; *list != NULL; list++)
 178                 if (strstr(model, *list) != NULL) {
 179                         drive->quirk_list = 2;
 180                         return;
 181                 }
 182
 183         drive->quirk_list = 0;
 184 }
 185
 186 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
 187 {
 188         if (drive->current_speed > XFER_UDMA_2)
 189                 pdc_old_enable_66MHz_clock(drive->hwif);
 190         if (drive->media != ide_disk || drive->addressing == 1) {
 191                 struct request *rq      = HWGROUP(drive)->rq;
 192                 ide_hwif_t *hwif        = HWIF(drive);
 193                 unsigned long high_16   = hwif->extra_base - 16;
 194                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 195                 u32 word_count  = 0;
 196                 u8 clock = inb(high_16 + 0x11);
 197
 198                 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
 199                 word_count = (rq->nr_sectors << 8);
 200                 word_count = (rq_data_dir(rq) == READ) ?
 201                                         word_count | 0x05000000 :
 202                                         word_count | 0x06000000;
 203                 outl(word_count, atapi_reg);
 204         }
 205         ide_dma_start(drive);
 206 }
 207
 208 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
 209 {
 210         if (drive->media != ide_disk || drive->addressing == 1) {
 211                 ide_hwif_t *hwif        = HWIF(drive);
 212                 unsigned long high_16   = hwif->extra_base - 16;
 213                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 214                 u8 clock                = 0;
 215
 216                 outl(0, atapi_reg); /* zero out extra */
 217                 clock = inb(high_16 + 0x11);
 218                 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
 219         }
 220         if (drive->current_speed > XFER_UDMA_2)
 221                 pdc_old_disable_66MHz_clock(drive->hwif);
 222         return __ide_dma_end(drive);
 223 }
 224
 225 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
 226 {
 227         ide_hwif_t *hwif        = HWIF(drive);
 228         unsigned long high_16   = hwif->extra_base - 16;
 229         u8 dma_stat             = inb(hwif->dma_status);
 230         u8 sc1d                 = inb(high_16 + 0x001d);
 231
 232         if (hwif->channel) {
 233                 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
 234                 if ((sc1d & 0x50) == 0x50)
 235                         goto somebody_else;
 236                 else if ((sc1d & 0x40) == 0x40)
 237                         return (dma_stat & 4) == 4;
 238         } else {
 239                 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
 240                 if ((sc1d & 0x05) == 0x05)
 241                         goto somebody_else;
 242                 else if ((sc1d & 0x04) == 0x04)
 243                         return (dma_stat & 4) == 4;
 244         }
 245 somebody_else:
 246         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
 247 }
 248
 249 static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
 250 {
 251         ide_hwif_t *hwif = HWIF(drive);
 252
 253         if (hwif->resetproc != NULL)
 254                 hwif->resetproc(drive);
 255
 256         ide_dma_lost_irq(drive);
 257 }
 258
 259 static void pdc202xx_dma_timeout(ide_drive_t *drive)
 260 {
 261         ide_hwif_t *hwif = HWIF(drive);
 262
 263         if (hwif->resetproc != NULL)
 264                 hwif->resetproc(drive);
 265
 266         ide_dma_timeout(drive);
 267 }
 268
 269 static void pdc202xx_reset_host (ide_hwif_t *hwif)
 270 {
 271         unsigned long high_16   = hwif->extra_base - 16;
 272         u8 udma_speed_flag      = inb(high_16 | 0x001f);
 273
 274         outb(udma_speed_flag | 0x10, high_16 | 0x001f);
 275         mdelay(100);
 276         outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
 277         mdelay(2000);   /* 2 seconds ?! */
 278
 279         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 280                 hwif->channel ? "Secondary" : "Primary");
 281 }
 282
 283 static void pdc202xx_reset (ide_drive_t *drive)
 284 {
 285         ide_hwif_t *hwif        = HWIF(drive);
 286         ide_hwif_t *mate        = hwif->mate;
 287
 288         pdc202xx_reset_host(hwif);
 289         pdc202xx_reset_host(mate);
 290
 291         ide_set_max_pio(drive);
 292 }
 293
 294 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
 295                                                         const char *name)
 296 {
 297         return dev->irq;
 298 }
 299
 300 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
 301 {
 302         struct pci_dev *dev = to_pci_dev(hwif->dev);
 303
 304         hwif->set_pio_mode = &pdc202xx_set_pio_mode;
 305         hwif->set_dma_mode = &pdc202xx_set_mode;
 306
 307         hwif->quirkproc = &pdc202xx_quirkproc;
 308
 309         if (dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 310                 hwif->resetproc = &pdc202xx_reset;
 311
 312                 hwif->cable_detect = pdc2026x_old_cable_detect;
 313         }
 314
 315         if (hwif->dma_base == 0)
 316                 return;
 317
 318         hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
 319         hwif->dma_timeout = &pdc202xx_dma_timeout;
 320
 321         if (dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 322                 hwif->dma_start = &pdc202xx_old_ide_dma_start;
 323                 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
 324         }
 325         hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
 326 }
 327
 328 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
 329 {
 330         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 331
 332         if (hwif->channel) {
 333                 ide_setup_dma(hwif, dmabase);
 334                 return;
 335         }
 336
 337         udma_speed_flag = inb(dmabase | 0x1f);
 338         primary_mode    = inb(dmabase | 0x1a);
 339         secondary_mode  = inb(dmabase | 0x1b);
 340         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 341                 "Primary %s Mode " \
 342                 "Secondary %s Mode.\n", hwif->cds->name,
 343                 (udma_speed_flag & 1) ? "EN" : "DIS",
 344                 (primary_mode & 1) ? "MASTER" : "PCI",
 345                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 346
 347 #ifdef CONFIG_PDC202XX_BURST
 348         if (!(udma_speed_flag & 1)) {
 349                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 350                         hwif->cds->name, udma_speed_flag,
 351                         (udma_speed_flag|1));
 352                 outb(udma_speed_flag | 1, dmabase | 0x1f);
 353                 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
 354         }
 355 #endif /* CONFIG_PDC202XX_BURST */
 356
 357         ide_setup_dma(hwif, dmabase);
 358 }
 359
 360 static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
 361                                            const char *name)
 362 {
 363         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 364                 u8 irq = 0, irq2 = 0;
 365                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 366                 /* 0xbc */
 367                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 368                 if (irq != irq2) {
 369                         pci_write_config_byte(dev,
 370                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 371                         printk(KERN_INFO "%s: PCI config space interrupt "
 372                                          "mirror fixed\n", name);
 373                 }
 374         }
 375 }
 376
 377 #define IDE_HFLAGS_PDC202XX \
 378         (IDE_HFLAG_ERROR_STOPS_FIFO | \
 379          IDE_HFLAG_ABUSE_SET_DMA_MODE | \
 380          IDE_HFLAG_OFF_BOARD)
 381
 382 #define DECLARE_PDC2026X_DEV(name_str, udma, extra_flags) \
 383         { \
 384                 .name           = name_str, \
 385                 .init_chipset   = init_chipset_pdc202xx, \
 386                 .init_hwif      = init_hwif_pdc202xx, \
 387                 .init_dma       = init_dma_pdc202xx, \
 388                 .extra          = 48, \
 389                 .host_flags     = IDE_HFLAGS_PDC202XX | extra_flags, \
 390                 .pio_mask       = ATA_PIO4, \
 391                 .mwdma_mask     = ATA_MWDMA2, \
 392                 .udma_mask      = udma, \
 393         }
 394
 395 static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
 396         {       /* 0 */
 397                 .name           = "PDC20246",
 398                 .init_chipset   = init_chipset_pdc202xx,
 399                 .init_hwif      = init_hwif_pdc202xx,
 400                 .init_dma       = init_dma_pdc202xx,
 401                 .extra          = 16,
 402                 .host_flags     = IDE_HFLAGS_PDC202XX,
 403                 .pio_mask       = ATA_PIO4,
 404                 .mwdma_mask     = ATA_MWDMA2,
 405                 .udma_mask      = ATA_UDMA2,
 406         },
 407
 408         /* 1 */ DECLARE_PDC2026X_DEV("PDC20262", ATA_UDMA4, 0),
 409         /* 2 */ DECLARE_PDC2026X_DEV("PDC20263", ATA_UDMA4, 0),
 410         /* 3 */ DECLARE_PDC2026X_DEV("PDC20265", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
 411         /* 4 */ DECLARE_PDC2026X_DEV("PDC20267", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
 412 };
 413
 414 /**
 415  *      pdc202xx_init_one       -       called when a PDC202xx is found
 416  *      @dev: the pdc202xx device
 417  *      @id: the matching pci id
 418  *
 419  *      Called when the PCI registration layer (or the IDE initialization)
 420  *      finds a device matching our IDE device tables.
 421  */
 422
 423 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 424 {
 425         const struct ide_port_info *d;
 426         u8 idx = id->driver_data;
 427
 428         d = &pdc202xx_chipsets[idx];
 429
 430         if (idx < 3)
 431                 pdc202ata4_fixup_irq(dev, d->name);
 432
 433         if (idx == 3) {
 434                 struct pci_dev *bridge = dev->bus->self;
 435
 436                 if (bridge &&
 437                     bridge->vendor == PCI_VENDOR_ID_INTEL &&
 438                     (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
 439                      bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
 440                         printk(KERN_INFO "ide: Skipping Promise PDC20265 "
 441                                 "attached to I2O RAID controller\n");
 442                         return -ENODEV;
 443                 }
 444         }
 445
 446         return ide_setup_pci_device(dev, d);
 447 }
 448
 449 static const struct pci_device_id pdc202xx_pci_tbl[] = {
 450         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
 451         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
 452         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 2 },
 453         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 3 },
 454         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 4 },
 455         { 0, },
 456 };
 457 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
 458
 459 static struct pci_driver driver = {
 460         .name           = "Promise_Old_IDE",
 461         .id_table       = pdc202xx_pci_tbl,
 462         .probe          = pdc202xx_init_one,
 463 };
 464
 465 static int __init pdc202xx_ide_init(void)
 466 {
 467         return ide_pci_register_driver(&driver);
 468 }
 469
 470 module_init(pdc202xx_ide_init);
 471
 472 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 473 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 474 MODULE_LICENSE("GPL");