2 * ipr.h -- driver for IBM Power Linux RAID adapters
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
6 * Copyright (C) 2003, 2004 IBM Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
29 #include <linux/types.h>
30 #include <linux/completion.h>
31 #include <linux/libata.h>
32 #include <linux/list.h>
33 #include <linux/kref.h>
34 #include <scsi/scsi.h>
35 #include <scsi/scsi_cmnd.h>
40 #define IPR_DRIVER_VERSION "2.4.3"
41 #define IPR_DRIVER_DATE "(June 10, 2009)"
44 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
45 * ops per device for devices not running tagged command queuing.
46 * This can be adjusted at runtime through sysfs device attributes.
48 #define IPR_MAX_CMD_PER_LUN 6
49 #define IPR_MAX_CMD_PER_ATA_LUN 1
52 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
53 * ops the mid-layer can send to the adapter.
55 #define IPR_NUM_BASE_CMD_BLKS 100
57 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
58 #define PCI_DEVICE_ID_IBM_SCAMP_E 0x034A
60 #define IPR_SUBS_DEV_ID_2780 0x0264
61 #define IPR_SUBS_DEV_ID_5702 0x0266
62 #define IPR_SUBS_DEV_ID_5703 0x0278
63 #define IPR_SUBS_DEV_ID_572E 0x028D
64 #define IPR_SUBS_DEV_ID_573E 0x02D3
65 #define IPR_SUBS_DEV_ID_573D 0x02D4
66 #define IPR_SUBS_DEV_ID_571A 0x02C0
67 #define IPR_SUBS_DEV_ID_571B 0x02BE
68 #define IPR_SUBS_DEV_ID_571E 0x02BF
69 #define IPR_SUBS_DEV_ID_571F 0x02D5
70 #define IPR_SUBS_DEV_ID_572A 0x02C1
71 #define IPR_SUBS_DEV_ID_572B 0x02C2
72 #define IPR_SUBS_DEV_ID_572F 0x02C3
73 #define IPR_SUBS_DEV_ID_574D 0x030B
74 #define IPR_SUBS_DEV_ID_574E 0x030A
75 #define IPR_SUBS_DEV_ID_575B 0x030D
76 #define IPR_SUBS_DEV_ID_575C 0x0338
77 #define IPR_SUBS_DEV_ID_575D 0x033E
78 #define IPR_SUBS_DEV_ID_57B3 0x033A
79 #define IPR_SUBS_DEV_ID_57B7 0x0360
80 #define IPR_SUBS_DEV_ID_57B8 0x02C2
82 #define IPR_NAME "ipr"
87 #define IPR_RC_JOB_CONTINUE 1
88 #define IPR_RC_JOB_RETURN 2
93 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
94 #define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
95 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000
96 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
97 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
98 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
99 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00
100 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
101 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
102 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
103 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
104 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
105 #define IPR_IOASC_BUS_WAS_RESET 0x06290000
106 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
107 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
109 #define IPR_FIRST_DRIVER_IOASC 0x10000000
110 #define IPR_IOASC_IOA_WAS_RESET 0x10000001
111 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
113 /* Driver data flags */
114 #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
115 #define IPR_USE_PCI_WARM_RESET 0x00000002
117 #define IPR_DEFAULT_MAX_ERROR_DUMP 984
118 #define IPR_NUM_LOG_HCAMS 2
119 #define IPR_NUM_CFG_CHG_HCAMS 2
120 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
121 #define IPR_MAX_NUM_TARGETS_PER_BUS 256
122 #define IPR_MAX_NUM_LUNS_PER_TARGET 256
123 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
124 #define IPR_VSET_BUS 0xff
125 #define IPR_IOA_BUS 0xff
126 #define IPR_IOA_TARGET 0xff
127 #define IPR_IOA_LUN 0xff
128 #define IPR_MAX_NUM_BUSES 16
129 #define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
131 #define IPR_NUM_RESET_RELOAD_RETRIES 3
133 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
134 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
135 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 3)
137 #define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
138 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
139 IPR_NUM_INTERNAL_CMD_BLKS)
141 #define IPR_MAX_PHYSICAL_DEVS 192
143 #define IPR_MAX_SGLIST 64
144 #define IPR_IOA_MAX_SECTORS 32767
145 #define IPR_VSET_MAX_SECTORS 512
146 #define IPR_MAX_CDB_LEN 16
148 #define IPR_DEFAULT_BUS_WIDTH 16
149 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
150 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
151 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
152 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
154 #define IPR_IOA_RES_HANDLE 0xffffffff
155 #define IPR_INVALID_RES_HANDLE 0
156 #define IPR_IOA_RES_ADDR 0x00ffffff
161 #define IPR_QUERY_RSRC_STATE 0xC2
162 #define IPR_RESET_DEVICE 0xC3
163 #define IPR_RESET_TYPE_SELECT 0x80
164 #define IPR_LUN_RESET 0x40
165 #define IPR_TARGET_RESET 0x20
166 #define IPR_BUS_RESET 0x10
167 #define IPR_ATA_PHY_RESET 0x80
168 #define IPR_ID_HOST_RR_Q 0xC4
169 #define IPR_QUERY_IOA_CONFIG 0xC5
170 #define IPR_CANCEL_ALL_REQUESTS 0xCE
171 #define IPR_HOST_CONTROLLED_ASYNC 0xCF
172 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
173 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
174 #define IPR_SET_SUPPORTED_DEVICES 0xFB
175 #define IPR_IOA_SHUTDOWN 0xF7
176 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
181 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
182 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
183 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
184 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
185 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
186 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
187 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
188 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
189 #define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
190 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
191 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
192 #define IPR_OPERATIONAL_TIMEOUT (5 * 60)
193 #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
194 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
195 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
196 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
197 #define IPR_PCI_RESET_TIMEOUT (HZ / 2)
198 #define IPR_DUMP_TIMEOUT (15 * HZ)
203 #define IPR_VENDOR_ID_LEN 8
204 #define IPR_PROD_ID_LEN 16
205 #define IPR_SERIAL_NUM_LEN 8
210 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
211 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
212 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
213 #define IPR_GET_FMT2_BAR_SEL(mbx) \
214 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
215 #define IPR_SDT_FMT2_BAR0_SEL 0x0
216 #define IPR_SDT_FMT2_BAR1_SEL 0x1
217 #define IPR_SDT_FMT2_BAR2_SEL 0x2
218 #define IPR_SDT_FMT2_BAR3_SEL 0x3
219 #define IPR_SDT_FMT2_BAR4_SEL 0x4
220 #define IPR_SDT_FMT2_BAR5_SEL 0x5
221 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
222 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
223 #define IPR_DOORBELL 0x82800000
224 #define IPR_RUNTIME_RESET 0x40000000
226 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
227 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
228 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
229 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
230 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
231 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
232 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
233 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
234 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
235 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
236 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
238 #define IPR_PCII_ERROR_INTERRUPTS \
239 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
240 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
242 #define IPR_PCII_OPER_INTERRUPTS \
243 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
245 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
246 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
248 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
249 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
254 #define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
255 #define IPR_NUM_SDT_ENTRIES 511
256 #define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
261 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
264 * Adapter interface types
267 struct ipr_res_addr {
272 #define IPR_GET_PHYS_LOC(res_addr) \
273 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
274 }__attribute__((packed, aligned (4)));
276 struct ipr_std_inq_vpids {
277 u8 vendor_id[IPR_VENDOR_ID_LEN];
278 u8 product_id[IPR_PROD_ID_LEN];
279 }__attribute__((packed));
282 struct ipr_std_inq_vpids vpids;
283 u8 sn[IPR_SERIAL_NUM_LEN];
284 }__attribute__((packed));
289 }__attribute__((packed));
291 struct ipr_std_inq_data {
292 u8 peri_qual_dev_type;
293 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
294 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
296 u8 removeable_medium_rsvd;
297 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
299 #define IPR_IS_DASD_DEVICE(std_inq) \
300 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
301 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
303 #define IPR_IS_SES_DEVICE(std_inq) \
304 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
313 struct ipr_std_inq_vpids vpids;
315 u8 ros_rsvd_ram_rsvd[4];
317 u8 serial_num[IPR_SERIAL_NUM_LEN];
318 }__attribute__ ((packed));
320 struct ipr_config_table_entry {
322 #define IPR_PROTO_SATA 0x02
323 #define IPR_PROTO_SATA_ATAPI 0x03
324 #define IPR_PROTO_SAS_STP 0x06
325 #define IPR_PROTO_SAS_STP_ATAPI 0x07
328 #define IPR_IS_IOA_RESOURCE 0x80
329 #define IPR_IS_ARRAY_MEMBER 0x20
330 #define IPR_IS_HOT_SPARE 0x10
333 #define IPR_RES_SUBTYPE(res) (((res)->cfgte.rsvd_subtype) & 0x0f)
334 #define IPR_SUBTYPE_AF_DASD 0
335 #define IPR_SUBTYPE_GENERIC_SCSI 1
336 #define IPR_SUBTYPE_VOLUME_SET 2
337 #define IPR_SUBTYPE_GENERIC_ATA 4
339 #define IPR_QUEUEING_MODEL(res) ((((res)->cfgte.flags) & 0x70) >> 4)
340 #define IPR_QUEUE_FROZEN_MODEL 0
341 #define IPR_QUEUE_NACA_MODEL 1
343 struct ipr_res_addr res_addr;
346 struct ipr_std_inq_data std_inq_data;
347 }__attribute__ ((packed, aligned (4)));
349 struct ipr_config_table_hdr {
352 #define IPR_UCODE_DOWNLOAD_REQ 0x10
354 }__attribute__((packed, aligned (4)));
356 struct ipr_config_table {
357 struct ipr_config_table_hdr hdr;
358 struct ipr_config_table_entry dev[IPR_MAX_PHYSICAL_DEVS];
359 }__attribute__((packed, aligned (4)));
361 struct ipr_hostrcb_cfg_ch_not {
362 struct ipr_config_table_entry cfgte;
364 }__attribute__((packed, aligned (4)));
366 struct ipr_supported_device {
370 struct ipr_std_inq_vpids vpids;
372 }__attribute__((packed, aligned (4)));
374 /* Command packet structure */
376 __be16 reserved; /* Reserved by IOA */
378 #define IPR_RQTYPE_SCSICDB 0x00
379 #define IPR_RQTYPE_IOACMD 0x01
380 #define IPR_RQTYPE_HCAM 0x02
381 #define IPR_RQTYPE_ATA_PASSTHRU 0x04
386 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
387 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
388 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
389 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
390 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04
393 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20
394 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
395 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
396 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02
397 #define IPR_FLAGS_LO_ORDERED_TASK 0x04
398 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
399 #define IPR_FLAGS_LO_ACA_TASK 0x08
403 }__attribute__ ((packed, aligned(4)));
405 struct ipr_ioarcb_ata_regs {
407 #define IPR_ATA_FLAG_PACKET_CMD 0x80
408 #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
409 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
427 }__attribute__ ((packed, aligned(4)));
429 struct ipr_ioadl_desc {
430 __be32 flags_and_data_len;
431 #define IPR_IOADL_FLAGS_MASK 0xff000000
432 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
433 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
434 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
435 #define IPR_IOADL_FLAGS_READ 0x48000000
436 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000
437 #define IPR_IOADL_FLAGS_WRITE 0x68000000
438 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
439 #define IPR_IOADL_FLAGS_LAST 0x01000000
442 }__attribute__((packed, aligned (8)));
444 struct ipr_ioarcb_add_data {
446 struct ipr_ioarcb_ata_regs regs;
447 struct ipr_ioadl_desc ioadl[5];
448 __be32 add_cmd_parms[10];
450 }__attribute__ ((packed, aligned(4)));
452 /* IOA Request Control Block 128 bytes */
454 __be32 ioarcb_host_pci_addr;
457 __be32 host_response_handle;
462 __be32 write_data_transfer_length;
463 __be32 read_data_transfer_length;
464 __be32 write_ioadl_addr;
465 __be32 write_ioadl_len;
466 __be32 read_ioadl_addr;
467 __be32 read_ioadl_len;
469 __be32 ioasa_host_pci_addr;
473 struct ipr_cmd_pkt cmd_pkt;
475 __be32 add_cmd_parms_len;
476 struct ipr_ioarcb_add_data add_data;
477 }__attribute__((packed, aligned (4)));
479 struct ipr_ioasa_vset {
480 __be32 failing_lba_hi;
481 __be32 failing_lba_lo;
483 }__attribute__((packed, aligned (4)));
485 struct ipr_ioasa_af_dasd {
488 }__attribute__((packed, aligned (4)));
490 struct ipr_ioasa_gpdd {
495 }__attribute__((packed, aligned (4)));
497 struct ipr_ioasa_gata {
499 u8 nsect; /* Interrupt reason */
505 u8 alt_status; /* ATA CTL */
510 }__attribute__((packed, aligned (4)));
512 struct ipr_auto_sense {
513 __be16 auto_sense_len;
515 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
520 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
521 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
522 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
523 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
525 __be16 ret_stat_len; /* Length of the returned IOASA */
527 __be16 avail_stat_len; /* Total Length of status available. */
529 __be32 residual_data_len; /* number of bytes in the host data */
530 /* buffers that were not used by the IOARCB command. */
533 #define IPR_NO_ILID 0
534 #define IPR_DRIVER_ILID 0xffffffff
538 __be32 fd_phys_locator;
540 __be32 fd_res_handle;
542 __be32 ioasc_specific; /* status code specific field */
543 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000
544 #define IPR_AUTOSENSE_VALID 0x40000000
545 #define IPR_ATA_DEVICE_WAS_RESET 0x20000000
546 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
547 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
548 #define IPR_FIELD_POINTER_MASK 0x0000ffff
551 struct ipr_ioasa_vset vset;
552 struct ipr_ioasa_af_dasd dasd;
553 struct ipr_ioasa_gpdd gpdd;
554 struct ipr_ioasa_gata gata;
557 struct ipr_auto_sense auto_sense;
558 }__attribute__((packed, aligned (4)));
560 struct ipr_mode_parm_hdr {
563 u8 device_spec_parms;
565 }__attribute__((packed));
567 struct ipr_mode_pages {
568 struct ipr_mode_parm_hdr hdr;
569 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
570 }__attribute__((packed));
572 struct ipr_mode_page_hdr {
574 #define IPR_MODE_PAGE_PS 0x80
575 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
577 }__attribute__ ((packed));
579 struct ipr_dev_bus_entry {
580 struct ipr_res_addr res_addr;
582 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80
583 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40
584 #define IPR_SCSI_ATTR_QAS_MASK 0xC0
585 #define IPR_SCSI_ATTR_ENABLE_TM 0x20
586 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
587 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
588 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
592 u8 extended_reset_delay;
593 #define IPR_EXTENDED_RESET_DELAY 7
595 __be32 max_xfer_rate;
600 }__attribute__((packed, aligned (4)));
602 struct ipr_mode_page28 {
603 struct ipr_mode_page_hdr hdr;
606 struct ipr_dev_bus_entry bus[0];
607 }__attribute__((packed));
609 struct ipr_mode_page24 {
610 struct ipr_mode_page_hdr hdr;
612 #define IPR_ENABLE_DUAL_IOA_AF 0x80
613 }__attribute__((packed));
616 struct ipr_std_inq_data std_inq_data;
617 u8 ascii_part_num[12];
619 u8 ascii_plant_code[4];
620 }__attribute__((packed));
622 struct ipr_inquiry_page3 {
623 u8 peri_qual_dev_type;
635 }__attribute__((packed));
637 struct ipr_inquiry_cap {
638 u8 peri_qual_dev_type;
646 #define IPR_CAP_DUAL_IOA_RAID 0x80
648 }__attribute__((packed));
650 #define IPR_INQUIRY_PAGE0_ENTRIES 20
651 struct ipr_inquiry_page0 {
652 u8 peri_qual_dev_type;
656 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
657 }__attribute__((packed));
659 struct ipr_hostrcb_device_data_entry {
661 struct ipr_res_addr dev_res_addr;
662 struct ipr_vpd new_vpd;
663 struct ipr_vpd ioa_last_with_dev_vpd;
664 struct ipr_vpd cfc_last_with_dev_vpd;
666 }__attribute__((packed, aligned (4)));
668 struct ipr_hostrcb_device_data_entry_enhanced {
669 struct ipr_ext_vpd vpd;
671 struct ipr_res_addr dev_res_addr;
672 struct ipr_ext_vpd new_vpd;
674 struct ipr_ext_vpd ioa_last_with_dev_vpd;
675 struct ipr_ext_vpd cfc_last_with_dev_vpd;
676 }__attribute__((packed, aligned (4)));
678 struct ipr_hostrcb_array_data_entry {
680 struct ipr_res_addr expected_dev_res_addr;
681 struct ipr_res_addr dev_res_addr;
682 }__attribute__((packed, aligned (4)));
684 struct ipr_hostrcb_array_data_entry_enhanced {
685 struct ipr_ext_vpd vpd;
687 struct ipr_res_addr expected_dev_res_addr;
688 struct ipr_res_addr dev_res_addr;
689 }__attribute__((packed, aligned (4)));
691 struct ipr_hostrcb_type_ff_error {
692 __be32 ioa_data[502];
693 }__attribute__((packed, aligned (4)));
695 struct ipr_hostrcb_type_01_error {
699 __be32 ioa_data[236];
700 }__attribute__((packed, aligned (4)));
702 struct ipr_hostrcb_type_02_error {
703 struct ipr_vpd ioa_vpd;
704 struct ipr_vpd cfc_vpd;
705 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
706 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
708 }__attribute__((packed, aligned (4)));
710 struct ipr_hostrcb_type_12_error {
711 struct ipr_ext_vpd ioa_vpd;
712 struct ipr_ext_vpd cfc_vpd;
713 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
714 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
716 }__attribute__((packed, aligned (4)));
718 struct ipr_hostrcb_type_03_error {
719 struct ipr_vpd ioa_vpd;
720 struct ipr_vpd cfc_vpd;
721 __be32 errors_detected;
722 __be32 errors_logged;
724 struct ipr_hostrcb_device_data_entry dev[3];
725 }__attribute__((packed, aligned (4)));
727 struct ipr_hostrcb_type_13_error {
728 struct ipr_ext_vpd ioa_vpd;
729 struct ipr_ext_vpd cfc_vpd;
730 __be32 errors_detected;
731 __be32 errors_logged;
732 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
733 }__attribute__((packed, aligned (4)));
735 struct ipr_hostrcb_type_04_error {
736 struct ipr_vpd ioa_vpd;
737 struct ipr_vpd cfc_vpd;
739 struct ipr_hostrcb_array_data_entry array_member[10];
740 __be32 exposed_mode_adn;
742 struct ipr_vpd incomp_dev_vpd;
744 struct ipr_hostrcb_array_data_entry array_member2[8];
745 struct ipr_res_addr last_func_vset_res_addr;
746 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
747 u8 protection_level[8];
748 }__attribute__((packed, aligned (4)));
750 struct ipr_hostrcb_type_14_error {
751 struct ipr_ext_vpd ioa_vpd;
752 struct ipr_ext_vpd cfc_vpd;
753 __be32 exposed_mode_adn;
755 struct ipr_res_addr last_func_vset_res_addr;
756 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
757 u8 protection_level[8];
759 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
760 }__attribute__((packed, aligned (4)));
762 struct ipr_hostrcb_type_07_error {
763 u8 failure_reason[64];
766 }__attribute__((packed, aligned (4)));
768 struct ipr_hostrcb_type_17_error {
769 u8 failure_reason[64];
770 struct ipr_ext_vpd vpd;
772 }__attribute__((packed, aligned (4)));
774 struct ipr_hostrcb_config_element {
776 #define IPR_PATH_CFG_TYPE_MASK 0xF0
777 #define IPR_PATH_CFG_NOT_EXIST 0x00
778 #define IPR_PATH_CFG_IOA_PORT 0x10
779 #define IPR_PATH_CFG_EXP_PORT 0x20
780 #define IPR_PATH_CFG_DEVICE_PORT 0x30
781 #define IPR_PATH_CFG_DEVICE_LUN 0x40
783 #define IPR_PATH_CFG_STATUS_MASK 0x0F
784 #define IPR_PATH_CFG_NO_PROB 0x00
785 #define IPR_PATH_CFG_DEGRADED 0x01
786 #define IPR_PATH_CFG_FAILED 0x02
787 #define IPR_PATH_CFG_SUSPECT 0x03
788 #define IPR_PATH_NOT_DETECTED 0x04
789 #define IPR_PATH_INCORRECT_CONN 0x05
791 u8 cascaded_expander;
794 #define IPR_PHY_LINK_RATE_MASK 0x0F
797 }__attribute__((packed, aligned (4)));
799 struct ipr_hostrcb_fabric_desc {
802 u8 cascaded_expander;
805 #define IPR_PATH_ACTIVE_MASK 0xC0
806 #define IPR_PATH_NO_INFO 0x00
807 #define IPR_PATH_ACTIVE 0x40
808 #define IPR_PATH_NOT_ACTIVE 0x80
810 #define IPR_PATH_STATE_MASK 0x0F
811 #define IPR_PATH_STATE_NO_INFO 0x00
812 #define IPR_PATH_HEALTHY 0x01
813 #define IPR_PATH_DEGRADED 0x02
814 #define IPR_PATH_FAILED 0x03
817 struct ipr_hostrcb_config_element elem[1];
818 }__attribute__((packed, aligned (4)));
820 #define for_each_fabric_cfg(fabric, cfg) \
821 for (cfg = (fabric)->elem; \
822 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
825 struct ipr_hostrcb_type_20_error {
826 u8 failure_reason[64];
829 struct ipr_hostrcb_fabric_desc desc[1];
830 }__attribute__((packed, aligned (4)));
832 struct ipr_hostrcb_error {
833 __be32 failing_dev_ioasc;
834 struct ipr_res_addr failing_dev_res_addr;
835 __be32 failing_dev_res_handle;
838 struct ipr_hostrcb_type_ff_error type_ff_error;
839 struct ipr_hostrcb_type_01_error type_01_error;
840 struct ipr_hostrcb_type_02_error type_02_error;
841 struct ipr_hostrcb_type_03_error type_03_error;
842 struct ipr_hostrcb_type_04_error type_04_error;
843 struct ipr_hostrcb_type_07_error type_07_error;
844 struct ipr_hostrcb_type_12_error type_12_error;
845 struct ipr_hostrcb_type_13_error type_13_error;
846 struct ipr_hostrcb_type_14_error type_14_error;
847 struct ipr_hostrcb_type_17_error type_17_error;
848 struct ipr_hostrcb_type_20_error type_20_error;
850 }__attribute__((packed, aligned (4)));
852 struct ipr_hostrcb_raw {
853 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
854 }__attribute__((packed, aligned (4)));
858 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
859 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
862 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
863 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
864 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
865 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
866 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
868 u8 notifications_lost;
869 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
870 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
873 #define IPR_HOSTRCB_INTERNAL_OPER 0x80
874 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40
877 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01
878 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02
879 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03
880 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04
881 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06
882 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07
883 #define IPR_HOST_RCB_OVERLAY_ID_12 0x12
884 #define IPR_HOST_RCB_OVERLAY_ID_13 0x13
885 #define IPR_HOST_RCB_OVERLAY_ID_14 0x14
886 #define IPR_HOST_RCB_OVERLAY_ID_16 0x16
887 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17
888 #define IPR_HOST_RCB_OVERLAY_ID_20 0x20
889 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
893 __be32 time_since_last_ioa_reset;
898 struct ipr_hostrcb_error error;
899 struct ipr_hostrcb_cfg_ch_not ccn;
900 struct ipr_hostrcb_raw raw;
902 }__attribute__((packed, aligned (4)));
905 struct ipr_hcam hcam;
906 dma_addr_t hostrcb_dma;
907 struct list_head queue;
908 struct ipr_ioa_cfg *ioa_cfg;
911 /* IPR smart dump table structures */
912 struct ipr_sdt_entry {
913 __be32 bar_str_offset;
919 #define IPR_SDT_ENDIAN 0x80
920 #define IPR_SDT_VALID_ENTRY 0x20
924 }__attribute__((packed, aligned (4)));
926 struct ipr_sdt_header {
929 __be32 num_entries_used;
931 }__attribute__((packed, aligned (4)));
934 struct ipr_sdt_header hdr;
935 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
936 }__attribute__((packed, aligned (4)));
939 struct ipr_sdt_header hdr;
940 struct ipr_sdt_entry entry[1];
941 }__attribute__((packed, aligned (4)));
946 struct ipr_bus_attributes {
954 struct ipr_sata_port {
955 struct ipr_ioa_cfg *ioa_cfg;
957 struct ipr_resource_entry *res;
958 struct ipr_ioasa_gata ioasa;
961 struct ipr_resource_entry {
962 struct ipr_config_table_entry cfgte;
963 u8 needs_sync_complete:1;
967 u8 resetting_device:1;
969 struct scsi_device *sdev;
970 struct ipr_sata_port *sata_port;
971 struct list_head queue;
974 struct ipr_resource_hdr {
979 struct ipr_resource_table {
980 struct ipr_resource_hdr hdr;
981 struct ipr_resource_entry dev[IPR_MAX_PHYSICAL_DEVS];
984 struct ipr_misc_cbs {
985 struct ipr_ioa_vpd ioa_vpd;
986 struct ipr_inquiry_page0 page0_data;
987 struct ipr_inquiry_page3 page3_data;
988 struct ipr_inquiry_cap cap;
989 struct ipr_mode_pages mode_pages;
990 struct ipr_supported_device supp_dev;
993 struct ipr_interrupt_offsets {
994 unsigned long set_interrupt_mask_reg;
995 unsigned long clr_interrupt_mask_reg;
996 unsigned long sense_interrupt_mask_reg;
997 unsigned long clr_interrupt_reg;
999 unsigned long sense_interrupt_reg;
1000 unsigned long ioarrin_reg;
1001 unsigned long sense_uproc_interrupt_reg;
1002 unsigned long set_uproc_interrupt_reg;
1003 unsigned long clr_uproc_interrupt_reg;
1006 struct ipr_interrupts {
1007 void __iomem *set_interrupt_mask_reg;
1008 void __iomem *clr_interrupt_mask_reg;
1009 void __iomem *sense_interrupt_mask_reg;
1010 void __iomem *clr_interrupt_reg;
1012 void __iomem *sense_interrupt_reg;
1013 void __iomem *ioarrin_reg;
1014 void __iomem *sense_uproc_interrupt_reg;
1015 void __iomem *set_uproc_interrupt_reg;
1016 void __iomem *clr_uproc_interrupt_reg;
1019 struct ipr_chip_cfg_t {
1022 struct ipr_interrupt_offsets regs;
1029 #define IPR_USE_LSI 0x00
1030 #define IPR_USE_MSI 0x01
1031 const struct ipr_chip_cfg_t *cfg;
1034 enum ipr_shutdown_type {
1035 IPR_SHUTDOWN_NORMAL = 0x00,
1036 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1037 IPR_SHUTDOWN_ABBREV = 0x80,
1038 IPR_SHUTDOWN_NONE = 0x100
1041 struct ipr_trace_entry {
1047 #define IPR_TRACE_START 0x00
1048 #define IPR_TRACE_FINISH 0xff
1064 struct scatterlist scatterlist[1];
1067 enum ipr_sdt_state {
1075 enum ipr_cache_state {
1082 /* Per-controller data */
1083 struct ipr_ioa_cfg {
1084 char eye_catcher[8];
1085 #define IPR_EYECATCHER "iprcfg"
1087 struct list_head queue;
1089 u8 allow_interrupts:1;
1090 u8 in_reset_reload:1;
1091 u8 in_ioa_bringdown:1;
1092 u8 ioa_unit_checked:1;
1096 u8 allow_ml_add_del:1;
1097 u8 needs_hard_reset:1;
1099 u8 needs_warm_reset:1;
1104 enum ipr_cache_state cache_state;
1105 u16 type; /* CCIN of the card */
1108 #define IPR_MAX_LOG_LEVEL 4
1109 #define IPR_DEFAULT_LOG_LEVEL 2
1111 #define IPR_NUM_TRACE_INDEX_BITS 8
1112 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1113 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1114 char trace_start[8];
1115 #define IPR_TRACE_START_LABEL "trace"
1116 struct ipr_trace_entry *trace;
1117 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1120 * Queue for free command blocks
1122 char ipr_free_label[8];
1123 #define IPR_FREEQ_LABEL "free-q"
1124 struct list_head free_q;
1127 * Queue for command blocks outstanding to the adapter
1129 char ipr_pending_label[8];
1130 #define IPR_PENDQ_LABEL "pend-q"
1131 struct list_head pending_q;
1133 char cfg_table_start[8];
1134 #define IPR_CFG_TBL_START "cfg"
1135 struct ipr_config_table *cfg_table;
1136 dma_addr_t cfg_table_dma;
1138 char resource_table_label[8];
1139 #define IPR_RES_TABLE_LABEL "res_tbl"
1140 struct ipr_resource_entry *res_entries;
1141 struct list_head free_res_q;
1142 struct list_head used_res_q;
1144 char ipr_hcam_label[8];
1145 #define IPR_HCAM_LABEL "hcams"
1146 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1147 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1148 struct list_head hostrcb_free_q;
1149 struct list_head hostrcb_pending_q;
1152 dma_addr_t host_rrq_dma;
1153 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
1154 #define IPR_HRRQ_RESP_BIT_SET 0x00000002
1155 #define IPR_HRRQ_TOGGLE_BIT 0x00000001
1156 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
1157 volatile __be32 *hrrq_start;
1158 volatile __be32 *hrrq_end;
1159 volatile __be32 *hrrq_curr;
1160 volatile u32 toggle_bit;
1162 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1164 unsigned int transop_timeout;
1165 const struct ipr_chip_cfg_t *chip_cfg;
1166 const struct ipr_chip_t *ipr_chip;
1168 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1169 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1170 void __iomem *ioa_mailbox;
1171 struct ipr_interrupts regs;
1173 u16 saved_pcix_cmd_reg;
1179 struct Scsi_Host *host;
1180 struct pci_dev *pdev;
1181 struct ipr_sglist *ucode_sglist;
1182 u8 saved_mode_page_len;
1184 struct work_struct work_q;
1186 wait_queue_head_t reset_wait_q;
1187 wait_queue_head_t msi_wait_q;
1189 struct ipr_dump *dump;
1190 enum ipr_sdt_state sdt_state;
1192 struct ipr_misc_cbs *vpd_cbs;
1193 dma_addr_t vpd_cbs_dma;
1195 struct pci_pool *ipr_cmd_pool;
1197 struct ipr_cmnd *reset_cmd;
1198 int (*reset) (struct ipr_cmnd *);
1200 struct ata_host ata_host;
1201 char ipr_cmd_label[8];
1202 #define IPR_CMD_LABEL "ipr_cmnd"
1203 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
1204 u32 ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
1208 struct ipr_ioarcb ioarcb;
1209 struct ipr_ioasa ioasa;
1210 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1211 struct list_head queue;
1212 struct scsi_cmnd *scsi_cmd;
1213 struct ata_queued_cmd *qc;
1214 struct completion completion;
1215 struct timer_list timer;
1216 void (*done) (struct ipr_cmnd *);
1217 int (*job_step) (struct ipr_cmnd *);
1218 int (*job_step_failed) (struct ipr_cmnd *);
1220 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1221 dma_addr_t sense_buffer_dma;
1222 unsigned short dma_use_sg;
1223 dma_addr_t dma_handle;
1224 struct ipr_cmnd *sibling;
1226 enum ipr_shutdown_type shutdown_type;
1227 struct ipr_hostrcb *hostrcb;
1228 unsigned long time_left;
1229 unsigned long scratch;
1230 struct ipr_resource_entry *res;
1231 struct scsi_device *sdev;
1234 struct ipr_ioa_cfg *ioa_cfg;
1237 struct ipr_ses_table_entry {
1238 char product_id[17];
1239 char compare_product_id_byte[17];
1240 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1243 struct ipr_dump_header {
1245 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1248 u32 first_entry_offset;
1250 #define IPR_DUMP_STATUS_SUCCESS 0
1251 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1252 #define IPR_DUMP_STATUS_FAILED 0xffffffff
1254 #define IPR_DUMP_OS_LINUX 0x4C4E5558
1256 #define IPR_DUMP_DRIVER_NAME 0x49505232
1257 }__attribute__((packed, aligned (4)));
1259 struct ipr_dump_entry_header {
1261 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1266 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1267 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1269 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1270 #define IPR_DUMP_LOCATION_ID 0x4C4F4341
1271 #define IPR_DUMP_TRACE_ID 0x54524143
1272 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1273 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1274 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1275 #define IPR_DUMP_PEND_OPS 0x414F5053
1277 }__attribute__((packed, aligned (4)));
1279 struct ipr_dump_location_entry {
1280 struct ipr_dump_entry_header hdr;
1282 }__attribute__((packed));
1284 struct ipr_dump_trace_entry {
1285 struct ipr_dump_entry_header hdr;
1286 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1287 }__attribute__((packed, aligned (4)));
1289 struct ipr_dump_version_entry {
1290 struct ipr_dump_entry_header hdr;
1291 u8 version[sizeof(IPR_DRIVER_VERSION)];
1294 struct ipr_dump_ioa_type_entry {
1295 struct ipr_dump_entry_header hdr;
1300 struct ipr_driver_dump {
1301 struct ipr_dump_header hdr;
1302 struct ipr_dump_version_entry version_entry;
1303 struct ipr_dump_location_entry location_entry;
1304 struct ipr_dump_ioa_type_entry ioa_type_entry;
1305 struct ipr_dump_trace_entry trace_entry;
1306 }__attribute__((packed));
1308 struct ipr_ioa_dump {
1309 struct ipr_dump_entry_header hdr;
1311 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1313 u32 next_page_index;
1316 #define IPR_SDT_FMT2 2
1317 #define IPR_SDT_UNKNOWN 3
1318 }__attribute__((packed, aligned (4)));
1322 struct ipr_ioa_cfg *ioa_cfg;
1323 struct ipr_driver_dump driver_dump;
1324 struct ipr_ioa_dump ioa_dump;
1327 struct ipr_error_table_t {
1334 struct ipr_software_inq_lid_info {
1336 __be32 timestamp[3];
1337 }__attribute__((packed, aligned (4)));
1339 struct ipr_ucode_image_header {
1340 __be32 header_length;
1341 __be32 lid_table_offset;
1344 u8 minor_release[2];
1346 char eyecatcher[16];
1348 struct ipr_software_inq_lid_info lid[1];
1349 }__attribute__((packed, aligned (4)));
1354 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1356 #ifdef CONFIG_SCSI_IPR_TRACE
1357 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1358 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1360 #define ipr_create_trace_file(kobj, attr) 0
1361 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1364 #ifdef CONFIG_SCSI_IPR_DUMP
1365 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1366 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1368 #define ipr_create_dump_file(kobj, attr) 0
1369 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1373 * Error logging macros
1375 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1376 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1377 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1379 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1380 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1381 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1383 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1384 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1386 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1387 ipr_ra_err(ioa_cfg, (res)->cfgte.res_addr, fmt, ##__VA_ARGS__)
1389 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1391 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1392 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1394 ipr_err(fmt": %d:%d:%d:%d\n", \
1395 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1396 (res).bus, (res).target, (res).lun); \
1400 #define ipr_hcam_err(hostrcb, fmt, ...) \
1402 if (ipr_is_device(&(hostrcb)->hcam.u.error.failing_dev_res_addr)) { \
1403 ipr_ra_err((hostrcb)->ioa_cfg, \
1404 (hostrcb)->hcam.u.error.failing_dev_res_addr, \
1405 fmt, ##__VA_ARGS__); \
1407 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, ##__VA_ARGS__); \
1411 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1412 __FILE__, __func__, __LINE__)
1414 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1415 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1417 #define ipr_err_separator \
1418 ipr_err("----------------------------------------------------------\n")
1426 * ipr_is_ioa_resource - Determine if a resource is the IOA
1427 * @res: resource entry struct
1430 * 1 if IOA / 0 if not IOA
1432 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1434 return (res->cfgte.flags & IPR_IS_IOA_RESOURCE) ? 1 : 0;
1438 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1439 * @res: resource entry struct
1442 * 1 if AF DASD / 0 if not AF DASD
1444 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1446 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) &&
1447 !ipr_is_ioa_resource(res) &&
1448 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_AF_DASD)
1455 * ipr_is_vset_device - Determine if a resource is a VSET
1456 * @res: resource entry struct
1459 * 1 if VSET / 0 if not VSET
1461 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1463 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) &&
1464 !ipr_is_ioa_resource(res) &&
1465 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_VOLUME_SET)
1472 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1473 * @res: resource entry struct
1476 * 1 if GSCSI / 0 if not GSCSI
1478 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1480 if (!ipr_is_ioa_resource(res) &&
1481 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_SCSI)
1488 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1489 * @res: resource entry struct
1492 * 1 if SCSI disk / 0 if not SCSI disk
1494 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1496 if (ipr_is_af_dasd_device(res) ||
1497 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data)))
1504 * ipr_is_gata - Determine if a resource is a generic ATA resource
1505 * @res: resource entry struct
1508 * 1 if GATA / 0 if not GATA
1510 static inline int ipr_is_gata(struct ipr_resource_entry *res)
1512 if (!ipr_is_ioa_resource(res) &&
1513 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_ATA)
1520 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1521 * @res: resource entry struct
1524 * 1 if NACA queueing model / 0 if not NACA queueing model
1526 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1528 if (ipr_is_gscsi(res) && IPR_QUEUEING_MODEL(res) == IPR_QUEUE_NACA_MODEL)
1534 * ipr_is_device - Determine if resource address is that of a device
1535 * @res_addr: resource address struct
1538 * 1 if AF / 0 if not AF
1540 static inline int ipr_is_device(struct ipr_res_addr *res_addr)
1542 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1543 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1550 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1551 * @sdt_word: SDT address
1554 * 1 if format 2 / 0 if not
1556 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1558 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1561 case IPR_SDT_FMT2_BAR0_SEL:
1562 case IPR_SDT_FMT2_BAR1_SEL:
1563 case IPR_SDT_FMT2_BAR2_SEL:
1564 case IPR_SDT_FMT2_BAR3_SEL:
1565 case IPR_SDT_FMT2_BAR4_SEL:
1566 case IPR_SDT_FMT2_BAR5_SEL:
1567 case IPR_SDT_FMT2_EXP_ROM_SEL: