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   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright (C) IBM Corporation, 2006
   5  *
   6  * Author: Jon Mason <jdmason@us.ibm.com>
   7  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   8
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  */
  23
  24 #include <linux/config.h>
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/init.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <asm/proto.h>
  39 #include <asm/calgary.h>
  40 #include <asm/tce.h>
  41 #include <asm/pci-direct.h>
  42 #include <asm/system.h>
  43 #include <asm/dma.h>
  44
  45 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  46 #define PCI_VENDOR_DEVICE_ID_CALGARY \
  47         (PCI_VENDOR_ID_IBM | PCI_DEVICE_ID_IBM_CALGARY << 16)
  48
  49 /* we need these for register space address calculation */
  50 #define START_ADDRESS           0xfe000000
  51 #define CHASSIS_BASE            0
  52 #define ONE_BASED_CHASSIS_NUM   1
  53
  54 /* register offsets inside the host bridge space */
  55 #define PHB_CSR_OFFSET          0x0110
  56 #define PHB_PLSSR_OFFSET        0x0120
  57 #define PHB_CONFIG_RW_OFFSET    0x0160
  58 #define PHB_IOBASE_BAR_LOW      0x0170
  59 #define PHB_IOBASE_BAR_HIGH     0x0180
  60 #define PHB_MEM_1_LOW           0x0190
  61 #define PHB_MEM_1_HIGH          0x01A0
  62 #define PHB_IO_ADDR_SIZE        0x01B0
  63 #define PHB_MEM_1_SIZE          0x01C0
  64 #define PHB_MEM_ST_OFFSET       0x01D0
  65 #define PHB_AER_OFFSET          0x0200
  66 #define PHB_CONFIG_0_HIGH       0x0220
  67 #define PHB_CONFIG_0_LOW        0x0230
  68 #define PHB_CONFIG_0_END        0x0240
  69 #define PHB_MEM_2_LOW           0x02B0
  70 #define PHB_MEM_2_HIGH          0x02C0
  71 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  72 #define PHB_MEM_2_SIZE_LOW      0x02E0
  73 #define PHB_DOSHOLE_OFFSET      0x08E0
  74
  75 /* PHB_CONFIG_RW */
  76 #define PHB_TCE_ENABLE          0x20000000
  77 #define PHB_SLOT_DISABLE        0x1C000000
  78 #define PHB_DAC_DISABLE         0x01000000
  79 #define PHB_MEM2_ENABLE         0x00400000
  80 #define PHB_MCSR_ENABLE         0x00100000
  81 /* TAR (Table Address Register) */
  82 #define TAR_SW_BITS             0x0000ffffffff800fUL
  83 #define TAR_VALID               0x0000000000000008UL
  84 /* CSR (Channel/DMA Status Register) */
  85 #define CSR_AGENT_MASK          0xffe0ffff
  86
  87 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
  88 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * 2) /* max dev->bus->number */
  89 #define PHBS_PER_CALGARY        4
  90
  91 /* register offsets in Calgary's internal register space */
  92 static const unsigned long tar_offsets[] = {
  93         0x0580 /* TAR0 */,
  94         0x0588 /* TAR1 */,
  95         0x0590 /* TAR2 */,
  96         0x0598 /* TAR3 */
  97 };
  98
  99 static const unsigned long split_queue_offsets[] = {
 100         0x4870 /* SPLIT QUEUE 0 */,
 101         0x5870 /* SPLIT QUEUE 1 */,
 102         0x6870 /* SPLIT QUEUE 2 */,
 103         0x7870 /* SPLIT QUEUE 3 */
 104 };
 105
 106 static const unsigned long phb_offsets[] = {
 107         0x8000 /* PHB0 */,
 108         0x9000 /* PHB1 */,
 109         0xA000 /* PHB2 */,
 110         0xB000 /* PHB3 */
 111 };
 112
 113 void* tce_table_kva[MAX_NUM_OF_PHBS * MAX_NUMNODES];
 114 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 115 static int translate_empty_slots __read_mostly = 0;
 116 static int calgary_detected __read_mostly = 0;
 117
 118 /*
 119  * the bitmap of PHBs the user requested that we disable
 120  * translation on.
 121  */
 122 static DECLARE_BITMAP(translation_disabled, MAX_NUMNODES * MAX_PHB_BUS_NUM);
 123
 124 static void tce_cache_blast(struct iommu_table *tbl);
 125
 126 /* enable this to stress test the chip's TCE cache */
 127 #ifdef CONFIG_IOMMU_DEBUG
 128 static inline void tce_cache_blast_stress(struct iommu_table *tbl)
 129 {
 130         tce_cache_blast(tbl);
 131 }
 132 #else
 133 static inline void tce_cache_blast_stress(struct iommu_table *tbl)
 134 {
 135 }
 136 #endif /* BLAST_TCE_CACHE_ON_UNMAP */
 137
 138 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
 139 {
 140         unsigned int npages;
 141
 142         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
 143         npages >>= PAGE_SHIFT;
 144
 145         return npages;
 146 }
 147
 148 static inline int translate_phb(struct pci_dev* dev)
 149 {
 150         int disabled = test_bit(dev->bus->number, translation_disabled);
 151         return !disabled;
 152 }
 153
 154 static void iommu_range_reserve(struct iommu_table *tbl,
 155         unsigned long start_addr, unsigned int npages)
 156 {
 157         unsigned long index;
 158         unsigned long end;
 159
 160         index = start_addr >> PAGE_SHIFT;
 161
 162         /* bail out if we're asked to reserve a region we don't cover */
 163         if (index >= tbl->it_size)
 164                 return;
 165
 166         end = index + npages;
 167         if (end > tbl->it_size) /* don't go off the table */
 168                 end = tbl->it_size;
 169
 170         while (index < end) {
 171                 if (test_bit(index, tbl->it_map))
 172                         printk(KERN_ERR "Calgary: entry already allocated at "
 173                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 174                                index, tbl, start_addr, npages);
 175                 ++index;
 176         }
 177         set_bit_string(tbl->it_map, start_addr >> PAGE_SHIFT, npages);
 178 }
 179
 180 static unsigned long iommu_range_alloc(struct iommu_table *tbl,
 181         unsigned int npages)
 182 {
 183         unsigned long offset;
 184
 185         BUG_ON(npages == 0);
 186
 187         offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
 188                                        tbl->it_size, npages);
 189         if (offset == ~0UL) {
 190                 tce_cache_blast(tbl);
 191                 offset = find_next_zero_string(tbl->it_map, 0,
 192                                                tbl->it_size, npages);
 193                 if (offset == ~0UL) {
 194                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 195                         if (panic_on_overflow)
 196                                 panic("Calgary: fix the allocator.\n");
 197                         else
 198                                 return bad_dma_address;
 199                 }
 200         }
 201
 202         set_bit_string(tbl->it_map, offset, npages);
 203         tbl->it_hint = offset + npages;
 204         BUG_ON(tbl->it_hint > tbl->it_size);
 205
 206         return offset;
 207 }
 208
 209 static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
 210         unsigned int npages, int direction)
 211 {
 212         unsigned long entry, flags;
 213         dma_addr_t ret = bad_dma_address;
 214
 215         spin_lock_irqsave(&tbl->it_lock, flags);
 216
 217         entry = iommu_range_alloc(tbl, npages);
 218
 219         if (unlikely(entry == bad_dma_address))
 220                 goto error;
 221
 222         /* set the return dma address */
 223         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 224
 225         /* put the TCEs in the HW table */
 226         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 227                   direction);
 228
 229         spin_unlock_irqrestore(&tbl->it_lock, flags);
 230
 231         return ret;
 232
 233 error:
 234         spin_unlock_irqrestore(&tbl->it_lock, flags);
 235         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 236                "iommu %p\n", npages, tbl);
 237         return bad_dma_address;
 238 }
 239
 240 static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 241         unsigned int npages)
 242 {
 243         unsigned long entry;
 244         unsigned long i;
 245
 246         entry = dma_addr >> PAGE_SHIFT;
 247
 248         BUG_ON(entry + npages > tbl->it_size);
 249
 250         tce_free(tbl, entry, npages);
 251
 252         for (i = 0; i < npages; ++i) {
 253                 if (!test_bit(entry + i, tbl->it_map))
 254                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 255                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 256                                entry + i, tbl, dma_addr, entry, npages);
 257         }
 258
 259         __clear_bit_string(tbl->it_map, entry, npages);
 260
 261         tce_cache_blast_stress(tbl);
 262 }
 263
 264 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 265         unsigned int npages)
 266 {
 267         unsigned long flags;
 268
 269         spin_lock_irqsave(&tbl->it_lock, flags);
 270
 271         __iommu_free(tbl, dma_addr, npages);
 272
 273         spin_unlock_irqrestore(&tbl->it_lock, flags);
 274 }
 275
 276 static void __calgary_unmap_sg(struct iommu_table *tbl,
 277         struct scatterlist *sglist, int nelems, int direction)
 278 {
 279         while (nelems--) {
 280                 unsigned int npages;
 281                 dma_addr_t dma = sglist->dma_address;
 282                 unsigned int dmalen = sglist->dma_length;
 283
 284                 if (dmalen == 0)
 285                         break;
 286
 287                 npages = num_dma_pages(dma, dmalen);
 288                 __iommu_free(tbl, dma, npages);
 289                 sglist++;
 290         }
 291 }
 292
 293 void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
 294                       int nelems, int direction)
 295 {
 296         unsigned long flags;
 297         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 298
 299         if (!translate_phb(to_pci_dev(dev)))
 300                 return;
 301
 302         spin_lock_irqsave(&tbl->it_lock, flags);
 303
 304         __calgary_unmap_sg(tbl, sglist, nelems, direction);
 305
 306         spin_unlock_irqrestore(&tbl->it_lock, flags);
 307 }
 308
 309 static int calgary_nontranslate_map_sg(struct device* dev,
 310         struct scatterlist *sg, int nelems, int direction)
 311 {
 312         int i;
 313
 314         for (i = 0; i < nelems; i++ ) {
 315                 struct scatterlist *s = &sg[i];
 316                 BUG_ON(!s->page);
 317                 s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
 318                 s->dma_length = s->length;
 319         }
 320         return nelems;
 321 }
 322
 323 int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 324         int nelems, int direction)
 325 {
 326         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 327         unsigned long flags;
 328         unsigned long vaddr;
 329         unsigned int npages;
 330         unsigned long entry;
 331         int i;
 332
 333         if (!translate_phb(to_pci_dev(dev)))
 334                 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
 335
 336         spin_lock_irqsave(&tbl->it_lock, flags);
 337
 338         for (i = 0; i < nelems; i++ ) {
 339                 struct scatterlist *s = &sg[i];
 340                 BUG_ON(!s->page);
 341
 342                 vaddr = (unsigned long)page_address(s->page) + s->offset;
 343                 npages = num_dma_pages(vaddr, s->length);
 344
 345                 entry = iommu_range_alloc(tbl, npages);
 346                 if (entry == bad_dma_address) {
 347                         /* makes sure unmap knows to stop */
 348                         s->dma_length = 0;
 349                         goto error;
 350                 }
 351
 352                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 353
 354                 /* insert into HW table */
 355                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 356                           direction);
 357
 358                 s->dma_length = s->length;
 359         }
 360
 361         spin_unlock_irqrestore(&tbl->it_lock, flags);
 362
 363         return nelems;
 364 error:
 365         __calgary_unmap_sg(tbl, sg, nelems, direction);
 366         for (i = 0; i < nelems; i++) {
 367                 sg[i].dma_address = bad_dma_address;
 368                 sg[i].dma_length = 0;
 369         }
 370         spin_unlock_irqrestore(&tbl->it_lock, flags);
 371         return 0;
 372 }
 373
 374 dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
 375         size_t size, int direction)
 376 {
 377         dma_addr_t dma_handle = bad_dma_address;
 378         unsigned long uaddr;
 379         unsigned int npages;
 380         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 381
 382         uaddr = (unsigned long)vaddr;
 383         npages = num_dma_pages(uaddr, size);
 384
 385         if (translate_phb(to_pci_dev(dev)))
 386                 dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
 387         else
 388                 dma_handle = virt_to_bus(vaddr);
 389
 390         return dma_handle;
 391 }
 392
 393 void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 394         size_t size, int direction)
 395 {
 396         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 397         unsigned int npages;
 398
 399         if (!translate_phb(to_pci_dev(dev)))
 400                 return;
 401
 402         npages = num_dma_pages(dma_handle, size);
 403         iommu_free(tbl, dma_handle, npages);
 404 }
 405
 406 void* calgary_alloc_coherent(struct device *dev, size_t size,
 407         dma_addr_t *dma_handle, gfp_t flag)
 408 {
 409         void *ret = NULL;
 410         dma_addr_t mapping;
 411         unsigned int npages, order;
 412         struct iommu_table *tbl;
 413
 414         tbl = to_pci_dev(dev)->bus->self->sysdata;
 415
 416         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 417         npages = size >> PAGE_SHIFT;
 418         order = get_order(size);
 419
 420         /* alloc enough pages (and possibly more) */
 421         ret = (void *)__get_free_pages(flag, order);
 422         if (!ret)
 423                 goto error;
 424         memset(ret, 0, size);
 425
 426         if (translate_phb(to_pci_dev(dev))) {
 427                 /* set up tces to cover the allocated range */
 428                 mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
 429                 if (mapping == bad_dma_address)
 430                         goto free;
 431
 432                 *dma_handle = mapping;
 433         } else /* non translated slot */
 434                 *dma_handle = virt_to_bus(ret);
 435
 436         return ret;
 437
 438 free:
 439         free_pages((unsigned long)ret, get_order(size));
 440         ret = NULL;
 441 error:
 442         return ret;
 443 }
 444
 445 static struct dma_mapping_ops calgary_dma_ops = {
 446         .alloc_coherent = calgary_alloc_coherent,
 447         .map_single = calgary_map_single,
 448         .unmap_single = calgary_unmap_single,
 449         .map_sg = calgary_map_sg,
 450         .unmap_sg = calgary_unmap_sg,
 451 };
 452
 453 static inline int busno_to_phbid(unsigned char num)
 454 {
 455         return bus_to_phb(num) % PHBS_PER_CALGARY;
 456 }
 457
 458 static inline unsigned long split_queue_offset(unsigned char num)
 459 {
 460         size_t idx = busno_to_phbid(num);
 461
 462         return split_queue_offsets[idx];
 463 }
 464
 465 static inline unsigned long tar_offset(unsigned char num)
 466 {
 467         size_t idx = busno_to_phbid(num);
 468
 469         return tar_offsets[idx];
 470 }
 471
 472 static inline unsigned long phb_offset(unsigned char num)
 473 {
 474         size_t idx = busno_to_phbid(num);
 475
 476         return phb_offsets[idx];
 477 }
 478
 479 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 480 {
 481         unsigned long target = ((unsigned long)bar) | offset;
 482         return (void __iomem*)target;
 483 }
 484
 485 static void tce_cache_blast(struct iommu_table *tbl)
 486 {
 487         u64 val;
 488         u32 aer;
 489         int i = 0;
 490         void __iomem *bbar = tbl->bbar;
 491         void __iomem *target;
 492
 493         /* disable arbitration on the bus */
 494         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 495         aer = readl(target);
 496         writel(0, target);
 497
 498         /* read plssr to ensure it got there */
 499         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 500         val = readl(target);
 501
 502         /* poll split queues until all DMA activity is done */
 503         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 504         do {
 505                 val = readq(target);
 506                 i++;
 507         } while ((val & 0xff) != 0xff && i < 100);
 508         if (i == 100)
 509                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 510                        "continuing anyway\n");
 511
 512         /* invalidate TCE cache */
 513         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 514         writeq(tbl->tar_val, target);
 515
 516         /* enable arbitration */
 517         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 518         writel(aer, target);
 519         (void)readl(target); /* flush */
 520 }
 521
 522 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 523         u64 limit)
 524 {
 525         unsigned int numpages;
 526
 527         limit = limit | 0xfffff;
 528         limit++;
 529
 530         numpages = ((limit - start) >> PAGE_SHIFT);
 531         iommu_range_reserve(dev->sysdata, start, numpages);
 532 }
 533
 534 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 535 {
 536         void __iomem *target;
 537         u64 low, high, sizelow;
 538         u64 start, limit;
 539         struct iommu_table *tbl = dev->sysdata;
 540         unsigned char busnum = dev->bus->number;
 541         void __iomem *bbar = tbl->bbar;
 542
 543         /* peripheral MEM_1 region */
 544         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 545         low = be32_to_cpu(readl(target));
 546         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 547         high = be32_to_cpu(readl(target));
 548         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 549         sizelow = be32_to_cpu(readl(target));
 550
 551         start = (high << 32) | low;
 552         limit = sizelow;
 553
 554         calgary_reserve_mem_region(dev, start, limit);
 555 }
 556
 557 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 558 {
 559         void __iomem *target;
 560         u32 val32;
 561         u64 low, high, sizelow, sizehigh;
 562         u64 start, limit;
 563         struct iommu_table *tbl = dev->sysdata;
 564         unsigned char busnum = dev->bus->number;
 565         void __iomem *bbar = tbl->bbar;
 566
 567         /* is it enabled? */
 568         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 569         val32 = be32_to_cpu(readl(target));
 570         if (!(val32 & PHB_MEM2_ENABLE))
 571                 return;
 572
 573         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 574         low = be32_to_cpu(readl(target));
 575         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 576         high = be32_to_cpu(readl(target));
 577         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 578         sizelow = be32_to_cpu(readl(target));
 579         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 580         sizehigh = be32_to_cpu(readl(target));
 581
 582         start = (high << 32) | low;
 583         limit = (sizehigh << 32) | sizelow;
 584
 585         calgary_reserve_mem_region(dev, start, limit);
 586 }
 587
 588 /*
 589  * some regions of the IO address space do not get translated, so we
 590  * must not give devices IO addresses in those regions. The regions
 591  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 592  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 593  * later.
 594  */
 595 static void __init calgary_reserve_regions(struct pci_dev *dev)
 596 {
 597         unsigned int npages;
 598         void __iomem *bbar;
 599         unsigned char busnum;
 600         u64 start;
 601         struct iommu_table *tbl = dev->sysdata;
 602
 603         bbar = tbl->bbar;
 604         busnum = dev->bus->number;
 605
 606         /* reserve bad_dma_address in case it's a legal address */
 607         iommu_range_reserve(tbl, bad_dma_address, 1);
 608
 609         /* avoid the BIOS/VGA first 640KB-1MB region */
 610         start = (640 * 1024);
 611         npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 612         iommu_range_reserve(tbl, start, npages);
 613
 614         /* reserve the two PCI peripheral memory regions in IO space */
 615         calgary_reserve_peripheral_mem_1(dev);
 616         calgary_reserve_peripheral_mem_2(dev);
 617 }
 618
 619 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 620 {
 621         u64 val64;
 622         u64 table_phys;
 623         void __iomem *target;
 624         int ret;
 625         struct iommu_table *tbl;
 626
 627         /* build TCE tables for each PHB */
 628         ret = build_tce_table(dev, bbar);
 629         if (ret)
 630                 return ret;
 631
 632         calgary_reserve_regions(dev);
 633
 634         /* set TARs for each PHB */
 635         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 636         val64 = be64_to_cpu(readq(target));
 637
 638         /* zero out all TAR bits under sw control */
 639         val64 &= ~TAR_SW_BITS;
 640
 641         tbl = dev->sysdata;
 642         table_phys = (u64)__pa(tbl->it_base);
 643         val64 |= table_phys;
 644
 645         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 646         val64 |= (u64) specified_table_size;
 647
 648         tbl->tar_val = cpu_to_be64(val64);
 649         writeq(tbl->tar_val, target);
 650         readq(target); /* flush */
 651
 652         return 0;
 653 }
 654
 655 static void __init calgary_free_tar(struct pci_dev *dev)
 656 {
 657         u64 val64;
 658         struct iommu_table *tbl = dev->sysdata;
 659         void __iomem *target;
 660
 661         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 662         val64 = be64_to_cpu(readq(target));
 663         val64 &= ~TAR_SW_BITS;
 664         writeq(cpu_to_be64(val64), target);
 665         readq(target); /* flush */
 666
 667         kfree(tbl);
 668         dev->sysdata = NULL;
 669 }
 670
 671 static void calgary_watchdog(unsigned long data)
 672 {
 673         struct pci_dev *dev = (struct pci_dev *)data;
 674         struct iommu_table *tbl = dev->sysdata;
 675         void __iomem *bbar = tbl->bbar;
 676         u32 val32;
 677         void __iomem *target;
 678
 679         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 680         val32 = be32_to_cpu(readl(target));
 681
 682         /* If no error, the agent ID in the CSR is not valid */
 683         if (val32 & CSR_AGENT_MASK) {
 684                 printk(KERN_EMERG "calgary_watchdog: DMA error on bus %d, "
 685                                   "CSR = %#x\n", dev->bus->number, val32);
 686                 writel(0, target);
 687
 688                 /* Disable bus that caused the error */
 689                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 690                                            PHB_CONFIG_RW_OFFSET);
 691                 val32 = be32_to_cpu(readl(target));
 692                 val32 |= PHB_SLOT_DISABLE;
 693                 writel(cpu_to_be32(val32), target);
 694                 readl(target); /* flush */
 695         } else {
 696                 /* Reset the timer */
 697                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 698         }
 699 }
 700
 701 static void __init calgary_enable_translation(struct pci_dev *dev)
 702 {
 703         u32 val32;
 704         unsigned char busnum;
 705         void __iomem *target;
 706         void __iomem *bbar;
 707         struct iommu_table *tbl;
 708
 709         busnum = dev->bus->number;
 710         tbl = dev->sysdata;
 711         bbar = tbl->bbar;
 712
 713         /* enable TCE in PHB Config Register */
 714         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 715         val32 = be32_to_cpu(readl(target));
 716         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
 717
 718         printk(KERN_INFO "Calgary: enabling translation on PHB %d\n", busnum);
 719         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
 720                "bus.\n");
 721
 722         writel(cpu_to_be32(val32), target);
 723         readl(target); /* flush */
 724
 725         init_timer(&tbl->watchdog_timer);
 726         tbl->watchdog_timer.function = &calgary_watchdog;
 727         tbl->watchdog_timer.data = (unsigned long)dev;
 728         mod_timer(&tbl->watchdog_timer, jiffies);
 729 }
 730
 731 static void __init calgary_disable_translation(struct pci_dev *dev)
 732 {
 733         u32 val32;
 734         unsigned char busnum;
 735         void __iomem *target;
 736         void __iomem *bbar;
 737         struct iommu_table *tbl;
 738
 739         busnum = dev->bus->number;
 740         tbl = dev->sysdata;
 741         bbar = tbl->bbar;
 742
 743         /* disable TCE in PHB Config Register */
 744         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 745         val32 = be32_to_cpu(readl(target));
 746         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
 747
 748         printk(KERN_INFO "Calgary: disabling translation on PHB %d!\n", busnum);
 749         writel(cpu_to_be32(val32), target);
 750         readl(target); /* flush */
 751
 752         del_timer_sync(&tbl->watchdog_timer);
 753 }
 754
 755 static inline unsigned int __init locate_register_space(struct pci_dev *dev)
 756 {
 757         int rionodeid;
 758         u32 address;
 759
 760         rionodeid = (dev->bus->number % 15 > 4) ? 3 : 2;
 761         /*
 762          * register space address calculation as follows:
 763          * FE0MB-8MB*OneBasedChassisNumber+1MB*(RioNodeId-ChassisBase)
 764          * ChassisBase is always zero for x366/x260/x460
 765          * RioNodeId is 2 for first Calgary, 3 for second Calgary
 766          */
 767         address = START_ADDRESS -
 768                 (0x800000 * (ONE_BASED_CHASSIS_NUM + dev->bus->number / 15)) +
 769                 (0x100000) * (rionodeid - CHASSIS_BASE);
 770         return address;
 771 }
 772
 773 static int __init calgary_init_one_nontraslated(struct pci_dev *dev)
 774 {
 775         dev->sysdata = NULL;
 776         dev->bus->self = dev;
 777
 778         return 0;
 779 }
 780
 781 static int __init calgary_init_one(struct pci_dev *dev)
 782 {
 783         u32 address;
 784         void __iomem *bbar;
 785         int ret;
 786
 787         address = locate_register_space(dev);
 788         /* map entire 1MB of Calgary config space */
 789         bbar = ioremap_nocache(address, 1024 * 1024);
 790         if (!bbar) {
 791                 ret = -ENODATA;
 792                 goto done;
 793         }
 794
 795         ret = calgary_setup_tar(dev, bbar);
 796         if (ret)
 797                 goto iounmap;
 798
 799         dev->bus->self = dev;
 800         calgary_enable_translation(dev);
 801
 802         return 0;
 803
 804 iounmap:
 805         iounmap(bbar);
 806 done:
 807         return ret;
 808 }
 809
 810 static int __init calgary_init(void)
 811 {
 812         int i, ret = -ENODEV;
 813         struct pci_dev *dev = NULL;
 814
 815         for (i = 0; i <= num_online_nodes() * MAX_NUM_OF_PHBS; i++) {
 816                 dev = pci_get_device(PCI_VENDOR_ID_IBM,
 817                                      PCI_DEVICE_ID_IBM_CALGARY,
 818                                      dev);
 819                 if (!dev)
 820                         break;
 821                 if (!translate_phb(dev)) {
 822                         calgary_init_one_nontraslated(dev);
 823                         continue;
 824                 }
 825                 if (!tce_table_kva[i] && !translate_empty_slots) {
 826                         pci_dev_put(dev);
 827                         continue;
 828                 }
 829                 ret = calgary_init_one(dev);
 830                 if (ret)
 831                         goto error;
 832         }
 833
 834         return ret;
 835
 836 error:
 837         for (i--; i >= 0; i--) {
 838                 dev = pci_find_device_reverse(PCI_VENDOR_ID_IBM,
 839                                               PCI_DEVICE_ID_IBM_CALGARY,
 840                                               dev);
 841                 if (!translate_phb(dev)) {
 842                         pci_dev_put(dev);
 843                         continue;
 844                 }
 845                 if (!tce_table_kva[i] && !translate_empty_slots)
 846                         continue;
 847                 calgary_disable_translation(dev);
 848                 calgary_free_tar(dev);
 849                 pci_dev_put(dev);
 850         }
 851
 852         return ret;
 853 }
 854
 855 static inline int __init determine_tce_table_size(u64 ram)
 856 {
 857         int ret;
 858
 859         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
 860                 return specified_table_size;
 861
 862         /*
 863          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
 864          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
 865          * larger table size has twice as many entries, so shift the
 866          * max ram address by 13 to divide by 8K and then look at the
 867          * order of the result to choose between 0-7.
 868          */
 869         ret = get_order(ram >> 13);
 870         if (ret > TCE_TABLE_SIZE_8M)
 871                 ret = TCE_TABLE_SIZE_8M;
 872
 873         return ret;
 874 }
 875
 876 void __init detect_calgary(void)
 877 {
 878         u32 val;
 879         int bus, table_idx;
 880         void *tbl;
 881         int detected = 0;
 882
 883         /*
 884          * if the user specified iommu=off or iommu=soft or we found
 885          * another HW IOMMU already, bail out.
 886          */
 887         if (swiotlb || no_iommu || iommu_detected)
 888                 return;
 889
 890         specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
 891
 892         for (bus = 0, table_idx = 0;
 893              bus <= num_online_nodes() * MAX_PHB_BUS_NUM;
 894              bus++) {
 895                 BUG_ON(bus > MAX_NUMNODES * MAX_PHB_BUS_NUM);
 896                 if (read_pci_config(bus, 0, 0, 0) != PCI_VENDOR_DEVICE_ID_CALGARY)
 897                         continue;
 898                 if (test_bit(bus, translation_disabled)) {
 899                         printk(KERN_INFO "Calgary: translation is disabled for "
 900                                "PHB 0x%x\n", bus);
 901                         /* skip this phb, don't allocate a tbl for it */
 902                         tce_table_kva[table_idx] = NULL;
 903                         table_idx++;
 904                         continue;
 905                 }
 906                 /*
 907                  * scan the first slot of the PCI bus to see if there
 908                  * are any devices present
 909                  */
 910                 val = read_pci_config(bus, 1, 0, 0);
 911                 if (val != 0xffffffff || translate_empty_slots) {
 912                         tbl = alloc_tce_table();
 913                         if (!tbl)
 914                                 goto cleanup;
 915                         detected = 1;
 916                 } else
 917                         tbl = NULL;
 918
 919                 tce_table_kva[table_idx] = tbl;
 920                 table_idx++;
 921         }
 922
 923         if (detected) {
 924                 iommu_detected = 1;
 925                 calgary_detected = 1;
 926                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected. "
 927                        "TCE table spec is %d.\n", specified_table_size);
 928         }
 929         return;
 930
 931 cleanup:
 932         for (--table_idx; table_idx >= 0; --table_idx)
 933                 if (tce_table_kva[table_idx])
 934                         free_tce_table(tce_table_kva[table_idx]);
 935 }
 936
 937 int __init calgary_iommu_init(void)
 938 {
 939         int ret;
 940
 941         if (no_iommu || swiotlb)
 942                 return -ENODEV;
 943
 944         if (!calgary_detected)
 945                 return -ENODEV;
 946
 947         /* ok, we're trying to use Calgary - let's roll */
 948         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
 949
 950         ret = calgary_init();
 951         if (ret) {
 952                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
 953                        "falling back to no_iommu\n", ret);
 954                 if (end_pfn > MAX_DMA32_PFN)
 955                         printk(KERN_ERR "WARNING more than 4GB of memory, "
 956                                         "32bit PCI may malfunction.\n");
 957                 return ret;
 958         }
 959
 960         force_iommu = 1;
 961         dma_ops = &calgary_dma_ops;
 962
 963         return 0;
 964 }
 965
 966 static int __init calgary_parse_options(char *p)
 967 {
 968         unsigned int bridge;
 969         size_t len;
 970         char* endp;
 971
 972         while (*p) {
 973                 if (!strncmp(p, "64k", 3))
 974                         specified_table_size = TCE_TABLE_SIZE_64K;
 975                 else if (!strncmp(p, "128k", 4))
 976                         specified_table_size = TCE_TABLE_SIZE_128K;
 977                 else if (!strncmp(p, "256k", 4))
 978                         specified_table_size = TCE_TABLE_SIZE_256K;
 979                 else if (!strncmp(p, "512k", 4))
 980                         specified_table_size = TCE_TABLE_SIZE_512K;
 981                 else if (!strncmp(p, "1M", 2))
 982                         specified_table_size = TCE_TABLE_SIZE_1M;
 983                 else if (!strncmp(p, "2M", 2))
 984                         specified_table_size = TCE_TABLE_SIZE_2M;
 985                 else if (!strncmp(p, "4M", 2))
 986                         specified_table_size = TCE_TABLE_SIZE_4M;
 987                 else if (!strncmp(p, "8M", 2))
 988                         specified_table_size = TCE_TABLE_SIZE_8M;
 989
 990                 len = strlen("translate_empty_slots");
 991                 if (!strncmp(p, "translate_empty_slots", len))
 992                         translate_empty_slots = 1;
 993
 994                 len = strlen("disable");
 995                 if (!strncmp(p, "disable", len)) {
 996                         p += len;
 997                         if (*p == '=')
 998                                 ++p;
 999                         if (*p == '\0')
1000                                 break;
1001                         bridge = simple_strtol(p, &endp, 0);
1002                         if (p == endp)
1003                                 break;
1004
1005                         if (bridge <= (num_online_nodes() * MAX_PHB_BUS_NUM)) {
1006                                 printk(KERN_INFO "Calgary: disabling "
1007                                        "translation for PHB 0x%x\n", bridge);
1008                                 set_bit(bridge, translation_disabled);
1009                         }
1010                 }
1011
1012                 p = strpbrk(p, ",");
1013                 if (!p)
1014                         break;
1015
1016                 p++; /* skip ',' */
1017         }
1018         return 1;
1019 }
1020 __setup("calgary=", calgary_parse_options);