5 * Common code specific definitions for mac80211 Prism54 drivers
7 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
8 * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de>
11 * - the islsm (softmac prism54) driver, which is:
12 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
14 * - LMAC API interface header file for STLC4560 (lmac_longbow.h)
15 * Copyright (C) 2007 Conexant Systems, Inc.
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
26 } __attribute__((packed));
28 #define PDR_SYNTH_FRONTEND_MASK 0x0007
29 #define PDR_SYNTH_IQ_CAL_MASK 0x0018
30 #define PDR_SYNTH_IQ_CAL_PA_DETECTOR 0x0000
31 #define PDR_SYNTH_IQ_CAL_DISABLED 0x0008
32 #define PDR_SYNTH_IQ_CAL_ZIF 0x0010
33 #define PDR_SYNTH_FAA_SWITCH_MASK 0x0020
34 #define PDR_SYNTH_FAA_SWITCH_ENABLED 0x0001
35 #define PDR_SYNTH_24_GHZ_MASK 0x0040
36 #define PDR_SYNTH_24_GHZ_DISABLED 0x0040
37 #define PDR_SYNTH_5_GHZ_MASK 0x0080
38 #define PDR_SYNTH_5_GHZ_DISABLED 0x0080
39 #define PDR_SYNTH_RX_DIV_MASK 0x0100
40 #define PDR_SYNTH_RX_DIV_SUPPORTED 0x0100
41 #define PDR_SYNTH_TX_DIV_MASK 0x0200
42 #define PDR_SYNTH_TX_DIV_SUPPORTED 0x0200
44 struct bootrec_exp_if {
50 } __attribute__((packed));
52 #define BR_DESC_PRIV_CAP_WEP BIT(0)
53 #define BR_DESC_PRIV_CAP_TKIP BIT(1)
54 #define BR_DESC_PRIV_CAP_MICHAEL BIT(2)
55 #define BR_DESC_PRIV_CAP_CCX_CP BIT(3)
56 #define BR_DESC_PRIV_CAP_CCX_MIC BIT(4)
57 #define BR_DESC_PRIV_CAP_AESCCMP BIT(5)
75 } __attribute__((packed));
77 #define BR_CODE_MIN 0x80000000
78 #define BR_CODE_COMPONENT_ID 0x80000001
79 #define BR_CODE_COMPONENT_VERSION 0x80000002
80 #define BR_CODE_DEPENDENT_IF 0x80000003
81 #define BR_CODE_EXPOSED_IF 0x80000004
82 #define BR_CODE_DESCR 0x80000101
83 #define BR_CODE_MAX 0x8FFFFFFF
84 #define BR_CODE_END_OF_BRA 0xFF0000FF
85 #define LEGACY_BR_CODE_END_OF_BRA 0xFFFFFFFF
87 #define P54_HDR_FLAG_DATA_ALIGN BIT(14)
88 #define P54_HDR_FLAG_DATA_OUT_PROMISC BIT(0)
89 #define P54_HDR_FLAG_DATA_OUT_TIMESTAMP BIT(1)
90 #define P54_HDR_FLAG_DATA_OUT_SEQNR BIT(2)
91 #define P54_HDR_FLAG_DATA_OUT_BIT3 BIT(3)
92 #define P54_HDR_FLAG_DATA_OUT_BURST BIT(4)
93 #define P54_HDR_FLAG_DATA_OUT_NOCANCEL BIT(5)
94 #define P54_HDR_FLAG_DATA_OUT_CLEARTIM BIT(6)
95 #define P54_HDR_FLAG_DATA_OUT_HITCHHIKE BIT(7)
96 #define P54_HDR_FLAG_DATA_OUT_COMPRESS BIT(8)
97 #define P54_HDR_FLAG_DATA_OUT_CONCAT BIT(9)
98 #define P54_HDR_FLAG_DATA_OUT_PCS_ACCEPT BIT(10)
99 #define P54_HDR_FLAG_DATA_OUT_WAITEOSP BIT(11)
101 #define P54_HDR_FLAG_DATA_IN_FCS_GOOD BIT(0)
102 #define P54_HDR_FLAG_DATA_IN_MATCH_MAC BIT(1)
103 #define P54_HDR_FLAG_DATA_IN_MCBC BIT(2)
104 #define P54_HDR_FLAG_DATA_IN_BEACON BIT(3)
105 #define P54_HDR_FLAG_DATA_IN_MATCH_BSS BIT(4)
106 #define P54_HDR_FLAG_DATA_IN_BCAST_BSS BIT(5)
107 #define P54_HDR_FLAG_DATA_IN_DATA BIT(6)
108 #define P54_HDR_FLAG_DATA_IN_TRUNCATED BIT(7)
109 #define P54_HDR_FLAG_DATA_IN_BIT8 BIT(8)
110 #define P54_HDR_FLAG_DATA_IN_TRANSPARENT BIT(9)
112 /* PDA defines are Copyright (C) 2005 Nokia Corporation (taken from islsm_pda.h) */
115 __le16 len; /* includes both code and data */
118 } __attribute__ ((packed));
120 struct eeprom_pda_wrap {
126 } __attribute__ ((packed));
128 struct pda_iq_autocal_entry {
131 } __attribute__ ((packed));
133 struct pda_channel_output_limit {
141 } __attribute__ ((packed));
143 struct pda_pa_curve_data_sample_rev0 {
147 } __attribute__ ((packed));
149 struct pda_pa_curve_data_sample_rev1 {
157 } __attribute__ ((packed));
159 struct p54_pa_curve_data_sample {
168 } __attribute__ ((packed));
170 struct pda_pa_curve_data {
173 u8 points_per_channel;
176 } __attribute__ ((packed));
178 struct pda_rssi_cal_entry {
181 } __attribute__ ((packed));
184 * this defines the PDR codes used to build PDAs as defined in document
185 * number 553155. The current implementation mirrors version 1.1 of the
186 * document and lists only PDRs supported by the ARM platform.
189 /* common and choice range (0x0000 - 0x0fff) */
190 #define PDR_END 0x0000
191 #define PDR_MANUFACTURING_PART_NUMBER 0x0001
192 #define PDR_PDA_VERSION 0x0002
193 #define PDR_NIC_SERIAL_NUMBER 0x0003
195 #define PDR_MAC_ADDRESS 0x0101
196 #define PDR_REGULATORY_DOMAIN_LIST 0x0103
197 #define PDR_TEMPERATURE_TYPE 0x0107
199 #define PDR_PRISM_PCI_IDENTIFIER 0x0402
201 /* ARM range (0x1000 - 0x1fff) */
202 #define PDR_COUNTRY_INFORMATION 0x1000
203 #define PDR_INTERFACE_LIST 0x1001
204 #define PDR_HARDWARE_PLATFORM_COMPONENT_ID 0x1002
205 #define PDR_OEM_NAME 0x1003
206 #define PDR_PRODUCT_NAME 0x1004
207 #define PDR_UTF8_OEM_NAME 0x1005
208 #define PDR_UTF8_PRODUCT_NAME 0x1006
209 #define PDR_COUNTRY_LIST 0x1007
210 #define PDR_DEFAULT_COUNTRY 0x1008
212 #define PDR_ANTENNA_GAIN 0x1100
214 #define PDR_PRISM_INDIGO_PA_CALIBRATION_DATA 0x1901
215 #define PDR_RSSI_LINEAR_APPROXIMATION 0x1902
216 #define PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS 0x1903
217 #define PDR_PRISM_PA_CAL_CURVE_DATA 0x1904
218 #define PDR_RSSI_LINEAR_APPROXIMATION_DUAL_BAND 0x1905
219 #define PDR_PRISM_ZIF_TX_IQ_CALIBRATION 0x1906
220 #define PDR_REGULATORY_POWER_LIMITS 0x1907
221 #define PDR_RSSI_LINEAR_APPROXIMATION_EXTENDED 0x1908
222 #define PDR_RADIATED_TRANSMISSION_CORRECTION 0x1909
223 #define PDR_PRISM_TX_IQ_CALIBRATION 0x190a
225 /* reserved range (0x2000 - 0x7fff) */
227 /* customer range (0x8000 - 0xffff) */
228 #define PDR_BASEBAND_REGISTERS 0x8000
229 #define PDR_PER_CHANNEL_BASEBAND_REGISTERS 0x8001
231 /* PDR definitions for default country & country list */
232 #define PDR_COUNTRY_CERT_CODE 0x80
233 #define PDR_COUNTRY_CERT_CODE_REAL 0x00
234 #define PDR_COUNTRY_CERT_CODE_PSEUDO 0x80
235 #define PDR_COUNTRY_CERT_BAND 0x40
236 #define PDR_COUNTRY_CERT_BAND_2GHZ 0x00
237 #define PDR_COUNTRY_CERT_BAND_5GHZ 0x40
238 #define PDR_COUNTRY_CERT_IODOOR 0x30
239 #define PDR_COUNTRY_CERT_IODOOR_BOTH 0x00
240 #define PDR_COUNTRY_CERT_IODOOR_INDOOR 0x20
241 #define PDR_COUNTRY_CERT_IODOOR_OUTDOOR 0x30
242 #define PDR_COUNTRY_CERT_INDEX 0x0F
244 /* stored in skb->cb */
250 struct p54_eeprom_lm86 {
265 } __attribute__ ((packed));
266 } __attribute__ ((packed));
268 enum p54_rx_decrypt_status {
269 P54_DECRYPT_NONE = 0,
272 P54_DECRYPT_NOMICHAEL,
273 P54_DECRYPT_NOCKIPMIC,
274 P54_DECRYPT_FAIL_WEP,
275 P54_DECRYPT_FAIL_TKIP,
276 P54_DECRYPT_FAIL_MICHAEL,
277 P54_DECRYPT_FAIL_CKIPKP,
278 P54_DECRYPT_FAIL_CKIPMIC,
279 P54_DECRYPT_FAIL_AESCCMP
295 } __attribute__ ((packed));
301 P54_TRAP_FAA_RADIO_ON,
302 P54_TRAP_FAA_RADIO_OFF,
313 } __attribute__ ((packed));
315 enum p54_frame_sent_status {
319 P54_TX_PSM_CANCELLED = 4
322 struct p54_frame_sent {
330 } __attribute__ ((packed));
332 enum p54_tx_data_crypt {
336 P54_CRYPTO_TKIPMICHAEL,
337 P54_CRYPTO_CCX_WEPMIC,
338 P54_CRYPTO_CCX_KPMIC,
358 } __attribute__ ((packed));
361 #define P54_TX_FRAME_LIFETIME 2000
362 #define P54_TX_TIMEOUT 4000
363 #define P54_STATISTICS_UPDATE 5000
365 #define P54_FILTER_TYPE_NONE 0
366 #define P54_FILTER_TYPE_STATION BIT(0)
367 #define P54_FILTER_TYPE_IBSS BIT(1)
368 #define P54_FILTER_TYPE_AP BIT(2)
369 #define P54_FILTER_TYPE_TRANSPARENT BIT(3)
370 #define P54_FILTER_TYPE_PROMISCUOUS BIT(4)
371 #define P54_FILTER_TYPE_HIBERNATE BIT(5)
372 #define P54_FILTER_TYPE_NOACK BIT(6)
373 #define P54_FILTER_TYPE_RX_DISABLED BIT(7)
375 struct p54_setup_mac {
377 u8 mac_addr[ETH_ALEN];
383 __le32 basic_rate_mask;
390 } v1 __attribute__ ((packed));
397 __le32 basic_rate_mask;
400 u8 rx_rssi_threshold;
403 __le16 lpf_bandwidth;
404 __le16 osc_start_delay;
405 } v2 __attribute__ ((packed));
406 } __attribute__ ((packed));
407 } __attribute__ ((packed));
409 #define P54_SETUP_V1_LEN 40
410 #define P54_SETUP_V2_LEN (sizeof(struct p54_setup_mac))
412 #define P54_SCAN_EXIT BIT(0)
413 #define P54_SCAN_TRAP BIT(1)
414 #define P54_SCAN_ACTIVE BIT(2)
415 #define P54_SCAN_FILTER BIT(3)
421 struct pda_iq_autocal_entry iq_autocal;
422 u8 pa_points_per_curve;
428 struct p54_pa_curve_data_sample curve_data[8];
434 struct pda_rssi_cal_entry v1_rssi;
437 __le32 basic_rate_mask;
439 struct pda_rssi_cal_entry rssi;
440 } v2 __attribute__ ((packed));
441 } __attribute__ ((packed));
442 } __attribute__ ((packed));
444 #define P54_SCAN_V1_LEN 0x70
445 #define P54_SCAN_V2_LEN 0x7c
449 __le16 led_temporary;
450 __le16 led_permanent;
452 } __attribute__ ((packed));
459 struct p54_edcf_queue_param queue[8];
462 __le16 round_trip_delay;
463 } __attribute__ ((packed));
465 struct p54_statistics {
475 __le32 sample_noise[8];
478 } __attribute__ ((packed));
480 struct p54_xbow_synth {
485 } __attribute__ ((packed));
489 } __attribute__ ((packed));
491 struct p54_keycache {
499 } __attribute__ ((packed));
506 __le16 durations[32];
507 } __attribute__ ((packed));
509 struct p54_psm_interval {
512 } __attribute__ ((packed));
514 #define P54_PSM BIT(0)
515 #define P54_PSM_DTIM BIT(1)
516 #define P54_PSM_MCBC BIT(2)
517 #define P54_PSM_CHECKSUM BIT(3)
518 #define P54_PSM_SKIP_MORE_DATA BIT(4)
519 #define P54_PSM_BEACON_TIMEOUT BIT(5)
520 #define P54_PSM_HFOSLEEP BIT(6)
521 #define P54_PSM_AUTOSWITCH_SLEEP BIT(7)
522 #define P54_PSM_LPIT BIT(8)
523 #define P54_PSM_BF_UCAST_SKIP BIT(9)
524 #define P54_PSM_BF_MCAST_SKIP BIT(10)
529 struct p54_psm_interval intervals[4];
530 u8 beacon_rssi_skip_max;
531 u8 rssi_delta_threshold;
534 } __attribute__ ((packed));
536 #define MC_FILTER_ADDRESS_NUM 4
538 struct p54_group_address_table {
539 __le16 filter_enable;
541 u8 mac_list[MC_FILTER_ADDRESS_NUM][ETH_ALEN];
542 } __attribute__ ((packed));
544 struct p54_txcancel {
546 } __attribute__ ((packed));
548 struct p54_sta_unlock {
551 } __attribute__ ((packed));
553 #define P54_TIM_CLEAR BIT(15)
558 } __attribute__ ((packed));
560 struct p54_cce_quiet {
562 } __attribute__ ((packed));
564 struct p54_bt_balancer {
567 } __attribute__ ((packed));
569 struct p54_arp_table {
570 __le16 filter_enable;
572 } __attribute__ ((packed));
574 #endif /* P54COMMON_H */