git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "core.h"
  19 #include "reg.h"
  20 #include "hw.h"
  21
  22 #define ATH_PCI_VERSION "0.1"
  23
  24 static char *dev_info = "ath9k";
  25
  26 MODULE_AUTHOR("Atheros Communications");
  27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  29 MODULE_LICENSE("Dual BSD/GPL");
  30
  31 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  32         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  33         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  34         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  35         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  36         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  37         { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
  38         { 0 }
  39 };
  40
  41 static void ath_detach(struct ath_softc *sc);
  42
  43 /* return bus cachesize in 4B word units */
  44
  45 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
  46 {
  47         u8 u8tmp;
  48
  49         pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE,
  50                              (u8 *)&u8tmp);
  51         *csz = (int)u8tmp;
  52
  53         /*
  54          * This check was put in to avoid "unplesant" consequences if
  55          * the bootrom has not fully initialized all PCI devices.
  56          * Sometimes the cache line size register is not set
  57          */
  58
  59         if (*csz == 0)
  60                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  61 }
  62
  63 static void ath_cache_conf_rate(struct ath_softc *sc,
  64                                 struct ieee80211_conf *conf)
  65 {
  66         switch (conf->channel->band) {
  67         case IEEE80211_BAND_2GHZ:
  68                 if (conf_is_ht20(conf))
  69                         sc->cur_rate_table =
  70                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
  71                 else if (conf_is_ht40_minus(conf))
  72                         sc->cur_rate_table =
  73                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
  74                 else if (conf_is_ht40_plus(conf))
  75                         sc->cur_rate_table =
  76                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
  77                 else
  78                         sc->cur_rate_table =
  79                           sc->hw_rate_table[ATH9K_MODE_11G];
  80                 break;
  81         case IEEE80211_BAND_5GHZ:
  82                 if (conf_is_ht20(conf))
  83                         sc->cur_rate_table =
  84                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
  85                 else if (conf_is_ht40_minus(conf))
  86                         sc->cur_rate_table =
  87                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
  88                 else if (conf_is_ht40_plus(conf))
  89                         sc->cur_rate_table =
  90                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
  91                 else
  92                         sc->cur_rate_table =
  93                           sc->hw_rate_table[ATH9K_MODE_11A];
  94                 break;
  95         default:
  96                 BUG_ON(1);
  97                 break;
  98         }
  99 }
 100
 101 static void ath_update_txpow(struct ath_softc *sc)
 102 {
 103         struct ath_hal *ah = sc->sc_ah;
 104         u32 txpow;
 105
 106         if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
 107                 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
 108                 /* read back in case value is clamped */
 109                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 110                 sc->sc_curtxpow = txpow;
 111         }
 112 }
 113
 114 static u8 parse_mpdudensity(u8 mpdudensity)
 115 {
 116         /*
 117          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 118          *   0 for no restriction
 119          *   1 for 1/4 us
 120          *   2 for 1/2 us
 121          *   3 for 1 us
 122          *   4 for 2 us
 123          *   5 for 4 us
 124          *   6 for 8 us
 125          *   7 for 16 us
 126          */
 127         switch (mpdudensity) {
 128         case 0:
 129                 return 0;
 130         case 1:
 131         case 2:
 132         case 3:
 133                 /* Our lower layer calculations limit our precision to
 134                    1 microsecond */
 135                 return 1;
 136         case 4:
 137                 return 2;
 138         case 5:
 139                 return 4;
 140         case 6:
 141                 return 8;
 142         case 7:
 143                 return 16;
 144         default:
 145                 return 0;
 146         }
 147 }
 148
 149 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 150 {
 151         struct ath_rate_table *rate_table = NULL;
 152         struct ieee80211_supported_band *sband;
 153         struct ieee80211_rate *rate;
 154         int i, maxrates;
 155
 156         switch (band) {
 157         case IEEE80211_BAND_2GHZ:
 158                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 159                 break;
 160         case IEEE80211_BAND_5GHZ:
 161                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 162                 break;
 163         default:
 164                 break;
 165         }
 166
 167         if (rate_table == NULL)
 168                 return;
 169
 170         sband = &sc->sbands[band];
 171         rate = sc->rates[band];
 172
 173         if (rate_table->rate_cnt > ATH_RATE_MAX)
 174                 maxrates = ATH_RATE_MAX;
 175         else
 176                 maxrates = rate_table->rate_cnt;
 177
 178         for (i = 0; i < maxrates; i++) {
 179                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 180                 rate[i].hw_value = rate_table->info[i].ratecode;
 181                 sband->n_bitrates++;
 182                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 183                         rate[i].bitrate / 10, rate[i].hw_value);
 184         }
 185 }
 186
 187 static int ath_setup_channels(struct ath_softc *sc)
 188 {
 189         struct ath_hal *ah = sc->sc_ah;
 190         int nchan, i, a = 0, b = 0;
 191         u8 regclassids[ATH_REGCLASSIDS_MAX];
 192         u32 nregclass = 0;
 193         struct ieee80211_supported_band *band_2ghz;
 194         struct ieee80211_supported_band *band_5ghz;
 195         struct ieee80211_channel *chan_2ghz;
 196         struct ieee80211_channel *chan_5ghz;
 197         struct ath9k_channel *c;
 198
 199         /* Fill in ah->ah_channels */
 200         if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
 201                                       regclassids, ATH_REGCLASSIDS_MAX,
 202                                       &nregclass, CTRY_DEFAULT, false, 1)) {
 203                 u32 rd = ah->ah_currentRD;
 204                 DPRINTF(sc, ATH_DBG_FATAL,
 205                         "Unable to collect channel list; "
 206                         "regdomain likely %u country code %u\n",
 207                         rd, CTRY_DEFAULT);
 208                 return -EINVAL;
 209         }
 210
 211         band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
 212         band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
 213         chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
 214         chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
 215
 216         for (i = 0; i < nchan; i++) {
 217                 c = &ah->ah_channels[i];
 218                 if (IS_CHAN_2GHZ(c)) {
 219                         chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
 220                         chan_2ghz[a].center_freq = c->channel;
 221                         chan_2ghz[a].max_power = c->maxTxPower;
 222                         c->chan = &chan_2ghz[a];
 223
 224                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 225                                 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
 226                         if (c->channelFlags & CHANNEL_PASSIVE)
 227                                 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 228
 229                         band_2ghz->n_channels = ++a;
 230
 231                         DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
 232                                 "channelFlags: 0x%x\n",
 233                                 c->channel, c->channelFlags);
 234                 } else if (IS_CHAN_5GHZ(c)) {
 235                         chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
 236                         chan_5ghz[b].center_freq = c->channel;
 237                         chan_5ghz[b].max_power = c->maxTxPower;
 238                         c->chan = &chan_5ghz[a];
 239
 240                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 241                                 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
 242                         if (c->channelFlags & CHANNEL_PASSIVE)
 243                                 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 244
 245                         band_5ghz->n_channels = ++b;
 246
 247                         DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
 248                                 "channelFlags: 0x%x\n",
 249                                 c->channel, c->channelFlags);
 250                 }
 251         }
 252
 253         return 0;
 254 }
 255
 256 /*
 257  * Set/change channels.  If the channel is really being changed, it's done
 258  * by reseting the chip.  To accomplish this we must first cleanup any pending
 259  * DMA, then restart stuff.
 260 */
 261 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 262 {
 263         struct ath_hal *ah = sc->sc_ah;
 264         bool fastcc = true, stopped;
 265         struct ieee80211_hw *hw = sc->hw;
 266         struct ieee80211_channel *channel = hw->conf.channel;
 267         int r;
 268
 269         if (sc->sc_flags & SC_OP_INVALID)
 270                 return -EIO;
 271
 272         /*
 273          * This is only performed if the channel settings have
 274          * actually changed.
 275          *
 276          * To switch channels clear any pending DMA operations;
 277          * wait long enough for the RX fifo to drain, reset the
 278          * hardware at the new frequency, and then re-enable
 279          * the relevant bits of the h/w.
 280          */
 281         ath9k_hw_set_interrupts(ah, 0);
 282         ath_draintxq(sc, false);
 283         stopped = ath_stoprecv(sc);
 284
 285         /* XXX: do not flush receive queue here. We don't want
 286          * to flush data frames already in queue because of
 287          * changing channel. */
 288
 289         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 290                 fastcc = false;
 291
 292         DPRINTF(sc, ATH_DBG_CONFIG,
 293                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 294                 sc->sc_ah->ah_curchan->channel,
 295                 channel->center_freq, sc->tx_chan_width);
 296
 297         spin_lock_bh(&sc->sc_resetlock);
 298
 299         r = ath9k_hw_reset(ah, hchan, fastcc);
 300         if (r) {
 301                 DPRINTF(sc, ATH_DBG_FATAL,
 302                         "Unable to reset channel (%u Mhz) "
 303                         "reset status %u\n",
 304                         channel->center_freq, r);
 305                 spin_unlock_bh(&sc->sc_resetlock);
 306                 return r;
 307         }
 308         spin_unlock_bh(&sc->sc_resetlock);
 309
 310         sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 311         sc->sc_flags &= ~SC_OP_FULL_RESET;
 312
 313         if (ath_startrecv(sc) != 0) {
 314                 DPRINTF(sc, ATH_DBG_FATAL,
 315                         "Unable to restart recv logic\n");
 316                 return -EIO;
 317         }
 318
 319         ath_cache_conf_rate(sc, &hw->conf);
 320         ath_update_txpow(sc);
 321         ath9k_hw_set_interrupts(ah, sc->sc_imask);
 322         return 0;
 323 }
 324
 325 /*
 326  *  This routine performs the periodic noise floor calibration function
 327  *  that is used to adjust and optimize the chip performance.  This
 328  *  takes environmental changes (location, temperature) into account.
 329  *  When the task is complete, it reschedules itself depending on the
 330  *  appropriate interval that was calculated.
 331  */
 332 static void ath_ani_calibrate(unsigned long data)
 333 {
 334         struct ath_softc *sc;
 335         struct ath_hal *ah;
 336         bool longcal = false;
 337         bool shortcal = false;
 338         bool aniflag = false;
 339         unsigned int timestamp = jiffies_to_msecs(jiffies);
 340         u32 cal_interval;
 341
 342         sc = (struct ath_softc *)data;
 343         ah = sc->sc_ah;
 344
 345         /*
 346         * don't calibrate when we're scanning.
 347         * we are most likely not on our home channel.
 348         */
 349         if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
 350                 return;
 351
 352         /* Long calibration runs independently of short calibration. */
 353         if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
 354                 longcal = true;
 355                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 356                 sc->sc_ani.sc_longcal_timer = timestamp;
 357         }
 358
 359         /* Short calibration applies only while sc_caldone is false */
 360         if (!sc->sc_ani.sc_caldone) {
 361                 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
 362                     ATH_SHORT_CALINTERVAL) {
 363                         shortcal = true;
 364                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 365                         sc->sc_ani.sc_shortcal_timer = timestamp;
 366                         sc->sc_ani.sc_resetcal_timer = timestamp;
 367                 }
 368         } else {
 369                 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
 370                     ATH_RESTART_CALINTERVAL) {
 371                         sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah);
 372                         if (sc->sc_ani.sc_caldone)
 373                                 sc->sc_ani.sc_resetcal_timer = timestamp;
 374                 }
 375         }
 376
 377         /* Verify whether we must check ANI */
 378         if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
 379            ATH_ANI_POLLINTERVAL) {
 380                 aniflag = true;
 381                 sc->sc_ani.sc_checkani_timer = timestamp;
 382         }
 383
 384         /* Skip all processing if there's nothing to do. */
 385         if (longcal || shortcal || aniflag) {
 386                 /* Call ANI routine if necessary */
 387                 if (aniflag)
 388                         ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
 389                                              ah->ah_curchan);
 390
 391                 /* Perform calibration if necessary */
 392                 if (longcal || shortcal) {
 393                         bool iscaldone = false;
 394
 395                         if (ath9k_hw_calibrate(ah, ah->ah_curchan,
 396                                                sc->sc_rx_chainmask, longcal,
 397                                                &iscaldone)) {
 398                                 if (longcal)
 399                                         sc->sc_ani.sc_noise_floor =
 400                                                 ath9k_hw_getchan_noise(ah,
 401                                                                ah->ah_curchan);
 402
 403                                 DPRINTF(sc, ATH_DBG_ANI,
 404                                         "calibrate chan %u/%x nf: %d\n",
 405                                         ah->ah_curchan->channel,
 406                                         ah->ah_curchan->channelFlags,
 407                                         sc->sc_ani.sc_noise_floor);
 408                         } else {
 409                                 DPRINTF(sc, ATH_DBG_ANY,
 410                                         "calibrate chan %u/%x failed\n",
 411                                         ah->ah_curchan->channel,
 412                                         ah->ah_curchan->channelFlags);
 413                         }
 414                         sc->sc_ani.sc_caldone = iscaldone;
 415                 }
 416         }
 417
 418         /*
 419         * Set timer interval based on previous results.
 420         * The interval must be the shortest necessary to satisfy ANI,
 421         * short calibration and long calibration.
 422         */
 423         cal_interval = ATH_LONG_CALINTERVAL;
 424         if (sc->sc_ah->ah_config.enable_ani)
 425                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 426         if (!sc->sc_ani.sc_caldone)
 427                 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
 428
 429         mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 430 }
 431
 432 /*
 433  * Update tx/rx chainmask. For legacy association,
 434  * hard code chainmask to 1x1, for 11n association, use
 435  * the chainmask configuration, for bt coexistence, use
 436  * the chainmask configuration even in legacy mode.
 437  */
 438 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 439 {
 440         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 441         if (is_ht ||
 442             (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
 443                 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
 444                 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
 445         } else {
 446                 sc->sc_tx_chainmask = 1;
 447                 sc->sc_rx_chainmask = 1;
 448         }
 449
 450         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 451                 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
 452 }
 453
 454 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 455 {
 456         struct ath_node *an;
 457
 458         an = (struct ath_node *)sta->drv_priv;
 459
 460         if (sc->sc_flags & SC_OP_TXAGGR)
 461                 ath_tx_node_init(sc, an);
 462
 463         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 464                              sta->ht_cap.ampdu_factor);
 465         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 466 }
 467
 468 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 469 {
 470         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 471
 472         if (sc->sc_flags & SC_OP_TXAGGR)
 473                 ath_tx_node_cleanup(sc, an);
 474 }
 475
 476 static void ath9k_tasklet(unsigned long data)
 477 {
 478         struct ath_softc *sc = (struct ath_softc *)data;
 479         u32 status = sc->sc_intrstatus;
 480
 481         if (status & ATH9K_INT_FATAL) {
 482                 /* need a chip reset */
 483                 ath_reset(sc, false);
 484                 return;
 485         } else {
 486
 487                 if (status &
 488                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 489                         spin_lock_bh(&sc->rx.rxflushlock);
 490                         ath_rx_tasklet(sc, 0);
 491                         spin_unlock_bh(&sc->rx.rxflushlock);
 492                 }
 493                 /* XXX: optimize this */
 494                 if (status & ATH9K_INT_TX)
 495                         ath_tx_tasklet(sc);
 496         }
 497
 498         /* re-enable hardware interrupt */
 499         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 500 }
 501
 502 static irqreturn_t ath_isr(int irq, void *dev)
 503 {
 504         struct ath_softc *sc = dev;
 505         struct ath_hal *ah = sc->sc_ah;
 506         enum ath9k_int status;
 507         bool sched = false;
 508
 509         do {
 510                 if (sc->sc_flags & SC_OP_INVALID) {
 511                         /*
 512                          * The hardware is not ready/present, don't
 513                          * touch anything. Note this can happen early
 514                          * on if the IRQ is shared.
 515                          */
 516                         return IRQ_NONE;
 517                 }
 518                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 519                         return IRQ_NONE;
 520                 }
 521
 522                 /*
 523                  * Figure out the reason(s) for the interrupt.  Note
 524                  * that the hal returns a pseudo-ISR that may include
 525                  * bits we haven't explicitly enabled so we mask the
 526                  * value to insure we only process bits we requested.
 527                  */
 528                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 529
 530                 status &= sc->sc_imask; /* discard unasked-for bits */
 531
 532                 /*
 533                  * If there are no status bits set, then this interrupt was not
 534                  * for me (should have been caught above).
 535                  */
 536                 if (!status)
 537                         return IRQ_NONE;
 538
 539                 sc->sc_intrstatus = status;
 540
 541                 if (status & ATH9K_INT_FATAL) {
 542                         /* need a chip reset */
 543                         sched = true;
 544                 } else if (status & ATH9K_INT_RXORN) {
 545                         /* need a chip reset */
 546                         sched = true;
 547                 } else {
 548                         if (status & ATH9K_INT_SWBA) {
 549                                 /* schedule a tasklet for beacon handling */
 550                                 tasklet_schedule(&sc->bcon_tasklet);
 551                         }
 552                         if (status & ATH9K_INT_RXEOL) {
 553                                 /*
 554                                  * NB: the hardware should re-read the link when
 555                                  *     RXE bit is written, but it doesn't work
 556                                  *     at least on older hardware revs.
 557                                  */
 558                                 sched = true;
 559                         }
 560
 561                         if (status & ATH9K_INT_TXURN)
 562                                 /* bump tx trigger level */
 563                                 ath9k_hw_updatetxtriglevel(ah, true);
 564                         /* XXX: optimize this */
 565                         if (status & ATH9K_INT_RX)
 566                                 sched = true;
 567                         if (status & ATH9K_INT_TX)
 568                                 sched = true;
 569                         if (status & ATH9K_INT_BMISS)
 570                                 sched = true;
 571                         /* carrier sense timeout */
 572                         if (status & ATH9K_INT_CST)
 573                                 sched = true;
 574                         if (status & ATH9K_INT_MIB) {
 575                                 /*
 576                                  * Disable interrupts until we service the MIB
 577                                  * interrupt; otherwise it will continue to
 578                                  * fire.
 579                                  */
 580                                 ath9k_hw_set_interrupts(ah, 0);
 581                                 /*
 582                                  * Let the hal handle the event. We assume
 583                                  * it will clear whatever condition caused
 584                                  * the interrupt.
 585                                  */
 586                                 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
 587                                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 588                         }
 589                         if (status & ATH9K_INT_TIM_TIMER) {
 590                                 if (!(ah->ah_caps.hw_caps &
 591                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 592                                         /* Clear RxAbort bit so that we can
 593                                          * receive frames */
 594                                         ath9k_hw_setrxabort(ah, 0);
 595                                         sched = true;
 596                                 }
 597                         }
 598                 }
 599         } while (0);
 600
 601         ath_debug_stat_interrupt(sc, status);
 602
 603         if (sched) {
 604                 /* turn off every interrupt except SWBA */
 605                 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
 606                 tasklet_schedule(&sc->intr_tq);
 607         }
 608
 609         return IRQ_HANDLED;
 610 }
 611
 612 static int ath_get_channel(struct ath_softc *sc,
 613                            struct ieee80211_channel *chan)
 614 {
 615         int i;
 616
 617         for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
 618                 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
 619                         return i;
 620         }
 621
 622         return -1;
 623 }
 624
 625 static u32 ath_get_extchanmode(struct ath_softc *sc,
 626                                struct ieee80211_channel *chan,
 627                                enum nl80211_channel_type channel_type)
 628 {
 629         u32 chanmode = 0;
 630
 631         switch (chan->band) {
 632         case IEEE80211_BAND_2GHZ:
 633                 switch(channel_type) {
 634                 case NL80211_CHAN_NO_HT:
 635                 case NL80211_CHAN_HT20:
 636                         chanmode = CHANNEL_G_HT20;
 637                         break;
 638                 case NL80211_CHAN_HT40PLUS:
 639                         chanmode = CHANNEL_G_HT40PLUS;
 640                         break;
 641                 case NL80211_CHAN_HT40MINUS:
 642                         chanmode = CHANNEL_G_HT40MINUS;
 643                         break;
 644                 }
 645                 break;
 646         case IEEE80211_BAND_5GHZ:
 647                 switch(channel_type) {
 648                 case NL80211_CHAN_NO_HT:
 649                 case NL80211_CHAN_HT20:
 650                         chanmode = CHANNEL_A_HT20;
 651                         break;
 652                 case NL80211_CHAN_HT40PLUS:
 653                         chanmode = CHANNEL_A_HT40PLUS;
 654                         break;
 655                 case NL80211_CHAN_HT40MINUS:
 656                         chanmode = CHANNEL_A_HT40MINUS;
 657                         break;
 658                 }
 659                 break;
 660         default:
 661                 break;
 662         }
 663
 664         return chanmode;
 665 }
 666
 667 static int ath_keyset(struct ath_softc *sc, u16 keyix,
 668                struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
 669 {
 670         bool status;
 671
 672         status = ath9k_hw_set_keycache_entry(sc->sc_ah,
 673                 keyix, hk, mac, false);
 674
 675         return status != false;
 676 }
 677
 678 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 679                            struct ath9k_keyval *hk,
 680                            const u8 *addr)
 681 {
 682         const u8 *key_rxmic;
 683         const u8 *key_txmic;
 684
 685         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 686         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 687
 688         if (addr == NULL) {
 689                 /* Group key installation */
 690                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 691                 return ath_keyset(sc, keyix, hk, addr);
 692         }
 693         if (!sc->sc_splitmic) {
 694                 /*
 695                  * data key goes at first index,
 696                  * the hal handles the MIC keys at index+64.
 697                  */
 698                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 699                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 700                 return ath_keyset(sc, keyix, hk, addr);
 701         }
 702         /*
 703          * TX key goes at first index, RX key at +32.
 704          * The hal handles the MIC keys at index+64.
 705          */
 706         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 707         if (!ath_keyset(sc, keyix, hk, NULL)) {
 708                 /* Txmic entry failed. No need to proceed further */
 709                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 710                         "Setting TX MIC Key Failed\n");
 711                 return 0;
 712         }
 713
 714         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 715         /* XXX delete tx key on failure? */
 716         return ath_keyset(sc, keyix + 32, hk, addr);
 717 }
 718
 719 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 720 {
 721         int i;
 722
 723         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
 724                 if (test_bit(i, sc->sc_keymap) ||
 725                     test_bit(i + 64, sc->sc_keymap))
 726                         continue; /* At least one part of TKIP key allocated */
 727                 if (sc->sc_splitmic &&
 728                     (test_bit(i + 32, sc->sc_keymap) ||
 729                      test_bit(i + 64 + 32, sc->sc_keymap)))
 730                         continue; /* At least one part of TKIP key allocated */
 731
 732                 /* Found a free slot for a TKIP key */
 733                 return i;
 734         }
 735         return -1;
 736 }
 737
 738 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 739 {
 740         int i;
 741
 742         /* First, try to find slots that would not be available for TKIP. */
 743         if (sc->sc_splitmic) {
 744                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
 745                         if (!test_bit(i, sc->sc_keymap) &&
 746                             (test_bit(i + 32, sc->sc_keymap) ||
 747                              test_bit(i + 64, sc->sc_keymap) ||
 748                              test_bit(i + 64 + 32, sc->sc_keymap)))
 749                                 return i;
 750                         if (!test_bit(i + 32, sc->sc_keymap) &&
 751                             (test_bit(i, sc->sc_keymap) ||
 752                              test_bit(i + 64, sc->sc_keymap) ||
 753                              test_bit(i + 64 + 32, sc->sc_keymap)))
 754                                 return i + 32;
 755                         if (!test_bit(i + 64, sc->sc_keymap) &&
 756                             (test_bit(i , sc->sc_keymap) ||
 757                              test_bit(i + 32, sc->sc_keymap) ||
 758                              test_bit(i + 64 + 32, sc->sc_keymap)))
 759                                 return i + 64;
 760                         if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
 761                             (test_bit(i, sc->sc_keymap) ||
 762                              test_bit(i + 32, sc->sc_keymap) ||
 763                              test_bit(i + 64, sc->sc_keymap)))
 764                                 return i + 64 + 32;
 765                 }
 766         } else {
 767                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
 768                         if (!test_bit(i, sc->sc_keymap) &&
 769                             test_bit(i + 64, sc->sc_keymap))
 770                                 return i;
 771                         if (test_bit(i, sc->sc_keymap) &&
 772                             !test_bit(i + 64, sc->sc_keymap))
 773                                 return i + 64;
 774                 }
 775         }
 776
 777         /* No partially used TKIP slots, pick any available slot */
 778         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
 779                 /* Do not allow slots that could be needed for TKIP group keys
 780                  * to be used. This limitation could be removed if we know that
 781                  * TKIP will not be used. */
 782                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 783                         continue;
 784                 if (sc->sc_splitmic) {
 785                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 786                                 continue;
 787                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 788                                 continue;
 789                 }
 790
 791                 if (!test_bit(i, sc->sc_keymap))
 792                         return i; /* Found a free slot for a key */
 793         }
 794
 795         /* No free slot found */
 796         return -1;
 797 }
 798
 799 static int ath_key_config(struct ath_softc *sc,
 800                           struct ieee80211_sta *sta,
 801                           struct ieee80211_key_conf *key)
 802 {
 803         struct ath9k_keyval hk;
 804         const u8 *mac = NULL;
 805         int ret = 0;
 806         int idx;
 807
 808         memset(&hk, 0, sizeof(hk));
 809
 810         switch (key->alg) {
 811         case ALG_WEP:
 812                 hk.kv_type = ATH9K_CIPHER_WEP;
 813                 break;
 814         case ALG_TKIP:
 815                 hk.kv_type = ATH9K_CIPHER_TKIP;
 816                 break;
 817         case ALG_CCMP:
 818                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 819                 break;
 820         default:
 821                 return -EOPNOTSUPP;
 822         }
 823
 824         hk.kv_len = key->keylen;
 825         memcpy(hk.kv_val, key->key, key->keylen);
 826
 827         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 828                 /* For now, use the default keys for broadcast keys. This may
 829                  * need to change with virtual interfaces. */
 830                 idx = key->keyidx;
 831         } else if (key->keyidx) {
 832                 struct ieee80211_vif *vif;
 833
 834                 if (WARN_ON(!sta))
 835                         return -EOPNOTSUPP;
 836                 mac = sta->addr;
 837
 838                 vif = sc->sc_vaps[0];
 839                 if (vif->type != NL80211_IFTYPE_AP) {
 840                         /* Only keyidx 0 should be used with unicast key, but
 841                          * allow this for client mode for now. */
 842                         idx = key->keyidx;
 843                 } else
 844                         return -EIO;
 845         } else {
 846                 if (WARN_ON(!sta))
 847                         return -EOPNOTSUPP;
 848                 mac = sta->addr;
 849
 850                 if (key->alg == ALG_TKIP)
 851                         idx = ath_reserve_key_cache_slot_tkip(sc);
 852                 else
 853                         idx = ath_reserve_key_cache_slot(sc);
 854                 if (idx < 0)
 855                         return -ENOSPC; /* no free key cache entries */
 856         }
 857
 858         if (key->alg == ALG_TKIP)
 859                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
 860         else
 861                 ret = ath_keyset(sc, idx, &hk, mac);
 862
 863         if (!ret)
 864                 return -EIO;
 865
 866         set_bit(idx, sc->sc_keymap);
 867         if (key->alg == ALG_TKIP) {
 868                 set_bit(idx + 64, sc->sc_keymap);
 869                 if (sc->sc_splitmic) {
 870                         set_bit(idx + 32, sc->sc_keymap);
 871                         set_bit(idx + 64 + 32, sc->sc_keymap);
 872                 }
 873         }
 874
 875         return idx;
 876 }
 877
 878 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 879 {
 880         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 881         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 882                 return;
 883
 884         clear_bit(key->hw_key_idx, sc->sc_keymap);
 885         if (key->alg != ALG_TKIP)
 886                 return;
 887
 888         clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
 889         if (sc->sc_splitmic) {
 890                 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
 891                 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
 892         }
 893 }
 894
 895 static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
 896 {
 897 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 898 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 899
 900         ht_info->ht_supported = true;
 901         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 902                        IEEE80211_HT_CAP_SM_PS |
 903                        IEEE80211_HT_CAP_SGI_40 |
 904                        IEEE80211_HT_CAP_DSSSCCK40;
 905
 906         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 907         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 908         /* set up supported mcs set */
 909         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 910         ht_info->mcs.rx_mask[0] = 0xff;
 911         ht_info->mcs.rx_mask[1] = 0xff;
 912         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 913 }
 914
 915 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 916                                  struct ieee80211_vif *vif,
 917                                  struct ieee80211_bss_conf *bss_conf)
 918 {
 919         struct ath_vap *avp = (void *)vif->drv_priv;
 920
 921         if (bss_conf->assoc) {
 922                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 923                         bss_conf->aid, sc->sc_curbssid);
 924
 925                 /* New association, store aid */
 926                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 927                         sc->sc_curaid = bss_conf->aid;
 928                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
 929                                                sc->sc_curaid);
 930                 }
 931
 932                 /* Configure the beacon */
 933                 ath_beacon_config(sc, 0);
 934                 sc->sc_flags |= SC_OP_BEACONS;
 935
 936                 /* Reset rssi stats */
 937                 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 938                 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 939                 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 940                 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 941
 942                 /* Start ANI */
 943                 mod_timer(&sc->sc_ani.timer,
 944                         jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 945
 946         } else {
 947                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 948                 sc->sc_curaid = 0;
 949         }
 950 }
 951
 952 /********************************/
 953 /*       LED functions          */
 954 /********************************/
 955
 956 static void ath_led_brightness(struct led_classdev *led_cdev,
 957                                enum led_brightness brightness)
 958 {
 959         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 960         struct ath_softc *sc = led->sc;
 961
 962         switch (brightness) {
 963         case LED_OFF:
 964                 if (led->led_type == ATH_LED_ASSOC ||
 965                     led->led_type == ATH_LED_RADIO)
 966                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 967                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 968                                 (led->led_type == ATH_LED_RADIO) ? 1 :
 969                                 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
 970                 break;
 971         case LED_FULL:
 972                 if (led->led_type == ATH_LED_ASSOC)
 973                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 974                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 975                 break;
 976         default:
 977                 break;
 978         }
 979 }
 980
 981 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 982                             char *trigger)
 983 {
 984         int ret;
 985
 986         led->sc = sc;
 987         led->led_cdev.name = led->name;
 988         led->led_cdev.default_trigger = trigger;
 989         led->led_cdev.brightness_set = ath_led_brightness;
 990
 991         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
 992         if (ret)
 993                 DPRINTF(sc, ATH_DBG_FATAL,
 994                         "Failed to register led:%s", led->name);
 995         else
 996                 led->registered = 1;
 997         return ret;
 998 }
 999
1000 static void ath_unregister_led(struct ath_led *led)
1001 {
1002         if (led->registered) {
1003                 led_classdev_unregister(&led->led_cdev);
1004                 led->registered = 0;
1005         }
1006 }
1007
1008 static void ath_deinit_leds(struct ath_softc *sc)
1009 {
1010         ath_unregister_led(&sc->assoc_led);
1011         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1012         ath_unregister_led(&sc->tx_led);
1013         ath_unregister_led(&sc->rx_led);
1014         ath_unregister_led(&sc->radio_led);
1015         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1016 }
1017
1018 static void ath_init_leds(struct ath_softc *sc)
1019 {
1020         char *trigger;
1021         int ret;
1022
1023         /* Configure gpio 1 for output */
1024         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1025                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1026         /* LED off, active low */
1027         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1028
1029         trigger = ieee80211_get_radio_led_name(sc->hw);
1030         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1031                 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1032         ret = ath_register_led(sc, &sc->radio_led, trigger);
1033         sc->radio_led.led_type = ATH_LED_RADIO;
1034         if (ret)
1035                 goto fail;
1036
1037         trigger = ieee80211_get_assoc_led_name(sc->hw);
1038         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1039                 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1040         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1041         sc->assoc_led.led_type = ATH_LED_ASSOC;
1042         if (ret)
1043                 goto fail;
1044
1045         trigger = ieee80211_get_tx_led_name(sc->hw);
1046         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1047                 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1048         ret = ath_register_led(sc, &sc->tx_led, trigger);
1049         sc->tx_led.led_type = ATH_LED_TX;
1050         if (ret)
1051                 goto fail;
1052
1053         trigger = ieee80211_get_rx_led_name(sc->hw);
1054         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1055                 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1056         ret = ath_register_led(sc, &sc->rx_led, trigger);
1057         sc->rx_led.led_type = ATH_LED_RX;
1058         if (ret)
1059                 goto fail;
1060
1061         return;
1062
1063 fail:
1064         ath_deinit_leds(sc);
1065 }
1066
1067 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1068
1069 /*******************/
1070 /*      Rfkill     */
1071 /*******************/
1072
1073 static void ath_radio_enable(struct ath_softc *sc)
1074 {
1075         struct ath_hal *ah = sc->sc_ah;
1076         struct ieee80211_channel *channel = sc->hw->conf.channel;
1077         int r;
1078
1079         spin_lock_bh(&sc->sc_resetlock);
1080
1081         r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1082
1083         if (r) {
1084                 DPRINTF(sc, ATH_DBG_FATAL,
1085                         "Unable to reset channel %u (%uMhz) ",
1086                         "reset status %u\n",
1087                         channel->center_freq, r);
1088         }
1089         spin_unlock_bh(&sc->sc_resetlock);
1090
1091         ath_update_txpow(sc);
1092         if (ath_startrecv(sc) != 0) {
1093                 DPRINTF(sc, ATH_DBG_FATAL,
1094                         "Unable to restart recv logic\n");
1095                 return;
1096         }
1097
1098         if (sc->sc_flags & SC_OP_BEACONS)
1099                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1100
1101         /* Re-Enable  interrupts */
1102         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1103
1104         /* Enable LED */
1105         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1106                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1107         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1108
1109         ieee80211_wake_queues(sc->hw);
1110 }
1111
1112 static void ath_radio_disable(struct ath_softc *sc)
1113 {
1114         struct ath_hal *ah = sc->sc_ah;
1115         struct ieee80211_channel *channel = sc->hw->conf.channel;
1116         int r;
1117
1118         ieee80211_stop_queues(sc->hw);
1119
1120         /* Disable LED */
1121         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1122         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1123
1124         /* Disable interrupts */
1125         ath9k_hw_set_interrupts(ah, 0);
1126
1127         ath_draintxq(sc, false);        /* clear pending tx frames */
1128         ath_stoprecv(sc);               /* turn off frame recv */
1129         ath_flushrecv(sc);              /* flush recv queue */
1130
1131         spin_lock_bh(&sc->sc_resetlock);
1132         r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1133         if (r) {
1134                 DPRINTF(sc, ATH_DBG_FATAL,
1135                         "Unable to reset channel %u (%uMhz) "
1136                         "reset status %u\n",
1137                         channel->center_freq, r);
1138         }
1139         spin_unlock_bh(&sc->sc_resetlock);
1140
1141         ath9k_hw_phy_disable(ah);
1142         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1143 }
1144
1145 static bool ath_is_rfkill_set(struct ath_softc *sc)
1146 {
1147         struct ath_hal *ah = sc->sc_ah;
1148
1149         return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1150                                   ah->ah_rfkill_polarity;
1151 }
1152
1153 /* h/w rfkill poll function */
1154 static void ath_rfkill_poll(struct work_struct *work)
1155 {
1156         struct ath_softc *sc = container_of(work, struct ath_softc,
1157                                             rf_kill.rfkill_poll.work);
1158         bool radio_on;
1159
1160         if (sc->sc_flags & SC_OP_INVALID)
1161                 return;
1162
1163         radio_on = !ath_is_rfkill_set(sc);
1164
1165         /*
1166          * enable/disable radio only when there is a
1167          * state change in RF switch
1168          */
1169         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1170                 enum rfkill_state state;
1171
1172                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1173                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1174                                 : RFKILL_STATE_HARD_BLOCKED;
1175                 } else if (radio_on) {
1176                         ath_radio_enable(sc);
1177                         state = RFKILL_STATE_UNBLOCKED;
1178                 } else {
1179                         ath_radio_disable(sc);
1180                         state = RFKILL_STATE_HARD_BLOCKED;
1181                 }
1182
1183                 if (state == RFKILL_STATE_HARD_BLOCKED)
1184                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1185                 else
1186                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1187
1188                 rfkill_force_state(sc->rf_kill.rfkill, state);
1189         }
1190
1191         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1192                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1193 }
1194
1195 /* s/w rfkill handler */
1196 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1197 {
1198         struct ath_softc *sc = data;
1199
1200         switch (state) {
1201         case RFKILL_STATE_SOFT_BLOCKED:
1202                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1203                     SC_OP_RFKILL_SW_BLOCKED)))
1204                         ath_radio_disable(sc);
1205                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1206                 return 0;
1207         case RFKILL_STATE_UNBLOCKED:
1208                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1209                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1210                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1211                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1212                                         "radio as it is disabled by h/w\n");
1213                                 return -EPERM;
1214                         }
1215                         ath_radio_enable(sc);
1216                 }
1217                 return 0;
1218         default:
1219                 return -EINVAL;
1220         }
1221 }
1222
1223 /* Init s/w rfkill */
1224 static int ath_init_sw_rfkill(struct ath_softc *sc)
1225 {
1226         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1227                                              RFKILL_TYPE_WLAN);
1228         if (!sc->rf_kill.rfkill) {
1229                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1230                 return -ENOMEM;
1231         }
1232
1233         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1234                 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1235         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1236         sc->rf_kill.rfkill->data = sc;
1237         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1238         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1239         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1240
1241         return 0;
1242 }
1243
1244 /* Deinitialize rfkill */
1245 static void ath_deinit_rfkill(struct ath_softc *sc)
1246 {
1247         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1248                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1249
1250         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1251                 rfkill_unregister(sc->rf_kill.rfkill);
1252                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1253                 sc->rf_kill.rfkill = NULL;
1254         }
1255 }
1256
1257 static int ath_start_rfkill_poll(struct ath_softc *sc)
1258 {
1259         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1260                 queue_delayed_work(sc->hw->workqueue,
1261                                    &sc->rf_kill.rfkill_poll, 0);
1262
1263         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1264                 if (rfkill_register(sc->rf_kill.rfkill)) {
1265                         DPRINTF(sc, ATH_DBG_FATAL,
1266                                 "Unable to register rfkill\n");
1267                         rfkill_free(sc->rf_kill.rfkill);
1268
1269                         /* Deinitialize the device */
1270                         ath_detach(sc);
1271                         if (to_pci_dev(sc->dev)->irq)
1272                                 free_irq(to_pci_dev(sc->dev)->irq, sc);
1273                         pci_iounmap(to_pci_dev(sc->dev), sc->mem);
1274                         pci_release_region(to_pci_dev(sc->dev), 0);
1275                         pci_disable_device(to_pci_dev(sc->dev));
1276                         ieee80211_free_hw(sc->hw);
1277                         return -EIO;
1278                 } else {
1279                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1280                 }
1281         }
1282
1283         return 0;
1284 }
1285 #endif /* CONFIG_RFKILL */
1286
1287 static void ath_detach(struct ath_softc *sc)
1288 {
1289         struct ieee80211_hw *hw = sc->hw;
1290         int i = 0;
1291
1292         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1293
1294 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1295         ath_deinit_rfkill(sc);
1296 #endif
1297         ath_deinit_leds(sc);
1298
1299         ieee80211_unregister_hw(hw);
1300         ath_rx_cleanup(sc);
1301         ath_tx_cleanup(sc);
1302
1303         tasklet_kill(&sc->intr_tq);
1304         tasklet_kill(&sc->bcon_tasklet);
1305
1306         if (!(sc->sc_flags & SC_OP_INVALID))
1307                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1308
1309         /* cleanup tx queues */
1310         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1311                 if (ATH_TXQ_SETUP(sc, i))
1312                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1313
1314         ath9k_hw_detach(sc->sc_ah);
1315         ath9k_exit_debug(sc);
1316 }
1317
1318 static int ath_init(u16 devid, struct ath_softc *sc)
1319 {
1320         struct ath_hal *ah = NULL;
1321         int status;
1322         int error = 0, i;
1323         int csz = 0;
1324
1325         /* XXX: hardware will not be ready until ath_open() being called */
1326         sc->sc_flags |= SC_OP_INVALID;
1327
1328         if (ath9k_init_debug(sc) < 0)
1329                 printk(KERN_ERR "Unable to create debugfs files\n");
1330
1331         spin_lock_init(&sc->sc_resetlock);
1332         mutex_init(&sc->mutex);
1333         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1334         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1335                      (unsigned long)sc);
1336
1337         /*
1338          * Cache line size is used to size and align various
1339          * structures used to communicate with the hardware.
1340          */
1341         bus_read_cachesize(sc, &csz);
1342         /* XXX assert csz is non-zero */
1343         sc->sc_cachelsz = csz << 2;     /* convert to bytes */
1344
1345         ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1346         if (ah == NULL) {
1347                 DPRINTF(sc, ATH_DBG_FATAL,
1348                         "Unable to attach hardware; HAL status %d\n", status);
1349                 error = -ENXIO;
1350                 goto bad;
1351         }
1352         sc->sc_ah = ah;
1353
1354         /* Get the hardware key cache size. */
1355         sc->sc_keymax = ah->ah_caps.keycache_size;
1356         if (sc->sc_keymax > ATH_KEYMAX) {
1357                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1358                         "Warning, using only %u entries in %u key cache\n",
1359                         ATH_KEYMAX, sc->sc_keymax);
1360                 sc->sc_keymax = ATH_KEYMAX;
1361         }
1362
1363         /*
1364          * Reset the key cache since some parts do not
1365          * reset the contents on initial power up.
1366          */
1367         for (i = 0; i < sc->sc_keymax; i++)
1368                 ath9k_hw_keyreset(ah, (u16) i);
1369
1370         /* Collect the channel list using the default country code */
1371
1372         error = ath_setup_channels(sc);
1373         if (error)
1374                 goto bad;
1375
1376         /* default to MONITOR mode */
1377         sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1378
1379
1380         /* Setup rate tables */
1381
1382         ath_rate_attach(sc);
1383         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1384         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1385
1386         /*
1387          * Allocate hardware transmit queues: one queue for
1388          * beacon frames and one data queue for each QoS
1389          * priority.  Note that the hal handles reseting
1390          * these queues at the needed time.
1391          */
1392         sc->beacon.beaconq = ath_beaconq_setup(ah);
1393         if (sc->beacon.beaconq == -1) {
1394                 DPRINTF(sc, ATH_DBG_FATAL,
1395                         "Unable to setup a beacon xmit queue\n");
1396                 error = -EIO;
1397                 goto bad2;
1398         }
1399         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1400         if (sc->beacon.cabq == NULL) {
1401                 DPRINTF(sc, ATH_DBG_FATAL,
1402                         "Unable to setup CAB xmit queue\n");
1403                 error = -EIO;
1404                 goto bad2;
1405         }
1406
1407         sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1408         ath_cabq_update(sc);
1409
1410         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1411                 sc->tx.hwq_map[i] = -1;
1412
1413         /* Setup data queues */
1414         /* NB: ensure BK queue is the lowest priority h/w queue */
1415         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1416                 DPRINTF(sc, ATH_DBG_FATAL,
1417                         "Unable to setup xmit queue for BK traffic\n");
1418                 error = -EIO;
1419                 goto bad2;
1420         }
1421
1422         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1423                 DPRINTF(sc, ATH_DBG_FATAL,
1424                         "Unable to setup xmit queue for BE traffic\n");
1425                 error = -EIO;
1426                 goto bad2;
1427         }
1428         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1429                 DPRINTF(sc, ATH_DBG_FATAL,
1430                         "Unable to setup xmit queue for VI traffic\n");
1431                 error = -EIO;
1432                 goto bad2;
1433         }
1434         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1435                 DPRINTF(sc, ATH_DBG_FATAL,
1436                         "Unable to setup xmit queue for VO traffic\n");
1437                 error = -EIO;
1438                 goto bad2;
1439         }
1440
1441         /* Initializes the noise floor to a reasonable default value.
1442          * Later on this will be updated during ANI processing. */
1443
1444         sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1445         setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1446
1447         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1448                                    ATH9K_CIPHER_TKIP, NULL)) {
1449                 /*
1450                  * Whether we should enable h/w TKIP MIC.
1451                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1452                  * report WMM capable, so it's always safe to turn on
1453                  * TKIP MIC in this case.
1454                  */
1455                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1456                                        0, 1, NULL);
1457         }
1458
1459         /*
1460          * Check whether the separate key cache entries
1461          * are required to handle both tx+rx MIC keys.
1462          * With split mic keys the number of stations is limited
1463          * to 27 otherwise 59.
1464          */
1465         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1466                                    ATH9K_CIPHER_TKIP, NULL)
1467             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1468                                       ATH9K_CIPHER_MIC, NULL)
1469             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1470                                       0, NULL))
1471                 sc->sc_splitmic = 1;
1472
1473         /* turn on mcast key search if possible */
1474         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1475                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1476                                              1, NULL);
1477
1478         sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1479         sc->sc_config.txpowlimit_override = 0;
1480
1481         /* 11n Capabilities */
1482         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1483                 sc->sc_flags |= SC_OP_TXAGGR;
1484                 sc->sc_flags |= SC_OP_RXAGGR;
1485         }
1486
1487         sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1488         sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1489
1490         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1491         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1492
1493         ath9k_hw_getmac(ah, sc->sc_myaddr);
1494         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1495                 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1496                 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1497                 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1498         }
1499
1500         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1501
1502         /* initialize beacon slots */
1503         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1504                 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1505
1506         /* save MISC configurations */
1507         sc->sc_config.swBeaconProcess = 1;
1508
1509         /* setup channels and rates */
1510
1511         sc->sbands[IEEE80211_BAND_2GHZ].channels =
1512                 sc->channels[IEEE80211_BAND_2GHZ];
1513         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1514                 sc->rates[IEEE80211_BAND_2GHZ];
1515         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1516
1517         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1518                 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1519                         sc->channels[IEEE80211_BAND_5GHZ];
1520                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1521                         sc->rates[IEEE80211_BAND_5GHZ];
1522                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1523         }
1524
1525         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1526                 ath9k_hw_btcoex_enable(sc->sc_ah);
1527
1528         return 0;
1529 bad2:
1530         /* cleanup tx queues */
1531         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1532                 if (ATH_TXQ_SETUP(sc, i))
1533                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1534 bad:
1535         if (ah)
1536                 ath9k_hw_detach(ah);
1537
1538         return error;
1539 }
1540
1541 static int ath_attach(u16 devid, struct ath_softc *sc)
1542 {
1543         struct ieee80211_hw *hw = sc->hw;
1544         int error = 0;
1545
1546         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1547
1548         error = ath_init(devid, sc);
1549         if (error != 0)
1550                 return error;
1551
1552         /* get mac address from hardware and set in mac80211 */
1553
1554         SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1555
1556         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1557                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1558                 IEEE80211_HW_SIGNAL_DBM |
1559                 IEEE80211_HW_AMPDU_AGGREGATION;
1560
1561         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah))
1562                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1563
1564         hw->wiphy->interface_modes =
1565                 BIT(NL80211_IFTYPE_AP) |
1566                 BIT(NL80211_IFTYPE_STATION) |
1567                 BIT(NL80211_IFTYPE_ADHOC);
1568
1569         hw->queues = 4;
1570         hw->max_rates = 4;
1571         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1572         hw->sta_data_size = sizeof(struct ath_node);
1573         hw->vif_data_size = sizeof(struct ath_vap);
1574
1575         hw->rate_control_algorithm = "ath9k_rate_control";
1576
1577         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1578                 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1579                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1580                         setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1581         }
1582
1583         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1584         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1585                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1586                         &sc->sbands[IEEE80211_BAND_5GHZ];
1587
1588         /* initialize tx/rx engine */
1589         error = ath_tx_init(sc, ATH_TXBUF);
1590         if (error != 0)
1591                 goto detach;
1592
1593         error = ath_rx_init(sc, ATH_RXBUF);
1594         if (error != 0)
1595                 goto detach;
1596
1597 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1598         /* Initialze h/w Rfkill */
1599         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1600                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1601
1602         /* Initialize s/w rfkill */
1603         if (ath_init_sw_rfkill(sc))
1604                 goto detach;
1605 #endif
1606
1607         error = ieee80211_register_hw(hw);
1608
1609         /* Initialize LED control */
1610         ath_init_leds(sc);
1611
1612         return 0;
1613 detach:
1614         ath_detach(sc);
1615         return error;
1616 }
1617
1618 int ath_reset(struct ath_softc *sc, bool retry_tx)
1619 {
1620         struct ath_hal *ah = sc->sc_ah;
1621         struct ieee80211_hw *hw = sc->hw;
1622         int r;
1623
1624         ath9k_hw_set_interrupts(ah, 0);
1625         ath_draintxq(sc, retry_tx);
1626         ath_stoprecv(sc);
1627         ath_flushrecv(sc);
1628
1629         spin_lock_bh(&sc->sc_resetlock);
1630         r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1631         if (r)
1632                 DPRINTF(sc, ATH_DBG_FATAL,
1633                         "Unable to reset hardware; reset status %u\n", r);
1634         spin_unlock_bh(&sc->sc_resetlock);
1635
1636         if (ath_startrecv(sc) != 0)
1637                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1638
1639         /*
1640          * We may be doing a reset in response to a request
1641          * that changes the channel so update any state that
1642          * might change as a result.
1643          */
1644         ath_cache_conf_rate(sc, &hw->conf);
1645
1646         ath_update_txpow(sc);
1647
1648         if (sc->sc_flags & SC_OP_BEACONS)
1649                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1650
1651         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1652
1653         if (retry_tx) {
1654                 int i;
1655                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1656                         if (ATH_TXQ_SETUP(sc, i)) {
1657                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1658                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1659                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1660                         }
1661                 }
1662         }
1663
1664         return r;
1665 }
1666
1667 /*
1668  *  This function will allocate both the DMA descriptor structure, and the
1669  *  buffers it contains.  These are used to contain the descriptors used
1670  *  by the system.
1671 */
1672 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1673                       struct list_head *head, const char *name,
1674                       int nbuf, int ndesc)
1675 {
1676 #define DS2PHYS(_dd, _ds)                                               \
1677         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1678 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1679 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1680
1681         struct ath_desc *ds;
1682         struct ath_buf *bf;
1683         int i, bsize, error;
1684
1685         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1686                 name, nbuf, ndesc);
1687
1688         /* ath_desc must be a multiple of DWORDs */
1689         if ((sizeof(struct ath_desc) % 4) != 0) {
1690                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1691                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1692                 error = -ENOMEM;
1693                 goto fail;
1694         }
1695
1696         dd->dd_name = name;
1697         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1698
1699         /*
1700          * Need additional DMA memory because we can't use
1701          * descriptors that cross the 4K page boundary. Assume
1702          * one skipped descriptor per 4K page.
1703          */
1704         if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1705                 u32 ndesc_skipped =
1706                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1707                 u32 dma_len;
1708
1709                 while (ndesc_skipped) {
1710                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1711                         dd->dd_desc_len += dma_len;
1712
1713                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1714                 };
1715         }
1716
1717         /* allocate descriptors */
1718         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1719                                          &dd->dd_desc_paddr, GFP_ATOMIC);
1720         if (dd->dd_desc == NULL) {
1721                 error = -ENOMEM;
1722                 goto fail;
1723         }
1724         ds = dd->dd_desc;
1725         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1726                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1727                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1728
1729         /* allocate buffers */
1730         bsize = sizeof(struct ath_buf) * nbuf;
1731         bf = kmalloc(bsize, GFP_KERNEL);
1732         if (bf == NULL) {
1733                 error = -ENOMEM;
1734                 goto fail2;
1735         }
1736         memset(bf, 0, bsize);
1737         dd->dd_bufptr = bf;
1738
1739         INIT_LIST_HEAD(head);
1740         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1741                 bf->bf_desc = ds;
1742                 bf->bf_daddr = DS2PHYS(dd, ds);
1743
1744                 if (!(sc->sc_ah->ah_caps.hw_caps &
1745                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1746                         /*
1747                          * Skip descriptor addresses which can cause 4KB
1748                          * boundary crossing (addr + length) with a 32 dword
1749                          * descriptor fetch.
1750                          */
1751                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1752                                 ASSERT((caddr_t) bf->bf_desc <
1753                                        ((caddr_t) dd->dd_desc +
1754                                         dd->dd_desc_len));
1755
1756                                 ds += ndesc;
1757                                 bf->bf_desc = ds;
1758                                 bf->bf_daddr = DS2PHYS(dd, ds);
1759                         }
1760                 }
1761                 list_add_tail(&bf->list, head);
1762         }
1763         return 0;
1764 fail2:
1765         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1766                           dd->dd_desc_paddr);
1767 fail:
1768         memset(dd, 0, sizeof(*dd));
1769         return error;
1770 #undef ATH_DESC_4KB_BOUND_CHECK
1771 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1772 #undef DS2PHYS
1773 }
1774
1775 void ath_descdma_cleanup(struct ath_softc *sc,
1776                          struct ath_descdma *dd,
1777                          struct list_head *head)
1778 {
1779         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1780                           dd->dd_desc_paddr);
1781
1782         INIT_LIST_HEAD(head);
1783         kfree(dd->dd_bufptr);
1784         memset(dd, 0, sizeof(*dd));
1785 }
1786
1787 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1788 {
1789         int qnum;
1790
1791         switch (queue) {
1792         case 0:
1793                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1794                 break;
1795         case 1:
1796                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1797                 break;
1798         case 2:
1799                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1800                 break;
1801         case 3:
1802                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1803                 break;
1804         default:
1805                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1806                 break;
1807         }
1808
1809         return qnum;
1810 }
1811
1812 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1813 {
1814         int qnum;
1815
1816         switch (queue) {
1817         case ATH9K_WME_AC_VO:
1818                 qnum = 0;
1819                 break;
1820         case ATH9K_WME_AC_VI:
1821                 qnum = 1;
1822                 break;
1823         case ATH9K_WME_AC_BE:
1824                 qnum = 2;
1825                 break;
1826         case ATH9K_WME_AC_BK:
1827                 qnum = 3;
1828                 break;
1829         default:
1830                 qnum = -1;
1831                 break;
1832         }
1833
1834         return qnum;
1835 }
1836
1837 /**********************/
1838 /* mac80211 callbacks */
1839 /**********************/
1840
1841 static int ath9k_start(struct ieee80211_hw *hw)
1842 {
1843         struct ath_softc *sc = hw->priv;
1844         struct ieee80211_channel *curchan = hw->conf.channel;
1845         struct ath9k_channel *init_channel;
1846         int r, pos;
1847
1848         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1849                 "initial channel: %d MHz\n", curchan->center_freq);
1850
1851         /* setup initial channel */
1852
1853         pos = ath_get_channel(sc, curchan);
1854         if (pos == -1) {
1855                 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
1856                 return -EINVAL;
1857         }
1858
1859         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1860         sc->sc_ah->ah_channels[pos].chanmode =
1861                 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1862         init_channel = &sc->sc_ah->ah_channels[pos];
1863
1864         /* Reset SERDES registers */
1865         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1866
1867         /*
1868          * The basic interface to setting the hardware in a good
1869          * state is ``reset''.  On return the hardware is known to
1870          * be powered up and with interrupts disabled.  This must
1871          * be followed by initialization of the appropriate bits
1872          * and then setup of the interrupt mask.
1873          */
1874         spin_lock_bh(&sc->sc_resetlock);
1875         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1876         if (r) {
1877                 DPRINTF(sc, ATH_DBG_FATAL,
1878                         "Unable to reset hardware; reset status %u "
1879                         "(freq %u MHz)\n", r,
1880                         curchan->center_freq);
1881                 spin_unlock_bh(&sc->sc_resetlock);
1882                 return r;
1883         }
1884         spin_unlock_bh(&sc->sc_resetlock);
1885
1886         /*
1887          * This is needed only to setup initial state
1888          * but it's best done after a reset.
1889          */
1890         ath_update_txpow(sc);
1891
1892         /*
1893          * Setup the hardware after reset:
1894          * The receive engine is set going.
1895          * Frame transmit is handled entirely
1896          * in the frame output path; there's nothing to do
1897          * here except setup the interrupt mask.
1898          */
1899         if (ath_startrecv(sc) != 0) {
1900                 DPRINTF(sc, ATH_DBG_FATAL,
1901                         "Unable to start recv logic\n");
1902                 return -EIO;
1903         }
1904
1905         /* Setup our intr mask. */
1906         sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1907                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1908                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1909
1910         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1911                 sc->sc_imask |= ATH9K_INT_GTT;
1912
1913         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1914                 sc->sc_imask |= ATH9K_INT_CST;
1915
1916         /*
1917          * Enable MIB interrupts when there are hardware phy counters.
1918          * Note we only do this (at the moment) for station mode.
1919          */
1920         if (ath9k_hw_phycounters(sc->sc_ah) &&
1921             ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1922              (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
1923                 sc->sc_imask |= ATH9K_INT_MIB;
1924         /*
1925          * Some hardware processes the TIM IE and fires an
1926          * interrupt when the TIM bit is set.  For hardware
1927          * that does, if not overridden by configuration,
1928          * enable the TIM interrupt when operating as station.
1929          */
1930         if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1931             (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
1932             !sc->sc_config.swBeaconProcess)
1933                 sc->sc_imask |= ATH9K_INT_TIM;
1934
1935         ath_cache_conf_rate(sc, &hw->conf);
1936
1937         sc->sc_flags &= ~SC_OP_INVALID;
1938
1939         /* Disable BMISS interrupt when we're not associated */
1940         sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1941         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1942
1943         ieee80211_wake_queues(sc->hw);
1944
1945 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1946         r = ath_start_rfkill_poll(sc);
1947 #endif
1948         return r;
1949 }
1950
1951 static int ath9k_tx(struct ieee80211_hw *hw,
1952                     struct sk_buff *skb)
1953 {
1954         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1955         struct ath_softc *sc = hw->priv;
1956         struct ath_tx_control txctl;
1957         int hdrlen, padsize;
1958
1959         memset(&txctl, 0, sizeof(struct ath_tx_control));
1960
1961         /*
1962          * As a temporary workaround, assign seq# here; this will likely need
1963          * to be cleaned up to work better with Beacon transmission and virtual
1964          * BSSes.
1965          */
1966         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1967                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1968                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1969                         sc->tx.seq_no += 0x10;
1970                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1971                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1972         }
1973
1974         /* Add the padding after the header if this is not already done */
1975         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1976         if (hdrlen & 3) {
1977                 padsize = hdrlen % 4;
1978                 if (skb_headroom(skb) < padsize)
1979                         return -1;
1980                 skb_push(skb, padsize);
1981                 memmove(skb->data, skb->data + padsize, hdrlen);
1982         }
1983
1984         /* Check if a tx queue is available */
1985
1986         txctl.txq = ath_test_get_txq(sc, skb);
1987         if (!txctl.txq)
1988                 goto exit;
1989
1990         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
1991
1992         if (ath_tx_start(sc, skb, &txctl) != 0) {
1993                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
1994                 goto exit;
1995         }
1996
1997         return 0;
1998 exit:
1999         dev_kfree_skb_any(skb);
2000         return 0;
2001 }
2002
2003 static void ath9k_stop(struct ieee80211_hw *hw)
2004 {
2005         struct ath_softc *sc = hw->priv;
2006
2007         if (sc->sc_flags & SC_OP_INVALID) {
2008                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2009                 return;
2010         }
2011
2012         DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
2013
2014         ieee80211_stop_queues(sc->hw);
2015
2016         /* make sure h/w will not generate any interrupt
2017          * before setting the invalid flag. */
2018         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2019
2020         if (!(sc->sc_flags & SC_OP_INVALID)) {
2021                 ath_draintxq(sc, false);
2022                 ath_stoprecv(sc);
2023                 ath9k_hw_phy_disable(sc->sc_ah);
2024         } else
2025                 sc->rx.rxlink = NULL;
2026
2027 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2028         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2029                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2030 #endif
2031         /* disable HAL and put h/w to sleep */
2032         ath9k_hw_disable(sc->sc_ah);
2033         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2034
2035         sc->sc_flags |= SC_OP_INVALID;
2036
2037         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2038 }
2039
2040 static int ath9k_add_interface(struct ieee80211_hw *hw,
2041                                struct ieee80211_if_init_conf *conf)
2042 {
2043         struct ath_softc *sc = hw->priv;
2044         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2045         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2046
2047         /* Support only vap for now */
2048
2049         if (sc->sc_nvaps)
2050                 return -ENOBUFS;
2051
2052         switch (conf->type) {
2053         case NL80211_IFTYPE_STATION:
2054                 ic_opmode = NL80211_IFTYPE_STATION;
2055                 break;
2056         case NL80211_IFTYPE_ADHOC:
2057                 ic_opmode = NL80211_IFTYPE_ADHOC;
2058                 break;
2059         case NL80211_IFTYPE_AP:
2060                 ic_opmode = NL80211_IFTYPE_AP;
2061                 break;
2062         default:
2063                 DPRINTF(sc, ATH_DBG_FATAL,
2064                         "Interface type %d not yet supported\n", conf->type);
2065                 return -EOPNOTSUPP;
2066         }
2067
2068         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2069
2070         /* Set the VAP opmode */
2071         avp->av_opmode = ic_opmode;
2072         avp->av_bslot = -1;
2073
2074         if (ic_opmode == NL80211_IFTYPE_AP)
2075                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2076
2077         sc->sc_vaps[0] = conf->vif;
2078         sc->sc_nvaps++;
2079
2080         /* Set the device opmode */
2081         sc->sc_ah->ah_opmode = ic_opmode;
2082
2083         if (conf->type == NL80211_IFTYPE_AP) {
2084                 /* TODO: is this a suitable place to start ANI for AP mode? */
2085                 /* Start ANI */
2086                 mod_timer(&sc->sc_ani.timer,
2087                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2088         }
2089
2090         return 0;
2091 }
2092
2093 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2094                                    struct ieee80211_if_init_conf *conf)
2095 {
2096         struct ath_softc *sc = hw->priv;
2097         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2098
2099         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2100
2101         /* Stop ANI */
2102         del_timer_sync(&sc->sc_ani.timer);
2103
2104         /* Reclaim beacon resources */
2105         if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2106             sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2107                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2108                 ath_beacon_return(sc, avp);
2109         }
2110
2111         sc->sc_flags &= ~SC_OP_BEACONS;
2112
2113         sc->sc_vaps[0] = NULL;
2114         sc->sc_nvaps--;
2115 }
2116
2117 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2118 {
2119         struct ath_softc *sc = hw->priv;
2120         struct ieee80211_conf *conf = &hw->conf;
2121
2122         mutex_lock(&sc->mutex);
2123         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2124                 struct ieee80211_channel *curchan = hw->conf.channel;
2125                 int pos;
2126
2127                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2128                         curchan->center_freq);
2129
2130                 pos = ath_get_channel(sc, curchan);
2131                 if (pos == -1) {
2132                         DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2133                                 curchan->center_freq);
2134                         mutex_unlock(&sc->mutex);
2135                         return -EINVAL;
2136                 }
2137
2138                 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2139                 sc->sc_ah->ah_channels[pos].chanmode =
2140                         (curchan->band == IEEE80211_BAND_2GHZ) ?
2141                         CHANNEL_G : CHANNEL_A;
2142
2143                 if (conf_is_ht(conf)) {
2144                         if (conf_is_ht40(conf))
2145                                 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2146
2147                         sc->sc_ah->ah_channels[pos].chanmode =
2148                                 ath_get_extchanmode(sc, curchan,
2149                                                     conf->channel_type);
2150                 }
2151
2152                 ath_update_chainmask(sc, conf_is_ht(conf));
2153
2154                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2155                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2156                         mutex_unlock(&sc->mutex);
2157                         return -EINVAL;
2158                 }
2159         }
2160
2161         if (changed & IEEE80211_CONF_CHANGE_POWER)
2162                 sc->sc_config.txpowlimit = 2 * conf->power_level;
2163
2164         mutex_unlock(&sc->mutex);
2165         return 0;
2166 }
2167
2168 static int ath9k_config_interface(struct ieee80211_hw *hw,
2169                                   struct ieee80211_vif *vif,
2170                                   struct ieee80211_if_conf *conf)
2171 {
2172         struct ath_softc *sc = hw->priv;
2173         struct ath_hal *ah = sc->sc_ah;
2174         struct ath_vap *avp = (void *)vif->drv_priv;
2175         u32 rfilt = 0;
2176         int error, i;
2177
2178         /* TODO: Need to decide which hw opmode to use for multi-interface
2179          * cases */
2180         if (vif->type == NL80211_IFTYPE_AP &&
2181             ah->ah_opmode != NL80211_IFTYPE_AP) {
2182                 ah->ah_opmode = NL80211_IFTYPE_STATION;
2183                 ath9k_hw_setopmode(ah);
2184                 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2185                 /* Request full reset to get hw opmode changed properly */
2186                 sc->sc_flags |= SC_OP_FULL_RESET;
2187         }
2188
2189         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2190             !is_zero_ether_addr(conf->bssid)) {
2191                 switch (vif->type) {
2192                 case NL80211_IFTYPE_STATION:
2193                 case NL80211_IFTYPE_ADHOC:
2194                         /* Set BSSID */
2195                         memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2196                         sc->sc_curaid = 0;
2197                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2198                                                sc->sc_curaid);
2199
2200                         /* Set aggregation protection mode parameters */
2201                         sc->sc_config.ath_aggr_prot = 0;
2202
2203                         DPRINTF(sc, ATH_DBG_CONFIG,
2204                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2205                                 rfilt, sc->sc_curbssid, sc->sc_curaid);
2206
2207                         /* need to reconfigure the beacon */
2208                         sc->sc_flags &= ~SC_OP_BEACONS ;
2209
2210                         break;
2211                 default:
2212                         break;
2213                 }
2214         }
2215
2216         if ((conf->changed & IEEE80211_IFCC_BEACON) &&
2217             ((vif->type == NL80211_IFTYPE_ADHOC) ||
2218              (vif->type == NL80211_IFTYPE_AP))) {
2219                 /*
2220                  * Allocate and setup the beacon frame.
2221                  *
2222                  * Stop any previous beacon DMA.  This may be
2223                  * necessary, for example, when an ibss merge
2224                  * causes reconfiguration; we may be called
2225                  * with beacon transmission active.
2226                  */
2227                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2228
2229                 error = ath_beacon_alloc(sc, 0);
2230                 if (error != 0)
2231                         return error;
2232
2233                 ath_beacon_sync(sc, 0);
2234         }
2235
2236         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2237         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2238                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2239                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2240                                 ath9k_hw_keysetmac(sc->sc_ah,
2241                                                    (u16)i,
2242                                                    sc->sc_curbssid);
2243         }
2244
2245         /* Only legacy IBSS for now */
2246         if (vif->type == NL80211_IFTYPE_ADHOC)
2247                 ath_update_chainmask(sc, 0);
2248
2249         return 0;
2250 }
2251
2252 #define SUPPORTED_FILTERS                       \
2253         (FIF_PROMISC_IN_BSS |                   \
2254         FIF_ALLMULTI |                          \
2255         FIF_CONTROL |                           \
2256         FIF_OTHER_BSS |                         \
2257         FIF_BCN_PRBRESP_PROMISC |               \
2258         FIF_FCSFAIL)
2259
2260 /* FIXME: sc->sc_full_reset ? */
2261 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2262                                    unsigned int changed_flags,
2263                                    unsigned int *total_flags,
2264                                    int mc_count,
2265                                    struct dev_mc_list *mclist)
2266 {
2267         struct ath_softc *sc = hw->priv;
2268         u32 rfilt;
2269
2270         changed_flags &= SUPPORTED_FILTERS;
2271         *total_flags &= SUPPORTED_FILTERS;
2272
2273         sc->rx.rxfilter = *total_flags;
2274         rfilt = ath_calcrxfilter(sc);
2275         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2276
2277         if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2278                 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2279                         ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2280         }
2281
2282         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2283 }
2284
2285 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2286                              struct ieee80211_vif *vif,
2287                              enum sta_notify_cmd cmd,
2288                              struct ieee80211_sta *sta)
2289 {
2290         struct ath_softc *sc = hw->priv;
2291
2292         switch (cmd) {
2293         case STA_NOTIFY_ADD:
2294                 ath_node_attach(sc, sta);
2295                 break;
2296         case STA_NOTIFY_REMOVE:
2297                 ath_node_detach(sc, sta);
2298                 break;
2299         default:
2300                 break;
2301         }
2302 }
2303
2304 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2305                          u16 queue,
2306                          const struct ieee80211_tx_queue_params *params)
2307 {
2308         struct ath_softc *sc = hw->priv;
2309         struct ath9k_tx_queue_info qi;
2310         int ret = 0, qnum;
2311
2312         if (queue >= WME_NUM_AC)
2313                 return 0;
2314
2315         qi.tqi_aifs = params->aifs;
2316         qi.tqi_cwmin = params->cw_min;
2317         qi.tqi_cwmax = params->cw_max;
2318         qi.tqi_burstTime = params->txop;
2319         qnum = ath_get_hal_qnum(queue, sc);
2320
2321         DPRINTF(sc, ATH_DBG_CONFIG,
2322                 "Configure tx [queue/halq] [%d/%d],  "
2323                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2324                 queue, qnum, params->aifs, params->cw_min,
2325                 params->cw_max, params->txop);
2326
2327         ret = ath_txq_update(sc, qnum, &qi);
2328         if (ret)
2329                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2330
2331         return ret;
2332 }
2333
2334 static int ath9k_set_key(struct ieee80211_hw *hw,
2335                          enum set_key_cmd cmd,
2336                          struct ieee80211_vif *vif,
2337                          struct ieee80211_sta *sta,
2338                          struct ieee80211_key_conf *key)
2339 {
2340         struct ath_softc *sc = hw->priv;
2341         int ret = 0;
2342
2343         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2344
2345         switch (cmd) {
2346         case SET_KEY:
2347                 ret = ath_key_config(sc, sta, key);
2348                 if (ret >= 0) {
2349                         key->hw_key_idx = ret;
2350                         /* push IV and Michael MIC generation to stack */
2351                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2352                         if (key->alg == ALG_TKIP)
2353                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2354                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2355                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2356                         ret = 0;
2357                 }
2358                 break;
2359         case DISABLE_KEY:
2360                 ath_key_delete(sc, key);
2361                 break;
2362         default:
2363                 ret = -EINVAL;
2364         }
2365
2366         return ret;
2367 }
2368
2369 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2370                                    struct ieee80211_vif *vif,
2371                                    struct ieee80211_bss_conf *bss_conf,
2372                                    u32 changed)
2373 {
2374         struct ath_softc *sc = hw->priv;
2375
2376         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2377                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2378                         bss_conf->use_short_preamble);
2379                 if (bss_conf->use_short_preamble)
2380                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2381                 else
2382                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2383         }
2384
2385         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2386                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2387                         bss_conf->use_cts_prot);
2388                 if (bss_conf->use_cts_prot &&
2389                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2390                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2391                 else
2392                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2393         }
2394
2395         if (changed & BSS_CHANGED_ASSOC) {
2396                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2397                         bss_conf->assoc);
2398                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2399         }
2400 }
2401
2402 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2403 {
2404         u64 tsf;
2405         struct ath_softc *sc = hw->priv;
2406         struct ath_hal *ah = sc->sc_ah;
2407
2408         tsf = ath9k_hw_gettsf64(ah);
2409
2410         return tsf;
2411 }
2412
2413 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2414 {
2415         struct ath_softc *sc = hw->priv;
2416         struct ath_hal *ah = sc->sc_ah;
2417
2418         ath9k_hw_reset_tsf(ah);
2419 }
2420
2421 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2422                        enum ieee80211_ampdu_mlme_action action,
2423                        struct ieee80211_sta *sta,
2424                        u16 tid, u16 *ssn)
2425 {
2426         struct ath_softc *sc = hw->priv;
2427         int ret = 0;
2428
2429         switch (action) {
2430         case IEEE80211_AMPDU_RX_START:
2431                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2432                         ret = -ENOTSUPP;
2433                 break;
2434         case IEEE80211_AMPDU_RX_STOP:
2435                 break;
2436         case IEEE80211_AMPDU_TX_START:
2437                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2438                 if (ret < 0)
2439                         DPRINTF(sc, ATH_DBG_FATAL,
2440                                 "Unable to start TX aggregation\n");
2441                 else
2442                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2443                 break;
2444         case IEEE80211_AMPDU_TX_STOP:
2445                 ret = ath_tx_aggr_stop(sc, sta, tid);
2446                 if (ret < 0)
2447                         DPRINTF(sc, ATH_DBG_FATAL,
2448                                 "Unable to stop TX aggregation\n");
2449
2450                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2451                 break;
2452         case IEEE80211_AMPDU_TX_RESUME:
2453                 ath_tx_aggr_resume(sc, sta, tid);
2454                 break;
2455         default:
2456                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2457         }
2458
2459         return ret;
2460 }
2461
2462 static struct ieee80211_ops ath9k_ops = {
2463         .tx                 = ath9k_tx,
2464         .start              = ath9k_start,
2465         .stop               = ath9k_stop,
2466         .add_interface      = ath9k_add_interface,
2467         .remove_interface   = ath9k_remove_interface,
2468         .config             = ath9k_config,
2469         .config_interface   = ath9k_config_interface,
2470         .configure_filter   = ath9k_configure_filter,
2471         .sta_notify         = ath9k_sta_notify,
2472         .conf_tx            = ath9k_conf_tx,
2473         .bss_info_changed   = ath9k_bss_info_changed,
2474         .set_key            = ath9k_set_key,
2475         .get_tsf            = ath9k_get_tsf,
2476         .reset_tsf          = ath9k_reset_tsf,
2477         .ampdu_action       = ath9k_ampdu_action,
2478 };
2479
2480 static struct {
2481         u32 version;
2482         const char * name;
2483 } ath_mac_bb_names[] = {
2484         { AR_SREV_VERSION_5416_PCI,     "5416" },
2485         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2486         { AR_SREV_VERSION_9100,         "9100" },
2487         { AR_SREV_VERSION_9160,         "9160" },
2488         { AR_SREV_VERSION_9280,         "9280" },
2489         { AR_SREV_VERSION_9285,         "9285" }
2490 };
2491
2492 static struct {
2493         u16 version;
2494         const char * name;
2495 } ath_rf_names[] = {
2496         { 0,                            "5133" },
2497         { AR_RAD5133_SREV_MAJOR,        "5133" },
2498         { AR_RAD5122_SREV_MAJOR,        "5122" },
2499         { AR_RAD2133_SREV_MAJOR,        "2133" },
2500         { AR_RAD2122_SREV_MAJOR,        "2122" }
2501 };
2502
2503 /*
2504  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2505  */
2506 static const char *
2507 ath_mac_bb_name(u32 mac_bb_version)
2508 {
2509         int i;
2510
2511         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2512                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2513                         return ath_mac_bb_names[i].name;
2514                 }
2515         }
2516
2517         return "????";
2518 }
2519
2520 /*
2521  * Return the RF name. "????" is returned if the RF is unknown.
2522  */
2523 static const char *
2524 ath_rf_name(u16 rf_version)
2525 {
2526         int i;
2527
2528         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2529                 if (ath_rf_names[i].version == rf_version) {
2530                         return ath_rf_names[i].name;
2531                 }
2532         }
2533
2534         return "????";
2535 }
2536
2537 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2538 {
2539         void __iomem *mem;
2540         struct ath_softc *sc;
2541         struct ieee80211_hw *hw;
2542         u8 csz;
2543         u32 val;
2544         int ret = 0;
2545         struct ath_hal *ah;
2546
2547         if (pci_enable_device(pdev))
2548                 return -EIO;
2549
2550         ret =  pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2551
2552         if (ret) {
2553                 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
2554                 goto bad;
2555         }
2556
2557         ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2558
2559         if (ret) {
2560                 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
2561                         "DMA enable failed\n");
2562                 goto bad;
2563         }
2564
2565         /*
2566          * Cache line size is used to size and align various
2567          * structures used to communicate with the hardware.
2568          */
2569         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2570         if (csz == 0) {
2571                 /*
2572                  * Linux 2.4.18 (at least) writes the cache line size
2573                  * register as a 16-bit wide register which is wrong.
2574                  * We must have this setup properly for rx buffer
2575                  * DMA to work so force a reasonable value here if it
2576                  * comes up zero.
2577                  */
2578                 csz = L1_CACHE_BYTES / sizeof(u32);
2579                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2580         }
2581         /*
2582          * The default setting of latency timer yields poor results,
2583          * set it to the value used by other systems. It may be worth
2584          * tweaking this setting more.
2585          */
2586         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2587
2588         pci_set_master(pdev);
2589
2590         /*
2591          * Disable the RETRY_TIMEOUT register (0x41) to keep
2592          * PCI Tx retries from interfering with C3 CPU state.
2593          */
2594         pci_read_config_dword(pdev, 0x40, &val);
2595         if ((val & 0x0000ff00) != 0)
2596                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2597
2598         ret = pci_request_region(pdev, 0, "ath9k");
2599         if (ret) {
2600                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2601                 ret = -ENODEV;
2602                 goto bad;
2603         }
2604
2605         mem = pci_iomap(pdev, 0, 0);
2606         if (!mem) {
2607                 printk(KERN_ERR "PCI memory map error\n") ;
2608                 ret = -EIO;
2609                 goto bad1;
2610         }
2611
2612         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2613         if (hw == NULL) {
2614                 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2615                 goto bad2;
2616         }
2617
2618         SET_IEEE80211_DEV(hw, &pdev->dev);
2619         pci_set_drvdata(pdev, hw);
2620
2621         sc = hw->priv;
2622         sc->hw = hw;
2623         sc->dev = &pdev->dev;
2624         sc->mem = mem;
2625
2626         if (ath_attach(id->device, sc) != 0) {
2627                 ret = -ENODEV;
2628                 goto bad3;
2629         }
2630
2631         /* setup interrupt service routine */
2632
2633         if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2634                 printk(KERN_ERR "%s: request_irq failed\n",
2635                         wiphy_name(hw->wiphy));
2636                 ret = -EIO;
2637                 goto bad4;
2638         }
2639
2640         ah = sc->sc_ah;
2641         printk(KERN_INFO
2642                "%s: Atheros AR%s MAC/BB Rev:%x "
2643                "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
2644                wiphy_name(hw->wiphy),
2645                ath_mac_bb_name(ah->ah_macVersion),
2646                ah->ah_macRev,
2647                ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2648                ah->ah_phyRev,
2649                (unsigned long)mem, pdev->irq);
2650
2651         return 0;
2652 bad4:
2653         ath_detach(sc);
2654 bad3:
2655         ieee80211_free_hw(hw);
2656 bad2:
2657         pci_iounmap(pdev, mem);
2658 bad1:
2659         pci_release_region(pdev, 0);
2660 bad:
2661         pci_disable_device(pdev);
2662         return ret;
2663 }
2664
2665 static void ath_pci_remove(struct pci_dev *pdev)
2666 {
2667         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2668         struct ath_softc *sc = hw->priv;
2669
2670         ath_detach(sc);
2671         if (pdev->irq)
2672                 free_irq(pdev->irq, sc);
2673         pci_iounmap(pdev, sc->mem);
2674         pci_release_region(pdev, 0);
2675         pci_disable_device(pdev);
2676         ieee80211_free_hw(hw);
2677 }
2678
2679 #ifdef CONFIG_PM
2680
2681 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2682 {
2683         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2684         struct ath_softc *sc = hw->priv;
2685
2686         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2687
2688 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2689         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2690                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2691 #endif
2692
2693         pci_save_state(pdev);
2694         pci_disable_device(pdev);
2695         pci_set_power_state(pdev, PCI_D3hot);
2696
2697         return 0;
2698 }
2699
2700 static int ath_pci_resume(struct pci_dev *pdev)
2701 {
2702         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2703         struct ath_softc *sc = hw->priv;
2704         u32 val;
2705         int err;
2706
2707         err = pci_enable_device(pdev);
2708         if (err)
2709                 return err;
2710         pci_restore_state(pdev);
2711         /*
2712          * Suspend/Resume resets the PCI configuration space, so we have to
2713          * re-disable the RETRY_TIMEOUT register (0x41) to keep
2714          * PCI Tx retries from interfering with C3 CPU state
2715          */
2716         pci_read_config_dword(pdev, 0x40, &val);
2717         if ((val & 0x0000ff00) != 0)
2718                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2719
2720         /* Enable LED */
2721         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2722                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2723         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2724
2725 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2726         /*
2727          * check the h/w rfkill state on resume
2728          * and start the rfkill poll timer
2729          */
2730         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2731                 queue_delayed_work(sc->hw->workqueue,
2732                                    &sc->rf_kill.rfkill_poll, 0);
2733 #endif
2734
2735         return 0;
2736 }
2737
2738 #endif /* CONFIG_PM */
2739
2740 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2741
2742 static struct pci_driver ath_pci_driver = {
2743         .name       = "ath9k",
2744         .id_table   = ath_pci_id_table,
2745         .probe      = ath_pci_probe,
2746         .remove     = ath_pci_remove,
2747 #ifdef CONFIG_PM
2748         .suspend    = ath_pci_suspend,
2749         .resume     = ath_pci_resume,
2750 #endif /* CONFIG_PM */
2751 };
2752
2753 static int __init init_ath_pci(void)
2754 {
2755         int error;
2756
2757         printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2758
2759         /* Register rate control algorithm */
2760         error = ath_rate_control_register();
2761         if (error != 0) {
2762                 printk(KERN_ERR
2763                         "Unable to register rate control algorithm: %d\n",
2764                         error);
2765                 ath_rate_control_unregister();
2766                 return error;
2767         }
2768
2769         if (pci_register_driver(&ath_pci_driver) < 0) {
2770                 printk(KERN_ERR
2771                         "ath_pci: No devices found, driver not installed.\n");
2772                 ath_rate_control_unregister();
2773                 pci_unregister_driver(&ath_pci_driver);
2774                 return -ENODEV;
2775         }
2776
2777         return 0;
2778 }
2779 module_init(init_ath_pci);
2780
2781 static void __exit exit_ath_pci(void)
2782 {
2783         ath_rate_control_unregister();
2784         pci_unregister_driver(&ath_pci_driver);
2785         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2786 }
2787 module_exit(exit_ath_pci);