git.oblomov.eu Git - linux-2.6/blob - arch/sparc64/kernel/smp.c

   1 /* smp.c: Sparc64 SMP support.
   2  *
   3  * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/kernel.h>
   8 #include <linux/sched.h>
   9 #include <linux/mm.h>
  10 #include <linux/pagemap.h>
  11 #include <linux/threads.h>
  12 #include <linux/smp.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/delay.h>
  16 #include <linux/init.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/fs.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/cache.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/profile.h>
  23 #include <linux/lmb.h>
  24
  25 #include <asm/head.h>
  26 #include <asm/ptrace.h>
  27 #include <asm/atomic.h>
  28 #include <asm/tlbflush.h>
  29 #include <asm/mmu_context.h>
  30 #include <asm/cpudata.h>
  31 #include <asm/hvtramp.h>
  32 #include <asm/io.h>
  33 #include <asm/timer.h>
  34
  35 #include <asm/irq.h>
  36 #include <asm/irq_regs.h>
  37 #include <asm/page.h>
  38 #include <asm/pgtable.h>
  39 #include <asm/oplib.h>
  40 #include <asm/uaccess.h>
  41 #include <asm/starfire.h>
  42 #include <asm/tlb.h>
  43 #include <asm/sections.h>
  44 #include <asm/prom.h>
  45 #include <asm/mdesc.h>
  46 #include <asm/ldc.h>
  47 #include <asm/hypervisor.h>
  48
  49 int sparc64_multi_core __read_mostly;
  50
  51 cpumask_t cpu_possible_map __read_mostly = CPU_MASK_NONE;
  52 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
  53 DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE;
  54 cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
  55         { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
  56
  57 EXPORT_SYMBOL(cpu_possible_map);
  58 EXPORT_SYMBOL(cpu_online_map);
  59 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
  60 EXPORT_SYMBOL(cpu_core_map);
  61
  62 static cpumask_t smp_commenced_mask;
  63
  64 void smp_info(struct seq_file *m)
  65 {
  66         int i;
  67
  68         seq_printf(m, "State:\n");
  69         for_each_online_cpu(i)
  70                 seq_printf(m, "CPU%d:\t\tonline\n", i);
  71 }
  72
  73 void smp_bogo(struct seq_file *m)
  74 {
  75         int i;
  76
  77         for_each_online_cpu(i)
  78                 seq_printf(m,
  79                            "Cpu%dClkTck\t: %016lx\n",
  80                            i, cpu_data(i).clock_tick);
  81 }
  82
  83 static __cacheline_aligned_in_smp DEFINE_SPINLOCK(call_lock);
  84
  85 extern void setup_sparc64_timer(void);
  86
  87 static volatile unsigned long callin_flag = 0;
  88
  89 void __cpuinit smp_callin(void)
  90 {
  91         int cpuid = hard_smp_processor_id();
  92
  93         __local_per_cpu_offset = __per_cpu_offset(cpuid);
  94
  95         if (tlb_type == hypervisor)
  96                 sun4v_ktsb_register();
  97
  98         __flush_tlb_all();
  99
 100         setup_sparc64_timer();
 101
 102         if (cheetah_pcache_forced_on)
 103                 cheetah_enable_pcache();
 104
 105         local_irq_enable();
 106
 107         callin_flag = 1;
 108         __asm__ __volatile__("membar #Sync\n\t"
 109                              "flush  %%g6" : : : "memory");
 110
 111         /* Clear this or we will die instantly when we
 112          * schedule back to this idler...
 113          */
 114         current_thread_info()->new_child = 0;
 115
 116         /* Attach to the address space of init_task. */
 117         atomic_inc(&init_mm.mm_count);
 118         current->active_mm = &init_mm;
 119
 120         while (!cpu_isset(cpuid, smp_commenced_mask))
 121                 rmb();
 122
 123         spin_lock(&call_lock);
 124         cpu_set(cpuid, cpu_online_map);
 125         spin_unlock(&call_lock);
 126
 127         /* idle thread is expected to have preempt disabled */
 128         preempt_disable();
 129 }
 130
 131 void cpu_panic(void)
 132 {
 133         printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
 134         panic("SMP bolixed\n");
 135 }
 136
 137 /* This tick register synchronization scheme is taken entirely from
 138  * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
 139  *
 140  * The only change I've made is to rework it so that the master
 141  * initiates the synchonization instead of the slave. -DaveM
 142  */
 143
 144 #define MASTER  0
 145 #define SLAVE   (SMP_CACHE_BYTES/sizeof(unsigned long))
 146
 147 #define NUM_ROUNDS      64      /* magic value */
 148 #define NUM_ITERS       5       /* likewise */
 149
 150 static DEFINE_SPINLOCK(itc_sync_lock);
 151 static unsigned long go[SLAVE + 1];
 152
 153 #define DEBUG_TICK_SYNC 0
 154
 155 static inline long get_delta (long *rt, long *master)
 156 {
 157         unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
 158         unsigned long tcenter, t0, t1, tm;
 159         unsigned long i;
 160
 161         for (i = 0; i < NUM_ITERS; i++) {
 162                 t0 = tick_ops->get_tick();
 163                 go[MASTER] = 1;
 164                 membar_storeload();
 165                 while (!(tm = go[SLAVE]))
 166                         rmb();
 167                 go[SLAVE] = 0;
 168                 wmb();
 169                 t1 = tick_ops->get_tick();
 170
 171                 if (t1 - t0 < best_t1 - best_t0)
 172                         best_t0 = t0, best_t1 = t1, best_tm = tm;
 173         }
 174
 175         *rt = best_t1 - best_t0;
 176         *master = best_tm - best_t0;
 177
 178         /* average best_t0 and best_t1 without overflow: */
 179         tcenter = (best_t0/2 + best_t1/2);
 180         if (best_t0 % 2 + best_t1 % 2 == 2)
 181                 tcenter++;
 182         return tcenter - best_tm;
 183 }
 184
 185 void smp_synchronize_tick_client(void)
 186 {
 187         long i, delta, adj, adjust_latency = 0, done = 0;
 188         unsigned long flags, rt, master_time_stamp, bound;
 189 #if DEBUG_TICK_SYNC
 190         struct {
 191                 long rt;        /* roundtrip time */
 192                 long master;    /* master's timestamp */
 193                 long diff;      /* difference between midpoint and master's timestamp */
 194                 long lat;       /* estimate of itc adjustment latency */
 195         } t[NUM_ROUNDS];
 196 #endif
 197
 198         go[MASTER] = 1;
 199
 200         while (go[MASTER])
 201                 rmb();
 202
 203         local_irq_save(flags);
 204         {
 205                 for (i = 0; i < NUM_ROUNDS; i++) {
 206                         delta = get_delta(&rt, &master_time_stamp);
 207                         if (delta == 0) {
 208                                 done = 1;       /* let's lock on to this... */
 209                                 bound = rt;
 210                         }
 211
 212                         if (!done) {
 213                                 if (i > 0) {
 214                                         adjust_latency += -delta;
 215                                         adj = -delta + adjust_latency/4;
 216                                 } else
 217                                         adj = -delta;
 218
 219                                 tick_ops->add_tick(adj);
 220                         }
 221 #if DEBUG_TICK_SYNC
 222                         t[i].rt = rt;
 223                         t[i].master = master_time_stamp;
 224                         t[i].diff = delta;
 225                         t[i].lat = adjust_latency/4;
 226 #endif
 227                 }
 228         }
 229         local_irq_restore(flags);
 230
 231 #if DEBUG_TICK_SYNC
 232         for (i = 0; i < NUM_ROUNDS; i++)
 233                 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
 234                        t[i].rt, t[i].master, t[i].diff, t[i].lat);
 235 #endif
 236
 237         printk(KERN_INFO "CPU %d: synchronized TICK with master CPU "
 238                "(last diff %ld cycles, maxerr %lu cycles)\n",
 239                smp_processor_id(), delta, rt);
 240 }
 241
 242 static void smp_start_sync_tick_client(int cpu);
 243
 244 static void smp_synchronize_one_tick(int cpu)
 245 {
 246         unsigned long flags, i;
 247
 248         go[MASTER] = 0;
 249
 250         smp_start_sync_tick_client(cpu);
 251
 252         /* wait for client to be ready */
 253         while (!go[MASTER])
 254                 rmb();
 255
 256         /* now let the client proceed into his loop */
 257         go[MASTER] = 0;
 258         membar_storeload();
 259
 260         spin_lock_irqsave(&itc_sync_lock, flags);
 261         {
 262                 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
 263                         while (!go[MASTER])
 264                                 rmb();
 265                         go[MASTER] = 0;
 266                         wmb();
 267                         go[SLAVE] = tick_ops->get_tick();
 268                         membar_storeload();
 269                 }
 270         }
 271         spin_unlock_irqrestore(&itc_sync_lock, flags);
 272 }
 273
 274 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
 275 /* XXX Put this in some common place. XXX */
 276 static unsigned long kimage_addr_to_ra(void *p)
 277 {
 278         unsigned long val = (unsigned long) p;
 279
 280         return kern_base + (val - KERNBASE);
 281 }
 282
 283 static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg)
 284 {
 285         extern unsigned long sparc64_ttable_tl0;
 286         extern unsigned long kern_locked_tte_data;
 287         struct hvtramp_descr *hdesc;
 288         unsigned long trampoline_ra;
 289         struct trap_per_cpu *tb;
 290         u64 tte_vaddr, tte_data;
 291         unsigned long hv_err;
 292         int i;
 293
 294         hdesc = kzalloc(sizeof(*hdesc) +
 295                         (sizeof(struct hvtramp_mapping) *
 296                          num_kernel_image_mappings - 1),
 297                         GFP_KERNEL);
 298         if (!hdesc) {
 299                 printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate "
 300                        "hvtramp_descr.\n");
 301                 return;
 302         }
 303
 304         hdesc->cpu = cpu;
 305         hdesc->num_mappings = num_kernel_image_mappings;
 306
 307         tb = &trap_block[cpu];
 308         tb->hdesc = hdesc;
 309
 310         hdesc->fault_info_va = (unsigned long) &tb->fault_info;
 311         hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
 312
 313         hdesc->thread_reg = thread_reg;
 314
 315         tte_vaddr = (unsigned long) KERNBASE;
 316         tte_data = kern_locked_tte_data;
 317
 318         for (i = 0; i < hdesc->num_mappings; i++) {
 319                 hdesc->maps[i].vaddr = tte_vaddr;
 320                 hdesc->maps[i].tte   = tte_data;
 321                 tte_vaddr += 0x400000;
 322                 tte_data  += 0x400000;
 323         }
 324
 325         trampoline_ra = kimage_addr_to_ra(hv_cpu_startup);
 326
 327         hv_err = sun4v_cpu_start(cpu, trampoline_ra,
 328                                  kimage_addr_to_ra(&sparc64_ttable_tl0),
 329                                  __pa(hdesc));
 330         if (hv_err)
 331                 printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() "
 332                        "gives error %lu\n", hv_err);
 333 }
 334 #endif
 335
 336 extern unsigned long sparc64_cpu_startup;
 337
 338 /* The OBP cpu startup callback truncates the 3rd arg cookie to
 339  * 32-bits (I think) so to be safe we have it read the pointer
 340  * contained here so we work on >4GB machines. -DaveM
 341  */
 342 static struct thread_info *cpu_new_thread = NULL;
 343
 344 static int __devinit smp_boot_one_cpu(unsigned int cpu)
 345 {
 346         struct trap_per_cpu *tb = &trap_block[cpu];
 347         unsigned long entry =
 348                 (unsigned long)(&sparc64_cpu_startup);
 349         unsigned long cookie =
 350                 (unsigned long)(&cpu_new_thread);
 351         struct task_struct *p;
 352         int timeout, ret;
 353
 354         p = fork_idle(cpu);
 355         if (IS_ERR(p))
 356                 return PTR_ERR(p);
 357         callin_flag = 0;
 358         cpu_new_thread = task_thread_info(p);
 359
 360         if (tlb_type == hypervisor) {
 361 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
 362                 if (ldom_domaining_enabled)
 363                         ldom_startcpu_cpuid(cpu,
 364                                             (unsigned long) cpu_new_thread);
 365                 else
 366 #endif
 367                         prom_startcpu_cpuid(cpu, entry, cookie);
 368         } else {
 369                 struct device_node *dp = of_find_node_by_cpuid(cpu);
 370
 371                 prom_startcpu(dp->node, entry, cookie);
 372         }
 373
 374         for (timeout = 0; timeout < 50000; timeout++) {
 375                 if (callin_flag)
 376                         break;
 377                 udelay(100);
 378         }
 379
 380         if (callin_flag) {
 381                 ret = 0;
 382         } else {
 383                 printk("Processor %d is stuck.\n", cpu);
 384                 ret = -ENODEV;
 385         }
 386         cpu_new_thread = NULL;
 387
 388         if (tb->hdesc) {
 389                 kfree(tb->hdesc);
 390                 tb->hdesc = NULL;
 391         }
 392
 393         return ret;
 394 }
 395
 396 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
 397 {
 398         u64 result, target;
 399         int stuck, tmp;
 400
 401         if (this_is_starfire) {
 402                 /* map to real upaid */
 403                 cpu = (((cpu & 0x3c) << 1) |
 404                         ((cpu & 0x40) >> 4) |
 405                         (cpu & 0x3));
 406         }
 407
 408         target = (cpu << 14) | 0x70;
 409 again:
 410         /* Ok, this is the real Spitfire Errata #54.
 411          * One must read back from a UDB internal register
 412          * after writes to the UDB interrupt dispatch, but
 413          * before the membar Sync for that write.
 414          * So we use the high UDB control register (ASI 0x7f,
 415          * ADDR 0x20) for the dummy read. -DaveM
 416          */
 417         tmp = 0x40;
 418         __asm__ __volatile__(
 419         "wrpr   %1, %2, %%pstate\n\t"
 420         "stxa   %4, [%0] %3\n\t"
 421         "stxa   %5, [%0+%8] %3\n\t"
 422         "add    %0, %8, %0\n\t"
 423         "stxa   %6, [%0+%8] %3\n\t"
 424         "membar #Sync\n\t"
 425         "stxa   %%g0, [%7] %3\n\t"
 426         "membar #Sync\n\t"
 427         "mov    0x20, %%g1\n\t"
 428         "ldxa   [%%g1] 0x7f, %%g0\n\t"
 429         "membar #Sync"
 430         : "=r" (tmp)
 431         : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
 432           "r" (data0), "r" (data1), "r" (data2), "r" (target),
 433           "r" (0x10), "0" (tmp)
 434         : "g1");
 435
 436         /* NOTE: PSTATE_IE is still clear. */
 437         stuck = 100000;
 438         do {
 439                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 440                         : "=r" (result)
 441                         : "i" (ASI_INTR_DISPATCH_STAT));
 442                 if (result == 0) {
 443                         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 444                                              : : "r" (pstate));
 445                         return;
 446                 }
 447                 stuck -= 1;
 448                 if (stuck == 0)
 449                         break;
 450         } while (result & 0x1);
 451         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 452                              : : "r" (pstate));
 453         if (stuck == 0) {
 454                 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
 455                        smp_processor_id(), result);
 456         } else {
 457                 udelay(2);
 458                 goto again;
 459         }
 460 }
 461
 462 static void spitfire_xcall_deliver(struct trap_per_cpu *tb, int cnt)
 463 {
 464         u64 *mondo, data0, data1, data2;
 465         u16 *cpu_list;
 466         u64 pstate;
 467         int i;
 468
 469         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 470         cpu_list = __va(tb->cpu_list_pa);
 471         mondo = __va(tb->cpu_mondo_block_pa);
 472         data0 = mondo[0];
 473         data1 = mondo[1];
 474         data2 = mondo[2];
 475         for (i = 0; i < cnt; i++)
 476                 spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]);
 477 }
 478
 479 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
 480  * packet, but we have no use for that.  However we do take advantage of
 481  * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
 482  */
 483 static void cheetah_xcall_deliver(struct trap_per_cpu *tb, int cnt)
 484 {
 485         int nack_busy_id, is_jbus, need_more;
 486         u64 *mondo, pstate, ver, busy_mask;
 487         u16 *cpu_list;
 488
 489         cpu_list = __va(tb->cpu_list_pa);
 490         mondo = __va(tb->cpu_mondo_block_pa);
 491
 492         /* Unfortunately, someone at Sun had the brilliant idea to make the
 493          * busy/nack fields hard-coded by ITID number for this Ultra-III
 494          * derivative processor.
 495          */
 496         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 497         is_jbus = ((ver >> 32) == __JALAPENO_ID ||
 498                    (ver >> 32) == __SERRANO_ID);
 499
 500         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 501
 502 retry:
 503         need_more = 0;
 504         __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
 505                              : : "r" (pstate), "i" (PSTATE_IE));
 506
 507         /* Setup the dispatch data registers. */
 508         __asm__ __volatile__("stxa      %0, [%3] %6\n\t"
 509                              "stxa      %1, [%4] %6\n\t"
 510                              "stxa      %2, [%5] %6\n\t"
 511                              "membar    #Sync\n\t"
 512                              : /* no outputs */
 513                              : "r" (mondo[0]), "r" (mondo[1]), "r" (mondo[2]),
 514                                "r" (0x40), "r" (0x50), "r" (0x60),
 515                                "i" (ASI_INTR_W));
 516
 517         nack_busy_id = 0;
 518         busy_mask = 0;
 519         {
 520                 int i;
 521
 522                 for (i = 0; i < cnt; i++) {
 523                         u64 target, nr;
 524
 525                         nr = cpu_list[i];
 526                         if (nr == 0xffff)
 527                                 continue;
 528
 529                         target = (nr << 14) | 0x70;
 530                         if (is_jbus) {
 531                                 busy_mask |= (0x1UL << (nr * 2));
 532                         } else {
 533                                 target |= (nack_busy_id << 24);
 534                                 busy_mask |= (0x1UL <<
 535                                               (nack_busy_id * 2));
 536                         }
 537                         __asm__ __volatile__(
 538                                 "stxa   %%g0, [%0] %1\n\t"
 539                                 "membar #Sync\n\t"
 540                                 : /* no outputs */
 541                                 : "r" (target), "i" (ASI_INTR_W));
 542                         nack_busy_id++;
 543                         if (nack_busy_id == 32) {
 544                                 need_more = 1;
 545                                 break;
 546                         }
 547                 }
 548         }
 549
 550         /* Now, poll for completion. */
 551         {
 552                 u64 dispatch_stat, nack_mask;
 553                 long stuck;
 554
 555                 stuck = 100000 * nack_busy_id;
 556                 nack_mask = busy_mask << 1;
 557                 do {
 558                         __asm__ __volatile__("ldxa      [%%g0] %1, %0"
 559                                              : "=r" (dispatch_stat)
 560                                              : "i" (ASI_INTR_DISPATCH_STAT));
 561                         if (!(dispatch_stat & (busy_mask | nack_mask))) {
 562                                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 563                                                      : : "r" (pstate));
 564                                 if (unlikely(need_more)) {
 565                                         int i, this_cnt = 0;
 566                                         for (i = 0; i < cnt; i++) {
 567                                                 if (cpu_list[i] == 0xffff)
 568                                                         continue;
 569                                                 cpu_list[i] = 0xffff;
 570                                                 this_cnt++;
 571                                                 if (this_cnt == 32)
 572                                                         break;
 573                                         }
 574                                         goto retry;
 575                                 }
 576                                 return;
 577                         }
 578                         if (!--stuck)
 579                                 break;
 580                 } while (dispatch_stat & busy_mask);
 581
 582                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 583                                      : : "r" (pstate));
 584
 585                 if (dispatch_stat & busy_mask) {
 586                         /* Busy bits will not clear, continue instead
 587                          * of freezing up on this cpu.
 588                          */
 589                         printk("CPU[%d]: mondo stuckage result[%016lx]\n",
 590                                smp_processor_id(), dispatch_stat);
 591                 } else {
 592                         int i, this_busy_nack = 0;
 593
 594                         /* Delay some random time with interrupts enabled
 595                          * to prevent deadlock.
 596                          */
 597                         udelay(2 * nack_busy_id);
 598
 599                         /* Clear out the mask bits for cpus which did not
 600                          * NACK us.
 601                          */
 602                         for (i = 0; i < cnt; i++) {
 603                                 u64 check_mask, nr;
 604
 605                                 nr = cpu_list[i];
 606                                 if (nr == 0xffff)
 607                                         continue;
 608
 609                                 if (is_jbus)
 610                                         check_mask = (0x2UL << (2*nr));
 611                                 else
 612                                         check_mask = (0x2UL <<
 613                                                       this_busy_nack);
 614                                 if ((dispatch_stat & check_mask) == 0)
 615                                         cpu_list[i] = 0xffff;
 616                                 this_busy_nack += 2;
 617                                 if (this_busy_nack == 64)
 618                                         break;
 619                         }
 620
 621                         goto retry;
 622                 }
 623         }
 624 }
 625
 626 /* Multi-cpu list version.  */
 627 static void hypervisor_xcall_deliver(struct trap_per_cpu *tb, int cnt)
 628 {
 629         int retries, this_cpu, prev_sent, i, saw_cpu_error;
 630         unsigned long status;
 631         u16 *cpu_list;
 632
 633         this_cpu = smp_processor_id();
 634
 635         cpu_list = __va(tb->cpu_list_pa);
 636
 637         saw_cpu_error = 0;
 638         retries = 0;
 639         prev_sent = 0;
 640         do {
 641                 int forward_progress, n_sent;
 642
 643                 status = sun4v_cpu_mondo_send(cnt,
 644                                               tb->cpu_list_pa,
 645                                               tb->cpu_mondo_block_pa);
 646
 647                 /* HV_EOK means all cpus received the xcall, we're done.  */
 648                 if (likely(status == HV_EOK))
 649                         break;
 650
 651                 /* First, see if we made any forward progress.
 652                  *
 653                  * The hypervisor indicates successful sends by setting
 654                  * cpu list entries to the value 0xffff.
 655                  */
 656                 n_sent = 0;
 657                 for (i = 0; i < cnt; i++) {
 658                         if (likely(cpu_list[i] == 0xffff))
 659                                 n_sent++;
 660                 }
 661
 662                 forward_progress = 0;
 663                 if (n_sent > prev_sent)
 664                         forward_progress = 1;
 665
 666                 prev_sent = n_sent;
 667
 668                 /* If we get a HV_ECPUERROR, then one or more of the cpus
 669                  * in the list are in error state.  Use the cpu_state()
 670                  * hypervisor call to find out which cpus are in error state.
 671                  */
 672                 if (unlikely(status == HV_ECPUERROR)) {
 673                         for (i = 0; i < cnt; i++) {
 674                                 long err;
 675                                 u16 cpu;
 676
 677                                 cpu = cpu_list[i];
 678                                 if (cpu == 0xffff)
 679                                         continue;
 680
 681                                 err = sun4v_cpu_state(cpu);
 682                                 if (err == HV_CPU_STATE_ERROR) {
 683                                         saw_cpu_error = (cpu + 1);
 684                                         cpu_list[i] = 0xffff;
 685                                 }
 686                         }
 687                 } else if (unlikely(status != HV_EWOULDBLOCK))
 688                         goto fatal_mondo_error;
 689
 690                 /* Don't bother rewriting the CPU list, just leave the
 691                  * 0xffff and non-0xffff entries in there and the
 692                  * hypervisor will do the right thing.
 693                  *
 694                  * Only advance timeout state if we didn't make any
 695                  * forward progress.
 696                  */
 697                 if (unlikely(!forward_progress)) {
 698                         if (unlikely(++retries > 10000))
 699                                 goto fatal_mondo_timeout;
 700
 701                         /* Delay a little bit to let other cpus catch up
 702                          * on their cpu mondo queue work.
 703                          */
 704                         udelay(2 * cnt);
 705                 }
 706         } while (1);
 707
 708         if (unlikely(saw_cpu_error))
 709                 goto fatal_mondo_cpu_error;
 710
 711         return;
 712
 713 fatal_mondo_cpu_error:
 714         printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
 715                "(including %d) were in error state\n",
 716                this_cpu, saw_cpu_error - 1);
 717         return;
 718
 719 fatal_mondo_timeout:
 720         printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
 721                " progress after %d retries.\n",
 722                this_cpu, retries);
 723         goto dump_cpu_list_and_out;
 724
 725 fatal_mondo_error:
 726         printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
 727                this_cpu, status);
 728         printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
 729                "mondo_block_pa(%lx)\n",
 730                this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
 731
 732 dump_cpu_list_and_out:
 733         printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
 734         for (i = 0; i < cnt; i++)
 735                 printk("%u ", cpu_list[i]);
 736         printk("]\n");
 737 }
 738
 739 static void (*xcall_deliver_impl)(struct trap_per_cpu *, int);
 740
 741 static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
 742 {
 743         struct trap_per_cpu *tb;
 744         int this_cpu, i, cnt;
 745         unsigned long flags;
 746         u16 *cpu_list;
 747         u64 *mondo;
 748
 749         /* We have to do this whole thing with interrupts fully disabled.
 750          * Otherwise if we send an xcall from interrupt context it will
 751          * corrupt both our mondo block and cpu list state.
 752          *
 753          * One consequence of this is that we cannot use timeout mechanisms
 754          * that depend upon interrupts being delivered locally.  So, for
 755          * example, we cannot sample jiffies and expect it to advance.
 756          *
 757          * Fortunately, udelay() uses %stick/%tick so we can use that.
 758          */
 759         local_irq_save(flags);
 760
 761         this_cpu = smp_processor_id();
 762         tb = &trap_block[this_cpu];
 763
 764         mondo = __va(tb->cpu_mondo_block_pa);
 765         mondo[0] = data0;
 766         mondo[1] = data1;
 767         mondo[2] = data2;
 768         wmb();
 769
 770         cpu_list = __va(tb->cpu_list_pa);
 771
 772         /* Setup the initial cpu list.  */
 773         cnt = 0;
 774         for_each_cpu_mask_nr(i, *mask) {
 775                 if (i == this_cpu || !cpu_online(i))
 776                         continue;
 777                 cpu_list[cnt++] = i;
 778         }
 779
 780         if (cnt)
 781                 xcall_deliver_impl(tb, cnt);
 782
 783         local_irq_restore(flags);
 784 }
 785
 786 /* Send cross call to all processors mentioned in MASK_P
 787  * except self.  Really, there are only two cases currently,
 788  * "&cpu_online_map" and "&mm->cpu_vm_mask".
 789  */
 790 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask)
 791 {
 792         u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
 793
 794         xcall_deliver(data0, data1, data2, mask);
 795 }
 796
 797 /* Send cross call to all processors except self. */
 798 static void smp_cross_call(unsigned long *func, u32 ctx, u64 data1, u64 data2)
 799 {
 800         smp_cross_call_masked(func, ctx, data1, data2, &cpu_online_map);
 801 }
 802
 803 extern unsigned long xcall_sync_tick;
 804
 805 static void smp_start_sync_tick_client(int cpu)
 806 {
 807         xcall_deliver((u64) &xcall_sync_tick, 0, 0,
 808                       &cpumask_of_cpu(cpu));
 809 }
 810
 811 extern unsigned long xcall_call_function;
 812
 813 void arch_send_call_function_ipi(cpumask_t mask)
 814 {
 815         xcall_deliver((u64) &xcall_call_function, 0, 0, &mask);
 816 }
 817
 818 extern unsigned long xcall_call_function_single;
 819
 820 void arch_send_call_function_single_ipi(int cpu)
 821 {
 822         xcall_deliver((u64) &xcall_call_function_single, 0, 0,
 823                       &cpumask_of_cpu(cpu));
 824 }
 825
 826 void smp_call_function_client(int irq, struct pt_regs *regs)
 827 {
 828         clear_softint(1 << irq);
 829         generic_smp_call_function_interrupt();
 830 }
 831
 832 void smp_call_function_single_client(int irq, struct pt_regs *regs)
 833 {
 834         clear_softint(1 << irq);
 835         generic_smp_call_function_single_interrupt();
 836 }
 837
 838 static void tsb_sync(void *info)
 839 {
 840         struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
 841         struct mm_struct *mm = info;
 842
 843         /* It is not valid to test "currrent->active_mm == mm" here.
 844          *
 845          * The value of "current" is not changed atomically with
 846          * switch_mm().  But that's OK, we just need to check the
 847          * current cpu's trap block PGD physical address.
 848          */
 849         if (tp->pgd_paddr == __pa(mm->pgd))
 850                 tsb_context_switch(mm);
 851 }
 852
 853 void smp_tsb_sync(struct mm_struct *mm)
 854 {
 855         smp_call_function_mask(mm->cpu_vm_mask, tsb_sync, mm, 1);
 856 }
 857
 858 extern unsigned long xcall_flush_tlb_mm;
 859 extern unsigned long xcall_flush_tlb_pending;
 860 extern unsigned long xcall_flush_tlb_kernel_range;
 861 extern unsigned long xcall_fetch_glob_regs;
 862 extern unsigned long xcall_receive_signal;
 863 extern unsigned long xcall_new_mmu_context_version;
 864 #ifdef CONFIG_KGDB
 865 extern unsigned long xcall_kgdb_capture;
 866 #endif
 867
 868 #ifdef DCACHE_ALIASING_POSSIBLE
 869 extern unsigned long xcall_flush_dcache_page_cheetah;
 870 #endif
 871 extern unsigned long xcall_flush_dcache_page_spitfire;
 872
 873 #ifdef CONFIG_DEBUG_DCFLUSH
 874 extern atomic_t dcpage_flushes;
 875 extern atomic_t dcpage_flushes_xcall;
 876 #endif
 877
 878 static inline void __local_flush_dcache_page(struct page *page)
 879 {
 880 #ifdef DCACHE_ALIASING_POSSIBLE
 881         __flush_dcache_page(page_address(page),
 882                             ((tlb_type == spitfire) &&
 883                              page_mapping(page) != NULL));
 884 #else
 885         if (page_mapping(page) != NULL &&
 886             tlb_type == spitfire)
 887                 __flush_icache_page(__pa(page_address(page)));
 888 #endif
 889 }
 890
 891 void smp_flush_dcache_page_impl(struct page *page, int cpu)
 892 {
 893         int this_cpu;
 894
 895         if (tlb_type == hypervisor)
 896                 return;
 897
 898 #ifdef CONFIG_DEBUG_DCFLUSH
 899         atomic_inc(&dcpage_flushes);
 900 #endif
 901
 902         this_cpu = get_cpu();
 903
 904         if (cpu == this_cpu) {
 905                 __local_flush_dcache_page(page);
 906         } else if (cpu_online(cpu)) {
 907                 void *pg_addr = page_address(page);
 908                 u64 data0 = 0;
 909
 910                 if (tlb_type == spitfire) {
 911                         data0 = ((u64)&xcall_flush_dcache_page_spitfire);
 912                         if (page_mapping(page) != NULL)
 913                                 data0 |= ((u64)1 << 32);
 914                 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 915 #ifdef DCACHE_ALIASING_POSSIBLE
 916                         data0 = ((u64)&xcall_flush_dcache_page_cheetah);
 917 #endif
 918                 }
 919                 if (data0) {
 920                         xcall_deliver(data0, __pa(pg_addr),
 921                                       (u64) pg_addr, &cpumask_of_cpu(cpu));
 922 #ifdef CONFIG_DEBUG_DCFLUSH
 923                         atomic_inc(&dcpage_flushes_xcall);
 924 #endif
 925                 }
 926         }
 927
 928         put_cpu();
 929 }
 930
 931 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
 932 {
 933         void *pg_addr;
 934         int this_cpu;
 935         u64 data0;
 936
 937         if (tlb_type == hypervisor)
 938                 return;
 939
 940         this_cpu = get_cpu();
 941
 942 #ifdef CONFIG_DEBUG_DCFLUSH
 943         atomic_inc(&dcpage_flushes);
 944 #endif
 945         data0 = 0;
 946         pg_addr = page_address(page);
 947         if (tlb_type == spitfire) {
 948                 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
 949                 if (page_mapping(page) != NULL)
 950                         data0 |= ((u64)1 << 32);
 951         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 952 #ifdef DCACHE_ALIASING_POSSIBLE
 953                 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
 954 #endif
 955         }
 956         if (data0) {
 957                 xcall_deliver(data0, __pa(pg_addr),
 958                               (u64) pg_addr, &cpu_online_map);
 959 #ifdef CONFIG_DEBUG_DCFLUSH
 960                 atomic_inc(&dcpage_flushes_xcall);
 961 #endif
 962         }
 963         __local_flush_dcache_page(page);
 964
 965         put_cpu();
 966 }
 967
 968 void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
 969 {
 970         struct mm_struct *mm;
 971         unsigned long flags;
 972
 973         clear_softint(1 << irq);
 974
 975         /* See if we need to allocate a new TLB context because
 976          * the version of the one we are using is now out of date.
 977          */
 978         mm = current->active_mm;
 979         if (unlikely(!mm || (mm == &init_mm)))
 980                 return;
 981
 982         spin_lock_irqsave(&mm->context.lock, flags);
 983
 984         if (unlikely(!CTX_VALID(mm->context)))
 985                 get_new_mmu_context(mm);
 986
 987         spin_unlock_irqrestore(&mm->context.lock, flags);
 988
 989         load_secondary_context(mm);
 990         __flush_tlb_mm(CTX_HWBITS(mm->context),
 991                        SECONDARY_CONTEXT);
 992 }
 993
 994 void smp_new_mmu_context_version(void)
 995 {
 996         smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
 997 }
 998
 999 #ifdef CONFIG_KGDB
1000 void kgdb_roundup_cpus(unsigned long flags)
1001 {
1002         smp_cross_call(&xcall_kgdb_capture, 0, 0, 0);
1003 }
1004 #endif
1005
1006 void smp_fetch_global_regs(void)
1007 {
1008         smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0);
1009 }
1010
1011 /* We know that the window frames of the user have been flushed
1012  * to the stack before we get here because all callers of us
1013  * are flush_tlb_*() routines, and these run after flush_cache_*()
1014  * which performs the flushw.
1015  *
1016  * The SMP TLB coherency scheme we use works as follows:
1017  *
1018  * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1019  *    space has (potentially) executed on, this is the heuristic
1020  *    we use to avoid doing cross calls.
1021  *
1022  *    Also, for flushing from kswapd and also for clones, we
1023  *    use cpu_vm_mask as the list of cpus to make run the TLB.
1024  *
1025  * 2) TLB context numbers are shared globally across all processors
1026  *    in the system, this allows us to play several games to avoid
1027  *    cross calls.
1028  *
1029  *    One invariant is that when a cpu switches to a process, and
1030  *    that processes tsk->active_mm->cpu_vm_mask does not have the
1031  *    current cpu's bit set, that tlb context is flushed locally.
1032  *
1033  *    If the address space is non-shared (ie. mm->count == 1) we avoid
1034  *    cross calls when we want to flush the currently running process's
1035  *    tlb state.  This is done by clearing all cpu bits except the current
1036  *    processor's in current->active_mm->cpu_vm_mask and performing the
1037  *    flush locally only.  This will force any subsequent cpus which run
1038  *    this task to flush the context from the local tlb if the process
1039  *    migrates to another cpu (again).
1040  *
1041  * 3) For shared address spaces (threads) and swapping we bite the
1042  *    bullet for most cases and perform the cross call (but only to
1043  *    the cpus listed in cpu_vm_mask).
1044  *
1045  *    The performance gain from "optimizing" away the cross call for threads is
1046  *    questionable (in theory the big win for threads is the massive sharing of
1047  *    address space state across processors).
1048  */
1049
1050 /* This currently is only used by the hugetlb arch pre-fault
1051  * hook on UltraSPARC-III+ and later when changing the pagesize
1052  * bits of the context register for an address space.
1053  */
1054 void smp_flush_tlb_mm(struct mm_struct *mm)
1055 {
1056         u32 ctx = CTX_HWBITS(mm->context);
1057         int cpu = get_cpu();
1058
1059         if (atomic_read(&mm->mm_users) == 1) {
1060                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1061                 goto local_flush_and_out;
1062         }
1063
1064         smp_cross_call_masked(&xcall_flush_tlb_mm,
1065                               ctx, 0, 0,
1066                               &mm->cpu_vm_mask);
1067
1068 local_flush_and_out:
1069         __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1070
1071         put_cpu();
1072 }
1073
1074 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1075 {
1076         u32 ctx = CTX_HWBITS(mm->context);
1077         int cpu = get_cpu();
1078
1079         if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
1080                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1081         else
1082                 smp_cross_call_masked(&xcall_flush_tlb_pending,
1083                                       ctx, nr, (unsigned long) vaddrs,
1084                                       &mm->cpu_vm_mask);
1085
1086         __flush_tlb_pending(ctx, nr, vaddrs);
1087
1088         put_cpu();
1089 }
1090
1091 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1092 {
1093         start &= PAGE_MASK;
1094         end    = PAGE_ALIGN(end);
1095         if (start != end) {
1096                 smp_cross_call(&xcall_flush_tlb_kernel_range,
1097                                0, start, end);
1098
1099                 __flush_tlb_kernel_range(start, end);
1100         }
1101 }
1102
1103 /* CPU capture. */
1104 /* #define CAPTURE_DEBUG */
1105 extern unsigned long xcall_capture;
1106
1107 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1108 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1109 static unsigned long penguins_are_doing_time;
1110
1111 void smp_capture(void)
1112 {
1113         int result = atomic_add_ret(1, &smp_capture_depth);
1114
1115         if (result == 1) {
1116                 int ncpus = num_online_cpus();
1117
1118 #ifdef CAPTURE_DEBUG
1119                 printk("CPU[%d]: Sending penguins to jail...",
1120                        smp_processor_id());
1121 #endif
1122                 penguins_are_doing_time = 1;
1123                 membar_storestore_loadstore();
1124                 atomic_inc(&smp_capture_registry);
1125                 smp_cross_call(&xcall_capture, 0, 0, 0);
1126                 while (atomic_read(&smp_capture_registry) != ncpus)
1127                         rmb();
1128 #ifdef CAPTURE_DEBUG
1129                 printk("done\n");
1130 #endif
1131         }
1132 }
1133
1134 void smp_release(void)
1135 {
1136         if (atomic_dec_and_test(&smp_capture_depth)) {
1137 #ifdef CAPTURE_DEBUG
1138                 printk("CPU[%d]: Giving pardon to "
1139                        "imprisoned penguins\n",
1140                        smp_processor_id());
1141 #endif
1142                 penguins_are_doing_time = 0;
1143                 membar_storeload_storestore();
1144                 atomic_dec(&smp_capture_registry);
1145         }
1146 }
1147
1148 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
1149  * can service tlb flush xcalls...
1150  */
1151 extern void prom_world(int);
1152
1153 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
1154 {
1155         clear_softint(1 << irq);
1156
1157         preempt_disable();
1158
1159         __asm__ __volatile__("flushw");
1160         prom_world(1);
1161         atomic_inc(&smp_capture_registry);
1162         membar_storeload_storestore();
1163         while (penguins_are_doing_time)
1164                 rmb();
1165         atomic_dec(&smp_capture_registry);
1166         prom_world(0);
1167
1168         preempt_enable();
1169 }
1170
1171 /* /proc/profile writes can call this, don't __init it please. */
1172 int setup_profiling_timer(unsigned int multiplier)
1173 {
1174         return -EINVAL;
1175 }
1176
1177 void __init smp_prepare_cpus(unsigned int max_cpus)
1178 {
1179 }
1180
1181 void __devinit smp_prepare_boot_cpu(void)
1182 {
1183 }
1184
1185 void __init smp_setup_processor_id(void)
1186 {
1187         if (tlb_type == spitfire)
1188                 xcall_deliver_impl = spitfire_xcall_deliver;
1189         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
1190                 xcall_deliver_impl = cheetah_xcall_deliver;
1191         else
1192                 xcall_deliver_impl = hypervisor_xcall_deliver;
1193 }
1194
1195 void __devinit smp_fill_in_sib_core_maps(void)
1196 {
1197         unsigned int i;
1198
1199         for_each_present_cpu(i) {
1200                 unsigned int j;
1201
1202                 cpus_clear(cpu_core_map[i]);
1203                 if (cpu_data(i).core_id == 0) {
1204                         cpu_set(i, cpu_core_map[i]);
1205                         continue;
1206                 }
1207
1208                 for_each_present_cpu(j) {
1209                         if (cpu_data(i).core_id ==
1210                             cpu_data(j).core_id)
1211                                 cpu_set(j, cpu_core_map[i]);
1212                 }
1213         }
1214
1215         for_each_present_cpu(i) {
1216                 unsigned int j;
1217
1218                 cpus_clear(per_cpu(cpu_sibling_map, i));
1219                 if (cpu_data(i).proc_id == -1) {
1220                         cpu_set(i, per_cpu(cpu_sibling_map, i));
1221                         continue;
1222                 }
1223
1224                 for_each_present_cpu(j) {
1225                         if (cpu_data(i).proc_id ==
1226                             cpu_data(j).proc_id)
1227                                 cpu_set(j, per_cpu(cpu_sibling_map, i));
1228                 }
1229         }
1230 }
1231
1232 int __cpuinit __cpu_up(unsigned int cpu)
1233 {
1234         int ret = smp_boot_one_cpu(cpu);
1235
1236         if (!ret) {
1237                 cpu_set(cpu, smp_commenced_mask);
1238                 while (!cpu_isset(cpu, cpu_online_map))
1239                         mb();
1240                 if (!cpu_isset(cpu, cpu_online_map)) {
1241                         ret = -ENODEV;
1242                 } else {
1243                         /* On SUN4V, writes to %tick and %stick are
1244                          * not allowed.
1245                          */
1246                         if (tlb_type != hypervisor)
1247                                 smp_synchronize_one_tick(cpu);
1248                 }
1249         }
1250         return ret;
1251 }
1252
1253 #ifdef CONFIG_HOTPLUG_CPU
1254 void cpu_play_dead(void)
1255 {
1256         int cpu = smp_processor_id();
1257         unsigned long pstate;
1258
1259         idle_task_exit();
1260
1261         if (tlb_type == hypervisor) {
1262                 struct trap_per_cpu *tb = &trap_block[cpu];
1263
1264                 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO,
1265                                 tb->cpu_mondo_pa, 0);
1266                 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO,
1267                                 tb->dev_mondo_pa, 0);
1268                 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR,
1269                                 tb->resum_mondo_pa, 0);
1270                 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR,
1271                                 tb->nonresum_mondo_pa, 0);
1272         }
1273
1274         cpu_clear(cpu, smp_commenced_mask);
1275         membar_safe("#Sync");
1276
1277         local_irq_disable();
1278
1279         __asm__ __volatile__(
1280                 "rdpr   %%pstate, %0\n\t"
1281                 "wrpr   %0, %1, %%pstate"
1282                 : "=r" (pstate)
1283                 : "i" (PSTATE_IE));
1284
1285         while (1)
1286                 barrier();
1287 }
1288
1289 int __cpu_disable(void)
1290 {
1291         int cpu = smp_processor_id();
1292         cpuinfo_sparc *c;
1293         int i;
1294
1295         for_each_cpu_mask(i, cpu_core_map[cpu])
1296                 cpu_clear(cpu, cpu_core_map[i]);
1297         cpus_clear(cpu_core_map[cpu]);
1298
1299         for_each_cpu_mask(i, per_cpu(cpu_sibling_map, cpu))
1300                 cpu_clear(cpu, per_cpu(cpu_sibling_map, i));
1301         cpus_clear(per_cpu(cpu_sibling_map, cpu));
1302
1303         c = &cpu_data(cpu);
1304
1305         c->core_id = 0;
1306         c->proc_id = -1;
1307
1308         spin_lock(&call_lock);
1309         cpu_clear(cpu, cpu_online_map);
1310         spin_unlock(&call_lock);
1311
1312         smp_wmb();
1313
1314         /* Make sure no interrupts point to this cpu.  */
1315         fixup_irqs();
1316
1317         local_irq_enable();
1318         mdelay(1);
1319         local_irq_disable();
1320
1321         return 0;
1322 }
1323
1324 void __cpu_die(unsigned int cpu)
1325 {
1326         int i;
1327
1328         for (i = 0; i < 100; i++) {
1329                 smp_rmb();
1330                 if (!cpu_isset(cpu, smp_commenced_mask))
1331                         break;
1332                 msleep(100);
1333         }
1334         if (cpu_isset(cpu, smp_commenced_mask)) {
1335                 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1336         } else {
1337 #if defined(CONFIG_SUN_LDOMS)
1338                 unsigned long hv_err;
1339                 int limit = 100;
1340
1341                 do {
1342                         hv_err = sun4v_cpu_stop(cpu);
1343                         if (hv_err == HV_EOK) {
1344                                 cpu_clear(cpu, cpu_present_map);
1345                                 break;
1346                         }
1347                 } while (--limit > 0);
1348                 if (limit <= 0) {
1349                         printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n",
1350                                hv_err);
1351                 }
1352 #endif
1353         }
1354 }
1355 #endif
1356
1357 void __init smp_cpus_done(unsigned int max_cpus)
1358 {
1359 }
1360
1361 void smp_send_reschedule(int cpu)
1362 {
1363         xcall_deliver((u64) &xcall_receive_signal, 0, 0,
1364                       &cpumask_of_cpu(cpu));
1365 }
1366
1367 void smp_receive_signal_client(int irq, struct pt_regs *regs)
1368 {
1369         clear_softint(1 << irq);
1370 }
1371
1372 /* This is a nop because we capture all other cpus
1373  * anyways when making the PROM active.
1374  */
1375 void smp_send_stop(void)
1376 {
1377 }
1378
1379 unsigned long __per_cpu_base __read_mostly;
1380 unsigned long __per_cpu_shift __read_mostly;
1381
1382 EXPORT_SYMBOL(__per_cpu_base);
1383 EXPORT_SYMBOL(__per_cpu_shift);
1384
1385 void __init real_setup_per_cpu_areas(void)
1386 {
1387         unsigned long paddr, goal, size, i;
1388         char *ptr;
1389
1390         /* Copy section for each CPU (we discard the original) */
1391         goal = PERCPU_ENOUGH_ROOM;
1392
1393         __per_cpu_shift = PAGE_SHIFT;
1394         for (size = PAGE_SIZE; size < goal; size <<= 1UL)
1395                 __per_cpu_shift++;
1396
1397         paddr = lmb_alloc(size * NR_CPUS, PAGE_SIZE);
1398         if (!paddr) {
1399                 prom_printf("Cannot allocate per-cpu memory.\n");
1400                 prom_halt();
1401         }
1402
1403         ptr = __va(paddr);
1404         __per_cpu_base = ptr - __per_cpu_start;
1405
1406         for (i = 0; i < NR_CPUS; i++, ptr += size)
1407                 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1408
1409         /* Setup %g5 for the boot cpu.  */
1410         __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());
1411 }