Merge commit '900cfa46191a7d87cf1891924cb90499287fd235'; branches 'timers/nohz',...
[linux-2.6] / arch / powerpc / boot / dts / mpc836x_mds.dts
1 /*
2  * MPC8360E EMDS Device Tree Source
3  *
4  * Copyright 2006 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12
13 /*
14 /memreserve/    00000000 1000000;
15 */
16
17 /dts-v1/;
18
19 / {
20         model = "MPC8360MDS";
21         compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
22         #address-cells = <1>;
23         #size-cells = <1>;
24
25         aliases {
26                 ethernet0 = &enet0;
27                 ethernet1 = &enet1;
28                 serial0 = &serial0;
29                 serial1 = &serial1;
30                 pci0 = &pci0;
31         };
32
33         cpus {
34                 #address-cells = <1>;
35                 #size-cells = <0>;
36
37                 PowerPC,8360@0 {
38                         device_type = "cpu";
39                         reg = <0x0>;
40                         d-cache-line-size = <32>;       // 32 bytes
41                         i-cache-line-size = <32>;       // 32 bytes
42                         d-cache-size = <32768>;         // L1, 32K
43                         i-cache-size = <32768>;         // L1, 32K
44                         timebase-frequency = <66000000>;
45                         bus-frequency = <264000000>;
46                         clock-frequency = <528000000>;
47                 };
48         };
49
50         memory {
51                 device_type = "memory";
52                 reg = <0x00000000 0x10000000>;
53         };
54
55         bcsr@f8000000 {
56                 device_type = "board-control";
57                 reg = <0xf8000000 0x8000>;
58         };
59
60         soc8360@e0000000 {
61                 #address-cells = <1>;
62                 #size-cells = <1>;
63                 device_type = "soc";
64                 ranges = <0x0 0xe0000000 0x00100000>;
65                 reg = <0xe0000000 0x00000200>;
66                 bus-frequency = <264000000>;
67
68                 wdt@200 {
69                         device_type = "watchdog";
70                         compatible = "mpc83xx_wdt";
71                         reg = <0x200 0x100>;
72                 };
73
74                 i2c@3000 {
75                         #address-cells = <1>;
76                         #size-cells = <0>;
77                         cell-index = <0>;
78                         compatible = "fsl-i2c";
79                         reg = <0x3000 0x100>;
80                         interrupts = <14 0x8>;
81                         interrupt-parent = <&ipic>;
82                         dfsrr;
83
84                         rtc@68 {
85                                 compatible = "dallas,ds1374";
86                                 reg = <0x68>;
87                         };
88                 };
89
90                 i2c@3100 {
91                         #address-cells = <1>;
92                         #size-cells = <0>;
93                         cell-index = <1>;
94                         compatible = "fsl-i2c";
95                         reg = <0x3100 0x100>;
96                         interrupts = <15 0x8>;
97                         interrupt-parent = <&ipic>;
98                         dfsrr;
99                 };
100
101                 serial0: serial@4500 {
102                         cell-index = <0>;
103                         device_type = "serial";
104                         compatible = "ns16550";
105                         reg = <0x4500 0x100>;
106                         clock-frequency = <264000000>;
107                         interrupts = <9 0x8>;
108                         interrupt-parent = <&ipic>;
109                 };
110
111                 serial1: serial@4600 {
112                         cell-index = <1>;
113                         device_type = "serial";
114                         compatible = "ns16550";
115                         reg = <0x4600 0x100>;
116                         clock-frequency = <264000000>;
117                         interrupts = <10 0x8>;
118                         interrupt-parent = <&ipic>;
119                 };
120
121                 crypto@30000 {
122                         device_type = "crypto";
123                         model = "SEC2";
124                         compatible = "talitos";
125                         reg = <0x30000 0x10000>;
126                         interrupts = <11 0x8>;
127                         interrupt-parent = <&ipic>;
128                         num-channels = <4>;
129                         channel-fifo-len = <24>;
130                         exec-units-mask = <0x0000007e>;
131                         /* desc mask is for rev1.x, we need runtime fixup for >=2.x */
132                         descriptor-types-mask = <0x01010ebf>;
133                 };
134
135                 ipic: pic@700 {
136                         interrupt-controller;
137                         #address-cells = <0>;
138                         #interrupt-cells = <2>;
139                         reg = <0x700 0x100>;
140                         device_type = "ipic";
141                 };
142
143                 par_io@1400 {
144                         reg = <0x1400 0x100>;
145                         device_type = "par_io";
146                         num-ports = <7>;
147
148                         pio1: ucc_pin@01 {
149                                 pio-map = <
150                         /* port  pin  dir  open_drain  assignment  has_irq */
151                                         0  3  1  0  1  0        /* TxD0 */
152                                         0  4  1  0  1  0        /* TxD1 */
153                                         0  5  1  0  1  0        /* TxD2 */
154                                         0  6  1  0  1  0        /* TxD3 */
155                                         1  6  1  0  3  0        /* TxD4 */
156                                         1  7  1  0  1  0        /* TxD5 */
157                                         1  9  1  0  2  0        /* TxD6 */
158                                         1  10 1  0  2  0        /* TxD7 */
159                                         0  9  2  0  1  0        /* RxD0 */
160                                         0  10 2  0  1  0        /* RxD1 */
161                                         0  11 2  0  1  0        /* RxD2 */
162                                         0  12 2  0  1  0        /* RxD3 */
163                                         0  13 2  0  1  0        /* RxD4 */
164                                         1  1  2  0  2  0        /* RxD5 */
165                                         1  0  2  0  2  0        /* RxD6 */
166                                         1  4  2  0  2  0        /* RxD7 */
167                                         0  7  1  0  1  0        /* TX_EN */
168                                         0  8  1  0  1  0        /* TX_ER */
169                                         0  15 2  0  1  0        /* RX_DV */
170                                         0  16 2  0  1  0        /* RX_ER */
171                                         0  0  2  0  1  0        /* RX_CLK */
172                                         2  9  1  0  3  0        /* GTX_CLK - CLK10 */
173                                         2  8  2  0  1  0>;      /* GTX125 - CLK9 */
174                         };
175                         pio2: ucc_pin@02 {
176                                 pio-map = <
177                         /* port  pin  dir  open_drain  assignment  has_irq */
178                                         0  17 1  0  1  0   /* TxD0 */
179                                         0  18 1  0  1  0   /* TxD1 */
180                                         0  19 1  0  1  0   /* TxD2 */
181                                         0  20 1  0  1  0   /* TxD3 */
182                                         1  2  1  0  1  0   /* TxD4 */
183                                         1  3  1  0  2  0   /* TxD5 */
184                                         1  5  1  0  3  0   /* TxD6 */
185                                         1  8  1  0  3  0   /* TxD7 */
186                                         0  23 2  0  1  0   /* RxD0 */
187                                         0  24 2  0  1  0   /* RxD1 */
188                                         0  25 2  0  1  0   /* RxD2 */
189                                         0  26 2  0  1  0   /* RxD3 */
190                                         0  27 2  0  1  0   /* RxD4 */
191                                         1  12 2  0  2  0   /* RxD5 */
192                                         1  13 2  0  3  0   /* RxD6 */
193                                         1  11 2  0  2  0   /* RxD7 */
194                                         0  21 1  0  1  0   /* TX_EN */
195                                         0  22 1  0  1  0   /* TX_ER */
196                                         0  29 2  0  1  0   /* RX_DV */
197                                         0  30 2  0  1  0   /* RX_ER */
198                                         0  31 2  0  1  0   /* RX_CLK */
199                                         2  2  1  0  2  0   /* GTX_CLK - CLK10 */
200                                         2  3  2  0  1  0   /* GTX125 - CLK4 */
201                                         0  1  3  0  2  0   /* MDIO */
202                                         0  2  1  0  1  0>; /* MDC */
203                         };
204
205                 };
206         };
207
208         qe@e0100000 {
209                 #address-cells = <1>;
210                 #size-cells = <1>;
211                 device_type = "qe";
212                 compatible = "fsl,qe";
213                 ranges = <0x0 0xe0100000 0x00100000>;
214                 reg = <0xe0100000 0x480>;
215                 brg-frequency = <0>;
216                 bus-frequency = <396000000>;
217
218                 muram@10000 {
219                         #address-cells = <1>;
220                         #size-cells = <1>;
221                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
222                         ranges = <0x0 0x00010000 0x0000c000>;
223
224                         data-only@0 {
225                                 compatible = "fsl,qe-muram-data",
226                                              "fsl,cpm-muram-data";
227                                 reg = <0x0 0xc000>;
228                         };
229                 };
230
231                 spi@4c0 {
232                         cell-index = <0>;
233                         compatible = "fsl,spi";
234                         reg = <0x4c0 0x40>;
235                         interrupts = <2>;
236                         interrupt-parent = <&qeic>;
237                         mode = "cpu";
238                 };
239
240                 spi@500 {
241                         cell-index = <1>;
242                         compatible = "fsl,spi";
243                         reg = <0x500 0x40>;
244                         interrupts = <1>;
245                         interrupt-parent = <&qeic>;
246                         mode = "cpu";
247                 };
248
249                 usb@6c0 {
250                         compatible = "qe_udc";
251                         reg = <0x6c0 0x40 0x8b00 0x100>;
252                         interrupts = <11>;
253                         interrupt-parent = <&qeic>;
254                         mode = "slave";
255                 };
256
257                 enet0: ucc@2000 {
258                         device_type = "network";
259                         compatible = "ucc_geth";
260                         cell-index = <1>;
261                         reg = <0x2000 0x200>;
262                         interrupts = <32>;
263                         interrupt-parent = <&qeic>;
264                         local-mac-address = [ 00 00 00 00 00 00 ];
265                         rx-clock-name = "none";
266                         tx-clock-name = "clk9";
267                         phy-handle = <&phy0>;
268                         phy-connection-type = "rgmii-id";
269                         pio-handle = <&pio1>;
270                 };
271
272                 enet1: ucc@3000 {
273                         device_type = "network";
274                         compatible = "ucc_geth";
275                         cell-index = <2>;
276                         reg = <0x3000 0x200>;
277                         interrupts = <33>;
278                         interrupt-parent = <&qeic>;
279                         local-mac-address = [ 00 00 00 00 00 00 ];
280                         rx-clock-name = "none";
281                         tx-clock-name = "clk4";
282                         phy-handle = <&phy1>;
283                         phy-connection-type = "rgmii-id";
284                         pio-handle = <&pio2>;
285                 };
286
287                 mdio@2120 {
288                         #address-cells = <1>;
289                         #size-cells = <0>;
290                         reg = <0x2120 0x18>;
291                         compatible = "fsl,ucc-mdio";
292
293                         phy0: ethernet-phy@00 {
294                                 interrupt-parent = <&ipic>;
295                                 interrupts = <17 0x8>;
296                                 reg = <0x0>;
297                                 device_type = "ethernet-phy";
298                         };
299                         phy1: ethernet-phy@01 {
300                                 interrupt-parent = <&ipic>;
301                                 interrupts = <18 0x8>;
302                                 reg = <0x1>;
303                                 device_type = "ethernet-phy";
304                         };
305                 };
306
307                 qeic: interrupt-controller@80 {
308                         interrupt-controller;
309                         compatible = "fsl,qe-ic";
310                         #address-cells = <0>;
311                         #interrupt-cells = <1>;
312                         reg = <0x80 0x80>;
313                         big-endian;
314                         interrupts = <32 0x8 33 0x8>; // high:32 low:33
315                         interrupt-parent = <&ipic>;
316                 };
317         };
318
319         pci0: pci@e0008500 {
320                 cell-index = <1>;
321                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
322                 interrupt-map = <
323
324                                 /* IDSEL 0x11 AD17 */
325                                  0x8800 0x0 0x0 0x1 &ipic 20 0x8
326                                  0x8800 0x0 0x0 0x2 &ipic 21 0x8
327                                  0x8800 0x0 0x0 0x3 &ipic 22 0x8
328                                  0x8800 0x0 0x0 0x4 &ipic 23 0x8
329
330                                 /* IDSEL 0x12 AD18 */
331                                  0x9000 0x0 0x0 0x1 &ipic 22 0x8
332                                  0x9000 0x0 0x0 0x2 &ipic 23 0x8
333                                  0x9000 0x0 0x0 0x3 &ipic 20 0x8
334                                  0x9000 0x0 0x0 0x4 &ipic 21 0x8
335
336                                 /* IDSEL 0x13 AD19 */
337                                  0x9800 0x0 0x0 0x1 &ipic 23 0x8
338                                  0x9800 0x0 0x0 0x2 &ipic 20 0x8
339                                  0x9800 0x0 0x0 0x3 &ipic 21 0x8
340                                  0x9800 0x0 0x0 0x4 &ipic 22 0x8
341
342                                 /* IDSEL 0x15 AD21*/
343                                  0xa800 0x0 0x0 0x1 &ipic 20 0x8
344                                  0xa800 0x0 0x0 0x2 &ipic 21 0x8
345                                  0xa800 0x0 0x0 0x3 &ipic 22 0x8
346                                  0xa800 0x0 0x0 0x4 &ipic 23 0x8
347
348                                 /* IDSEL 0x16 AD22*/
349                                  0xb000 0x0 0x0 0x1 &ipic 23 0x8
350                                  0xb000 0x0 0x0 0x2 &ipic 20 0x8
351                                  0xb000 0x0 0x0 0x3 &ipic 21 0x8
352                                  0xb000 0x0 0x0 0x4 &ipic 22 0x8
353
354                                 /* IDSEL 0x17 AD23*/
355                                  0xb800 0x0 0x0 0x1 &ipic 22 0x8
356                                  0xb800 0x0 0x0 0x2 &ipic 23 0x8
357                                  0xb800 0x0 0x0 0x3 &ipic 20 0x8
358                                  0xb800 0x0 0x0 0x4 &ipic 21 0x8
359
360                                 /* IDSEL 0x18 AD24*/
361                                  0xc000 0x0 0x0 0x1 &ipic 21 0x8
362                                  0xc000 0x0 0x0 0x2 &ipic 22 0x8
363                                  0xc000 0x0 0x0 0x3 &ipic 23 0x8
364                                  0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
365                 interrupt-parent = <&ipic>;
366                 interrupts = <66 0x8>;
367                 bus-range = <0 0>;
368                 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
369                           0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
370                           0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
371                 clock-frequency = <66666666>;
372                 #interrupt-cells = <1>;
373                 #size-cells = <2>;
374                 #address-cells = <3>;
375                 reg = <0xe0008500 0x100>;
376                 compatible = "fsl,mpc8349-pci";
377                 device_type = "pci";
378         };
379 };