git.oblomov.eu Git - linux-2.6/blob - arch/i386/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/sched.h>
  29 #include <linux/config.h>
  30 #include <linux/smp_lock.h>
  31 #include <linux/mc146818rtc.h>
  32 #include <linux/compiler.h>
  33 #include <linux/acpi.h>
  34 #include <linux/module.h>
  35 #include <linux/sysdev.h>
  36 #include <asm/io.h>
  37 #include <asm/smp.h>
  38 #include <asm/desc.h>
  39 #include <asm/timer.h>
  40
  41 #include <mach_apic.h>
  42
  43 #include "io_ports.h"
  44
  45 int (*ioapic_renumber_irq)(int ioapic, int irq);
  46 atomic_t irq_mis_count;
  47
  48 static DEFINE_SPINLOCK(ioapic_lock);
  49
  50 /*
  51  *      Is the SiS APIC rmw bug present ?
  52  *      -1 = don't know, 0 = no, 1 = yes
  53  */
  54 int sis_apic_bug = -1;
  55
  56 /*
  57  * # of IRQ routing registers
  58  */
  59 int nr_ioapic_registers[MAX_IO_APICS];
  60
  61 /*
  62  * Rough estimation of how many shared IRQs there are, can
  63  * be changed anytime.
  64  */
  65 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  66 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  67
  68 /*
  69  * This is performance-critical, we want to do it O(1)
  70  *
  71  * the indexing order of this array favors 1:1 mappings
  72  * between pins and IRQs.
  73  */
  74
  75 static struct irq_pin_list {
  76         int apic, pin, next;
  77 } irq_2_pin[PIN_MAP_SIZE];
  78
  79 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
  80 #ifdef CONFIG_PCI_MSI
  81 #define vector_to_irq(vector)   \
  82         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  83 #else
  84 #define vector_to_irq(vector)   (vector)
  85 #endif
  86
  87 /*
  88  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  89  * shared ISA-space IRQs, so we have to support them. We are super
  90  * fast in the common case, and fast for shared ISA-space IRQs.
  91  */
  92 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
  93 {
  94         static int first_free_entry = NR_IRQS;
  95         struct irq_pin_list *entry = irq_2_pin + irq;
  96
  97         while (entry->next)
  98                 entry = irq_2_pin + entry->next;
  99
 100         if (entry->pin != -1) {
 101                 entry->next = first_free_entry;
 102                 entry = irq_2_pin + entry->next;
 103                 if (++first_free_entry >= PIN_MAP_SIZE)
 104                         panic("io_apic.c: whoops");
 105         }
 106         entry->apic = apic;
 107         entry->pin = pin;
 108 }
 109
 110 /*
 111  * Reroute an IRQ to a different pin.
 112  */
 113 static void __init replace_pin_at_irq(unsigned int irq,
 114                                       int oldapic, int oldpin,
 115                                       int newapic, int newpin)
 116 {
 117         struct irq_pin_list *entry = irq_2_pin + irq;
 118
 119         while (1) {
 120                 if (entry->apic == oldapic && entry->pin == oldpin) {
 121                         entry->apic = newapic;
 122                         entry->pin = newpin;
 123                 }
 124                 if (!entry->next)
 125                         break;
 126                 entry = irq_2_pin + entry->next;
 127         }
 128 }
 129
 130 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 131 {
 132         struct irq_pin_list *entry = irq_2_pin + irq;
 133         unsigned int pin, reg;
 134
 135         for (;;) {
 136                 pin = entry->pin;
 137                 if (pin == -1)
 138                         break;
 139                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 140                 reg &= ~disable;
 141                 reg |= enable;
 142                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 143                 if (!entry->next)
 144                         break;
 145                 entry = irq_2_pin + entry->next;
 146         }
 147 }
 148
 149 /* mask = 1 */
 150 static void __mask_IO_APIC_irq (unsigned int irq)
 151 {
 152         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 153 }
 154
 155 /* mask = 0 */
 156 static void __unmask_IO_APIC_irq (unsigned int irq)
 157 {
 158         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 159 }
 160
 161 /* mask = 1, trigger = 0 */
 162 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 163 {
 164         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 165 }
 166
 167 /* mask = 0, trigger = 1 */
 168 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 169 {
 170         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 171 }
 172
 173 static void mask_IO_APIC_irq (unsigned int irq)
 174 {
 175         unsigned long flags;
 176
 177         spin_lock_irqsave(&ioapic_lock, flags);
 178         __mask_IO_APIC_irq(irq);
 179         spin_unlock_irqrestore(&ioapic_lock, flags);
 180 }
 181
 182 static void unmask_IO_APIC_irq (unsigned int irq)
 183 {
 184         unsigned long flags;
 185
 186         spin_lock_irqsave(&ioapic_lock, flags);
 187         __unmask_IO_APIC_irq(irq);
 188         spin_unlock_irqrestore(&ioapic_lock, flags);
 189 }
 190
 191 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 192 {
 193         struct IO_APIC_route_entry entry;
 194         unsigned long flags;
 195
 196         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 197         spin_lock_irqsave(&ioapic_lock, flags);
 198         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 199         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 200         spin_unlock_irqrestore(&ioapic_lock, flags);
 201         if (entry.delivery_mode == dest_SMI)
 202                 return;
 203
 204         /*
 205          * Disable it in the IO-APIC irq-routing table:
 206          */
 207         memset(&entry, 0, sizeof(entry));
 208         entry.mask = 1;
 209         spin_lock_irqsave(&ioapic_lock, flags);
 210         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 211         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 212         spin_unlock_irqrestore(&ioapic_lock, flags);
 213 }
 214
 215 static void clear_IO_APIC (void)
 216 {
 217         int apic, pin;
 218
 219         for (apic = 0; apic < nr_ioapics; apic++)
 220                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 221                         clear_IO_APIC_pin(apic, pin);
 222 }
 223
 224 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 225 {
 226         unsigned long flags;
 227         int pin;
 228         struct irq_pin_list *entry = irq_2_pin + irq;
 229         unsigned int apicid_value;
 230
 231         apicid_value = cpu_mask_to_apicid(cpumask);
 232         /* Prepare to do the io_apic_write */
 233         apicid_value = apicid_value << 24;
 234         spin_lock_irqsave(&ioapic_lock, flags);
 235         for (;;) {
 236                 pin = entry->pin;
 237                 if (pin == -1)
 238                         break;
 239                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 240                 if (!entry->next)
 241                         break;
 242                 entry = irq_2_pin + entry->next;
 243         }
 244         spin_unlock_irqrestore(&ioapic_lock, flags);
 245 }
 246
 247 #if defined(CONFIG_IRQBALANCE)
 248 # include <asm/processor.h>     /* kernel_thread() */
 249 # include <linux/kernel_stat.h> /* kstat */
 250 # include <linux/slab.h>                /* kmalloc() */
 251 # include <linux/timer.h>       /* time_after() */
 252
 253 # ifdef CONFIG_BALANCED_IRQ_DEBUG
 254 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 255 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 256 # else
 257 #  define TDprintk(x...)
 258 #  define Dprintk(x...)
 259 # endif
 260
 261 cpumask_t __cacheline_aligned pending_irq_balance_cpumask[NR_IRQS];
 262
 263 #define IRQBALANCE_CHECK_ARCH -999
 264 static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
 265 static int physical_balance = 0;
 266
 267 static struct irq_cpu_info {
 268         unsigned long * last_irq;
 269         unsigned long * irq_delta;
 270         unsigned long irq;
 271 } irq_cpu_data[NR_CPUS];
 272
 273 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 274 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 275 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 276
 277 #define IDLE_ENOUGH(cpu,now) \
 278         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 279
 280 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 281
 282 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 283
 284 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 285 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 286 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 287 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 288
 289 static long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
 290
 291 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 292                         unsigned long now, int direction)
 293 {
 294         int search_idle = 1;
 295         int cpu = curr_cpu;
 296
 297         goto inside;
 298
 299         do {
 300                 if (unlikely(cpu == curr_cpu))
 301                         search_idle = 0;
 302 inside:
 303                 if (direction == 1) {
 304                         cpu++;
 305                         if (cpu >= NR_CPUS)
 306                                 cpu = 0;
 307                 } else {
 308                         cpu--;
 309                         if (cpu == -1)
 310                                 cpu = NR_CPUS-1;
 311                 }
 312         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 313                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 314
 315         return cpu;
 316 }
 317
 318 static inline void balance_irq(int cpu, int irq)
 319 {
 320         unsigned long now = jiffies;
 321         cpumask_t allowed_mask;
 322         unsigned int new_cpu;
 323
 324         if (irqbalance_disabled)
 325                 return;
 326
 327         cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
 328         new_cpu = move(cpu, allowed_mask, now, 1);
 329         if (cpu != new_cpu) {
 330                 irq_desc_t *desc = irq_desc + irq;
 331                 unsigned long flags;
 332
 333                 spin_lock_irqsave(&desc->lock, flags);
 334                 pending_irq_balance_cpumask[irq] = cpumask_of_cpu(new_cpu);
 335                 spin_unlock_irqrestore(&desc->lock, flags);
 336         }
 337 }
 338
 339 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 340 {
 341         int i, j;
 342         Dprintk("Rotating IRQs among CPUs.\n");
 343         for (i = 0; i < NR_CPUS; i++) {
 344                 for (j = 0; cpu_online(i) && (j < NR_IRQS); j++) {
 345                         if (!irq_desc[j].action)
 346                                 continue;
 347                         /* Is it a significant load ?  */
 348                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 349                                                 useful_load_threshold)
 350                                 continue;
 351                         balance_irq(i, j);
 352                 }
 353         }
 354         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 355                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 356         return;
 357 }
 358
 359 static void do_irq_balance(void)
 360 {
 361         int i, j;
 362         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 363         unsigned long move_this_load = 0;
 364         int max_loaded = 0, min_loaded = 0;
 365         int load;
 366         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 367         int selected_irq;
 368         int tmp_loaded, first_attempt = 1;
 369         unsigned long tmp_cpu_irq;
 370         unsigned long imbalance = 0;
 371         cpumask_t allowed_mask, target_cpu_mask, tmp;
 372
 373         for (i = 0; i < NR_CPUS; i++) {
 374                 int package_index;
 375                 CPU_IRQ(i) = 0;
 376                 if (!cpu_online(i))
 377                         continue;
 378                 package_index = CPU_TO_PACKAGEINDEX(i);
 379                 for (j = 0; j < NR_IRQS; j++) {
 380                         unsigned long value_now, delta;
 381                         /* Is this an active IRQ? */
 382                         if (!irq_desc[j].action)
 383                                 continue;
 384                         if ( package_index == i )
 385                                 IRQ_DELTA(package_index,j) = 0;
 386                         /* Determine the total count per processor per IRQ */
 387                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 388
 389                         /* Determine the activity per processor per IRQ */
 390                         delta = value_now - LAST_CPU_IRQ(i,j);
 391
 392                         /* Update last_cpu_irq[][] for the next time */
 393                         LAST_CPU_IRQ(i,j) = value_now;
 394
 395                         /* Ignore IRQs whose rate is less than the clock */
 396                         if (delta < useful_load_threshold)
 397                                 continue;
 398                         /* update the load for the processor or package total */
 399                         IRQ_DELTA(package_index,j) += delta;
 400
 401                         /* Keep track of the higher numbered sibling as well */
 402                         if (i != package_index)
 403                                 CPU_IRQ(i) += delta;
 404                         /*
 405                          * We have sibling A and sibling B in the package
 406                          *
 407                          * cpu_irq[A] = load for cpu A + load for cpu B
 408                          * cpu_irq[B] = load for cpu B
 409                          */
 410                         CPU_IRQ(package_index) += delta;
 411                 }
 412         }
 413         /* Find the least loaded processor package */
 414         for (i = 0; i < NR_CPUS; i++) {
 415                 if (!cpu_online(i))
 416                         continue;
 417                 if (i != CPU_TO_PACKAGEINDEX(i))
 418                         continue;
 419                 if (min_cpu_irq > CPU_IRQ(i)) {
 420                         min_cpu_irq = CPU_IRQ(i);
 421                         min_loaded = i;
 422                 }
 423         }
 424         max_cpu_irq = ULONG_MAX;
 425
 426 tryanothercpu:
 427         /* Look for heaviest loaded processor.
 428          * We may come back to get the next heaviest loaded processor.
 429          * Skip processors with trivial loads.
 430          */
 431         tmp_cpu_irq = 0;
 432         tmp_loaded = -1;
 433         for (i = 0; i < NR_CPUS; i++) {
 434                 if (!cpu_online(i))
 435                         continue;
 436                 if (i != CPU_TO_PACKAGEINDEX(i))
 437                         continue;
 438                 if (max_cpu_irq <= CPU_IRQ(i))
 439                         continue;
 440                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 441                         tmp_cpu_irq = CPU_IRQ(i);
 442                         tmp_loaded = i;
 443                 }
 444         }
 445
 446         if (tmp_loaded == -1) {
 447          /* In the case of small number of heavy interrupt sources,
 448           * loading some of the cpus too much. We use Ingo's original
 449           * approach to rotate them around.
 450           */
 451                 if (!first_attempt && imbalance >= useful_load_threshold) {
 452                         rotate_irqs_among_cpus(useful_load_threshold);
 453                         return;
 454                 }
 455                 goto not_worth_the_effort;
 456         }
 457
 458         first_attempt = 0;              /* heaviest search */
 459         max_cpu_irq = tmp_cpu_irq;      /* load */
 460         max_loaded = tmp_loaded;        /* processor */
 461         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 462
 463         Dprintk("max_loaded cpu = %d\n", max_loaded);
 464         Dprintk("min_loaded cpu = %d\n", min_loaded);
 465         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 466         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 467         Dprintk("load imbalance = %lu\n", imbalance);
 468
 469         /* if imbalance is less than approx 10% of max load, then
 470          * observe diminishing returns action. - quit
 471          */
 472         if (imbalance < (max_cpu_irq >> 3)) {
 473                 Dprintk("Imbalance too trivial\n");
 474                 goto not_worth_the_effort;
 475         }
 476
 477 tryanotherirq:
 478         /* if we select an IRQ to move that can't go where we want, then
 479          * see if there is another one to try.
 480          */
 481         move_this_load = 0;
 482         selected_irq = -1;
 483         for (j = 0; j < NR_IRQS; j++) {
 484                 /* Is this an active IRQ? */
 485                 if (!irq_desc[j].action)
 486                         continue;
 487                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 488                         continue;
 489                 /* Try to find the IRQ that is closest to the imbalance
 490                  * without going over.
 491                  */
 492                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 493                         move_this_load = IRQ_DELTA(max_loaded,j);
 494                         selected_irq = j;
 495                 }
 496         }
 497         if (selected_irq == -1) {
 498                 goto tryanothercpu;
 499         }
 500
 501         imbalance = move_this_load;
 502
 503         /* For physical_balance case, we accumlated both load
 504          * values in the one of the siblings cpu_irq[],
 505          * to use the same code for physical and logical processors
 506          * as much as possible.
 507          *
 508          * NOTE: the cpu_irq[] array holds the sum of the load for
 509          * sibling A and sibling B in the slot for the lowest numbered
 510          * sibling (A), _AND_ the load for sibling B in the slot for
 511          * the higher numbered sibling.
 512          *
 513          * We seek the least loaded sibling by making the comparison
 514          * (A+B)/2 vs B
 515          */
 516         load = CPU_IRQ(min_loaded) >> 1;
 517         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 518                 if (load > CPU_IRQ(j)) {
 519                         /* This won't change cpu_sibling_map[min_loaded] */
 520                         load = CPU_IRQ(j);
 521                         min_loaded = j;
 522                 }
 523         }
 524
 525         cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
 526         target_cpu_mask = cpumask_of_cpu(min_loaded);
 527         cpus_and(tmp, target_cpu_mask, allowed_mask);
 528
 529         if (!cpus_empty(tmp)) {
 530                 irq_desc_t *desc = irq_desc + selected_irq;
 531                 unsigned long flags;
 532
 533                 Dprintk("irq = %d moved to cpu = %d\n",
 534                                 selected_irq, min_loaded);
 535                 /* mark for change destination */
 536                 spin_lock_irqsave(&desc->lock, flags);
 537                 pending_irq_balance_cpumask[selected_irq] =
 538                                         cpumask_of_cpu(min_loaded);
 539                 spin_unlock_irqrestore(&desc->lock, flags);
 540                 /* Since we made a change, come back sooner to
 541                  * check for more variation.
 542                  */
 543                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 544                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 545                 return;
 546         }
 547         goto tryanotherirq;
 548
 549 not_worth_the_effort:
 550         /*
 551          * if we did not find an IRQ to move, then adjust the time interval
 552          * upward
 553          */
 554         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 555                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 556         Dprintk("IRQ worth rotating not found\n");
 557         return;
 558 }
 559
 560 static int balanced_irq(void *unused)
 561 {
 562         int i;
 563         unsigned long prev_balance_time = jiffies;
 564         long time_remaining = balanced_irq_interval;
 565
 566         daemonize("kirqd");
 567
 568         /* push everything to CPU 0 to give us a starting point.  */
 569         for (i = 0 ; i < NR_IRQS ; i++) {
 570                 pending_irq_balance_cpumask[i] = cpumask_of_cpu(0);
 571         }
 572
 573         for ( ; ; ) {
 574                 set_current_state(TASK_INTERRUPTIBLE);
 575                 time_remaining = schedule_timeout(time_remaining);
 576                 try_to_freeze(PF_FREEZE);
 577                 if (time_after(jiffies,
 578                                 prev_balance_time+balanced_irq_interval)) {
 579                         do_irq_balance();
 580                         prev_balance_time = jiffies;
 581                         time_remaining = balanced_irq_interval;
 582                 }
 583         }
 584         return 0;
 585 }
 586
 587 static int __init balanced_irq_init(void)
 588 {
 589         int i;
 590         struct cpuinfo_x86 *c;
 591         cpumask_t tmp;
 592
 593         cpus_shift_right(tmp, cpu_online_map, 2);
 594         c = &boot_cpu_data;
 595         /* When not overwritten by the command line ask subarchitecture. */
 596         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 597                 irqbalance_disabled = NO_BALANCE_IRQ;
 598         if (irqbalance_disabled)
 599                 return 0;
 600
 601          /* disable irqbalance completely if there is only one processor online */
 602         if (num_online_cpus() < 2) {
 603                 irqbalance_disabled = 1;
 604                 return 0;
 605         }
 606         /*
 607          * Enable physical balance only if more than 1 physical processor
 608          * is present
 609          */
 610         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 611                 physical_balance = 1;
 612
 613         for (i = 0; i < NR_CPUS; i++) {
 614                 if (!cpu_online(i))
 615                         continue;
 616                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 617                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 618                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 619                         printk(KERN_ERR "balanced_irq_init: out of memory");
 620                         goto failed;
 621                 }
 622                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 623                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 624         }
 625
 626         printk(KERN_INFO "Starting balanced_irq\n");
 627         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 628                 return 0;
 629         else
 630                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 631 failed:
 632         for (i = 0; i < NR_CPUS; i++) {
 633                 if(irq_cpu_data[i].irq_delta)
 634                         kfree(irq_cpu_data[i].irq_delta);
 635                 if(irq_cpu_data[i].last_irq)
 636                         kfree(irq_cpu_data[i].last_irq);
 637         }
 638         return 0;
 639 }
 640
 641 int __init irqbalance_disable(char *str)
 642 {
 643         irqbalance_disabled = 1;
 644         return 0;
 645 }
 646
 647 __setup("noirqbalance", irqbalance_disable);
 648
 649 static inline void move_irq(int irq)
 650 {
 651         /* note - we hold the desc->lock */
 652         if (unlikely(!cpus_empty(pending_irq_balance_cpumask[irq]))) {
 653                 set_ioapic_affinity_irq(irq, pending_irq_balance_cpumask[irq]);
 654                 cpus_clear(pending_irq_balance_cpumask[irq]);
 655         }
 656 }
 657
 658 late_initcall(balanced_irq_init);
 659
 660 #else /* !CONFIG_IRQBALANCE */
 661 static inline void move_irq(int irq) { }
 662 #endif /* CONFIG_IRQBALANCE */
 663
 664 #ifndef CONFIG_SMP
 665 void fastcall send_IPI_self(int vector)
 666 {
 667         unsigned int cfg;
 668
 669         /*
 670          * Wait for idle.
 671          */
 672         apic_wait_icr_idle();
 673         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 674         /*
 675          * Send the IPI. The write to APIC_ICR fires this off.
 676          */
 677         apic_write_around(APIC_ICR, cfg);
 678 }
 679 #endif /* !CONFIG_SMP */
 680
 681
 682 /*
 683  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 684  * specific CPU-side IRQs.
 685  */
 686
 687 #define MAX_PIRQS 8
 688 static int pirq_entries [MAX_PIRQS];
 689 static int pirqs_enabled;
 690 int skip_ioapic_setup;
 691
 692 static int __init ioapic_setup(char *str)
 693 {
 694         skip_ioapic_setup = 1;
 695         return 1;
 696 }
 697
 698 __setup("noapic", ioapic_setup);
 699
 700 static int __init ioapic_pirq_setup(char *str)
 701 {
 702         int i, max;
 703         int ints[MAX_PIRQS+1];
 704
 705         get_options(str, ARRAY_SIZE(ints), ints);
 706
 707         for (i = 0; i < MAX_PIRQS; i++)
 708                 pirq_entries[i] = -1;
 709
 710         pirqs_enabled = 1;
 711         apic_printk(APIC_VERBOSE, KERN_INFO
 712                         "PIRQ redirection, working around broken MP-BIOS.\n");
 713         max = MAX_PIRQS;
 714         if (ints[0] < MAX_PIRQS)
 715                 max = ints[0];
 716
 717         for (i = 0; i < max; i++) {
 718                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 719                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 720                 /*
 721                  * PIRQs are mapped upside down, usually.
 722                  */
 723                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 724         }
 725         return 1;
 726 }
 727
 728 __setup("pirq=", ioapic_pirq_setup);
 729
 730 /*
 731  * Find the IRQ entry number of a certain pin.
 732  */
 733 static int find_irq_entry(int apic, int pin, int type)
 734 {
 735         int i;
 736
 737         for (i = 0; i < mp_irq_entries; i++)
 738                 if (mp_irqs[i].mpc_irqtype == type &&
 739                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 740                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 741                     mp_irqs[i].mpc_dstirq == pin)
 742                         return i;
 743
 744         return -1;
 745 }
 746
 747 /*
 748  * Find the pin to which IRQ[irq] (ISA) is connected
 749  */
 750 static int find_isa_irq_pin(int irq, int type)
 751 {
 752         int i;
 753
 754         for (i = 0; i < mp_irq_entries; i++) {
 755                 int lbus = mp_irqs[i].mpc_srcbus;
 756
 757                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 758                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 759                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 760                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 761                     ) &&
 762                     (mp_irqs[i].mpc_irqtype == type) &&
 763                     (mp_irqs[i].mpc_srcbusirq == irq))
 764
 765                         return mp_irqs[i].mpc_dstirq;
 766         }
 767         return -1;
 768 }
 769
 770 /*
 771  * Find a specific PCI IRQ entry.
 772  * Not an __init, possibly needed by modules
 773  */
 774 static int pin_2_irq(int idx, int apic, int pin);
 775
 776 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 777 {
 778         int apic, i, best_guess = -1;
 779
 780         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 781                 "slot:%d, pin:%d.\n", bus, slot, pin);
 782         if (mp_bus_id_to_pci_bus[bus] == -1) {
 783                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 784                 return -1;
 785         }
 786         for (i = 0; i < mp_irq_entries; i++) {
 787                 int lbus = mp_irqs[i].mpc_srcbus;
 788
 789                 for (apic = 0; apic < nr_ioapics; apic++)
 790                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 791                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 792                                 break;
 793
 794                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 795                     !mp_irqs[i].mpc_irqtype &&
 796                     (bus == lbus) &&
 797                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 798                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 799
 800                         if (!(apic || IO_APIC_IRQ(irq)))
 801                                 continue;
 802
 803                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 804                                 return irq;
 805                         /*
 806                          * Use the first all-but-pin matching entry as a
 807                          * best-guess fuzzy result for broken mptables.
 808                          */
 809                         if (best_guess < 0)
 810                                 best_guess = irq;
 811                 }
 812         }
 813         return best_guess;
 814 }
 815 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 816
 817 /*
 818  * This function currently is only a helper for the i386 smp boot process where
 819  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 820  * so mask in all cases should simply be TARGET_CPUS
 821  */
 822 void __init setup_ioapic_dest(void)
 823 {
 824         int pin, ioapic, irq, irq_entry;
 825
 826         if (skip_ioapic_setup == 1)
 827                 return;
 828
 829         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 830                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 831                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 832                         if (irq_entry == -1)
 833                                 continue;
 834                         irq = pin_2_irq(irq_entry, ioapic, pin);
 835                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 836                 }
 837
 838         }
 839 }
 840
 841 /*
 842  * EISA Edge/Level control register, ELCR
 843  */
 844 static int EISA_ELCR(unsigned int irq)
 845 {
 846         if (irq < 16) {
 847                 unsigned int port = 0x4d0 + (irq >> 3);
 848                 return (inb(port) >> (irq & 7)) & 1;
 849         }
 850         apic_printk(APIC_VERBOSE, KERN_INFO
 851                         "Broken MPtable reports ISA irq %d\n", irq);
 852         return 0;
 853 }
 854
 855 /* EISA interrupts are always polarity zero and can be edge or level
 856  * trigger depending on the ELCR value.  If an interrupt is listed as
 857  * EISA conforming in the MP table, that means its trigger type must
 858  * be read in from the ELCR */
 859
 860 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 861 #define default_EISA_polarity(idx)      (0)
 862
 863 /* ISA interrupts are always polarity zero edge triggered,
 864  * when listed as conforming in the MP table. */
 865
 866 #define default_ISA_trigger(idx)        (0)
 867 #define default_ISA_polarity(idx)       (0)
 868
 869 /* PCI interrupts are always polarity one level triggered,
 870  * when listed as conforming in the MP table. */
 871
 872 #define default_PCI_trigger(idx)        (1)
 873 #define default_PCI_polarity(idx)       (1)
 874
 875 /* MCA interrupts are always polarity zero level triggered,
 876  * when listed as conforming in the MP table. */
 877
 878 #define default_MCA_trigger(idx)        (1)
 879 #define default_MCA_polarity(idx)       (0)
 880
 881 /* NEC98 interrupts are always polarity zero edge triggered,
 882  * when listed as conforming in the MP table. */
 883
 884 #define default_NEC98_trigger(idx)     (0)
 885 #define default_NEC98_polarity(idx)    (0)
 886
 887 static int __init MPBIOS_polarity(int idx)
 888 {
 889         int bus = mp_irqs[idx].mpc_srcbus;
 890         int polarity;
 891
 892         /*
 893          * Determine IRQ line polarity (high active or low active):
 894          */
 895         switch (mp_irqs[idx].mpc_irqflag & 3)
 896         {
 897                 case 0: /* conforms, ie. bus-type dependent polarity */
 898                 {
 899                         switch (mp_bus_id_to_type[bus])
 900                         {
 901                                 case MP_BUS_ISA: /* ISA pin */
 902                                 {
 903                                         polarity = default_ISA_polarity(idx);
 904                                         break;
 905                                 }
 906                                 case MP_BUS_EISA: /* EISA pin */
 907                                 {
 908                                         polarity = default_EISA_polarity(idx);
 909                                         break;
 910                                 }
 911                                 case MP_BUS_PCI: /* PCI pin */
 912                                 {
 913                                         polarity = default_PCI_polarity(idx);
 914                                         break;
 915                                 }
 916                                 case MP_BUS_MCA: /* MCA pin */
 917                                 {
 918                                         polarity = default_MCA_polarity(idx);
 919                                         break;
 920                                 }
 921                                 case MP_BUS_NEC98: /* NEC 98 pin */
 922                                 {
 923                                         polarity = default_NEC98_polarity(idx);
 924                                         break;
 925                                 }
 926                                 default:
 927                                 {
 928                                         printk(KERN_WARNING "broken BIOS!!\n");
 929                                         polarity = 1;
 930                                         break;
 931                                 }
 932                         }
 933                         break;
 934                 }
 935                 case 1: /* high active */
 936                 {
 937                         polarity = 0;
 938                         break;
 939                 }
 940                 case 2: /* reserved */
 941                 {
 942                         printk(KERN_WARNING "broken BIOS!!\n");
 943                         polarity = 1;
 944                         break;
 945                 }
 946                 case 3: /* low active */
 947                 {
 948                         polarity = 1;
 949                         break;
 950                 }
 951                 default: /* invalid */
 952                 {
 953                         printk(KERN_WARNING "broken BIOS!!\n");
 954                         polarity = 1;
 955                         break;
 956                 }
 957         }
 958         return polarity;
 959 }
 960
 961 static int MPBIOS_trigger(int idx)
 962 {
 963         int bus = mp_irqs[idx].mpc_srcbus;
 964         int trigger;
 965
 966         /*
 967          * Determine IRQ trigger mode (edge or level sensitive):
 968          */
 969         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 970         {
 971                 case 0: /* conforms, ie. bus-type dependent */
 972                 {
 973                         switch (mp_bus_id_to_type[bus])
 974                         {
 975                                 case MP_BUS_ISA: /* ISA pin */
 976                                 {
 977                                         trigger = default_ISA_trigger(idx);
 978                                         break;
 979                                 }
 980                                 case MP_BUS_EISA: /* EISA pin */
 981                                 {
 982                                         trigger = default_EISA_trigger(idx);
 983                                         break;
 984                                 }
 985                                 case MP_BUS_PCI: /* PCI pin */
 986                                 {
 987                                         trigger = default_PCI_trigger(idx);
 988                                         break;
 989                                 }
 990                                 case MP_BUS_MCA: /* MCA pin */
 991                                 {
 992                                         trigger = default_MCA_trigger(idx);
 993                                         break;
 994                                 }
 995                                 case MP_BUS_NEC98: /* NEC 98 pin */
 996                                 {
 997                                         trigger = default_NEC98_trigger(idx);
 998                                         break;
 999                                 }
1000                                 default:
1001                                 {
1002                                         printk(KERN_WARNING "broken BIOS!!\n");
1003                                         trigger = 1;
1004                                         break;
1005                                 }
1006                         }
1007                         break;
1008                 }
1009                 case 1: /* edge */
1010                 {
1011                         trigger = 0;
1012                         break;
1013                 }
1014                 case 2: /* reserved */
1015                 {
1016                         printk(KERN_WARNING "broken BIOS!!\n");
1017                         trigger = 1;
1018                         break;
1019                 }
1020                 case 3: /* level */
1021                 {
1022                         trigger = 1;
1023                         break;
1024                 }
1025                 default: /* invalid */
1026                 {
1027                         printk(KERN_WARNING "broken BIOS!!\n");
1028                         trigger = 0;
1029                         break;
1030                 }
1031         }
1032         return trigger;
1033 }
1034
1035 static inline int irq_polarity(int idx)
1036 {
1037         return MPBIOS_polarity(idx);
1038 }
1039
1040 static inline int irq_trigger(int idx)
1041 {
1042         return MPBIOS_trigger(idx);
1043 }
1044
1045 static int pin_2_irq(int idx, int apic, int pin)
1046 {
1047         int irq, i;
1048         int bus = mp_irqs[idx].mpc_srcbus;
1049
1050         /*
1051          * Debugging check, we are in big trouble if this message pops up!
1052          */
1053         if (mp_irqs[idx].mpc_dstirq != pin)
1054                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1055
1056         switch (mp_bus_id_to_type[bus])
1057         {
1058                 case MP_BUS_ISA: /* ISA pin */
1059                 case MP_BUS_EISA:
1060                 case MP_BUS_MCA:
1061                 case MP_BUS_NEC98:
1062                 {
1063                         irq = mp_irqs[idx].mpc_srcbusirq;
1064                         break;
1065                 }
1066                 case MP_BUS_PCI: /* PCI pin */
1067                 {
1068                         /*
1069                          * PCI IRQs are mapped in order
1070                          */
1071                         i = irq = 0;
1072                         while (i < apic)
1073                                 irq += nr_ioapic_registers[i++];
1074                         irq += pin;
1075
1076                         /*
1077                          * For MPS mode, so far only needed by ES7000 platform
1078                          */
1079                         if (ioapic_renumber_irq)
1080                                 irq = ioapic_renumber_irq(apic, irq);
1081
1082                         break;
1083                 }
1084                 default:
1085                 {
1086                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1087                         irq = 0;
1088                         break;
1089                 }
1090         }
1091
1092         /*
1093          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1094          */
1095         if ((pin >= 16) && (pin <= 23)) {
1096                 if (pirq_entries[pin-16] != -1) {
1097                         if (!pirq_entries[pin-16]) {
1098                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1099                                                 "disabling PIRQ%d\n", pin-16);
1100                         } else {
1101                                 irq = pirq_entries[pin-16];
1102                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1103                                                 "using PIRQ%d -> IRQ %d\n",
1104                                                 pin-16, irq);
1105                         }
1106                 }
1107         }
1108         return irq;
1109 }
1110
1111 static inline int IO_APIC_irq_trigger(int irq)
1112 {
1113         int apic, idx, pin;
1114
1115         for (apic = 0; apic < nr_ioapics; apic++) {
1116                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1117                         idx = find_irq_entry(apic,pin,mp_INT);
1118                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1119                                 return irq_trigger(idx);
1120                 }
1121         }
1122         /*
1123          * nonexistent IRQs are edge default
1124          */
1125         return 0;
1126 }
1127
1128 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1129 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
1130
1131 int assign_irq_vector(int irq)
1132 {
1133         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1134
1135         BUG_ON(irq >= NR_IRQ_VECTORS);
1136         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1137                 return IO_APIC_VECTOR(irq);
1138 next:
1139         current_vector += 8;
1140         if (current_vector == SYSCALL_VECTOR)
1141                 goto next;
1142
1143         if (current_vector >= FIRST_SYSTEM_VECTOR) {
1144                 offset++;
1145                 if (!(offset%8))
1146                         return -ENOSPC;
1147                 current_vector = FIRST_DEVICE_VECTOR + offset;
1148         }
1149
1150         vector_irq[current_vector] = irq;
1151         if (irq != AUTO_ASSIGN)
1152                 IO_APIC_VECTOR(irq) = current_vector;
1153
1154         return current_vector;
1155 }
1156
1157 static struct hw_interrupt_type ioapic_level_type;
1158 static struct hw_interrupt_type ioapic_edge_type;
1159
1160 #define IOAPIC_AUTO     -1
1161 #define IOAPIC_EDGE     0
1162 #define IOAPIC_LEVEL    1
1163
1164 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1165 {
1166         if (use_pci_vector() && !platform_legacy_irq(irq)) {
1167                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1168                                 trigger == IOAPIC_LEVEL)
1169                         irq_desc[vector].handler = &ioapic_level_type;
1170                 else
1171                         irq_desc[vector].handler = &ioapic_edge_type;
1172                 set_intr_gate(vector, interrupt[vector]);
1173         } else  {
1174                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1175                                 trigger == IOAPIC_LEVEL)
1176                         irq_desc[irq].handler = &ioapic_level_type;
1177                 else
1178                         irq_desc[irq].handler = &ioapic_edge_type;
1179                 set_intr_gate(vector, interrupt[irq]);
1180         }
1181 }
1182
1183 static void __init setup_IO_APIC_irqs(void)
1184 {
1185         struct IO_APIC_route_entry entry;
1186         int apic, pin, idx, irq, first_notcon = 1, vector;
1187         unsigned long flags;
1188
1189         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1190
1191         for (apic = 0; apic < nr_ioapics; apic++) {
1192         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1193
1194                 /*
1195                  * add it to the IO-APIC irq-routing table:
1196                  */
1197                 memset(&entry,0,sizeof(entry));
1198
1199                 entry.delivery_mode = INT_DELIVERY_MODE;
1200                 entry.dest_mode = INT_DEST_MODE;
1201                 entry.mask = 0;                         /* enable IRQ */
1202                 entry.dest.logical.logical_dest =
1203                                         cpu_mask_to_apicid(TARGET_CPUS);
1204
1205                 idx = find_irq_entry(apic,pin,mp_INT);
1206                 if (idx == -1) {
1207                         if (first_notcon) {
1208                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1209                                                 " IO-APIC (apicid-pin) %d-%d",
1210                                                 mp_ioapics[apic].mpc_apicid,
1211                                                 pin);
1212                                 first_notcon = 0;
1213                         } else
1214                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1215                                         mp_ioapics[apic].mpc_apicid, pin);
1216                         continue;
1217                 }
1218
1219                 entry.trigger = irq_trigger(idx);
1220                 entry.polarity = irq_polarity(idx);
1221
1222                 if (irq_trigger(idx)) {
1223                         entry.trigger = 1;
1224                         entry.mask = 1;
1225                 }
1226
1227                 irq = pin_2_irq(idx, apic, pin);
1228                 /*
1229                  * skip adding the timer int on secondary nodes, which causes
1230                  * a small but painful rift in the time-space continuum
1231                  */
1232                 if (multi_timer_check(apic, irq))
1233                         continue;
1234                 else
1235                         add_pin_to_irq(irq, apic, pin);
1236
1237                 if (!apic && !IO_APIC_IRQ(irq))
1238                         continue;
1239
1240                 if (IO_APIC_IRQ(irq)) {
1241                         vector = assign_irq_vector(irq);
1242                         entry.vector = vector;
1243                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1244
1245                         if (!apic && (irq < 16))
1246                                 disable_8259A_irq(irq);
1247                 }
1248                 spin_lock_irqsave(&ioapic_lock, flags);
1249                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1250                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1251                 spin_unlock_irqrestore(&ioapic_lock, flags);
1252         }
1253         }
1254
1255         if (!first_notcon)
1256                 apic_printk(APIC_VERBOSE, " not connected.\n");
1257 }
1258
1259 /*
1260  * Set up the 8259A-master output pin:
1261  */
1262 static void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
1263 {
1264         struct IO_APIC_route_entry entry;
1265         unsigned long flags;
1266
1267         memset(&entry,0,sizeof(entry));
1268
1269         disable_8259A_irq(0);
1270
1271         /* mask LVT0 */
1272         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1273
1274         /*
1275          * We use logical delivery to get the timer IRQ
1276          * to the first CPU.
1277          */
1278         entry.dest_mode = INT_DEST_MODE;
1279         entry.mask = 0;                                 /* unmask IRQ now */
1280         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1281         entry.delivery_mode = INT_DELIVERY_MODE;
1282         entry.polarity = 0;
1283         entry.trigger = 0;
1284         entry.vector = vector;
1285
1286         /*
1287          * The timer IRQ doesn't have to know that behind the
1288          * scene we have a 8259A-master in AEOI mode ...
1289          */
1290         irq_desc[0].handler = &ioapic_edge_type;
1291
1292         /*
1293          * Add it to the IO-APIC irq-routing table:
1294          */
1295         spin_lock_irqsave(&ioapic_lock, flags);
1296         io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1297         io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1298         spin_unlock_irqrestore(&ioapic_lock, flags);
1299
1300         enable_8259A_irq(0);
1301 }
1302
1303 static inline void UNEXPECTED_IO_APIC(void)
1304 {
1305 }
1306
1307 void __init print_IO_APIC(void)
1308 {
1309         int apic, i;
1310         union IO_APIC_reg_00 reg_00;
1311         union IO_APIC_reg_01 reg_01;
1312         union IO_APIC_reg_02 reg_02;
1313         union IO_APIC_reg_03 reg_03;
1314         unsigned long flags;
1315
1316         if (apic_verbosity == APIC_QUIET)
1317                 return;
1318
1319         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1320         for (i = 0; i < nr_ioapics; i++)
1321                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1322                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1323
1324         /*
1325          * We are a bit conservative about what we expect.  We have to
1326          * know about every hardware change ASAP.
1327          */
1328         printk(KERN_INFO "testing the IO APIC.......................\n");
1329
1330         for (apic = 0; apic < nr_ioapics; apic++) {
1331
1332         spin_lock_irqsave(&ioapic_lock, flags);
1333         reg_00.raw = io_apic_read(apic, 0);
1334         reg_01.raw = io_apic_read(apic, 1);
1335         if (reg_01.bits.version >= 0x10)
1336                 reg_02.raw = io_apic_read(apic, 2);
1337         if (reg_01.bits.version >= 0x20)
1338                 reg_03.raw = io_apic_read(apic, 3);
1339         spin_unlock_irqrestore(&ioapic_lock, flags);
1340
1341         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1342         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1343         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1344         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1345         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1346         if (reg_00.bits.ID >= get_physical_broadcast())
1347                 UNEXPECTED_IO_APIC();
1348         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1349                 UNEXPECTED_IO_APIC();
1350
1351         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1352         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1353         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1354                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1355                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1356                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1357                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1358                 (reg_01.bits.entries != 0x2E) &&
1359                 (reg_01.bits.entries != 0x3F)
1360         )
1361                 UNEXPECTED_IO_APIC();
1362
1363         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1364         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1365         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1366                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1367                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1368                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1369                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1370         )
1371                 UNEXPECTED_IO_APIC();
1372         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1373                 UNEXPECTED_IO_APIC();
1374
1375         /*
1376          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1377          * but the value of reg_02 is read as the previous read register
1378          * value, so ignore it if reg_02 == reg_01.
1379          */
1380         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1381                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1382                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1383                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1384                         UNEXPECTED_IO_APIC();
1385         }
1386
1387         /*
1388          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1389          * or reg_03, but the value of reg_0[23] is read as the previous read
1390          * register value, so ignore it if reg_03 == reg_0[12].
1391          */
1392         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1393             reg_03.raw != reg_01.raw) {
1394                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1395                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1396                 if (reg_03.bits.__reserved_1)
1397                         UNEXPECTED_IO_APIC();
1398         }
1399
1400         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1401
1402         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1403                           " Stat Dest Deli Vect:   \n");
1404
1405         for (i = 0; i <= reg_01.bits.entries; i++) {
1406                 struct IO_APIC_route_entry entry;
1407
1408                 spin_lock_irqsave(&ioapic_lock, flags);
1409                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1410                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1411                 spin_unlock_irqrestore(&ioapic_lock, flags);
1412
1413                 printk(KERN_DEBUG " %02x %03X %02X  ",
1414                         i,
1415                         entry.dest.logical.logical_dest,
1416                         entry.dest.physical.physical_dest
1417                 );
1418
1419                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1420                         entry.mask,
1421                         entry.trigger,
1422                         entry.irr,
1423                         entry.polarity,
1424                         entry.delivery_status,
1425                         entry.dest_mode,
1426                         entry.delivery_mode,
1427                         entry.vector
1428                 );
1429         }
1430         }
1431         if (use_pci_vector())
1432                 printk(KERN_INFO "Using vector-based indexing\n");
1433         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1434         for (i = 0; i < NR_IRQS; i++) {
1435                 struct irq_pin_list *entry = irq_2_pin + i;
1436                 if (entry->pin < 0)
1437                         continue;
1438                 if (use_pci_vector() && !platform_legacy_irq(i))
1439                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1440                 else
1441                         printk(KERN_DEBUG "IRQ%d ", i);
1442                 for (;;) {
1443                         printk("-> %d:%d", entry->apic, entry->pin);
1444                         if (!entry->next)
1445                                 break;
1446                         entry = irq_2_pin + entry->next;
1447                 }
1448                 printk("\n");
1449         }
1450
1451         printk(KERN_INFO ".................................... done.\n");
1452
1453         return;
1454 }
1455
1456 #if 0
1457
1458 static void print_APIC_bitfield (int base)
1459 {
1460         unsigned int v;
1461         int i, j;
1462
1463         if (apic_verbosity == APIC_QUIET)
1464                 return;
1465
1466         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1467         for (i = 0; i < 8; i++) {
1468                 v = apic_read(base + i*0x10);
1469                 for (j = 0; j < 32; j++) {
1470                         if (v & (1<<j))
1471                                 printk("1");
1472                         else
1473                                 printk("0");
1474                 }
1475                 printk("\n");
1476         }
1477 }
1478
1479 void /*__init*/ print_local_APIC(void * dummy)
1480 {
1481         unsigned int v, ver, maxlvt;
1482
1483         if (apic_verbosity == APIC_QUIET)
1484                 return;
1485
1486         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1487                 smp_processor_id(), hard_smp_processor_id());
1488         v = apic_read(APIC_ID);
1489         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1490         v = apic_read(APIC_LVR);
1491         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1492         ver = GET_APIC_VERSION(v);
1493         maxlvt = get_maxlvt();
1494
1495         v = apic_read(APIC_TASKPRI);
1496         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1497
1498         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1499                 v = apic_read(APIC_ARBPRI);
1500                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1501                         v & APIC_ARBPRI_MASK);
1502                 v = apic_read(APIC_PROCPRI);
1503                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1504         }
1505
1506         v = apic_read(APIC_EOI);
1507         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1508         v = apic_read(APIC_RRR);
1509         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1510         v = apic_read(APIC_LDR);
1511         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1512         v = apic_read(APIC_DFR);
1513         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1514         v = apic_read(APIC_SPIV);
1515         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1516
1517         printk(KERN_DEBUG "... APIC ISR field:\n");
1518         print_APIC_bitfield(APIC_ISR);
1519         printk(KERN_DEBUG "... APIC TMR field:\n");
1520         print_APIC_bitfield(APIC_TMR);
1521         printk(KERN_DEBUG "... APIC IRR field:\n");
1522         print_APIC_bitfield(APIC_IRR);
1523
1524         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1525                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1526                         apic_write(APIC_ESR, 0);
1527                 v = apic_read(APIC_ESR);
1528                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1529         }
1530
1531         v = apic_read(APIC_ICR);
1532         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1533         v = apic_read(APIC_ICR2);
1534         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1535
1536         v = apic_read(APIC_LVTT);
1537         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1538
1539         if (maxlvt > 3) {                       /* PC is LVT#4. */
1540                 v = apic_read(APIC_LVTPC);
1541                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1542         }
1543         v = apic_read(APIC_LVT0);
1544         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1545         v = apic_read(APIC_LVT1);
1546         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1547
1548         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1549                 v = apic_read(APIC_LVTERR);
1550                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1551         }
1552
1553         v = apic_read(APIC_TMICT);
1554         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1555         v = apic_read(APIC_TMCCT);
1556         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1557         v = apic_read(APIC_TDCR);
1558         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1559         printk("\n");
1560 }
1561
1562 void print_all_local_APICs (void)
1563 {
1564         on_each_cpu(print_local_APIC, NULL, 1, 1);
1565 }
1566
1567 void /*__init*/ print_PIC(void)
1568 {
1569         extern spinlock_t i8259A_lock;
1570         unsigned int v;
1571         unsigned long flags;
1572
1573         if (apic_verbosity == APIC_QUIET)
1574                 return;
1575
1576         printk(KERN_DEBUG "\nprinting PIC contents\n");
1577
1578         spin_lock_irqsave(&i8259A_lock, flags);
1579
1580         v = inb(0xa1) << 8 | inb(0x21);
1581         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1582
1583         v = inb(0xa0) << 8 | inb(0x20);
1584         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1585
1586         outb(0x0b,0xa0);
1587         outb(0x0b,0x20);
1588         v = inb(0xa0) << 8 | inb(0x20);
1589         outb(0x0a,0xa0);
1590         outb(0x0a,0x20);
1591
1592         spin_unlock_irqrestore(&i8259A_lock, flags);
1593
1594         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1595
1596         v = inb(0x4d1) << 8 | inb(0x4d0);
1597         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1598 }
1599
1600 #endif  /*  0  */
1601
1602 static void __init enable_IO_APIC(void)
1603 {
1604         union IO_APIC_reg_01 reg_01;
1605         int i;
1606         unsigned long flags;
1607
1608         for (i = 0; i < PIN_MAP_SIZE; i++) {
1609                 irq_2_pin[i].pin = -1;
1610                 irq_2_pin[i].next = 0;
1611         }
1612         if (!pirqs_enabled)
1613                 for (i = 0; i < MAX_PIRQS; i++)
1614                         pirq_entries[i] = -1;
1615
1616         /*
1617          * The number of IO-APIC IRQ registers (== #pins):
1618          */
1619         for (i = 0; i < nr_ioapics; i++) {
1620                 spin_lock_irqsave(&ioapic_lock, flags);
1621                 reg_01.raw = io_apic_read(i, 1);
1622                 spin_unlock_irqrestore(&ioapic_lock, flags);
1623                 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1624         }
1625
1626         /*
1627          * Do not trust the IO-APIC being empty at bootup
1628          */
1629         clear_IO_APIC();
1630 }
1631
1632 /*
1633  * Not an __init, needed by the reboot code
1634  */
1635 void disable_IO_APIC(void)
1636 {
1637         /*
1638          * Clear the IO-APIC before rebooting:
1639          */
1640         clear_IO_APIC();
1641
1642         disconnect_bsp_APIC();
1643 }
1644
1645 /*
1646  * function to set the IO-APIC physical IDs based on the
1647  * values stored in the MPC table.
1648  *
1649  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1650  */
1651
1652 #ifndef CONFIG_X86_NUMAQ
1653 static void __init setup_ioapic_ids_from_mpc(void)
1654 {
1655         union IO_APIC_reg_00 reg_00;
1656         physid_mask_t phys_id_present_map;
1657         int apic;
1658         int i;
1659         unsigned char old_id;
1660         unsigned long flags;
1661
1662         /*
1663          * Don't check I/O APIC IDs for xAPIC systems.  They have
1664          * no meaning without the serial APIC bus.
1665          */
1666         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86 < 15))
1667                 return;
1668         /*
1669          * This is broken; anything with a real cpu count has to
1670          * circumvent this idiocy regardless.
1671          */
1672         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1673
1674         /*
1675          * Set the IOAPIC ID to the value stored in the MPC table.
1676          */
1677         for (apic = 0; apic < nr_ioapics; apic++) {
1678
1679                 /* Read the register 0 value */
1680                 spin_lock_irqsave(&ioapic_lock, flags);
1681                 reg_00.raw = io_apic_read(apic, 0);
1682                 spin_unlock_irqrestore(&ioapic_lock, flags);
1683
1684                 old_id = mp_ioapics[apic].mpc_apicid;
1685
1686                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1687                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1688                                 apic, mp_ioapics[apic].mpc_apicid);
1689                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1690                                 reg_00.bits.ID);
1691                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1692                 }
1693
1694                 /*
1695                  * Sanity check, is the ID really free? Every APIC in a
1696                  * system must have a unique ID or we get lots of nice
1697                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1698                  */
1699                 if (check_apicid_used(phys_id_present_map,
1700                                         mp_ioapics[apic].mpc_apicid)) {
1701                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1702                                 apic, mp_ioapics[apic].mpc_apicid);
1703                         for (i = 0; i < get_physical_broadcast(); i++)
1704                                 if (!physid_isset(i, phys_id_present_map))
1705                                         break;
1706                         if (i >= get_physical_broadcast())
1707                                 panic("Max APIC ID exceeded!\n");
1708                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1709                                 i);
1710                         physid_set(i, phys_id_present_map);
1711                         mp_ioapics[apic].mpc_apicid = i;
1712                 } else {
1713                         physid_mask_t tmp;
1714                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1715                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1716                                         "phys_id_present_map\n",
1717                                         mp_ioapics[apic].mpc_apicid);
1718                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1719                 }
1720
1721
1722                 /*
1723                  * We need to adjust the IRQ routing table
1724                  * if the ID changed.
1725                  */
1726                 if (old_id != mp_ioapics[apic].mpc_apicid)
1727                         for (i = 0; i < mp_irq_entries; i++)
1728                                 if (mp_irqs[i].mpc_dstapic == old_id)
1729                                         mp_irqs[i].mpc_dstapic
1730                                                 = mp_ioapics[apic].mpc_apicid;
1731
1732                 /*
1733                  * Read the right value from the MPC table and
1734                  * write it into the ID register.
1735                  */
1736                 apic_printk(APIC_VERBOSE, KERN_INFO
1737                         "...changing IO-APIC physical APIC ID to %d ...",
1738                         mp_ioapics[apic].mpc_apicid);
1739
1740                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1741                 spin_lock_irqsave(&ioapic_lock, flags);
1742                 io_apic_write(apic, 0, reg_00.raw);
1743                 spin_unlock_irqrestore(&ioapic_lock, flags);
1744
1745                 /*
1746                  * Sanity check
1747                  */
1748                 spin_lock_irqsave(&ioapic_lock, flags);
1749                 reg_00.raw = io_apic_read(apic, 0);
1750                 spin_unlock_irqrestore(&ioapic_lock, flags);
1751                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1752                         printk("could not set ID!\n");
1753                 else
1754                         apic_printk(APIC_VERBOSE, " ok.\n");
1755         }
1756 }
1757 #else
1758 static void __init setup_ioapic_ids_from_mpc(void) { }
1759 #endif
1760
1761 /*
1762  * There is a nasty bug in some older SMP boards, their mptable lies
1763  * about the timer IRQ. We do the following to work around the situation:
1764  *
1765  *      - timer IRQ defaults to IO-APIC IRQ
1766  *      - if this function detects that timer IRQs are defunct, then we fall
1767  *        back to ISA timer IRQs
1768  */
1769 static int __init timer_irq_works(void)
1770 {
1771         unsigned long t1 = jiffies;
1772
1773         local_irq_enable();
1774         /* Let ten ticks pass... */
1775         mdelay((10 * 1000) / HZ);
1776
1777         /*
1778          * Expect a few ticks at least, to be sure some possible
1779          * glue logic does not lock up after one or two first
1780          * ticks in a non-ExtINT mode.  Also the local APIC
1781          * might have cached one ExtINT interrupt.  Finally, at
1782          * least one tick may be lost due to delays.
1783          */
1784         if (jiffies - t1 > 4)
1785                 return 1;
1786
1787         return 0;
1788 }
1789
1790 /*
1791  * In the SMP+IOAPIC case it might happen that there are an unspecified
1792  * number of pending IRQ events unhandled. These cases are very rare,
1793  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1794  * better to do it this way as thus we do not have to be aware of
1795  * 'pending' interrupts in the IRQ path, except at this point.
1796  */
1797 /*
1798  * Edge triggered needs to resend any interrupt
1799  * that was delayed but this is now handled in the device
1800  * independent code.
1801  */
1802
1803 /*
1804  * Starting up a edge-triggered IO-APIC interrupt is
1805  * nasty - we need to make sure that we get the edge.
1806  * If it is already asserted for some reason, we need
1807  * return 1 to indicate that is was pending.
1808  *
1809  * This is not complete - we should be able to fake
1810  * an edge even if it isn't on the 8259A...
1811  */
1812 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1813 {
1814         int was_pending = 0;
1815         unsigned long flags;
1816
1817         spin_lock_irqsave(&ioapic_lock, flags);
1818         if (irq < 16) {
1819                 disable_8259A_irq(irq);
1820                 if (i8259A_irq_pending(irq))
1821                         was_pending = 1;
1822         }
1823         __unmask_IO_APIC_irq(irq);
1824         spin_unlock_irqrestore(&ioapic_lock, flags);
1825
1826         return was_pending;
1827 }
1828
1829 /*
1830  * Once we have recorded IRQ_PENDING already, we can mask the
1831  * interrupt for real. This prevents IRQ storms from unhandled
1832  * devices.
1833  */
1834 static void ack_edge_ioapic_irq(unsigned int irq)
1835 {
1836         move_irq(irq);
1837         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1838                                         == (IRQ_PENDING | IRQ_DISABLED))
1839                 mask_IO_APIC_irq(irq);
1840         ack_APIC_irq();
1841 }
1842
1843 /*
1844  * Level triggered interrupts can just be masked,
1845  * and shutting down and starting up the interrupt
1846  * is the same as enabling and disabling them -- except
1847  * with a startup need to return a "was pending" value.
1848  *
1849  * Level triggered interrupts are special because we
1850  * do not touch any IO-APIC register while handling
1851  * them. We ack the APIC in the end-IRQ handler, not
1852  * in the start-IRQ-handler. Protection against reentrance
1853  * from the same interrupt is still provided, both by the
1854  * generic IRQ layer and by the fact that an unacked local
1855  * APIC does not accept IRQs.
1856  */
1857 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1858 {
1859         unmask_IO_APIC_irq(irq);
1860
1861         return 0; /* don't check for pending */
1862 }
1863
1864 static void end_level_ioapic_irq (unsigned int irq)
1865 {
1866         unsigned long v;
1867         int i;
1868
1869         move_irq(irq);
1870 /*
1871  * It appears there is an erratum which affects at least version 0x11
1872  * of I/O APIC (that's the 82093AA and cores integrated into various
1873  * chipsets).  Under certain conditions a level-triggered interrupt is
1874  * erroneously delivered as edge-triggered one but the respective IRR
1875  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1876  * message but it will never arrive and further interrupts are blocked
1877  * from the source.  The exact reason is so far unknown, but the
1878  * phenomenon was observed when two consecutive interrupt requests
1879  * from a given source get delivered to the same CPU and the source is
1880  * temporarily disabled in between.
1881  *
1882  * A workaround is to simulate an EOI message manually.  We achieve it
1883  * by setting the trigger mode to edge and then to level when the edge
1884  * trigger mode gets detected in the TMR of a local APIC for a
1885  * level-triggered interrupt.  We mask the source for the time of the
1886  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1887  * The idea is from Manfred Spraul.  --macro
1888  */
1889         i = IO_APIC_VECTOR(irq);
1890
1891         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1892
1893         ack_APIC_irq();
1894
1895         if (!(v & (1 << (i & 0x1f)))) {
1896                 atomic_inc(&irq_mis_count);
1897                 spin_lock(&ioapic_lock);
1898                 __mask_and_edge_IO_APIC_irq(irq);
1899                 __unmask_and_level_IO_APIC_irq(irq);
1900                 spin_unlock(&ioapic_lock);
1901         }
1902 }
1903
1904 #ifdef CONFIG_PCI_MSI
1905 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1906 {
1907         int irq = vector_to_irq(vector);
1908
1909         return startup_edge_ioapic_irq(irq);
1910 }
1911
1912 static void ack_edge_ioapic_vector(unsigned int vector)
1913 {
1914         int irq = vector_to_irq(vector);
1915
1916         ack_edge_ioapic_irq(irq);
1917 }
1918
1919 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1920 {
1921         int irq = vector_to_irq(vector);
1922
1923         return startup_level_ioapic_irq (irq);
1924 }
1925
1926 static void end_level_ioapic_vector (unsigned int vector)
1927 {
1928         int irq = vector_to_irq(vector);
1929
1930         end_level_ioapic_irq(irq);
1931 }
1932
1933 static void mask_IO_APIC_vector (unsigned int vector)
1934 {
1935         int irq = vector_to_irq(vector);
1936
1937         mask_IO_APIC_irq(irq);
1938 }
1939
1940 static void unmask_IO_APIC_vector (unsigned int vector)
1941 {
1942         int irq = vector_to_irq(vector);
1943
1944         unmask_IO_APIC_irq(irq);
1945 }
1946
1947 static void set_ioapic_affinity_vector (unsigned int vector,
1948                                         cpumask_t cpu_mask)
1949 {
1950         int irq = vector_to_irq(vector);
1951
1952         set_ioapic_affinity_irq(irq, cpu_mask);
1953 }
1954 #endif
1955
1956 /*
1957  * Level and edge triggered IO-APIC interrupts need different handling,
1958  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1959  * handled with the level-triggered descriptor, but that one has slightly
1960  * more overhead. Level-triggered interrupts cannot be handled with the
1961  * edge-triggered handler, without risking IRQ storms and other ugly
1962  * races.
1963  */
1964 static struct hw_interrupt_type ioapic_edge_type = {
1965         .typename       = "IO-APIC-edge",
1966         .startup        = startup_edge_ioapic,
1967         .shutdown       = shutdown_edge_ioapic,
1968         .enable         = enable_edge_ioapic,
1969         .disable        = disable_edge_ioapic,
1970         .ack            = ack_edge_ioapic,
1971         .end            = end_edge_ioapic,
1972         .set_affinity   = set_ioapic_affinity,
1973 };
1974
1975 static struct hw_interrupt_type ioapic_level_type = {
1976         .typename       = "IO-APIC-level",
1977         .startup        = startup_level_ioapic,
1978         .shutdown       = shutdown_level_ioapic,
1979         .enable         = enable_level_ioapic,
1980         .disable        = disable_level_ioapic,
1981         .ack            = mask_and_ack_level_ioapic,
1982         .end            = end_level_ioapic,
1983         .set_affinity   = set_ioapic_affinity,
1984 };
1985
1986 static inline void init_IO_APIC_traps(void)
1987 {
1988         int irq;
1989
1990         /*
1991          * NOTE! The local APIC isn't very good at handling
1992          * multiple interrupts at the same interrupt level.
1993          * As the interrupt level is determined by taking the
1994          * vector number and shifting that right by 4, we
1995          * want to spread these out a bit so that they don't
1996          * all fall in the same interrupt level.
1997          *
1998          * Also, we've got to be careful not to trash gate
1999          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2000          */
2001         for (irq = 0; irq < NR_IRQS ; irq++) {
2002                 int tmp = irq;
2003                 if (use_pci_vector()) {
2004                         if (!platform_legacy_irq(tmp))
2005                                 if ((tmp = vector_to_irq(tmp)) == -1)
2006                                         continue;
2007                 }
2008                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2009                         /*
2010                          * Hmm.. We don't have an entry for this,
2011                          * so default to an old-fashioned 8259
2012                          * interrupt if we can..
2013                          */
2014                         if (irq < 16)
2015                                 make_8259A_irq(irq);
2016                         else
2017                                 /* Strange. Oh, well.. */
2018                                 irq_desc[irq].handler = &no_irq_type;
2019                 }
2020         }
2021 }
2022
2023 static void enable_lapic_irq (unsigned int irq)
2024 {
2025         unsigned long v;
2026
2027         v = apic_read(APIC_LVT0);
2028         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2029 }
2030
2031 static void disable_lapic_irq (unsigned int irq)
2032 {
2033         unsigned long v;
2034
2035         v = apic_read(APIC_LVT0);
2036         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2037 }
2038
2039 static void ack_lapic_irq (unsigned int irq)
2040 {
2041         ack_APIC_irq();
2042 }
2043
2044 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2045
2046 static struct hw_interrupt_type lapic_irq_type = {
2047         .typename       = "local-APIC-edge",
2048         .startup        = NULL, /* startup_irq() not used for IRQ0 */
2049         .shutdown       = NULL, /* shutdown_irq() not used for IRQ0 */
2050         .enable         = enable_lapic_irq,
2051         .disable        = disable_lapic_irq,
2052         .ack            = ack_lapic_irq,
2053         .end            = end_lapic_irq
2054 };
2055
2056 static void setup_nmi (void)
2057 {
2058         /*
2059          * Dirty trick to enable the NMI watchdog ...
2060          * We put the 8259A master into AEOI mode and
2061          * unmask on all local APICs LVT0 as NMI.
2062          *
2063          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2064          * is from Maciej W. Rozycki - so we do not have to EOI from
2065          * the NMI handler or the timer interrupt.
2066          */
2067         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2068
2069         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2070
2071         apic_printk(APIC_VERBOSE, " done.\n");
2072 }
2073
2074 /*
2075  * This looks a bit hackish but it's about the only one way of sending
2076  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2077  * not support the ExtINT mode, unfortunately.  We need to send these
2078  * cycles as some i82489DX-based boards have glue logic that keeps the
2079  * 8259A interrupt line asserted until INTA.  --macro
2080  */
2081 static inline void unlock_ExtINT_logic(void)
2082 {
2083         int pin, i;
2084         struct IO_APIC_route_entry entry0, entry1;
2085         unsigned char save_control, save_freq_select;
2086         unsigned long flags;
2087
2088         pin = find_isa_irq_pin(8, mp_INT);
2089         if (pin == -1)
2090                 return;
2091
2092         spin_lock_irqsave(&ioapic_lock, flags);
2093         *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
2094         *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
2095         spin_unlock_irqrestore(&ioapic_lock, flags);
2096         clear_IO_APIC_pin(0, pin);
2097
2098         memset(&entry1, 0, sizeof(entry1));
2099
2100         entry1.dest_mode = 0;                   /* physical delivery */
2101         entry1.mask = 0;                        /* unmask IRQ now */
2102         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2103         entry1.delivery_mode = dest_ExtINT;
2104         entry1.polarity = entry0.polarity;
2105         entry1.trigger = 0;
2106         entry1.vector = 0;
2107
2108         spin_lock_irqsave(&ioapic_lock, flags);
2109         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2110         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2111         spin_unlock_irqrestore(&ioapic_lock, flags);
2112
2113         save_control = CMOS_READ(RTC_CONTROL);
2114         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2115         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2116                    RTC_FREQ_SELECT);
2117         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2118
2119         i = 100;
2120         while (i-- > 0) {
2121                 mdelay(10);
2122                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2123                         i -= 10;
2124         }
2125
2126         CMOS_WRITE(save_control, RTC_CONTROL);
2127         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2128         clear_IO_APIC_pin(0, pin);
2129
2130         spin_lock_irqsave(&ioapic_lock, flags);
2131         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2132         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2133         spin_unlock_irqrestore(&ioapic_lock, flags);
2134 }
2135
2136 /*
2137  * This code may look a bit paranoid, but it's supposed to cooperate with
2138  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2139  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2140  * fanatically on his truly buggy board.
2141  */
2142 static inline void check_timer(void)
2143 {
2144         int pin1, pin2;
2145         int vector;
2146
2147         /*
2148          * get/set the timer IRQ vector:
2149          */
2150         disable_8259A_irq(0);
2151         vector = assign_irq_vector(0);
2152         set_intr_gate(vector, interrupt[0]);
2153
2154         /*
2155          * Subtle, code in do_timer_interrupt() expects an AEOI
2156          * mode for the 8259A whenever interrupts are routed
2157          * through I/O APICs.  Also IRQ0 has to be enabled in
2158          * the 8259A which implies the virtual wire has to be
2159          * disabled in the local APIC.
2160          */
2161         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2162         init_8259A(1);
2163         timer_ack = 1;
2164         enable_8259A_irq(0);
2165
2166         pin1 = find_isa_irq_pin(0, mp_INT);
2167         pin2 = find_isa_irq_pin(0, mp_ExtINT);
2168
2169         printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
2170
2171         if (pin1 != -1) {
2172                 /*
2173                  * Ok, does IRQ0 through the IOAPIC work?
2174                  */
2175                 unmask_IO_APIC_irq(0);
2176                 if (timer_irq_works()) {
2177                         if (nmi_watchdog == NMI_IO_APIC) {
2178                                 disable_8259A_irq(0);
2179                                 setup_nmi();
2180                                 enable_8259A_irq(0);
2181                         }
2182                         return;
2183                 }
2184                 clear_IO_APIC_pin(0, pin1);
2185                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
2186         }
2187
2188         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2189         if (pin2 != -1) {
2190                 printk("\n..... (found pin %d) ...", pin2);
2191                 /*
2192                  * legacy devices should be connected to IO APIC #0
2193                  */
2194                 setup_ExtINT_IRQ0_pin(pin2, vector);
2195                 if (timer_irq_works()) {
2196                         printk("works.\n");
2197                         if (pin1 != -1)
2198                                 replace_pin_at_irq(0, 0, pin1, 0, pin2);
2199                         else
2200                                 add_pin_to_irq(0, 0, pin2);
2201                         if (nmi_watchdog == NMI_IO_APIC) {
2202                                 setup_nmi();
2203                         }
2204                         return;
2205                 }
2206                 /*
2207                  * Cleanup, just in case ...
2208                  */
2209                 clear_IO_APIC_pin(0, pin2);
2210         }
2211         printk(" failed.\n");
2212
2213         if (nmi_watchdog == NMI_IO_APIC) {
2214                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2215                 nmi_watchdog = 0;
2216         }
2217
2218         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2219
2220         disable_8259A_irq(0);
2221         irq_desc[0].handler = &lapic_irq_type;
2222         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2223         enable_8259A_irq(0);
2224
2225         if (timer_irq_works()) {
2226                 printk(" works.\n");
2227                 return;
2228         }
2229         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2230         printk(" failed.\n");
2231
2232         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2233
2234         timer_ack = 0;
2235         init_8259A(0);
2236         make_8259A_irq(0);
2237         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2238
2239         unlock_ExtINT_logic();
2240
2241         if (timer_irq_works()) {
2242                 printk(" works.\n");
2243                 return;
2244         }
2245         printk(" failed :(.\n");
2246         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2247                 "report.  Then try booting with the 'noapic' option");
2248 }
2249
2250 /*
2251  *
2252  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2253  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2254  *   Linux doesn't really care, as it's not actually used
2255  *   for any interrupt handling anyway.
2256  */
2257 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2258
2259 void __init setup_IO_APIC(void)
2260 {
2261         enable_IO_APIC();
2262
2263         if (acpi_ioapic)
2264                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2265         else
2266                 io_apic_irqs = ~PIC_IRQS;
2267
2268         printk("ENABLING IO-APIC IRQs\n");
2269
2270         /*
2271          * Set up IO-APIC IRQ routing.
2272          */
2273         if (!acpi_ioapic)
2274                 setup_ioapic_ids_from_mpc();
2275         sync_Arb_IDs();
2276         setup_IO_APIC_irqs();
2277         init_IO_APIC_traps();
2278         check_timer();
2279         if (!acpi_ioapic)
2280                 print_IO_APIC();
2281 }
2282
2283 /*
2284  *      Called after all the initialization is done. If we didnt find any
2285  *      APIC bugs then we can allow the modify fast path
2286  */
2287
2288 static int __init io_apic_bug_finalize(void)
2289 {
2290         if(sis_apic_bug == -1)
2291                 sis_apic_bug = 0;
2292         return 0;
2293 }
2294
2295 late_initcall(io_apic_bug_finalize);
2296
2297 struct sysfs_ioapic_data {
2298         struct sys_device dev;
2299         struct IO_APIC_route_entry entry[0];
2300 };
2301 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2302
2303 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2304 {
2305         struct IO_APIC_route_entry *entry;
2306         struct sysfs_ioapic_data *data;
2307         unsigned long flags;
2308         int i;
2309
2310         data = container_of(dev, struct sysfs_ioapic_data, dev);
2311         entry = data->entry;
2312         spin_lock_irqsave(&ioapic_lock, flags);
2313         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2314                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2315                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2316         }
2317         spin_unlock_irqrestore(&ioapic_lock, flags);
2318
2319         return 0;
2320 }
2321
2322 static int ioapic_resume(struct sys_device *dev)
2323 {
2324         struct IO_APIC_route_entry *entry;
2325         struct sysfs_ioapic_data *data;
2326         unsigned long flags;
2327         union IO_APIC_reg_00 reg_00;
2328         int i;
2329
2330         data = container_of(dev, struct sysfs_ioapic_data, dev);
2331         entry = data->entry;
2332
2333         spin_lock_irqsave(&ioapic_lock, flags);
2334         reg_00.raw = io_apic_read(dev->id, 0);
2335         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2336                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2337                 io_apic_write(dev->id, 0, reg_00.raw);
2338         }
2339         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2340                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2341                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2342         }
2343         spin_unlock_irqrestore(&ioapic_lock, flags);
2344
2345         return 0;
2346 }
2347
2348 static struct sysdev_class ioapic_sysdev_class = {
2349         set_kset_name("ioapic"),
2350         .suspend = ioapic_suspend,
2351         .resume = ioapic_resume,
2352 };
2353
2354 static int __init ioapic_init_sysfs(void)
2355 {
2356         struct sys_device * dev;
2357         int i, size, error = 0;
2358
2359         error = sysdev_class_register(&ioapic_sysdev_class);
2360         if (error)
2361                 return error;
2362
2363         for (i = 0; i < nr_ioapics; i++ ) {
2364                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2365                         * sizeof(struct IO_APIC_route_entry);
2366                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2367                 if (!mp_ioapic_data[i]) {
2368                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2369                         continue;
2370                 }
2371                 memset(mp_ioapic_data[i], 0, size);
2372                 dev = &mp_ioapic_data[i]->dev;
2373                 dev->id = i;
2374                 dev->cls = &ioapic_sysdev_class;
2375                 error = sysdev_register(dev);
2376                 if (error) {
2377                         kfree(mp_ioapic_data[i]);
2378                         mp_ioapic_data[i] = NULL;
2379                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2380                         continue;
2381                 }
2382         }
2383
2384         return 0;
2385 }
2386
2387 device_initcall(ioapic_init_sysfs);
2388
2389 /* --------------------------------------------------------------------------
2390                           ACPI-based IOAPIC Configuration
2391    -------------------------------------------------------------------------- */
2392
2393 #ifdef CONFIG_ACPI_BOOT
2394
2395 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2396 {
2397         union IO_APIC_reg_00 reg_00;
2398         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2399         physid_mask_t tmp;
2400         unsigned long flags;
2401         int i = 0;
2402
2403         /*
2404          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2405          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2406          * supports up to 16 on one shared APIC bus.
2407          *
2408          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2409          *      advantage of new APIC bus architecture.
2410          */
2411
2412         if (physids_empty(apic_id_map))
2413                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2414
2415         spin_lock_irqsave(&ioapic_lock, flags);
2416         reg_00.raw = io_apic_read(ioapic, 0);
2417         spin_unlock_irqrestore(&ioapic_lock, flags);
2418
2419         if (apic_id >= get_physical_broadcast()) {
2420                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2421                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2422                 apic_id = reg_00.bits.ID;
2423         }
2424
2425         /*
2426          * Every APIC in a system must have a unique ID or we get lots of nice
2427          * 'stuck on smp_invalidate_needed IPI wait' messages.
2428          */
2429         if (check_apicid_used(apic_id_map, apic_id)) {
2430
2431                 for (i = 0; i < get_physical_broadcast(); i++) {
2432                         if (!check_apicid_used(apic_id_map, i))
2433                                 break;
2434                 }
2435
2436                 if (i == get_physical_broadcast())
2437                         panic("Max apic_id exceeded!\n");
2438
2439                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2440                         "trying %d\n", ioapic, apic_id, i);
2441
2442                 apic_id = i;
2443         }
2444
2445         tmp = apicid_to_cpu_present(apic_id);
2446         physids_or(apic_id_map, apic_id_map, tmp);
2447
2448         if (reg_00.bits.ID != apic_id) {
2449                 reg_00.bits.ID = apic_id;
2450
2451                 spin_lock_irqsave(&ioapic_lock, flags);
2452                 io_apic_write(ioapic, 0, reg_00.raw);
2453                 reg_00.raw = io_apic_read(ioapic, 0);
2454                 spin_unlock_irqrestore(&ioapic_lock, flags);
2455
2456                 /* Sanity check */
2457                 if (reg_00.bits.ID != apic_id)
2458                         panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
2459         }
2460
2461         apic_printk(APIC_VERBOSE, KERN_INFO
2462                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2463
2464         return apic_id;
2465 }
2466
2467
2468 int __init io_apic_get_version (int ioapic)
2469 {
2470         union IO_APIC_reg_01    reg_01;
2471         unsigned long flags;
2472
2473         spin_lock_irqsave(&ioapic_lock, flags);
2474         reg_01.raw = io_apic_read(ioapic, 1);
2475         spin_unlock_irqrestore(&ioapic_lock, flags);
2476
2477         return reg_01.bits.version;
2478 }
2479
2480
2481 int __init io_apic_get_redir_entries (int ioapic)
2482 {
2483         union IO_APIC_reg_01    reg_01;
2484         unsigned long flags;
2485
2486         spin_lock_irqsave(&ioapic_lock, flags);
2487         reg_01.raw = io_apic_read(ioapic, 1);
2488         spin_unlock_irqrestore(&ioapic_lock, flags);
2489
2490         return reg_01.bits.entries;
2491 }
2492
2493
2494 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2495 {
2496         struct IO_APIC_route_entry entry;
2497         unsigned long flags;
2498
2499         if (!IO_APIC_IRQ(irq)) {
2500                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2501                         ioapic);
2502                 return -EINVAL;
2503         }
2504
2505         /*
2506          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2507          * Note that we mask (disable) IRQs now -- these get enabled when the
2508          * corresponding device driver registers for this IRQ.
2509          */
2510
2511         memset(&entry,0,sizeof(entry));
2512
2513         entry.delivery_mode = INT_DELIVERY_MODE;
2514         entry.dest_mode = INT_DEST_MODE;
2515         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2516         entry.trigger = edge_level;
2517         entry.polarity = active_high_low;
2518         entry.mask  = 1;
2519
2520         /*
2521          * IRQs < 16 are already in the irq_2_pin[] map
2522          */
2523         if (irq >= 16)
2524                 add_pin_to_irq(irq, ioapic, pin);
2525
2526         entry.vector = assign_irq_vector(irq);
2527
2528         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2529                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2530                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2531                 edge_level, active_high_low);
2532
2533         ioapic_register_intr(irq, entry.vector, edge_level);
2534
2535         if (!ioapic && (irq < 16))
2536                 disable_8259A_irq(irq);
2537
2538         spin_lock_irqsave(&ioapic_lock, flags);
2539         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2540         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2541         spin_unlock_irqrestore(&ioapic_lock, flags);
2542
2543         return 0;
2544 }
2545
2546 #endif /*CONFIG_ACPI_BOOT*/