2 * Device driver for the via ADB on (many) Mac II-class machines
4 * Based on the original ADB keyboard handler Copyright (c) 1997 Alan Cox
5 * Also derived from code Copyright (C) 1996 Paul Mackerras.
7 * With various updates provided over the years by Michael Schmitz,
8 * Guideo Koerber and others.
10 * Rewrite for Unified ADB by Joshua M. Thompson (funaho@jurai.org)
12 * 1999-08-02 (jmt) - Initial rewrite for Unified ADB.
13 * 2000-03-29 Tony Mantler <tonym@mac.linux-m68k.org>
14 * - Big overhaul, should actually work now.
15 * 2006-12-31 Finn Thain <fthain@telegraphics.com.au> - Another overhaul.
18 * Inside Macintosh, ch. 5 ADB Manager
19 * Guide to the Macinstosh Family Hardware, ch. 8 Apple Desktop Bus
20 * Rockwell R6522 VIA datasheet
22 * Apple's "ADB Analyzer" bus sniffer is invaluable:
23 * ftp://ftp.apple.com/developer/Tool_Chest/Devices_-_Hardware/Apple_Desktop_Bus/
27 #include <linux/types.h>
28 #include <linux/errno.h>
29 #include <linux/kernel.h>
30 #include <linux/delay.h>
31 #include <linux/adb.h>
32 #include <linux/interrupt.h>
33 #include <linux/init.h>
34 #include <asm/macintosh.h>
35 #include <asm/macints.h>
36 #include <asm/machw.h>
37 #include <asm/mac_via.h>
38 #include <asm/system.h>
40 static volatile unsigned char *via;
42 /* VIA registers - spaced 0x200 bytes apart */
43 #define RS 0x200 /* skip between registers */
44 #define B 0 /* B-side data */
45 #define A RS /* A-side data */
46 #define DIRB (2*RS) /* B-side direction (1=output) */
47 #define DIRA (3*RS) /* A-side direction (1=output) */
48 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
49 #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */
50 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
51 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
52 #define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */
53 #define T2CH (9*RS) /* Timer 2 counter (high 8 bits) */
54 #define SR (10*RS) /* Shift register */
55 #define ACR (11*RS) /* Auxiliary control register */
56 #define PCR (12*RS) /* Peripheral control register */
57 #define IFR (13*RS) /* Interrupt flag register */
58 #define IER (14*RS) /* Interrupt enable register */
59 #define ANH (15*RS) /* A-side data, no handshake */
61 /* Bits in B data register: all active low */
62 #define CTLR_IRQ 0x08 /* Controller rcv status (input) */
63 #define ST_MASK 0x30 /* mask for selecting ADB state bits */
66 #define SR_CTRL 0x1c /* Shift register control bits */
67 #define SR_EXT 0x0c /* Shift on external clock */
68 #define SR_OUT 0x10 /* Shift out if 1 */
70 /* Bits in IFR and IER */
71 #define IER_SET 0x80 /* set bits in IER */
72 #define IER_CLR 0 /* clear bits in IER */
73 #define SR_INT 0x04 /* Shift register full/empty */
75 /* ADB transaction states according to GMHW */
76 #define ST_CMD 0x00 /* ADB state: command byte */
77 #define ST_EVEN 0x10 /* ADB state: even data byte */
78 #define ST_ODD 0x20 /* ADB state: odd data byte */
79 #define ST_IDLE 0x30 /* ADB state: idle, nothing to send */
81 static int macii_init_via(void);
82 static void macii_start(void);
83 static irqreturn_t macii_interrupt(int irq, void *arg);
84 static void macii_queue_poll(void);
86 static int macii_probe(void);
87 static int macii_init(void);
88 static int macii_send_request(struct adb_request *req, int sync);
89 static int macii_write(struct adb_request *req);
90 static int macii_autopoll(int devs);
91 static void macii_poll(void);
92 static int macii_reset_bus(void);
94 struct adb_driver via_macii_driver = {
104 static enum macii_state {
111 static struct adb_request *current_req; /* first request struct in the queue */
112 static struct adb_request *last_req; /* last request struct in the queue */
113 static unsigned char reply_buf[16]; /* storage for autopolled replies */
114 static unsigned char *reply_ptr; /* next byte in req->data or reply_buf */
115 static int reading_reply; /* store reply in reply_buf else req->reply */
116 static int data_index; /* index of the next byte to send from req->data */
117 static int reply_len; /* number of bytes received in reply_buf or req->reply */
118 static int status; /* VIA's ADB status bits captured upon interrupt */
119 static int last_status; /* status bits as at previous interrupt */
120 static int srq_asserted; /* have to poll for the device that asserted it */
121 static int command_byte; /* the most recent command byte transmitted */
122 static int autopoll_devs; /* bits set are device addresses to be polled */
124 /* Sanity check for request queue. Doesn't check for cycles. */
125 static int request_is_queued(struct adb_request *req) {
126 struct adb_request *cur;
128 local_irq_save(flags);
132 local_irq_restore(flags);
137 local_irq_restore(flags);
141 /* Check for MacII style ADB */
142 static int macii_probe(void)
144 if (macintosh_config->adb_type != MAC_ADB_II) return -ENODEV;
148 printk("adb: Mac II ADB Driver v1.0 for Unified ADB\n");
152 /* Initialize the driver */
158 local_irq_save(flags);
160 err = macii_init_via();
163 err = request_irq(IRQ_MAC_ADB, macii_interrupt, IRQ_FLG_LOCK, "ADB",
169 local_irq_restore(flags);
173 /* initialize the hardware */
174 static int macii_init_via(void)
178 /* We want CTLR_IRQ as input and ST_EVEN | ST_ODD as output lines. */
179 via[DIRB] = (via[DIRB] | ST_EVEN | ST_ODD) & ~CTLR_IRQ;
181 /* Set up state: idle */
183 last_status = via[B] & (ST_MASK|CTLR_IRQ);
185 /* Shift register on input */
186 via[ACR] = (via[ACR] & ~SR_CTRL) | SR_EXT;
188 /* Wipe any pending data and int */
194 /* Send an ADB poll (Talk Register 0 command prepended to the request queue) */
195 static void macii_queue_poll(void)
197 /* No point polling the active device as it will never assert SRQ, so
198 * poll the next device in the autopoll list. This could leave us
199 * stuck in a polling loop if an unprobed device is asserting SRQ.
200 * In theory, that could only happen if a device was plugged in after
201 * probing started. Unplugging it again will break the cycle.
202 * (Simply polling the next higher device often ends up polling almost
203 * every device (after wrapping around), which takes too long.)
207 static struct adb_request req;
209 if (!autopoll_devs) return;
211 device_mask = (1 << (((command_byte & 0xF0) >> 4) + 1)) - 1;
212 if (autopoll_devs & ~device_mask)
213 next_device = ffs(autopoll_devs & ~device_mask) - 1;
215 next_device = ffs(autopoll_devs) - 1;
217 BUG_ON(request_is_queued(&req));
219 adb_request(&req, NULL, ADBREQ_NOSEND, 1,
220 ADB_READREG(next_device, 0));
225 req.next = current_req;
227 if (current_req != NULL) {
235 /* Send an ADB request; if sync, poll out the reply 'till it's done */
236 static int macii_send_request(struct adb_request *req, int sync)
241 BUG_ON(request_is_queued(req));
243 local_irq_save(flags);
244 err = macii_write(req);
245 local_irq_restore(flags);
248 while (!req->complete) {
251 BUG_ON(request_is_queued(req));
257 /* Send an ADB request (append to request queue) */
258 static int macii_write(struct adb_request *req)
260 if (req->nbytes < 2 || req->data[0] != ADB_PACKET || req->nbytes > 15) {
270 if (current_req != NULL) {
271 last_req->next = req;
276 if (macii_state == idle) macii_start();
281 /* Start auto-polling */
282 static int macii_autopoll(int devs)
284 static struct adb_request req;
288 /* bit 1 == device 1, and so on. */
289 autopoll_devs = devs & 0xFFFE;
291 if (!autopoll_devs) return 0;
293 local_irq_save(flags);
295 if (current_req == NULL) {
296 /* Send a Talk Reg 0. The controller will repeatedly transmit
297 * this as long as it is idle.
299 adb_request(&req, NULL, ADBREQ_NOSEND, 1,
300 ADB_READREG(ffs(autopoll_devs) - 1, 0));
301 err = macii_write(&req);
304 local_irq_restore(flags);
308 static inline int need_autopoll(void) {
309 /* Was the last command Talk Reg 0
310 * and is the target on the autopoll list?
312 if ((command_byte & 0x0F) == 0x0C &&
313 ((1 << ((command_byte & 0xF0) >> 4)) & autopoll_devs))
318 /* Prod the chip without interrupts */
319 static void macii_poll(void)
321 disable_irq(IRQ_MAC_ADB);
322 macii_interrupt(0, NULL);
323 enable_irq(IRQ_MAC_ADB);
327 static int macii_reset_bus(void)
329 static struct adb_request req;
331 if (request_is_queued(&req))
334 /* Command = 0, Address = ignored */
335 adb_request(&req, NULL, 0, 1, ADB_BUSRESET);
337 /* Don't want any more requests during the Global Reset low time. */
343 /* Start sending ADB packet */
344 static void macii_start(void)
346 struct adb_request *req;
352 BUG_ON(macii_state != idle);
354 /* Now send it. Be careful though, that first byte of the request
355 * is actually ADB_PACKET; the real data begins at index 1!
356 * And req->nbytes is the number of bytes of real data plus one.
359 /* store command byte */
360 command_byte = req->data[1];
364 via[SR] = req->data[1];
365 /* set ADB state to 'command' */
366 via[B] = (via[B] & ~ST_MASK) | ST_CMD;
368 macii_state = sending;
373 * The notorious ADB interrupt handler - does all of the protocol handling.
374 * Relies on the ADB controller sending and receiving data, thereby
375 * generating shift register interrupts (SR_INT) for us. This means there has
376 * to be activity on the ADB bus. The chip will poll to achieve this.
378 * The basic ADB state machine was left unchanged from the original MacII code
379 * by Alan Cox, which was based on the CUDA driver for PowerMac.
380 * The syntax of the ADB status lines is totally different on MacII,
381 * though. MacII uses the states Command -> Even -> Odd -> Even ->...-> Idle
382 * for sending and Idle -> Even -> Odd -> Even ->...-> Idle for receiving.
383 * Start and end of a receive packet are signalled by asserting /IRQ on the
384 * interrupt line (/IRQ means the CTLR_IRQ bit in port B; not to be confused
385 * with the VIA shift register interrupt. /IRQ never actually interrupts the
386 * processor, it's just an ordinary input.)
388 static irqreturn_t macii_interrupt(int irq, void *arg)
392 struct adb_request *req;
395 /* Clear the SR IRQ flag when polling. */
396 if (via[IFR] & SR_INT)
404 last_status = status;
405 status = via[B] & (ST_MASK|CTLR_IRQ);
407 switch (macii_state) {
410 reply_ptr = current_req->reply;
412 BUG_ON(current_req != NULL);
413 reply_ptr = reply_buf;
418 if ((status & CTLR_IRQ) && (x == 0xFF)) {
419 /* Bus timeout without SRQ sequence:
420 * data is "FF" while CTLR_IRQ is "H"
424 macii_state = read_done;
426 macii_state = reading;
431 /* set ADB state = even for first data byte */
432 via[B] = (via[B] & ~ST_MASK) | ST_EVEN;
437 if (data_index >= req->nbytes) {
441 if (req->reply_expected) {
445 current_req = req->next;
446 if (req->done) (*req->done)(req);
452 macii_autopoll(autopoll_devs);
455 if (macii_state == idle) {
456 /* reset to shift in */
459 /* set ADB state idle - might get SRQ */
460 via[B] = (via[B] & ~ST_MASK) | ST_IDLE;
463 via[SR] = req->data[data_index++];
465 if ( (via[B] & ST_MASK) == ST_CMD ) {
466 /* just sent the command byte, set to EVEN */
467 via[B] = (via[B] & ~ST_MASK) | ST_EVEN;
469 /* invert state bits, toggle ODD/EVEN */
477 BUG_ON((status & ST_MASK) == ST_CMD ||
478 (status & ST_MASK) == ST_IDLE);
480 /* Bus timeout with SRQ sequence:
481 * data is "XX FF" while CTLR_IRQ is "L L"
482 * End of packet without SRQ sequence:
483 * data is "XX...YY 00" while CTLR_IRQ is "L...H L"
484 * End of packet SRQ sequence:
485 * data is "XX...YY 00" while CTLR_IRQ is "L...L L"
486 * (where XX is the first response byte and
487 * YY is the last byte of valid response data.)
491 if (!(status & CTLR_IRQ)) {
493 if (!(last_status & CTLR_IRQ)) {
494 macii_state = read_done;
498 } else if (x == 0x00) {
499 macii_state = read_done;
500 if (!(last_status & CTLR_IRQ))
505 if (macii_state == reading) {
506 BUG_ON(reply_len > 15);
512 /* invert state bits, toggle ODD/EVEN */
522 req->reply_len = reply_len;
524 current_req = req->next;
525 if (req->done) (*req->done)(req);
526 } else if (reply_len && autopoll_devs)
527 adb_input(reply_buf, reply_len, 0);
531 /* SRQ seen before, initiate poll now */
539 macii_autopoll(autopoll_devs);
541 if (macii_state == idle)
542 via[B] = (via[B] & ~ST_MASK) | ST_IDLE;