2 This is part of rtl8180 OpenSource driver.
3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public Licence)
6 Parts of this driver are based on the GPL part of the
7 official Realtek driver.
8 Parts of this driver are based on the rtl8180 driver skeleton
9 from Patric Schenke & Andres Salomon.
10 Parts of this driver are based on the Intel Pro Wireless
13 We want to tanks the Authors of those projects
14 and the Ndiswrapper project Authors.
17 /* Mariusz Matuszek added full registers definition with Realtek's name */
19 /* this file contains register definitions for the rtl8180 MAC controller */
23 #define CONFIG_RTL8185B //support for rtl8185B, xiong-2006-11-15
24 #define CONFIG_RTL818X_S
26 #define BIT0 0x00000001
27 #define BIT1 0x00000002
28 #define BIT2 0x00000004
29 #define BIT3 0x00000008
30 #define BIT4 0x00000010
31 #define BIT5 0x00000020
32 #define BIT6 0x00000040
33 #define BIT7 0x00000080
34 #define BIT8 0x00000100
35 #define BIT9 0x00000200
36 #define BIT10 0x00000400
37 #define BIT11 0x00000800
38 #define BIT12 0x00001000
39 #define BIT13 0x00002000
40 #define BIT14 0x00004000
41 #define BIT15 0x00008000
42 #define BIT16 0x00010000
43 #define BIT17 0x00020000
44 #define BIT18 0x00040000
45 #define BIT19 0x00080000
46 #define BIT20 0x00100000
47 #define BIT21 0x00200000
48 #define BIT22 0x00400000
49 #define BIT23 0x00800000
50 #define BIT24 0x01000000
51 #define BIT25 0x02000000
52 #define BIT26 0x04000000
53 #define BIT27 0x08000000
54 #define BIT28 0x10000000
55 #define BIT29 0x20000000
56 #define BIT30 0x40000000
57 #define BIT31 0x80000000
59 #define MAX_SLEEP_TIME (10000)
60 #define MIN_SLEEP_TIME (50)
62 #define BB_ANTATTEN_CHAN14 0x0c
63 #define BB_ANTENNA_B 0x40
65 #define BB_HOST_BANG (1<<30)
66 #define BB_HOST_BANG_EN (1<<2)
67 #define BB_HOST_BANG_CLK (1<<1)
68 #define BB_HOST_BANG_DATA 1
70 #define ANAPARAM_TXDACOFF_SHIFT 27
71 #define ANAPARAM_PWR0_MASK ((1<<30)|(1<<29)|(1<<28))
72 #define ANAPARAM_PWR0_SHIFT 28
73 #define ANAPARAM_PWR1_MASK ((1<<26)|(1<<25)|(1<<24)|(1<<23)|(1<<22)|(1<<21)|(1<<20))
74 #define ANAPARAM_PWR1_SHIFT 20
83 #define CMD_RST_SHIFT 4
84 #define CMD_RESERVED_MASK ((1<<1) | (1<<5) | (1<<6) | (1<<7))
85 #define CMD_RX_ENABLE_SHIFT 3
86 #define CMD_TX_ENABLE_SHIFT 2
88 #define EPROM_CMD 0x50
89 #define EPROM_CMD_RESERVED_MASK ((1<<5)|(1<<4))
90 #define EPROM_CMD_OPERATING_MODE_SHIFT 6
91 #define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
92 #define EPROM_CMD_CONFIG 0x3
93 #define EPROM_CMD_NORMAL 0
94 #define EPROM_CMD_LOAD 1
95 #define EPROM_CMD_PROGRAM 2
96 #define EPROM_CS_SHIFT 3
97 #define EPROM_CK_SHIFT 2
98 #define EPROM_W_SHIFT 1
99 #define EPROM_R_SHIFT 0
100 #define CONFIG2_DMA_POLLING_MODE_SHIFT 3
102 #define INTA_TXOVERFLOW (1<<15)
103 #define INTA_TIMEOUT (1<<14)
104 #define INTA_BEACONTIMEOUT (1<<13)
105 #define INTA_ATIM (1<<12)
106 #define INTA_BEACONDESCERR (1<<11)
107 #define INTA_BEACONDESCOK (1<<10)
108 #define INTA_HIPRIORITYDESCERR (1<<9)
109 #define INTA_HIPRIORITYDESCOK (1<<8)
110 #define INTA_NORMPRIORITYDESCERR (1<<7)
111 #define INTA_NORMPRIORITYDESCOK (1<<6)
112 #define INTA_RXOVERFLOW (1<<5)
113 #define INTA_RXDESCERR (1<<4)
114 #define INTA_LOWPRIORITYDESCERR (1<<3)
115 #define INTA_LOWPRIORITYDESCOK (1<<2)
116 #define INTA_RXCRCERR (1<<1)
117 #define INTA_RXOK (1)
118 #define INTA_MASK 0x3c
119 #define RXRING_ADDR 0xe4 // page 0
120 #define PGSELECT 0x5e
121 #define PGSELECT_PG_SHIFT 0
123 #define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \
124 (1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23))
125 #define RX_CHECK_BSSID_SHIFT 23
126 #define ACCEPT_PWR_FRAME_SHIFT 22
127 #define ACCEPT_MNG_FRAME_SHIFT 20
128 #define ACCEPT_CTL_FRAME_SHIFT 19
129 #define ACCEPT_DATA_FRAME_SHIFT 18
130 #define ACCEPT_ICVERR_FRAME_SHIFT 12
131 #define ACCEPT_CRCERR_FRAME_SHIFT 5
132 #define ACCEPT_BCAST_FRAME_SHIFT 3
133 #define ACCEPT_MCAST_FRAME_SHIFT 2
134 #define ACCEPT_ALLMAC_FRAME_SHIFT 0
135 #define ACCEPT_NICMAC_FRAME_SHIFT 1
136 #define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15))
137 #define RX_FIFO_THRESHOLD_SHIFT 13
138 #define RX_FIFO_THRESHOLD_128 3
139 #define RX_FIFO_THRESHOLD_256 4
140 #define RX_FIFO_THRESHOLD_512 5
141 #define RX_FIFO_THRESHOLD_1024 6
142 #define RX_FIFO_THRESHOLD_NONE 7
143 #define RX_AUTORESETPHY_SHIFT 28
144 #define EPROM_TYPE_SHIFT 6
146 #define TX_CONF_HEADER_AUTOICREMENT_SHIFT 30
147 #define TX_LOOPBACK_SHIFT 17
148 #define TX_LOOPBACK_MAC 1
149 #define TX_LOOPBACK_BASEBAND 2
150 #define TX_LOOPBACK_NONE 0
151 #define TX_LOOPBACK_CONTINUE 3
152 #define TX_LOOPBACK_MASK ((1<<17)|(1<<18))
153 #define TX_DPRETRY_SHIFT 0
154 #define R8180_MAX_RETRY 255
155 #define TX_RTSRETRY_SHIFT 8
156 #define TX_NOICV_SHIFT 19
157 #define TX_NOCRC_SHIFT 16
158 #define TX_DMA_POLLING 0xd9
159 #define TX_DMA_POLLING_BEACON_SHIFT 7
160 #define TX_DMA_POLLING_HIPRIORITY_SHIFT 6
161 #define TX_DMA_POLLING_NORMPRIORITY_SHIFT 5
162 #define TX_DMA_POLLING_LOWPRIORITY_SHIFT 4
163 #define TX_DMA_STOP_BEACON_SHIFT 3
164 #define TX_DMA_STOP_HIPRIORITY_SHIFT 2
165 #define TX_DMA_STOP_NORMPRIORITY_SHIFT 1
166 #define TX_DMA_STOP_LOWPRIORITY_SHIFT 0
167 #define TX_MANAGEPRIORITY_RING_ADDR 0x0C
168 #define TX_BKPRIORITY_RING_ADDR 0x10
169 #define TX_BEPRIORITY_RING_ADDR 0x14
170 #define TX_VIPRIORITY_RING_ADDR 0x20
171 #define TX_VOPRIORITY_RING_ADDR 0x24
172 #define TX_HIGHPRIORITY_RING_ADDR 0x28
173 //AC_VI and Low priority share the sane queue
174 #define TX_LOWPRIORITY_RING_ADDR TX_VIPRIORITY_RING_ADDR
175 //AC_VO and Norm priority share the same queue
176 #define TX_NORMPRIORITY_RING_ADDR TX_VOPRIORITY_RING_ADDR
178 #define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10))
179 #define MAX_RX_DMA_2048 7
180 #define MAX_RX_DMA_1024 6
181 #define MAX_RX_DMA_SHIFT 10
182 #define INT_TIMEOUT 0x48
183 #define CONFIG3_CLKRUN_SHIFT 2
184 #define CONFIG3_ANAPARAM_W_SHIFT 6
185 #define ANAPARAM 0x54
186 #define BEACON_INTERVAL 0x70
187 #define BEACON_INTERVAL_MASK ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)| \
188 (1<<6)|(1<<7)|(1<<8)|(1<<9))
189 #define ATIM_MASK ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)| \
192 #define EPROM_CS_SHIFT 3
193 #define EPROM_CK_SHIFT 2
194 #define PHY_DELAY 0x78
195 #define PHY_CONFIG 0x80
197 #define PHY_READ 0x7e
198 #define CARRIER_SENSE_COUNTER 0x79 //byte
199 #define SECURITY 0x5f //1209 this is sth wrong
200 #define SECURITY_WEP_TX_ENABLE_SHIFT 1
201 #define SECURITY_WEP_RX_ENABLE_SHIFT 0
202 #define SECURITY_ENCRYP_104 1
203 #define SECURITY_ENCRYP_SHIFT 4
204 #define SECURITY_ENCRYP_MASK ((1<<4)|(1<<5))
205 #define KEY0 0x90 //1209 this is sth wrong
206 #define CONFIG2_ANTENNA_SHIFT 6
207 #define TX_BEACON_RING_ADDR 0x4c
208 #define CONFIG0_WEP40_SHIFT 7
209 #define CONFIG0_WEP104_SHIFT 6
210 #define AGCRESET_SHIFT 5
215 * Operational registers offsets in PCI (I/O) space.
216 * RealTek names are used.
226 /* 0x0006 - 0x0007 - reserved */
237 /* 0x0010 - 0x0017 - reserved */
240 #define TSFTR_END 0x001F
243 #define TLPDA_END 0x0023
245 #define TNPDA_END 0x0027
247 #define THPDA_END 0x002B
250 #define BSSID_END 0x0033
254 #ifdef CONFIG_RTL8185B
255 #define RF_SW_CONFIG 0x8 // store data which is transmitted to RF for driver
256 #define RF_SW_CFG_SI BIT1
257 #define PIFS 0x2C // PCF InterFrame Spacing Timer Setting.
258 #define EIFS 0x2D // Extended InterFrame Space Timer, in unit of 4 us.
260 #define BRSR 0x34 // Basic rate set
266 #define BRSR_END 0x002D
268 /* 0x0034 - 0x0034 - reserved */
272 #define IMR_END 0x003D
274 #define ISR_END 0x003F
278 #define TCR_END 0x0043
281 #define RCR_END 0x0047
283 #define TimerInt 0x0048
284 #define TimerInt_END 0x004B
287 #define TBDA_END 0x004F
289 #define CR9346 0x0050
291 #define CONFIG0 0x0051
292 #define CONFIG1 0x0052
293 #define CONFIG2 0x0053
295 #define ANA_PARM 0x0054
296 #define ANA_PARM_END 0x0x0057
300 #define CONFIG3 0x0059
301 #define CONFIG4 0x005A
302 #ifdef CONFIG_RTL8185B
303 #ifdef CONFIG_RTL818X_S
304 // SD3 szuyitasi: Mac0x57= CC -> B0 Mac0x60= D1 -> C6
305 // Mac0x60 = 0x000004C6 power save parameters
306 #define ANAPARM_ASIC_ON 0xB0054D00
307 #define ANAPARM2_ASIC_ON 0x000004C6
309 #define ANAPARM_ON ANAPARM_ASIC_ON
310 #define ANAPARM2_ON ANAPARM2_ASIC_ON
313 #define ANAPARM_ASIC_ON 0x45090658
314 #define ANAPARM2_ASIC_ON 0x727f3f52
316 #define ANAPARM_ON ANAPARM_ASIC_ON
317 #define ANAPARM2_ON ANAPARM2_ASIC_ON
323 /* 0x005C - 0x005D - reserved */
327 /* 0x0060 - 0x006F - reserved */
329 #define BcnItv 0x0070
330 #define BcnItv_END 0x0071
332 #define AtimWnd 0x0072
333 #define AtimWnd_END 0x0073
335 #define BintrItv 0x0074
336 #define BintrItv_END 0x0075
338 #define AtimtrItv 0x0076
339 #define AtimtrItv_END 0x0077
341 #define PhyDelay 0x0078
343 #define CRCount 0x0079
345 /* 0x007A - 0x007B - reserved */
347 #define PhyAddr 0x007C
348 #define PhyDataW 0x007D
349 #define PhyDataR 0x007E
351 #define PhyCFG 0x0080
352 #define PhyCFG_END 0x0083
354 /* following are for rtl8185 */
355 #define RFPinsOutput 0x80
356 #define RFPinsEnable 0x82
357 #define RF_TIMING 0x8c
358 #define RFPinsSelect 0x84
359 #define ANAPARAM2 0x60
361 #define RFPinsInput 0x86
362 #define GP_ENABLE 0x90
364 #define SW_CONTROL_GPIO 0x400
365 #define TX_ANTENNA 0x9f
366 #define TX_GAIN_OFDM 0x9e
367 #define TX_GAIN_CCK 0x9d
368 #define WPA_CONFIG 0xb0
369 #define TX_AGC_CTL 0x9c
370 #define TX_AGC_CTL_PERPACKET_GAIN_SHIFT 0
371 #define TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT 1
372 #define TX_AGC_CTL_FEEDBACK_ANT 2
373 #define RESP_RATE 0x34
379 #define CW_CONF_PERPACKET_RETRY_SHIFT 1
380 #define CW_CONF_PERPACKET_CW_SHIFT 0
382 #define MAX_RESP_RATE_SHIFT 4
383 #define MIN_RESP_RATE_SHIFT 0
384 #define RATE_FALLBACK 0xbe
386 * 0x0084 - 0x00D3 is selected to page 1 when PSEn bit (bit0, PSR)
390 #define Wakeup0 0x0084
391 #define Wakeup0_END 0x008B
393 #define Wakeup1 0x008C
394 #define Wakeup1_END 0x0093
396 #define Wakeup2LD 0x0094
397 #define Wakeup2LD_END 0x009B
398 #define Wakeup2HD 0x009C
399 #define Wakeup2HD_END 0x00A3
401 #define Wakeup3LD 0x00A4
402 #define Wakeup3LD_END 0x00AB
403 #define Wakeup3HD 0x00AC
404 #define Wakeup3HD_END 0x00B3
406 #define Wakeup4LD 0x00B4
407 #define Wakeup4LD_END 0x00BB
408 #define Wakeup4HD 0x00BC
409 #define Wakeup4HD_END 0x00C3
412 #define CRC0_END 0x00C5
414 #define CRC1_END 0x00C7
416 #define CRC2_END 0x00C9
418 #define CRC3_END 0x00CB
420 #define CRC4_END 0x00CD
422 /* 0x00CE - 0x00D3 - reserved */
427 * 0x0084 - 0x00D3 is selected to page 0 when PSEn bit (bit0, PSR)
431 /* 0x0084 - 0x008F - reserved */
434 #define DK0_END 0x009F
436 #define DK1_END 0x00AF
438 #define DK2_END 0x00BF
440 #define DK3_END 0x00CF
442 /* 0x00D0 - 0x00D3 - reserved */
448 /* 0x00D4 - 0x00D7 - reserved */
450 #define CONFIG5 0x00D8
452 #define TPPoll 0x00D9
454 /* 0x00DA - 0x00DB - reserved */
456 #ifdef CONFIG_RTL818X_S
457 #define PHYPR 0xDA //0xDA - 0x0B PHY Parameter Register.
461 #define CWR_END 0x00DD
463 #define RetryCTR 0x00DE
465 /* 0x00DF - 0x00E3 - reserved */
468 #define RDSAR_END 0x00E7
470 /* 0x00E8 - 0x00EF - reserved */
471 #ifdef CONFIG_RTL818X_S
472 #define LED_CONTROL 0xED
476 #define FER_END 0x00F3
478 #ifdef CONFIG_RTL8185B
479 #define FEMR 0x1D4 // Function Event Mask register
482 #define FEMR_END 0x00F7
486 #define FPSR_END 0x00FB
489 #define FFER_END 0x00FF
494 * Bitmasks for specific register functions.
495 * Names are derived from the register name and function name.
497 * <REGISTER>_<FUNCTION>[<bit>]
499 * this leads to some awkward names...
502 #define BRSR_BPLCP ((1<< 8))
503 #define BRSR_MBR ((1<< 1)|(1<< 0))
504 #define BRSR_MBR_8185 ((1<< 11)|(1<< 10)|(1<< 9)|(1<< 8)|(1<< 7)|(1<< 6)|(1<< 5)|(1<< 4)|(1<< 3)|(1<< 2)|(1<< 1)|(1<< 0))
505 #define BRSR_MBR0 ((1<< 0))
506 #define BRSR_MBR1 ((1<< 1))
508 #define CR_RST ((1<< 4))
509 #define CR_RE ((1<< 3))
510 #define CR_TE ((1<< 2))
511 #define CR_MulRW ((1<< 0))
513 #ifdef CONFIG_RTL8185B
514 #define IMR_Dot11hInt ((1<< 25)) // 802.11h Measurement Interrupt
515 #define IMR_BcnDmaInt ((1<< 24)) // Beacon DMA Interrupt // What differenct between BcnDmaInt and BcnInt???
516 #define IMR_WakeInt ((1<< 23)) // Wake Up Interrupt
517 #define IMR_TXFOVW ((1<< 22)) // Tx FIFO Overflow Interrupt
518 #define IMR_TimeOut1 ((1<< 21)) // Time Out Interrupt 1
519 #define IMR_BcnInt ((1<< 20)) // Beacon Time out Interrupt
520 #define IMR_ATIMInt ((1<< 19)) // ATIM Time Out Interrupt
521 #define IMR_TBDER ((1<< 18)) // Tx Beacon Descriptor Error Interrupt
522 #define IMR_TBDOK ((1<< 17)) // Tx Beacon Descriptor OK Interrupt
523 #define IMR_THPDER ((1<< 16)) // Tx High Priority Descriptor Error Interrupt
524 #define IMR_THPDOK ((1<< 15)) // Tx High Priority Descriptor OK Interrupt
525 #define IMR_TVODER ((1<< 14)) // Tx AC_VO Descriptor Error Interrupt
526 #define IMR_TVODOK ((1<< 13)) // Tx AC_VO Descriptor OK Interrupt
527 #define IMR_FOVW ((1<< 12)) // Rx FIFO Overflow Interrupt
528 #define IMR_RDU ((1<< 11)) // Rx Descriptor Unavailable Interrupt
529 #define IMR_TVIDER ((1<< 10)) // Tx AC_VI Descriptor Error Interrupt
530 #define IMR_TVIDOK ((1<< 9)) // Tx AC_VI Descriptor OK Interrupt
531 #define IMR_RER ((1<< 8)) // Rx Error Interrupt
532 #define IMR_ROK ((1<< 7)) // Receive OK Interrupt
533 #define IMR_TBEDER ((1<< 6)) // Tx AC_BE Descriptor Error Interrupt
534 #define IMR_TBEDOK ((1<< 5)) // Tx AC_BE Descriptor OK Interrupt
535 #define IMR_TBKDER ((1<< 4)) // Tx AC_BK Descriptor Error Interrupt
536 #define IMR_TBKDOK ((1<< 3)) // Tx AC_BK Descriptor OK Interrupt
537 #define IMR_RQoSOK ((1<< 2)) // Rx QoS OK Interrupt
538 #define IMR_TimeOut2 ((1<< 1)) // Time Out Interrupt 2
539 #define IMR_TimeOut3 ((1<< 0)) // Time Out Interrupt 3
540 #define IMR_TMGDOK ((1<<30))
541 #define ISR_Dot11hInt ((1<< 25)) // 802.11h Measurement Interrupt
542 #define ISR_BcnDmaInt ((1<< 24)) // Beacon DMA Interrupt // What differenct between BcnDmaInt and BcnInt???
543 #define ISR_WakeInt ((1<< 23)) // Wake Up Interrupt
544 #define ISR_TXFOVW ((1<< 22)) // Tx FIFO Overflow Interrupt
545 #define ISR_TimeOut1 ((1<< 21)) // Time Out Interrupt 1
546 #define ISR_BcnInt ((1<< 20)) // Beacon Time out Interrupt
547 #define ISR_ATIMInt ((1<< 19)) // ATIM Time Out Interrupt
548 #define ISR_TBDER ((1<< 18)) // Tx Beacon Descriptor Error Interrupt
549 #define ISR_TBDOK ((1<< 17)) // Tx Beacon Descriptor OK Interrupt
550 #define ISR_THPDER ((1<< 16)) // Tx High Priority Descriptor Error Interrupt
551 #define ISR_THPDOK ((1<< 15)) // Tx High Priority Descriptor OK Interrupt
552 #define ISR_TVODER ((1<< 14)) // Tx AC_VO Descriptor Error Interrupt
553 #define ISR_TVODOK ((1<< 13)) // Tx AC_VO Descriptor OK Interrupt
554 #define ISR_FOVW ((1<< 12)) // Rx FIFO Overflow Interrupt
555 #define ISR_RDU ((1<< 11)) // Rx Descriptor Unavailable Interrupt
556 #define ISR_TVIDER ((1<< 10)) // Tx AC_VI Descriptor Error Interrupt
557 #define ISR_TVIDOK ((1<< 9)) // Tx AC_VI Descriptor OK Interrupt
558 #define ISR_RER ((1<< 8)) // Rx Error Interrupt
559 #define ISR_ROK ((1<< 7)) // Receive OK Interrupt
560 #define ISR_TBEDER ((1<< 6)) // Tx AC_BE Descriptor Error Interrupt
561 #define ISR_TBEDOK ((1<< 5)) // Tx AC_BE Descriptor OK Interrupt
562 #define ISR_TBKDER ((1<< 4)) // Tx AC_BK Descriptor Error Interrupt
563 #define ISR_TBKDOK ((1<< 3)) // Tx AC_BK Descriptor OK Interrupt
564 #define ISR_RQoSOK ((1<< 2)) // Rx QoS OK Interrupt
565 #define ISR_TimeOut2 ((1<< 1)) // Time Out Interrupt 2
566 #define ISR_TimeOut3 ((1<< 0)) // Time Out Interrupt 3
568 //these definition is used for Tx/Rx test temporarily
569 #define ISR_TLPDER ISR_TVIDER
570 #define ISR_TLPDOK ISR_TVIDOK
571 #define ISR_TNPDER ISR_TVODER
572 #define ISR_TNPDOK ISR_TVODOK
573 #define ISR_TimeOut ISR_TimeOut1
574 #define ISR_RXFOVW ISR_FOVW
577 #define IMR_TXFOVW ((1<<15))
578 #define IMR_TimeOut ((1<<14))
579 #define IMR_BcnInt ((1<<13))
580 #define IMR_ATIMInt ((1<<12))
581 #define IMR_TBDER ((1<<11))
582 #define IMR_TBDOK ((1<<10))
583 #define IMR_THPDER ((1<< 9))
584 #define IMR_THPDOK ((1<< 8))
585 #define IMR_TNPDER ((1<< 7))
586 #define IMR_TNPDOK ((1<< 6))
587 #define IMR_RXFOVW ((1<< 5))
588 #define IMR_RDU ((1<< 4))
589 #define IMR_TLPDER ((1<< 3))
590 #define IMR_TLPDOK ((1<< 2))
591 #define IMR_RER ((1<< 1))
592 #define IMR_ROK ((1<< 0))
594 #define ISR_TXFOVW ((1<<15))
595 #define ISR_TimeOut ((1<<14))
596 #define ISR_BcnInt ((1<<13))
597 #define ISR_ATIMInt ((1<<12))
598 #define ISR_TBDER ((1<<11))
599 #define ISR_TBDOK ((1<<10))
600 #define ISR_THPDER ((1<< 9))
601 #define ISR_THPDOK ((1<< 8))
602 #define ISR_TNPDER ((1<< 7))
603 #define ISR_TNPDOK ((1<< 6))
604 #define ISR_RXFOVW ((1<< 5))
605 #define ISR_RDU ((1<< 4))
606 #define ISR_TLPDER ((1<< 3))
607 #define ISR_TLPDOK ((1<< 2))
608 #define ISR_RER ((1<< 1))
609 #define ISR_ROK ((1<< 0))
612 #define HW_VERID_R8180_F 3
613 #define HW_VERID_R8180_ABCD 2
614 #define HW_VERID_R8185_ABC 4
615 #define HW_VERID_R8185_D 5
616 #ifdef CONFIG_RTL8185B
617 #define HW_VERID_R8185B_B 6
620 #define TCR_CWMIN ((1<<31))
621 #define TCR_SWSEQ ((1<<30))
622 #define TCR_HWVERID_MASK ((1<<27)|(1<<26)|(1<<25))
623 #define TCR_HWVERID_SHIFT 25
624 #define TCR_SAT ((1<<24))
625 #define TCR_PLCP_LEN TCR_SAT // rtl8180
626 #define TCR_MXDMA_MASK ((1<<23)|(1<<22)|(1<<21))
627 #define TCR_MXDMA_1024 6
628 #define TCR_MXDMA_2048 7
629 #define TCR_MXDMA_SHIFT 21
630 #define TCR_DISCW ((1<<20))
631 #define TCR_ICV ((1<<19))
632 #define TCR_LBK ((1<<18)|(1<<17))
633 #define TCR_LBK1 ((1<<18))
634 #define TCR_LBK0 ((1<<17))
635 #define TCR_CRC ((1<<16))
636 #define TCR_DPRETRY_MASK ((1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8))
637 #define TCR_RTSRETRY_MASK ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7))
638 #define TCR_PROBE_NOTIMESTAMP_SHIFT 29 //rtl8185
640 #define RCR_ONLYERLPKT ((1<<31))
641 #define RCR_CS_SHIFT 29
642 #define RCR_CS_MASK ((1<<30) | (1<<29))
643 #define RCR_ENMARP ((1<<28))
644 #define RCR_CBSSID ((1<<23))
645 #define RCR_APWRMGT ((1<<22))
646 #define RCR_ADD3 ((1<<21))
647 #define RCR_AMF ((1<<20))
648 #define RCR_ACF ((1<<19))
649 #define RCR_ADF ((1<<18))
650 #define RCR_RXFTH ((1<<15)|(1<<14)|(1<<13))
651 #define RCR_RXFTH2 ((1<<15))
652 #define RCR_RXFTH1 ((1<<14))
653 #define RCR_RXFTH0 ((1<<13))
654 #define RCR_AICV ((1<<12))
655 #define RCR_MXDMA ((1<<10)|(1<< 9)|(1<< 8))
656 #define RCR_MXDMA2 ((1<<10))
657 #define RCR_MXDMA1 ((1<< 9))
658 #define RCR_MXDMA0 ((1<< 8))
659 #define RCR_9356SEL ((1<< 6))
660 #define RCR_ACRC32 ((1<< 5))
661 #define RCR_AB ((1<< 3))
662 #define RCR_AM ((1<< 2))
663 #define RCR_APM ((1<< 1))
664 #define RCR_AAP ((1<< 0))
666 #define CR9346_EEM ((1<<7)|(1<<6))
667 #define CR9346_EEM1 ((1<<7))
668 #define CR9346_EEM0 ((1<<6))
669 #define CR9346_EECS ((1<<3))
670 #define CR9346_EESK ((1<<2))
671 #define CR9346_EED1 ((1<<1))
672 #define CR9346_EED0 ((1<<0))
674 #define CONFIG0_WEP104 ((1<<6))
675 #define CONFIG0_LEDGPO_En ((1<<4))
676 #define CONFIG0_Aux_Status ((1<<3))
677 #define CONFIG0_GL ((1<<1)|(1<<0))
678 #define CONFIG0_GL1 ((1<<1))
679 #define CONFIG0_GL0 ((1<<0))
681 #define CONFIG1_LEDS ((1<<7)|(1<<6))
682 #define CONFIG1_LEDS1 ((1<<7))
683 #define CONFIG1_LEDS0 ((1<<6))
684 #define CONFIG1_LWACT ((1<<4))
685 #define CONFIG1_MEMMAP ((1<<3))
686 #define CONFIG1_IOMAP ((1<<2))
687 #define CONFIG1_VPD ((1<<1))
688 #define CONFIG1_PMEn ((1<<0))
690 #define CONFIG2_LCK ((1<<7))
691 #define CONFIG2_ANT ((1<<6))
692 #define CONFIG2_DPS ((1<<3))
693 #define CONFIG2_PAPE_sign ((1<<2))
694 #define CONFIG2_PAPE_time ((1<<1)|(1<<0))
695 #define CONFIG2_PAPE_time1 ((1<<1))
696 #define CONFIG2_PAPE_time0 ((1<<0))
698 #define CONFIG3_GNTSel ((1<<7))
699 #define CONFIG3_PARM_En ((1<<6))
700 #define CONFIG3_Magic ((1<<5))
701 #define CONFIG3_CardB_En ((1<<3))
702 #define CONFIG3_CLKRUN_En ((1<<2))
703 #define CONFIG3_FuncRegEn ((1<<1))
704 #define CONFIG3_FBtbEn ((1<<0))
706 #define CONFIG4_VCOPDN ((1<<7))
707 #define CONFIG4_PWROFF ((1<<6))
708 #define CONFIG4_PWRMGT ((1<<5))
709 #define CONFIG4_LWPME ((1<<4))
710 #define CONFIG4_LWPTN ((1<<2))
711 #define CONFIG4_RFTYPE ((1<<1)|(1<<0))
712 #define CONFIG4_RFTYPE1 ((1<<1))
713 #define CONFIG4_RFTYPE0 ((1<<0))
715 #define CONFIG5_TX_FIFO_OK ((1<<7))
716 #define CONFIG5_RX_FIFO_OK ((1<<6))
717 #define CONFIG5_CALON ((1<<5))
718 #define CONFIG5_EACPI ((1<<2))
719 #define CONFIG5_LANWake ((1<<1))
720 #define CONFIG5_PME_STS ((1<<0))
722 #define MSR_LINK_MASK ((1<<2)|(1<<3))
723 #define MSR_LINK_MANAGED 2
724 #define MSR_LINK_NONE 0
725 #define MSR_LINK_SHIFT 2
726 #define MSR_LINK_ADHOC 1
727 #define MSR_LINK_MASTER 3
729 #define PSR_GPO ((1<<7))
730 #define PSR_GPI ((1<<6))
731 #define PSR_LEDGPO1 ((1<<5))
732 #define PSR_LEDGPO0 ((1<<4))
733 #define PSR_UWF ((1<<1))
734 #define PSR_PSEn ((1<<0))
736 #define SCR_KM ((1<<5)|(1<<4))
737 #define SCR_KM1 ((1<<5))
738 #define SCR_KM0 ((1<<4))
739 #define SCR_TXSECON ((1<<1))
740 #define SCR_RXSECON ((1<<0))
742 #define BcnItv_BcnItv (0x01FF)
744 #define AtimWnd_AtimWnd (0x01FF)
746 #define BintrItv_BintrItv (0x01FF)
748 #define AtimtrItv_AtimtrItv (0x01FF)
750 #define PhyDelay_PhyDelay ((1<<2)|(1<<1)|(1<<0))
752 #define TPPoll_BQ ((1<<7))
753 #define TPPoll_HPQ ((1<<6))
754 #define TPPoll_NPQ ((1<<5))
755 #define TPPoll_LPQ ((1<<4))
756 #define TPPoll_SBQ ((1<<3))
757 #define TPPoll_SHPQ ((1<<2))
758 #define TPPoll_SNPQ ((1<<1))
759 #define TPPoll_SLPQ ((1<<0))
761 #define CWR_CW (0x01FF)
763 #define FER_INTR ((1<<15))
764 #define FER_GWAKE ((1<< 4))
766 #define FEMR_INTR ((1<<15))
767 #define FEMR_WKUP ((1<<14))
768 #define FEMR_GWAKE ((1<< 4))
770 #define FPSR_INTR ((1<<15))
771 #define FPSR_GWAKE ((1<< 4))
773 #define FFER_INTR ((1<<15))
774 #define FFER_GWAKE ((1<< 4))
776 #ifdef CONFIG_RTL8185B
778 #define SW_THREE_WIRE 0
779 #define HW_THREE_WIRE 2
781 #define HW_THREE_WIRE_PI 5
782 #define HW_THREE_WIRE_SI 6
784 #define TCR_LRL_OFFSET 0
785 #define TCR_SRL_OFFSET 8
786 #define TCR_MXDMA_OFFSET 21
787 #define TCR_DISReqQsize_OFFSET 28
788 #define TCR_DurProcMode_OFFSET 30
790 #define RCR_MXDMA_OFFSET 8
791 #define RCR_FIFO_OFFSET 13
793 #define TMGDS 0x0C // Tx Management Descriptor Address
794 #define TBKDS 0x10 // Tx AC_BK Descriptor Address
795 #define TBEDS 0x14 // Tx AC_BE Descriptor Address
796 #define TLPDS 0x20 // Tx AC_VI Descriptor Address
797 #define TNPDS 0x24 // Tx AC_VO Descriptor Address
798 #define THPDS 0x28 // Tx Hign Priority Descriptor Address
800 #define TBDS 0x4c // Beacon descriptor queue start address
802 #define RDSA 0xE4 // Receive descriptor queue start address
804 #define AckTimeOutReg 0x79 // ACK timeout register, in unit of 4 us.
806 #define RFTiming 0x8C
808 #define TPPollStop 0x93
810 #define TXAGC_CTL 0x9C // <RJ_TODO_8185B> TX_AGC_CONTROL (0x9C seems be removed at 8185B, see p37).
811 #define CCK_TXAGC 0x9D
812 #define OFDM_TXAGC 0x9E
815 #define ACM_CONTROL 0x00BF // ACM Control Registe
817 #define RTL8185B_VER_REG 0xE1
819 #define IntMig 0xE2 // Interrupt Migration (0xE2 ~ 0xE3)
821 #define TID_AC_MAP 0xE8 // TID to AC Mapping Register
823 #define ANAPARAM3 0xEE // <RJ_TODO_8185B> How to use it?
825 #define AC_VO_PARAM 0xF0 // AC_VO Parameters Record
826 #define AC_VI_PARAM 0xF4 // AC_VI Parameters Record
827 #define AC_BE_PARAM 0xF8 // AC_BE Parameters Record
828 #define AC_BK_PARAM 0xFC // AC_BK Parameters Record
830 #ifdef CONFIG_RTL818X_S
831 #define BcnTimingAdjust 0x16A // Beacon Timing Adjust Register.
832 #define GPIOCtrl 0x16B // GPIO Control Register.
833 #define PSByGC 0x180 // 0x180 - 0x183 Power Saving by Gated Clock.
835 #define ARFR 0x1E0 // Auto Rate Fallback Register (0x1e0 ~ 0x1e2)
837 #define RFSW_CTRL 0x272 // 0x272-0x273.
838 #define SW_3W_DB0 0x274 // Software 3-wire data buffer bit 31~0.
839 #define SW_3W_DB1 0x278 // Software 3-wire data buffer bit 63~32.
840 #define SW_3W_CMD0 0x27C // Software 3-wire Control/Status Register.
841 #define SW_3W_CMD1 0x27D // Software 3-wire Control/Status Register.
843 #ifdef CONFIG_RTL818X_S
844 #define PI_DATA_READ 0X360 // 0x360 - 0x361 Parallel Interface Data Register.
845 #define SI_DATA_READ 0x362 // 0x362 - 0x363 Serial Interface Data Register.
848 //----------------------------------------------------------------------------
849 // 8185B TPPoll bits (offset 0xd9, 1 byte)
850 //----------------------------------------------------------------------------
851 #define TPPOLL_BQ (0x01 << 7)
852 #define TPPOLL_HPQ (0x01 << 6)
853 #define TPPOLL_AC_VOQ (0x01 << 5)
854 #define TPPOLL_AC_VIQ (0x01 << 4)
855 #define TPPOLL_AC_BEQ (0x01 << 3)
856 #define TPPOLL_AC_BKQ (0x01 << 2)
857 #define TPPOLL_AC_MGQ (0x01 << 1)
859 //----------------------------------------------------------------------------
860 // 8185B TPPollStop bits (offset 0x93, 1 byte)
861 //----------------------------------------------------------------------------
862 #define TPPOLLSTOP_BQ (0x01 << 7)
863 #define TPPOLLSTOP_HPQ (0x01 << 6)
864 #define TPPOLLSTOP_AC_VOQ (0x01 << 5)
865 #define TPPOLLSTOP_AC_VIQ (0x01 << 4)
866 #define TPPOLLSTOP_AC_BEQ (0x01 << 3)
867 #define TPPOLLSTOP_AC_BKQ (0x01 << 2)
868 #define TPPOLLSTOP_AC_MGQ (0x01 << 1)
871 #define MSR_LINK_ENEDCA (1<<4)
873 //----------------------------------------------------------------------------
874 // 8187B AC_XX_PARAM bits
875 //----------------------------------------------------------------------------
876 #define AC_PARAM_TXOP_LIMIT_OFFSET 16
877 #define AC_PARAM_ECW_MAX_OFFSET 12
878 #define AC_PARAM_ECW_MIN_OFFSET 8
879 #define AC_PARAM_AIFS_OFFSET 0
881 //----------------------------------------------------------------------------
882 // 8187B ACM_CONTROL bits (Offset 0xBF, 1 Byte)
883 //----------------------------------------------------------------------------
884 #define VOQ_ACM_EN (0x01 << 7) //BIT7
885 #define VIQ_ACM_EN (0x01 << 6) //BIT6
886 #define BEQ_ACM_EN (0x01 << 5) //BIT5
887 #define ACM_HW_EN (0x01 << 4) //BIT4
888 #define TXOPSEL (0x01 << 3) //BIT3
889 #define VOQ_ACM_CTL (0x01 << 2) //BIT2 // Set to 1 when AC_VO used time reaches or exceeds the admitted time
890 #define VIQ_ACM_CTL (0x01 << 1) //BIT1 // Set to 1 when AC_VI used time reaches or exceeds the admitted time
891 #define BEQ_ACM_CTL (0x01 << 0) //BIT0 // Set to 1 when AC_BE used time reaches or exceeds the admitted time
894 //----------------------------------------------------------------------------
895 // 8185B SW_3W_CMD bits (Offset 0x27C-0x27D, 16bit)
896 //----------------------------------------------------------------------------
897 #define SW_3W_CMD0_HOLD ((1<< 7))
898 #define SW_3W_CMD1_RE ((1<< 0)) // BIT8
899 #define SW_3W_CMD1_WE ((1<< 1)) // BIT9
900 #define SW_3W_CMD1_DONE ((1<< 2)) // BIT10
902 #define BB_HOST_BANG_RW (1<<3)
904 //----------------------------------------------------------------------------
905 // 8185B RATE_FALLBACK_CTL bits (Offset 0xBE, 8bit)
906 //----------------------------------------------------------------------------
907 #define RATE_FALLBACK_CTL_ENABLE ((1<< 7))
908 #define RATE_FALLBACK_CTL_ENABLE_RTSCTS ((1<< 6))
909 // Auto rate fallback per 2^n retry.
910 #define RATE_FALLBACK_CTL_AUTO_STEP0 0x00
911 #define RATE_FALLBACK_CTL_AUTO_STEP1 0x01
912 #define RATE_FALLBACK_CTL_AUTO_STEP2 0x02
913 #define RATE_FALLBACK_CTL_AUTO_STEP3 0x03
916 #define RTL8225z2_ANAPARAM_OFF 0x55480658
917 #define RTL8225z2_ANAPARAM2_OFF 0x72003f70
918 //by amy for power save
919 #define RF_CHANGE_BY_SW BIT31
920 #define RF_CHANGE_BY_HW BIT30
921 #define RF_CHANGE_BY_PS BIT29
922 #define RF_CHANGE_BY_IPS BIT28
923 //by amy for power save
925 #define EEPROM_SW_REVD_OFFSET 0x3f
926 // BIT[8-9] is for SW Antenna Diversity. Only the value EEPROM_SW_AD_ENABLE means enable, other values are diable.
927 #define EEPROM_SW_AD_MASK 0x0300
928 #define EEPROM_SW_AD_ENABLE 0x0100
930 // BIT[10-11] determine if Antenna 1 is the Default Antenna. Only the value EEPROM_DEF_ANT_1 means TRUE, other values are FALSE.
931 #define EEPROM_DEF_ANT_MASK 0x0C00
932 #define EEPROM_DEF_ANT_1 0x0400
935 //0x7C, 0x7D Crystal calibration and Tx Power tracking mechanism. Added by Roger. 2007.12.10.
936 #define EEPROM_RSV 0x7C
937 #define EEPROM_XTAL_CAL_MASK 0x00FF // 0x7C[7:0], Crystal calibration mask.
938 #define EEPROM_XTAL_CAL_XOUT_MASK 0x0F // 0x7C[3:0], Crystal calibration for Xout.
939 #define EEPROM_XTAL_CAL_XIN_MASK 0xF0 // 0x7C[7:4], Crystal calibration for Xin.
940 #define EEPROM_THERMAL_METER_MASK 0x0F00 // 0x7D[3:0], Thermal meter reference level.
941 #define EEPROM_XTAL_CAL_ENABLE 0x1000 // 0x7D[4], Crystal calibration enabled/disabled BIT.
942 #define EEPROM_THERMAL_METER_ENABLE 0x2000 // 0x7D[5], Thermal meter enabled/disabled BIT.
943 #define EEPROM_CID_RSVD1 0x3F
944 #define EN_LPF_CAL 0x238 // Enable LPF Calibration.
945 #define PWR_METER_EN BIT1
946 // <RJ_TODO_8185B> where are false alarm counters in 8185B?
947 #define CCK_FALSE_ALARM 0xD0
948 #define OFDM_FALSE_ALARM 0xD2
951 //YJ,add for Country IE, 080630
952 #define EEPROM_COUNTRY_CODE 0x2E
projects / linux-2.6 / blob