1 menu "Processor selection"
7 select SH_WRITETHROUGH if !CPU_SH2A
23 select CPU_HAS_PTEA if !CPU_SUBTYPE_ST40
33 config CPU_SUBTYPE_ST40
36 select CPU_HAS_INTC2_IRQ
45 comment "SH-2 Processor Support"
47 config CPU_SUBTYPE_SH7604
48 bool "Support SH7604 processor"
51 config CPU_SUBTYPE_SH7619
52 bool "Support SH7619 processor"
55 comment "SH-2A Processor Support"
57 config CPU_SUBTYPE_SH7206
58 bool "Support SH7206 processor"
61 comment "SH-3 Processor Support"
63 config CPU_SUBTYPE_SH7300
64 bool "Support SH7300 processor"
67 config CPU_SUBTYPE_SH7705
68 bool "Support SH7705 processor"
70 select CPU_HAS_PINT_IRQ
72 config CPU_SUBTYPE_SH7706
73 bool "Support SH7706 processor"
76 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
78 config CPU_SUBTYPE_SH7707
79 bool "Support SH7707 processor"
81 select CPU_HAS_PINT_IRQ
83 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
85 config CPU_SUBTYPE_SH7708
86 bool "Support SH7708 processor"
89 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or
90 if you have a 100 Mhz SH-3 HD6417708R CPU.
92 config CPU_SUBTYPE_SH7709
93 bool "Support SH7709 processor"
95 select CPU_HAS_PINT_IRQ
97 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
99 config CPU_SUBTYPE_SH7710
100 bool "Support SH7710 processor"
103 Select SH7710 if you have a SH3-DSP SH7710 CPU.
105 comment "SH-4 Processor Support"
107 config CPU_SUBTYPE_SH7750
108 bool "Support SH7750 processor"
110 select CPU_HAS_IPR_IRQ
112 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
114 config CPU_SUBTYPE_SH7091
115 bool "Support SH7091 processor"
117 select CPU_SUBTYPE_SH7750
119 Select SH7091 if you have an SH-4 based Sega device (such as
120 the Dreamcast, Naomi, and Naomi 2).
122 config CPU_SUBTYPE_SH7750R
123 bool "Support SH7750R processor"
125 select CPU_SUBTYPE_SH7750
126 select CPU_HAS_IPR_IRQ
128 config CPU_SUBTYPE_SH7750S
129 bool "Support SH7750S processor"
131 select CPU_SUBTYPE_SH7750
132 select CPU_HAS_IPR_IRQ
134 config CPU_SUBTYPE_SH7751
135 bool "Support SH7751 processor"
137 select CPU_HAS_IPR_IRQ
139 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
140 or if you have a HD6417751R CPU.
142 config CPU_SUBTYPE_SH7751R
143 bool "Support SH7751R processor"
145 select CPU_SUBTYPE_SH7751
146 select CPU_HAS_IPR_IRQ
148 config CPU_SUBTYPE_SH7760
149 bool "Support SH7760 processor"
151 select CPU_HAS_INTC2_IRQ
153 config CPU_SUBTYPE_SH4_202
154 bool "Support SH4-202 processor"
157 comment "ST40 Processor Support"
159 config CPU_SUBTYPE_ST40STB1
160 bool "Support ST40STB1/ST40RA processors"
161 select CPU_SUBTYPE_ST40
163 Select ST40STB1 if you have a ST40RA CPU.
164 This was previously called the ST40STB1, hence the option name.
166 config CPU_SUBTYPE_ST40GX1
167 bool "Support ST40GX1 processor"
168 select CPU_SUBTYPE_ST40
170 Select ST40GX1 if you have a ST40GX1 CPU.
172 comment "SH-4A Processor Support"
174 config CPU_SUBTYPE_SH7770
175 bool "Support SH7770 processor"
178 config CPU_SUBTYPE_SH7780
179 bool "Support SH7780 processor"
181 select CPU_HAS_INTC2_IRQ
183 config CPU_SUBTYPE_SH7785
184 bool "Support SH7785 processor"
187 select CPU_HAS_INTC2_IRQ
189 comment "SH4AL-DSP Processor Support"
191 config CPU_SUBTYPE_SH73180
192 bool "Support SH73180 processor"
195 config CPU_SUBTYPE_SH7343
196 bool "Support SH7343 processor"
199 config CPU_SUBTYPE_SH7722
200 bool "Support SH7722 processor"
203 select CPU_HAS_IPR_IRQ
207 menu "Memory management options"
210 bool "Support for memory management hardware"
214 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
215 boot on these systems, this option must not be set.
217 On other systems (such as the SH-3 and 4) where an MMU exists,
218 turning this off will boot the kernel on these machines with the
219 MMU implicitly switched off.
223 default "0x80000000" if MMU
227 hex "Physical memory start address"
230 Computers built with Hitachi SuperH processors always
231 map the ROM starting at address zero. But the processor
232 does not specify the range that RAM takes.
234 The physical memory (RAM) start address will be automatically
235 set to 08000000. Other platforms, such as the Solution Engine
236 boards typically map RAM at 0C000000.
238 Tweak this only when porting to a new machine which does not
239 already have a defconfig. Changing it from the known correct
240 value on any of the known systems will only lead to disaster.
243 hex "Physical memory size"
246 This sets the default memory size assumed by your SH kernel. It can
247 be overridden as normal by the 'mem=' argument on the kernel command
248 line. If unsure, consult your board specifications or just leave it
249 as 0x00400000 which was the default value before this became
253 bool "Support 32-bit physical addressing through PMB"
254 depends on CPU_SH4A && MMU && (!X2TLB || BROKEN)
257 If you say Y here, physical addressing will be extended to
258 32-bits through the SH-4A PMB. If this is not set, legacy
259 29-bit physical addressing will be used.
262 bool "Enable extended TLB mode"
263 depends on CPU_SHX2 && MMU && EXPERIMENTAL
265 Selecting this option will enable the extended mode of the SH-X2
266 TLB. For legacy SH-X behaviour and interoperability, say N. For
267 all of the fun new features and a willingless to submit bug reports,
271 bool "Support vsyscall page"
275 This will enable support for the kernel mapping a vDSO page
276 in process space, and subsequently handing down the entry point
277 to the libc through the ELF auxiliary vector.
279 From the kernel side this is used for the signal trampoline.
280 For systems with an MMU that can afford to give up a page,
281 (the default value) say Y.
284 prompt "Kernel page size"
285 default PAGE_SIZE_4KB
290 This is the default page size used by all SuperH CPUs.
294 depends on EXPERIMENTAL && X2TLB
296 This enables 8kB pages as supported by SH-X2 and later MMUs.
298 config PAGE_SIZE_64KB
300 depends on EXPERIMENTAL && CPU_SH4
302 This enables support for 64kB pages, possible on all SH-4
303 CPUs and later. Highly experimental, not recommended.
308 prompt "HugeTLB page size"
309 depends on HUGETLB_PAGE && CPU_SH4 && MMU
310 default HUGETLB_PAGE_SIZE_64K
312 config HUGETLB_PAGE_SIZE_64K
315 config HUGETLB_PAGE_SIZE_256K
319 config HUGETLB_PAGE_SIZE_1MB
322 config HUGETLB_PAGE_SIZE_4MB
326 config HUGETLB_PAGE_SIZE_64MB
336 menu "Cache configuration"
338 config SH7705_CACHE_32KB
339 bool "Enable 32KB cache size for SH7705"
340 depends on CPU_SUBTYPE_SH7705
343 config SH_DIRECT_MAPPED
344 bool "Use direct-mapped caching"
347 Selecting this option will configure the caches to be direct-mapped,
348 even if the cache supports a 2 or 4-way mode. This is useful primarily
349 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
350 SH4-202, SH4-501, etc.)
352 Turn this option off for platforms that do not have a direct-mapped
353 cache, and you have no need to run the caches in such a configuration.
355 config SH_WRITETHROUGH
356 bool "Use write-through caching"
358 Selecting this option will configure the caches in write-through
359 mode, as opposed to the default write-back configuration.
361 Since there's sill some aliasing issues on SH-4, this option will
362 unfortunately still require the majority of flushing functions to
363 be implemented to deal with aliasing.
368 bool "Operand Cache RAM (OCRAM) support"
370 Selecting this option will automatically tear down the number of
371 sets in the dcache by half, which in turn exposes a memory range.
373 The addresses for the OC RAM base will vary according to the
374 processor version. Consult vendor documentation for specifics.