git.oblomov.eu Git - linux-2.6/blob - drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey. It's neither supported nor endorsed
   7  *      by NVIDIA Corp. Use at your own risk.
   8  *
   9  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  10  * trademarks of NVIDIA Corporation in the United States and other
  11  * countries.
  12  *
  13  * Copyright (C) 2003,4,5 Manfred Spraul
  14  * Copyright (C) 2004 Andrew de Quincey (wol support)
  15  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  16  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  17  * Copyright (c) 2004 NVIDIA Corporation
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  32  *
  33  * Changelog:
  34  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  35  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  36  *                         Check all PCI BARs for the register window.
  37  *                         udelay added to mii_rw.
  38  *      0.03: 06 Oct 2003: Initialize dev->irq.
  39  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  40  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  41  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  42  *                         irq mask updated
  43  *      0.07: 14 Oct 2003: Further irq mask updates.
  44  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  45  *                         added into irq handler, NULL check for drain_ring.
  46  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  47  *                         requested interrupt sources.
  48  *      0.10: 20 Oct 2003: First cleanup for release.
  49  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  50  *                         MAC Address init fix, set_multicast cleanup.
  51  *      0.12: 23 Oct 2003: Cleanups for release.
  52  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  53  *                         Set link speed correctly. start rx before starting
  54  *                         tx (nv_start_rx sets the link speed).
  55  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  56  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  57  *                         open.
  58  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  59  *                         increased to 1628 bytes.
  60  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  61  *                         the tx length.
  62  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  63  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  64  *                         addresses, really stop rx if already running
  65  *                         in nv_start_rx, clean up a bit.
  66  *      0.20: 07 Dec 2003: alloc fixes
  67  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  68  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  69  *                         on close.
  70  *      0.23: 26 Jan 2004: various small cleanups
  71  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  72  *      0.25: 09 Mar 2004: wol support
  73  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  74  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  75  *                         added CK804/MCP04 device IDs, code fixes
  76  *                         for registers, link status and other minor fixes.
  77  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  78  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  79  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  80  *                         into nv_close, otherwise reenabling for wol can
  81  *                         cause DMA to kfree'd memory.
  82  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  83  *                         capabilities.
  84  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  85  *      0.33: 16 May 2005: Support for MCP51 added.
  86  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  87  *      0.35: 26 Jun 2005: Support for MCP55 added.
  88  *      0.36: 28 Jun 2005: Add jumbo frame support.
  89  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  90  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  91  *                         per-packet flags.
  92  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  93  *      0.40: 19 Jul 2005: Add support for mac address change.
  94  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  95  *                         of nv_remove
  96  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  97  *                         in the second (and later) nv_open call
  98  *      0.43: 10 Aug 2005: Add support for tx checksum.
  99  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
 100  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 101  *      0.46: 20 Oct 2005: Add irq optimization modes.
 102  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 103  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 104  *      0.49: 10 Dec 2005: Fix tso for large buffers.
 105  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
 106  *      0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
 107  *      0.52: 20 Jan 2006: Add MSI/MSIX support.
 108  *      0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
 109  *      0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
 110  *      0.55: 22 Mar 2006: Add flow control (pause frame).
 111  *      0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
 112  *      0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
 113  *      0.58: 30 Oct 2006: Added support for sideband management unit.
 114  *
 115  * Known bugs:
 116  * We suspect that on some hardware no TX done interrupts are generated.
 117  * This means recovery from netif_stop_queue only happens if the hw timer
 118  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 119  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 120  * If your hardware reliably generates tx done interrupts, then you can remove
 121  * DEV_NEED_TIMERIRQ from the driver_data flags.
 122  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 123  * superfluous timer interrupts from the nic.
 124  */
 125 #ifdef CONFIG_FORCEDETH_NAPI
 126 #define DRIVERNAPI "-NAPI"
 127 #else
 128 #define DRIVERNAPI
 129 #endif
 130 #define FORCEDETH_VERSION               "0.58"
 131 #define DRV_NAME                        "forcedeth"
 132
 133 #include <linux/module.h>
 134 #include <linux/types.h>
 135 #include <linux/pci.h>
 136 #include <linux/interrupt.h>
 137 #include <linux/netdevice.h>
 138 #include <linux/etherdevice.h>
 139 #include <linux/delay.h>
 140 #include <linux/spinlock.h>
 141 #include <linux/ethtool.h>
 142 #include <linux/timer.h>
 143 #include <linux/skbuff.h>
 144 #include <linux/mii.h>
 145 #include <linux/random.h>
 146 #include <linux/init.h>
 147 #include <linux/if_vlan.h>
 148 #include <linux/dma-mapping.h>
 149
 150 #include <asm/irq.h>
 151 #include <asm/io.h>
 152 #include <asm/uaccess.h>
 153 #include <asm/system.h>
 154
 155 #if 0
 156 #define dprintk                 printk
 157 #else
 158 #define dprintk(x...)           do { } while (0)
 159 #endif
 160
 161
 162 /*
 163  * Hardware access:
 164  */
 165
 166 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 167 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 168 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 169 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 170 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
 171 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
 172 #define DEV_HAS_MSI             0x0040  /* device supports MSI */
 173 #define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */
 174 #define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */
 175 #define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */
 176 #define DEV_HAS_STATISTICS      0x0400  /* device supports hw statistics */
 177 #define DEV_HAS_TEST_EXTENDED   0x0800  /* device supports extended diagnostic test */
 178 #define DEV_HAS_MGMT_UNIT       0x1000  /* device supports management unit */
 179
 180 enum {
 181         NvRegIrqStatus = 0x000,
 182 #define NVREG_IRQSTAT_MIIEVENT  0x040
 183 #define NVREG_IRQSTAT_MASK              0x1ff
 184         NvRegIrqMask = 0x004,
 185 #define NVREG_IRQ_RX_ERROR              0x0001
 186 #define NVREG_IRQ_RX                    0x0002
 187 #define NVREG_IRQ_RX_NOBUF              0x0004
 188 #define NVREG_IRQ_TX_ERR                0x0008
 189 #define NVREG_IRQ_TX_OK                 0x0010
 190 #define NVREG_IRQ_TIMER                 0x0020
 191 #define NVREG_IRQ_LINK                  0x0040
 192 #define NVREG_IRQ_RX_FORCED             0x0080
 193 #define NVREG_IRQ_TX_FORCED             0x0100
 194 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 195 #define NVREG_IRQMASK_CPU               0x0040
 196 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 197 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 198 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK)
 199
 200 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 201                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
 202                                         NVREG_IRQ_TX_FORCED))
 203
 204         NvRegUnknownSetupReg6 = 0x008,
 205 #define NVREG_UNKSETUP6_VAL             3
 206
 207 /*
 208  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 209  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 210  */
 211         NvRegPollingInterval = 0x00c,
 212 #define NVREG_POLL_DEFAULT_THROUGHPUT   970
 213 #define NVREG_POLL_DEFAULT_CPU  13
 214         NvRegMSIMap0 = 0x020,
 215         NvRegMSIMap1 = 0x024,
 216         NvRegMSIIrqMask = 0x030,
 217 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 218         NvRegMisc1 = 0x080,
 219 #define NVREG_MISC1_PAUSE_TX    0x01
 220 #define NVREG_MISC1_HD          0x02
 221 #define NVREG_MISC1_FORCE       0x3b0f3c
 222
 223         NvRegMacReset = 0x3c,
 224 #define NVREG_MAC_RESET_ASSERT  0x0F3
 225         NvRegTransmitterControl = 0x084,
 226 #define NVREG_XMITCTL_START     0x01
 227 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 228 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 229 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 230 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 231 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 232 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 233 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 234 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 235 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 236         NvRegTransmitterStatus = 0x088,
 237 #define NVREG_XMITSTAT_BUSY     0x01
 238
 239         NvRegPacketFilterFlags = 0x8c,
 240 #define NVREG_PFF_PAUSE_RX      0x08
 241 #define NVREG_PFF_ALWAYS        0x7F0000
 242 #define NVREG_PFF_PROMISC       0x80
 243 #define NVREG_PFF_MYADDR        0x20
 244 #define NVREG_PFF_LOOPBACK      0x10
 245
 246         NvRegOffloadConfig = 0x90,
 247 #define NVREG_OFFLOAD_HOMEPHY   0x601
 248 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 249         NvRegReceiverControl = 0x094,
 250 #define NVREG_RCVCTL_START      0x01
 251         NvRegReceiverStatus = 0x98,
 252 #define NVREG_RCVSTAT_BUSY      0x01
 253
 254         NvRegRandomSeed = 0x9c,
 255 #define NVREG_RNDSEED_MASK      0x00ff
 256 #define NVREG_RNDSEED_FORCE     0x7f00
 257 #define NVREG_RNDSEED_FORCE2    0x2d00
 258 #define NVREG_RNDSEED_FORCE3    0x7400
 259
 260         NvRegTxDeferral = 0xA0,
 261 #define NVREG_TX_DEFERRAL_DEFAULT       0x15050f
 262 #define NVREG_TX_DEFERRAL_RGMII_10_100  0x16070f
 263 #define NVREG_TX_DEFERRAL_RGMII_1000    0x14050f
 264         NvRegRxDeferral = 0xA4,
 265 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 266         NvRegMacAddrA = 0xA8,
 267         NvRegMacAddrB = 0xAC,
 268         NvRegMulticastAddrA = 0xB0,
 269 #define NVREG_MCASTADDRA_FORCE  0x01
 270         NvRegMulticastAddrB = 0xB4,
 271         NvRegMulticastMaskA = 0xB8,
 272         NvRegMulticastMaskB = 0xBC,
 273
 274         NvRegPhyInterface = 0xC0,
 275 #define PHY_RGMII               0x10000000
 276
 277         NvRegTxRingPhysAddr = 0x100,
 278         NvRegRxRingPhysAddr = 0x104,
 279         NvRegRingSizes = 0x108,
 280 #define NVREG_RINGSZ_TXSHIFT 0
 281 #define NVREG_RINGSZ_RXSHIFT 16
 282         NvRegTransmitPoll = 0x10c,
 283 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 284         NvRegLinkSpeed = 0x110,
 285 #define NVREG_LINKSPEED_FORCE 0x10000
 286 #define NVREG_LINKSPEED_10      1000
 287 #define NVREG_LINKSPEED_100     100
 288 #define NVREG_LINKSPEED_1000    50
 289 #define NVREG_LINKSPEED_MASK    (0xFFF)
 290         NvRegUnknownSetupReg5 = 0x130,
 291 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 292         NvRegTxWatermark = 0x13c,
 293 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 294 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 295 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 296         NvRegTxRxControl = 0x144,
 297 #define NVREG_TXRXCTL_KICK      0x0001
 298 #define NVREG_TXRXCTL_BIT1      0x0002
 299 #define NVREG_TXRXCTL_BIT2      0x0004
 300 #define NVREG_TXRXCTL_IDLE      0x0008
 301 #define NVREG_TXRXCTL_RESET     0x0010
 302 #define NVREG_TXRXCTL_RXCHECK   0x0400
 303 #define NVREG_TXRXCTL_DESC_1    0
 304 #define NVREG_TXRXCTL_DESC_2    0x02100
 305 #define NVREG_TXRXCTL_DESC_3    0x02200
 306 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 307 #define NVREG_TXRXCTL_VLANINS   0x00080
 308         NvRegTxRingPhysAddrHigh = 0x148,
 309         NvRegRxRingPhysAddrHigh = 0x14C,
 310         NvRegTxPauseFrame = 0x170,
 311 #define NVREG_TX_PAUSEFRAME_DISABLE     0x1ff0080
 312 #define NVREG_TX_PAUSEFRAME_ENABLE      0x0c00030
 313         NvRegMIIStatus = 0x180,
 314 #define NVREG_MIISTAT_ERROR             0x0001
 315 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 316 #define NVREG_MIISTAT_MASK              0x000f
 317 #define NVREG_MIISTAT_MASK2             0x000f
 318         NvRegMIIMask = 0x184,
 319 #define NVREG_MII_LINKCHANGE            0x0008
 320
 321         NvRegAdapterControl = 0x188,
 322 #define NVREG_ADAPTCTL_START    0x02
 323 #define NVREG_ADAPTCTL_LINKUP   0x04
 324 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 325 #define NVREG_ADAPTCTL_RUNNING  0x100000
 326 #define NVREG_ADAPTCTL_PHYSHIFT 24
 327         NvRegMIISpeed = 0x18c,
 328 #define NVREG_MIISPEED_BIT8     (1<<8)
 329 #define NVREG_MIIDELAY  5
 330         NvRegMIIControl = 0x190,
 331 #define NVREG_MIICTL_INUSE      0x08000
 332 #define NVREG_MIICTL_WRITE      0x00400
 333 #define NVREG_MIICTL_ADDRSHIFT  5
 334         NvRegMIIData = 0x194,
 335         NvRegWakeUpFlags = 0x200,
 336 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 337 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 338 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 339 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 340 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 341 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 342 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 343 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 344 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 345 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 346 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 347
 348         NvRegPatternCRC = 0x204,
 349         NvRegPatternMask = 0x208,
 350         NvRegPowerCap = 0x268,
 351 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 352 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 353 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 354         NvRegPowerState = 0x26c,
 355 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 356 #define NVREG_POWERSTATE_VALID          0x0100
 357 #define NVREG_POWERSTATE_MASK           0x0003
 358 #define NVREG_POWERSTATE_D0             0x0000
 359 #define NVREG_POWERSTATE_D1             0x0001
 360 #define NVREG_POWERSTATE_D2             0x0002
 361 #define NVREG_POWERSTATE_D3             0x0003
 362         NvRegTxCnt = 0x280,
 363         NvRegTxZeroReXmt = 0x284,
 364         NvRegTxOneReXmt = 0x288,
 365         NvRegTxManyReXmt = 0x28c,
 366         NvRegTxLateCol = 0x290,
 367         NvRegTxUnderflow = 0x294,
 368         NvRegTxLossCarrier = 0x298,
 369         NvRegTxExcessDef = 0x29c,
 370         NvRegTxRetryErr = 0x2a0,
 371         NvRegRxFrameErr = 0x2a4,
 372         NvRegRxExtraByte = 0x2a8,
 373         NvRegRxLateCol = 0x2ac,
 374         NvRegRxRunt = 0x2b0,
 375         NvRegRxFrameTooLong = 0x2b4,
 376         NvRegRxOverflow = 0x2b8,
 377         NvRegRxFCSErr = 0x2bc,
 378         NvRegRxFrameAlignErr = 0x2c0,
 379         NvRegRxLenErr = 0x2c4,
 380         NvRegRxUnicast = 0x2c8,
 381         NvRegRxMulticast = 0x2cc,
 382         NvRegRxBroadcast = 0x2d0,
 383         NvRegTxDef = 0x2d4,
 384         NvRegTxFrame = 0x2d8,
 385         NvRegRxCnt = 0x2dc,
 386         NvRegTxPause = 0x2e0,
 387         NvRegRxPause = 0x2e4,
 388         NvRegRxDropFrame = 0x2e8,
 389         NvRegVlanControl = 0x300,
 390 #define NVREG_VLANCONTROL_ENABLE        0x2000
 391         NvRegMSIXMap0 = 0x3e0,
 392         NvRegMSIXMap1 = 0x3e4,
 393         NvRegMSIXIrqStatus = 0x3f0,
 394
 395         NvRegPowerState2 = 0x600,
 396 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
 397 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 398 };
 399
 400 /* Big endian: should work, but is untested */
 401 struct ring_desc {
 402         __le32 buf;
 403         __le32 flaglen;
 404 };
 405
 406 struct ring_desc_ex {
 407         __le32 bufhigh;
 408         __le32 buflow;
 409         __le32 txvlan;
 410         __le32 flaglen;
 411 };
 412
 413 union ring_type {
 414         struct ring_desc* orig;
 415         struct ring_desc_ex* ex;
 416 };
 417
 418 #define FLAG_MASK_V1 0xffff0000
 419 #define FLAG_MASK_V2 0xffffc000
 420 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 421 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 422
 423 #define NV_TX_LASTPACKET        (1<<16)
 424 #define NV_TX_RETRYERROR        (1<<19)
 425 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 426 #define NV_TX_DEFERRED          (1<<26)
 427 #define NV_TX_CARRIERLOST       (1<<27)
 428 #define NV_TX_LATECOLLISION     (1<<28)
 429 #define NV_TX_UNDERFLOW         (1<<29)
 430 #define NV_TX_ERROR             (1<<30)
 431 #define NV_TX_VALID             (1<<31)
 432
 433 #define NV_TX2_LASTPACKET       (1<<29)
 434 #define NV_TX2_RETRYERROR       (1<<18)
 435 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 436 #define NV_TX2_DEFERRED         (1<<25)
 437 #define NV_TX2_CARRIERLOST      (1<<26)
 438 #define NV_TX2_LATECOLLISION    (1<<27)
 439 #define NV_TX2_UNDERFLOW        (1<<28)
 440 /* error and valid are the same for both */
 441 #define NV_TX2_ERROR            (1<<30)
 442 #define NV_TX2_VALID            (1<<31)
 443 #define NV_TX2_TSO              (1<<28)
 444 #define NV_TX2_TSO_SHIFT        14
 445 #define NV_TX2_TSO_MAX_SHIFT    14
 446 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 447 #define NV_TX2_CHECKSUM_L3      (1<<27)
 448 #define NV_TX2_CHECKSUM_L4      (1<<26)
 449
 450 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 451
 452 #define NV_RX_DESCRIPTORVALID   (1<<16)
 453 #define NV_RX_MISSEDFRAME       (1<<17)
 454 #define NV_RX_SUBSTRACT1        (1<<18)
 455 #define NV_RX_ERROR1            (1<<23)
 456 #define NV_RX_ERROR2            (1<<24)
 457 #define NV_RX_ERROR3            (1<<25)
 458 #define NV_RX_ERROR4            (1<<26)
 459 #define NV_RX_CRCERR            (1<<27)
 460 #define NV_RX_OVERFLOW          (1<<28)
 461 #define NV_RX_FRAMINGERR        (1<<29)
 462 #define NV_RX_ERROR             (1<<30)
 463 #define NV_RX_AVAIL             (1<<31)
 464
 465 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 466 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 467 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 468 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 469 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 470 #define NV_RX2_SUBSTRACT1       (1<<25)
 471 #define NV_RX2_ERROR1           (1<<18)
 472 #define NV_RX2_ERROR2           (1<<19)
 473 #define NV_RX2_ERROR3           (1<<20)
 474 #define NV_RX2_ERROR4           (1<<21)
 475 #define NV_RX2_CRCERR           (1<<22)
 476 #define NV_RX2_OVERFLOW         (1<<23)
 477 #define NV_RX2_FRAMINGERR       (1<<24)
 478 /* error and avail are the same for both */
 479 #define NV_RX2_ERROR            (1<<30)
 480 #define NV_RX2_AVAIL            (1<<31)
 481
 482 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 483 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 484
 485 /* Miscelaneous hardware related defines: */
 486 #define NV_PCI_REGSZ_VER1       0x270
 487 #define NV_PCI_REGSZ_VER2       0x604
 488
 489 /* various timeout delays: all in usec */
 490 #define NV_TXRX_RESET_DELAY     4
 491 #define NV_TXSTOP_DELAY1        10
 492 #define NV_TXSTOP_DELAY1MAX     500000
 493 #define NV_TXSTOP_DELAY2        100
 494 #define NV_RXSTOP_DELAY1        10
 495 #define NV_RXSTOP_DELAY1MAX     500000
 496 #define NV_RXSTOP_DELAY2        100
 497 #define NV_SETUP5_DELAY         5
 498 #define NV_SETUP5_DELAYMAX      50000
 499 #define NV_POWERUP_DELAY        5
 500 #define NV_POWERUP_DELAYMAX     5000
 501 #define NV_MIIBUSY_DELAY        50
 502 #define NV_MIIPHY_DELAY 10
 503 #define NV_MIIPHY_DELAYMAX      10000
 504 #define NV_MAC_RESET_DELAY      64
 505
 506 #define NV_WAKEUPPATTERNS       5
 507 #define NV_WAKEUPMASKENTRIES    4
 508
 509 /* General driver defaults */
 510 #define NV_WATCHDOG_TIMEO       (5*HZ)
 511
 512 #define RX_RING_DEFAULT         128
 513 #define TX_RING_DEFAULT         256
 514 #define RX_RING_MIN             128
 515 #define TX_RING_MIN             64
 516 #define RING_MAX_DESC_VER_1     1024
 517 #define RING_MAX_DESC_VER_2_3   16384
 518 /*
 519  * Difference between the get and put pointers for the tx ring.
 520  * This is used to throttle the amount of data outstanding in the
 521  * tx ring.
 522  */
 523 #define TX_LIMIT_DIFFERENCE     1
 524
 525 /* rx/tx mac addr + type + vlan + align + slack*/
 526 #define NV_RX_HEADERS           (64)
 527 /* even more slack. */
 528 #define NV_RX_ALLOC_PAD         (64)
 529
 530 /* maximum mtu size */
 531 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 532 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 533
 534 #define OOM_REFILL      (1+HZ/20)
 535 #define POLL_WAIT       (1+HZ/100)
 536 #define LINK_TIMEOUT    (3*HZ)
 537 #define STATS_INTERVAL  (10*HZ)
 538
 539 /*
 540  * desc_ver values:
 541  * The nic supports three different descriptor types:
 542  * - DESC_VER_1: Original
 543  * - DESC_VER_2: support for jumbo frames.
 544  * - DESC_VER_3: 64-bit format.
 545  */
 546 #define DESC_VER_1      1
 547 #define DESC_VER_2      2
 548 #define DESC_VER_3      3
 549
 550 /* PHY defines */
 551 #define PHY_OUI_MARVELL 0x5043
 552 #define PHY_OUI_CICADA  0x03f1
 553 #define PHYID1_OUI_MASK 0x03ff
 554 #define PHYID1_OUI_SHFT 6
 555 #define PHYID2_OUI_MASK 0xfc00
 556 #define PHYID2_OUI_SHFT 10
 557 #define PHYID2_MODEL_MASK               0x03f0
 558 #define PHY_MODEL_MARVELL_E3016         0x220
 559 #define PHY_MARVELL_E3016_INITMASK      0x0300
 560 #define PHY_INIT1       0x0f000
 561 #define PHY_INIT2       0x0e00
 562 #define PHY_INIT3       0x01000
 563 #define PHY_INIT4       0x0200
 564 #define PHY_INIT5       0x0004
 565 #define PHY_INIT6       0x02000
 566 #define PHY_GIGABIT     0x0100
 567
 568 #define PHY_TIMEOUT     0x1
 569 #define PHY_ERROR       0x2
 570
 571 #define PHY_100 0x1
 572 #define PHY_1000        0x2
 573 #define PHY_HALF        0x100
 574
 575 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 576 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 577 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 578 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 579 #define NV_PAUSEFRAME_RX_REQ     0x0010
 580 #define NV_PAUSEFRAME_TX_REQ     0x0020
 581 #define NV_PAUSEFRAME_AUTONEG    0x0040
 582
 583 /* MSI/MSI-X defines */
 584 #define NV_MSI_X_MAX_VECTORS  8
 585 #define NV_MSI_X_VECTORS_MASK 0x000f
 586 #define NV_MSI_CAPABLE        0x0010
 587 #define NV_MSI_X_CAPABLE      0x0020
 588 #define NV_MSI_ENABLED        0x0040
 589 #define NV_MSI_X_ENABLED      0x0080
 590
 591 #define NV_MSI_X_VECTOR_ALL   0x0
 592 #define NV_MSI_X_VECTOR_RX    0x0
 593 #define NV_MSI_X_VECTOR_TX    0x1
 594 #define NV_MSI_X_VECTOR_OTHER 0x2
 595
 596 /* statistics */
 597 struct nv_ethtool_str {
 598         char name[ETH_GSTRING_LEN];
 599 };
 600
 601 static const struct nv_ethtool_str nv_estats_str[] = {
 602         { "tx_bytes" },
 603         { "tx_zero_rexmt" },
 604         { "tx_one_rexmt" },
 605         { "tx_many_rexmt" },
 606         { "tx_late_collision" },
 607         { "tx_fifo_errors" },
 608         { "tx_carrier_errors" },
 609         { "tx_excess_deferral" },
 610         { "tx_retry_error" },
 611         { "tx_deferral" },
 612         { "tx_packets" },
 613         { "tx_pause" },
 614         { "rx_frame_error" },
 615         { "rx_extra_byte" },
 616         { "rx_late_collision" },
 617         { "rx_runt" },
 618         { "rx_frame_too_long" },
 619         { "rx_over_errors" },
 620         { "rx_crc_errors" },
 621         { "rx_frame_align_error" },
 622         { "rx_length_error" },
 623         { "rx_unicast" },
 624         { "rx_multicast" },
 625         { "rx_broadcast" },
 626         { "rx_bytes" },
 627         { "rx_pause" },
 628         { "rx_drop_frame" },
 629         { "rx_packets" },
 630         { "rx_errors_total" }
 631 };
 632
 633 struct nv_ethtool_stats {
 634         u64 tx_bytes;
 635         u64 tx_zero_rexmt;
 636         u64 tx_one_rexmt;
 637         u64 tx_many_rexmt;
 638         u64 tx_late_collision;
 639         u64 tx_fifo_errors;
 640         u64 tx_carrier_errors;
 641         u64 tx_excess_deferral;
 642         u64 tx_retry_error;
 643         u64 tx_deferral;
 644         u64 tx_packets;
 645         u64 tx_pause;
 646         u64 rx_frame_error;
 647         u64 rx_extra_byte;
 648         u64 rx_late_collision;
 649         u64 rx_runt;
 650         u64 rx_frame_too_long;
 651         u64 rx_over_errors;
 652         u64 rx_crc_errors;
 653         u64 rx_frame_align_error;
 654         u64 rx_length_error;
 655         u64 rx_unicast;
 656         u64 rx_multicast;
 657         u64 rx_broadcast;
 658         u64 rx_bytes;
 659         u64 rx_pause;
 660         u64 rx_drop_frame;
 661         u64 rx_packets;
 662         u64 rx_errors_total;
 663 };
 664
 665 /* diagnostics */
 666 #define NV_TEST_COUNT_BASE 3
 667 #define NV_TEST_COUNT_EXTENDED 4
 668
 669 static const struct nv_ethtool_str nv_etests_str[] = {
 670         { "link      (online/offline)" },
 671         { "register  (offline)       " },
 672         { "interrupt (offline)       " },
 673         { "loopback  (offline)       " }
 674 };
 675
 676 struct register_test {
 677         __le32 reg;
 678         __le32 mask;
 679 };
 680
 681 static const struct register_test nv_registers_test[] = {
 682         { NvRegUnknownSetupReg6, 0x01 },
 683         { NvRegMisc1, 0x03c },
 684         { NvRegOffloadConfig, 0x03ff },
 685         { NvRegMulticastAddrA, 0xffffffff },
 686         { NvRegTxWatermark, 0x0ff },
 687         { NvRegWakeUpFlags, 0x07777 },
 688         { 0,0 }
 689 };
 690
 691 /*
 692  * SMP locking:
 693  * All hardware access under dev->priv->lock, except the performance
 694  * critical parts:
 695  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 696  *      by the arch code for interrupts.
 697  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 698  *      needs dev->priv->lock :-(
 699  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 700  */
 701
 702 /* in dev: base, irq */
 703 struct fe_priv {
 704         spinlock_t lock;
 705
 706         /* General data:
 707          * Locking: spin_lock(&np->lock); */
 708         struct net_device_stats stats;
 709         struct nv_ethtool_stats estats;
 710         int in_shutdown;
 711         u32 linkspeed;
 712         int duplex;
 713         int autoneg;
 714         int fixed_mode;
 715         int phyaddr;
 716         int wolenabled;
 717         unsigned int phy_oui;
 718         unsigned int phy_model;
 719         u16 gigabit;
 720         int intr_test;
 721
 722         /* General data: RO fields */
 723         dma_addr_t ring_addr;
 724         struct pci_dev *pci_dev;
 725         u32 orig_mac[2];
 726         u32 irqmask;
 727         u32 desc_ver;
 728         u32 txrxctl_bits;
 729         u32 vlanctl_bits;
 730         u32 driver_data;
 731         u32 register_size;
 732         int rx_csum;
 733         u32 mac_in_use;
 734
 735         void __iomem *base;
 736
 737         /* rx specific fields.
 738          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 739          */
 740         union ring_type rx_ring;
 741         unsigned int cur_rx, refill_rx;
 742         struct sk_buff **rx_skbuff;
 743         dma_addr_t *rx_dma;
 744         unsigned int rx_buf_sz;
 745         unsigned int pkt_limit;
 746         struct timer_list oom_kick;
 747         struct timer_list nic_poll;
 748         struct timer_list stats_poll;
 749         u32 nic_poll_irq;
 750         int rx_ring_size;
 751
 752         /* media detection workaround.
 753          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 754          */
 755         int need_linktimer;
 756         unsigned long link_timeout;
 757         /*
 758          * tx specific fields.
 759          */
 760         union ring_type tx_ring;
 761         unsigned int next_tx, nic_tx;
 762         struct sk_buff **tx_skbuff;
 763         dma_addr_t *tx_dma;
 764         unsigned int *tx_dma_len;
 765         u32 tx_flags;
 766         int tx_ring_size;
 767         int tx_limit_start;
 768         int tx_limit_stop;
 769
 770         /* vlan fields */
 771         struct vlan_group *vlangrp;
 772
 773         /* msi/msi-x fields */
 774         u32 msi_flags;
 775         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 776
 777         /* flow control */
 778         u32 pause_flags;
 779 };
 780
 781 /*
 782  * Maximum number of loops until we assume that a bit in the irq mask
 783  * is stuck. Overridable with module param.
 784  */
 785 static int max_interrupt_work = 5;
 786
 787 /*
 788  * Optimization can be either throuput mode or cpu mode
 789  *
 790  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 791  * CPU Mode: Interrupts are controlled by a timer.
 792  */
 793 enum {
 794         NV_OPTIMIZATION_MODE_THROUGHPUT,
 795         NV_OPTIMIZATION_MODE_CPU
 796 };
 797 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 798
 799 /*
 800  * Poll interval for timer irq
 801  *
 802  * This interval determines how frequent an interrupt is generated.
 803  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 804  * Min = 0, and Max = 65535
 805  */
 806 static int poll_interval = -1;
 807
 808 /*
 809  * MSI interrupts
 810  */
 811 enum {
 812         NV_MSI_INT_DISABLED,
 813         NV_MSI_INT_ENABLED
 814 };
 815 static int msi = NV_MSI_INT_ENABLED;
 816
 817 /*
 818  * MSIX interrupts
 819  */
 820 enum {
 821         NV_MSIX_INT_DISABLED,
 822         NV_MSIX_INT_ENABLED
 823 };
 824 static int msix = NV_MSIX_INT_ENABLED;
 825
 826 /*
 827  * DMA 64bit
 828  */
 829 enum {
 830         NV_DMA_64BIT_DISABLED,
 831         NV_DMA_64BIT_ENABLED
 832 };
 833 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 834
 835 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 836 {
 837         return netdev_priv(dev);
 838 }
 839
 840 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 841 {
 842         return ((struct fe_priv *)netdev_priv(dev))->base;
 843 }
 844
 845 static inline void pci_push(u8 __iomem *base)
 846 {
 847         /* force out pending posted writes */
 848         readl(base);
 849 }
 850
 851 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 852 {
 853         return le32_to_cpu(prd->flaglen)
 854                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 855 }
 856
 857 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 858 {
 859         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 860 }
 861
 862 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 863                                 int delay, int delaymax, const char *msg)
 864 {
 865         u8 __iomem *base = get_hwbase(dev);
 866
 867         pci_push(base);
 868         do {
 869                 udelay(delay);
 870                 delaymax -= delay;
 871                 if (delaymax < 0) {
 872                         if (msg)
 873                                 printk(msg);
 874                         return 1;
 875                 }
 876         } while ((readl(base + offset) & mask) != target);
 877         return 0;
 878 }
 879
 880 #define NV_SETUP_RX_RING 0x01
 881 #define NV_SETUP_TX_RING 0x02
 882
 883 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 884 {
 885         struct fe_priv *np = get_nvpriv(dev);
 886         u8 __iomem *base = get_hwbase(dev);
 887
 888         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 889                 if (rxtx_flags & NV_SETUP_RX_RING) {
 890                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 891                 }
 892                 if (rxtx_flags & NV_SETUP_TX_RING) {
 893                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 894                 }
 895         } else {
 896                 if (rxtx_flags & NV_SETUP_RX_RING) {
 897                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 898                         writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
 899                 }
 900                 if (rxtx_flags & NV_SETUP_TX_RING) {
 901                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 902                         writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
 903                 }
 904         }
 905 }
 906
 907 static void free_rings(struct net_device *dev)
 908 {
 909         struct fe_priv *np = get_nvpriv(dev);
 910
 911         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 912                 if (np->rx_ring.orig)
 913                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
 914                                             np->rx_ring.orig, np->ring_addr);
 915         } else {
 916                 if (np->rx_ring.ex)
 917                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
 918                                             np->rx_ring.ex, np->ring_addr);
 919         }
 920         if (np->rx_skbuff)
 921                 kfree(np->rx_skbuff);
 922         if (np->rx_dma)
 923                 kfree(np->rx_dma);
 924         if (np->tx_skbuff)
 925                 kfree(np->tx_skbuff);
 926         if (np->tx_dma)
 927                 kfree(np->tx_dma);
 928         if (np->tx_dma_len)
 929                 kfree(np->tx_dma_len);
 930 }
 931
 932 static int using_multi_irqs(struct net_device *dev)
 933 {
 934         struct fe_priv *np = get_nvpriv(dev);
 935
 936         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
 937             ((np->msi_flags & NV_MSI_X_ENABLED) &&
 938              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
 939                 return 0;
 940         else
 941                 return 1;
 942 }
 943
 944 static void nv_enable_irq(struct net_device *dev)
 945 {
 946         struct fe_priv *np = get_nvpriv(dev);
 947
 948         if (!using_multi_irqs(dev)) {
 949                 if (np->msi_flags & NV_MSI_X_ENABLED)
 950                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 951                 else
 952                         enable_irq(dev->irq);
 953         } else {
 954                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 955                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 956                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 957         }
 958 }
 959
 960 static void nv_disable_irq(struct net_device *dev)
 961 {
 962         struct fe_priv *np = get_nvpriv(dev);
 963
 964         if (!using_multi_irqs(dev)) {
 965                 if (np->msi_flags & NV_MSI_X_ENABLED)
 966                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 967                 else
 968                         disable_irq(dev->irq);
 969         } else {
 970                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 971                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 972                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 973         }
 974 }
 975
 976 /* In MSIX mode, a write to irqmask behaves as XOR */
 977 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
 978 {
 979         u8 __iomem *base = get_hwbase(dev);
 980
 981         writel(mask, base + NvRegIrqMask);
 982 }
 983
 984 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
 985 {
 986         struct fe_priv *np = get_nvpriv(dev);
 987         u8 __iomem *base = get_hwbase(dev);
 988
 989         if (np->msi_flags & NV_MSI_X_ENABLED) {
 990                 writel(mask, base + NvRegIrqMask);
 991         } else {
 992                 if (np->msi_flags & NV_MSI_ENABLED)
 993                         writel(0, base + NvRegMSIIrqMask);
 994                 writel(0, base + NvRegIrqMask);
 995         }
 996 }
 997
 998 #define MII_READ        (-1)
 999 /* mii_rw: read/write a register on the PHY.
1000  *
1001  * Caller must guarantee serialization
1002  */
1003 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1004 {
1005         u8 __iomem *base = get_hwbase(dev);
1006         u32 reg;
1007         int retval;
1008
1009         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1010
1011         reg = readl(base + NvRegMIIControl);
1012         if (reg & NVREG_MIICTL_INUSE) {
1013                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1014                 udelay(NV_MIIBUSY_DELAY);
1015         }
1016
1017         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1018         if (value != MII_READ) {
1019                 writel(value, base + NvRegMIIData);
1020                 reg |= NVREG_MIICTL_WRITE;
1021         }
1022         writel(reg, base + NvRegMIIControl);
1023
1024         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1025                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1026                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1027                                 dev->name, miireg, addr);
1028                 retval = -1;
1029         } else if (value != MII_READ) {
1030                 /* it was a write operation - fewer failures are detectable */
1031                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1032                                 dev->name, value, miireg, addr);
1033                 retval = 0;
1034         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1035                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1036                                 dev->name, miireg, addr);
1037                 retval = -1;
1038         } else {
1039                 retval = readl(base + NvRegMIIData);
1040                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1041                                 dev->name, miireg, addr, retval);
1042         }
1043
1044         return retval;
1045 }
1046
1047 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1048 {
1049         struct fe_priv *np = netdev_priv(dev);
1050         u32 miicontrol;
1051         unsigned int tries = 0;
1052
1053         miicontrol = BMCR_RESET | bmcr_setup;
1054         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1055                 return -1;
1056         }
1057
1058         /* wait for 500ms */
1059         msleep(500);
1060
1061         /* must wait till reset is deasserted */
1062         while (miicontrol & BMCR_RESET) {
1063                 msleep(10);
1064                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1065                 /* FIXME: 100 tries seem excessive */
1066                 if (tries++ > 100)
1067                         return -1;
1068         }
1069         return 0;
1070 }
1071
1072 static int phy_init(struct net_device *dev)
1073 {
1074         struct fe_priv *np = get_nvpriv(dev);
1075         u8 __iomem *base = get_hwbase(dev);
1076         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1077
1078         /* phy errata for E3016 phy */
1079         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1080                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1081                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1082                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1083                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1084                         return PHY_ERROR;
1085                 }
1086         }
1087
1088         /* set advertise register */
1089         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1090         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1091         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1092                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1093                 return PHY_ERROR;
1094         }
1095
1096         /* get phy interface type */
1097         phyinterface = readl(base + NvRegPhyInterface);
1098
1099         /* see if gigabit phy */
1100         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1101         if (mii_status & PHY_GIGABIT) {
1102                 np->gigabit = PHY_GIGABIT;
1103                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1104                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1105                 if (phyinterface & PHY_RGMII)
1106                         mii_control_1000 |= ADVERTISE_1000FULL;
1107                 else
1108                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1109
1110                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1111                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1112                         return PHY_ERROR;
1113                 }
1114         }
1115         else
1116                 np->gigabit = 0;
1117
1118         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1119         mii_control |= BMCR_ANENABLE;
1120
1121         /* reset the phy
1122          * (certain phys need bmcr to be setup with reset)
1123          */
1124         if (phy_reset(dev, mii_control)) {
1125                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1126                 return PHY_ERROR;
1127         }
1128
1129         /* phy vendor specific configuration */
1130         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1131                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1132                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1133                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1134                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1135                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1136                         return PHY_ERROR;
1137                 }
1138                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1139                 phy_reserved |= PHY_INIT5;
1140                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1141                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1142                         return PHY_ERROR;
1143                 }
1144         }
1145         if (np->phy_oui == PHY_OUI_CICADA) {
1146                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1147                 phy_reserved |= PHY_INIT6;
1148                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1149                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1150                         return PHY_ERROR;
1151                 }
1152         }
1153         /* some phys clear out pause advertisment on reset, set it back */
1154         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1155
1156         /* restart auto negotiation */
1157         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1158         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1159         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1160                 return PHY_ERROR;
1161         }
1162
1163         return 0;
1164 }
1165
1166 static void nv_start_rx(struct net_device *dev)
1167 {
1168         struct fe_priv *np = netdev_priv(dev);
1169         u8 __iomem *base = get_hwbase(dev);
1170
1171         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1172         /* Already running? Stop it. */
1173         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
1174                 writel(0, base + NvRegReceiverControl);
1175                 pci_push(base);
1176         }
1177         writel(np->linkspeed, base + NvRegLinkSpeed);
1178         pci_push(base);
1179         writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
1180         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1181                                 dev->name, np->duplex, np->linkspeed);
1182         pci_push(base);
1183 }
1184
1185 static void nv_stop_rx(struct net_device *dev)
1186 {
1187         u8 __iomem *base = get_hwbase(dev);
1188
1189         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1190         writel(0, base + NvRegReceiverControl);
1191         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1192                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1193                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1194
1195         udelay(NV_RXSTOP_DELAY2);
1196         writel(0, base + NvRegLinkSpeed);
1197 }
1198
1199 static void nv_start_tx(struct net_device *dev)
1200 {
1201         u8 __iomem *base = get_hwbase(dev);
1202
1203         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1204         writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
1205         pci_push(base);
1206 }
1207
1208 static void nv_stop_tx(struct net_device *dev)
1209 {
1210         u8 __iomem *base = get_hwbase(dev);
1211
1212         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1213         writel(0, base + NvRegTransmitterControl);
1214         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1215                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1216                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1217
1218         udelay(NV_TXSTOP_DELAY2);
1219         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
1220 }
1221
1222 static void nv_txrx_reset(struct net_device *dev)
1223 {
1224         struct fe_priv *np = netdev_priv(dev);
1225         u8 __iomem *base = get_hwbase(dev);
1226
1227         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1228         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1229         pci_push(base);
1230         udelay(NV_TXRX_RESET_DELAY);
1231         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1232         pci_push(base);
1233 }
1234
1235 static void nv_mac_reset(struct net_device *dev)
1236 {
1237         struct fe_priv *np = netdev_priv(dev);
1238         u8 __iomem *base = get_hwbase(dev);
1239
1240         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1241         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1242         pci_push(base);
1243         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1244         pci_push(base);
1245         udelay(NV_MAC_RESET_DELAY);
1246         writel(0, base + NvRegMacReset);
1247         pci_push(base);
1248         udelay(NV_MAC_RESET_DELAY);
1249         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1250         pci_push(base);
1251 }
1252
1253 /*
1254  * nv_get_stats: dev->get_stats function
1255  * Get latest stats value from the nic.
1256  * Called with read_lock(&dev_base_lock) held for read -
1257  * only synchronized against unregister_netdevice.
1258  */
1259 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1260 {
1261         struct fe_priv *np = netdev_priv(dev);
1262
1263         /* It seems that the nic always generates interrupts and doesn't
1264          * accumulate errors internally. Thus the current values in np->stats
1265          * are already up to date.
1266          */
1267         return &np->stats;
1268 }
1269
1270 /*
1271  * nv_alloc_rx: fill rx ring entries.
1272  * Return 1 if the allocations for the skbs failed and the
1273  * rx engine is without Available descriptors
1274  */
1275 static int nv_alloc_rx(struct net_device *dev)
1276 {
1277         struct fe_priv *np = netdev_priv(dev);
1278         unsigned int refill_rx = np->refill_rx;
1279         int nr;
1280
1281         while (np->cur_rx != refill_rx) {
1282                 struct sk_buff *skb;
1283
1284                 nr = refill_rx % np->rx_ring_size;
1285                 if (np->rx_skbuff[nr] == NULL) {
1286
1287                         skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1288                         if (!skb)
1289                                 break;
1290
1291                         skb->dev = dev;
1292                         np->rx_skbuff[nr] = skb;
1293                 } else {
1294                         skb = np->rx_skbuff[nr];
1295                 }
1296                 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
1297                                         skb->end-skb->data, PCI_DMA_FROMDEVICE);
1298                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1299                         np->rx_ring.orig[nr].buf = cpu_to_le32(np->rx_dma[nr]);
1300                         wmb();
1301                         np->rx_ring.orig[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1302                 } else {
1303                         np->rx_ring.ex[nr].bufhigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
1304                         np->rx_ring.ex[nr].buflow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
1305                         wmb();
1306                         np->rx_ring.ex[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1307                 }
1308                 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
1309                                         dev->name, refill_rx);
1310                 refill_rx++;
1311         }
1312         np->refill_rx = refill_rx;
1313         if (np->cur_rx - refill_rx == np->rx_ring_size)
1314                 return 1;
1315         return 0;
1316 }
1317
1318 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1319 #ifdef CONFIG_FORCEDETH_NAPI
1320 static void nv_do_rx_refill(unsigned long data)
1321 {
1322         struct net_device *dev = (struct net_device *) data;
1323
1324         /* Just reschedule NAPI rx processing */
1325         netif_rx_schedule(dev);
1326 }
1327 #else
1328 static void nv_do_rx_refill(unsigned long data)
1329 {
1330         struct net_device *dev = (struct net_device *) data;
1331         struct fe_priv *np = netdev_priv(dev);
1332
1333         if (!using_multi_irqs(dev)) {
1334                 if (np->msi_flags & NV_MSI_X_ENABLED)
1335                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1336                 else
1337                         disable_irq(dev->irq);
1338         } else {
1339                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1340         }
1341         if (nv_alloc_rx(dev)) {
1342                 spin_lock_irq(&np->lock);
1343                 if (!np->in_shutdown)
1344                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1345                 spin_unlock_irq(&np->lock);
1346         }
1347         if (!using_multi_irqs(dev)) {
1348                 if (np->msi_flags & NV_MSI_X_ENABLED)
1349                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1350                 else
1351                         enable_irq(dev->irq);
1352         } else {
1353                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1354         }
1355 }
1356 #endif
1357
1358 static void nv_init_rx(struct net_device *dev)
1359 {
1360         struct fe_priv *np = netdev_priv(dev);
1361         int i;
1362
1363         np->cur_rx = np->rx_ring_size;
1364         np->refill_rx = 0;
1365         for (i = 0; i < np->rx_ring_size; i++)
1366                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1367                         np->rx_ring.orig[i].flaglen = 0;
1368                 else
1369                         np->rx_ring.ex[i].flaglen = 0;
1370 }
1371
1372 static void nv_init_tx(struct net_device *dev)
1373 {
1374         struct fe_priv *np = netdev_priv(dev);
1375         int i;
1376
1377         np->next_tx = np->nic_tx = 0;
1378         for (i = 0; i < np->tx_ring_size; i++) {
1379                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1380                         np->tx_ring.orig[i].flaglen = 0;
1381                 else
1382                         np->tx_ring.ex[i].flaglen = 0;
1383                 np->tx_skbuff[i] = NULL;
1384                 np->tx_dma[i] = 0;
1385         }
1386 }
1387
1388 static int nv_init_ring(struct net_device *dev)
1389 {
1390         nv_init_tx(dev);
1391         nv_init_rx(dev);
1392         return nv_alloc_rx(dev);
1393 }
1394
1395 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
1396 {
1397         struct fe_priv *np = netdev_priv(dev);
1398
1399         dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
1400                 dev->name, skbnr);
1401
1402         if (np->tx_dma[skbnr]) {
1403                 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
1404                                np->tx_dma_len[skbnr],
1405                                PCI_DMA_TODEVICE);
1406                 np->tx_dma[skbnr] = 0;
1407         }
1408
1409         if (np->tx_skbuff[skbnr]) {
1410                 dev_kfree_skb_any(np->tx_skbuff[skbnr]);
1411                 np->tx_skbuff[skbnr] = NULL;
1412                 return 1;
1413         } else {
1414                 return 0;
1415         }
1416 }
1417
1418 static void nv_drain_tx(struct net_device *dev)
1419 {
1420         struct fe_priv *np = netdev_priv(dev);
1421         unsigned int i;
1422
1423         for (i = 0; i < np->tx_ring_size; i++) {
1424                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1425                         np->tx_ring.orig[i].flaglen = 0;
1426                 else
1427                         np->tx_ring.ex[i].flaglen = 0;
1428                 if (nv_release_txskb(dev, i))
1429                         np->stats.tx_dropped++;
1430         }
1431 }
1432
1433 static void nv_drain_rx(struct net_device *dev)
1434 {
1435         struct fe_priv *np = netdev_priv(dev);
1436         int i;
1437         for (i = 0; i < np->rx_ring_size; i++) {
1438                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1439                         np->rx_ring.orig[i].flaglen = 0;
1440                 else
1441                         np->rx_ring.ex[i].flaglen = 0;
1442                 wmb();
1443                 if (np->rx_skbuff[i]) {
1444                         pci_unmap_single(np->pci_dev, np->rx_dma[i],
1445                                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1446                                                 PCI_DMA_FROMDEVICE);
1447                         dev_kfree_skb(np->rx_skbuff[i]);
1448                         np->rx_skbuff[i] = NULL;
1449                 }
1450         }
1451 }
1452
1453 static void drain_ring(struct net_device *dev)
1454 {
1455         nv_drain_tx(dev);
1456         nv_drain_rx(dev);
1457 }
1458
1459 /*
1460  * nv_start_xmit: dev->hard_start_xmit function
1461  * Called with netif_tx_lock held.
1462  */
1463 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1464 {
1465         struct fe_priv *np = netdev_priv(dev);
1466         u32 tx_flags = 0;
1467         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1468         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1469         unsigned int nr = (np->next_tx - 1) % np->tx_ring_size;
1470         unsigned int start_nr = np->next_tx % np->tx_ring_size;
1471         unsigned int i;
1472         u32 offset = 0;
1473         u32 bcnt;
1474         u32 size = skb->len-skb->data_len;
1475         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1476         u32 tx_flags_vlan = 0;
1477
1478         /* add fragments to entries count */
1479         for (i = 0; i < fragments; i++) {
1480                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1481                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1482         }
1483
1484         spin_lock_irq(&np->lock);
1485
1486         if ((np->next_tx - np->nic_tx + entries - 1) > np->tx_limit_stop) {
1487                 spin_unlock_irq(&np->lock);
1488                 netif_stop_queue(dev);
1489                 return NETDEV_TX_BUSY;
1490         }
1491
1492         /* setup the header buffer */
1493         do {
1494                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1495                 nr = (nr + 1) % np->tx_ring_size;
1496
1497                 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1498                                                 PCI_DMA_TODEVICE);
1499                 np->tx_dma_len[nr] = bcnt;
1500
1501                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1502                         np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
1503                         np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1504                 } else {
1505                         np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1506                         np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1507                         np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1508                 }
1509                 tx_flags = np->tx_flags;
1510                 offset += bcnt;
1511                 size -= bcnt;
1512         } while (size);
1513
1514         /* setup the fragments */
1515         for (i = 0; i < fragments; i++) {
1516                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1517                 u32 size = frag->size;
1518                 offset = 0;
1519
1520                 do {
1521                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1522                         nr = (nr + 1) % np->tx_ring_size;
1523
1524                         np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1525                                                       PCI_DMA_TODEVICE);
1526                         np->tx_dma_len[nr] = bcnt;
1527
1528                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1529                                 np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
1530                                 np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1531                         } else {
1532                                 np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1533                                 np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1534                                 np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1535                         }
1536                         offset += bcnt;
1537                         size -= bcnt;
1538                 } while (size);
1539         }
1540
1541         /* set last fragment flag  */
1542         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1543                 np->tx_ring.orig[nr].flaglen |= cpu_to_le32(tx_flags_extra);
1544         } else {
1545                 np->tx_ring.ex[nr].flaglen |= cpu_to_le32(tx_flags_extra);
1546         }
1547
1548         np->tx_skbuff[nr] = skb;
1549
1550 #ifdef NETIF_F_TSO
1551         if (skb_is_gso(skb))
1552                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1553         else
1554 #endif
1555         tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1556                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1557
1558         /* vlan tag */
1559         if (np->vlangrp && vlan_tx_tag_present(skb)) {
1560                 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
1561         }
1562
1563         /* set tx flags */
1564         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1565                 np->tx_ring.orig[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1566         } else {
1567                 np->tx_ring.ex[start_nr].txvlan = cpu_to_le32(tx_flags_vlan);
1568                 np->tx_ring.ex[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1569         }
1570
1571         dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1572                 dev->name, np->next_tx, entries, tx_flags_extra);
1573         {
1574                 int j;
1575                 for (j=0; j<64; j++) {
1576                         if ((j%16) == 0)
1577                                 dprintk("\n%03x:", j);
1578                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1579                 }
1580                 dprintk("\n");
1581         }
1582
1583         np->next_tx += entries;
1584
1585         dev->trans_start = jiffies;
1586         spin_unlock_irq(&np->lock);
1587         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1588         pci_push(get_hwbase(dev));
1589         return NETDEV_TX_OK;
1590 }
1591
1592 /*
1593  * nv_tx_done: check for completed packets, release the skbs.
1594  *
1595  * Caller must own np->lock.
1596  */
1597 static void nv_tx_done(struct net_device *dev)
1598 {
1599         struct fe_priv *np = netdev_priv(dev);
1600         u32 flags;
1601         unsigned int i;
1602         struct sk_buff *skb;
1603
1604         while (np->nic_tx != np->next_tx) {
1605                 i = np->nic_tx % np->tx_ring_size;
1606
1607                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1608                         flags = le32_to_cpu(np->tx_ring.orig[i].flaglen);
1609                 else
1610                         flags = le32_to_cpu(np->tx_ring.ex[i].flaglen);
1611
1612                 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, flags 0x%x.\n",
1613                                         dev->name, np->nic_tx, flags);
1614                 if (flags & NV_TX_VALID)
1615                         break;
1616                 if (np->desc_ver == DESC_VER_1) {
1617                         if (flags & NV_TX_LASTPACKET) {
1618                                 skb = np->tx_skbuff[i];
1619                                 if (flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1620                                              NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1621                                         if (flags & NV_TX_UNDERFLOW)
1622                                                 np->stats.tx_fifo_errors++;
1623                                         if (flags & NV_TX_CARRIERLOST)
1624                                                 np->stats.tx_carrier_errors++;
1625                                         np->stats.tx_errors++;
1626                                 } else {
1627                                         np->stats.tx_packets++;
1628                                         np->stats.tx_bytes += skb->len;
1629                                 }
1630                         }
1631                 } else {
1632                         if (flags & NV_TX2_LASTPACKET) {
1633                                 skb = np->tx_skbuff[i];
1634                                 if (flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1635                                              NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1636                                         if (flags & NV_TX2_UNDERFLOW)
1637                                                 np->stats.tx_fifo_errors++;
1638                                         if (flags & NV_TX2_CARRIERLOST)
1639                                                 np->stats.tx_carrier_errors++;
1640                                         np->stats.tx_errors++;
1641                                 } else {
1642                                         np->stats.tx_packets++;
1643                                         np->stats.tx_bytes += skb->len;
1644                                 }
1645                         }
1646                 }
1647                 nv_release_txskb(dev, i);
1648                 np->nic_tx++;
1649         }
1650         if (np->next_tx - np->nic_tx < np->tx_limit_start)
1651                 netif_wake_queue(dev);
1652 }
1653
1654 /*
1655  * nv_tx_timeout: dev->tx_timeout function
1656  * Called with netif_tx_lock held.
1657  */
1658 static void nv_tx_timeout(struct net_device *dev)
1659 {
1660         struct fe_priv *np = netdev_priv(dev);
1661         u8 __iomem *base = get_hwbase(dev);
1662         u32 status;
1663
1664         if (np->msi_flags & NV_MSI_X_ENABLED)
1665                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1666         else
1667                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1668
1669         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1670
1671         {
1672                 int i;
1673
1674                 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1675                                 dev->name, (unsigned long)np->ring_addr,
1676                                 np->next_tx, np->nic_tx);
1677                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1678                 for (i=0;i<=np->register_size;i+= 32) {
1679                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1680                                         i,
1681                                         readl(base + i + 0), readl(base + i + 4),
1682                                         readl(base + i + 8), readl(base + i + 12),
1683                                         readl(base + i + 16), readl(base + i + 20),
1684                                         readl(base + i + 24), readl(base + i + 28));
1685                 }
1686                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1687                 for (i=0;i<np->tx_ring_size;i+= 4) {
1688                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1689                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1690                                        i,
1691                                        le32_to_cpu(np->tx_ring.orig[i].buf),
1692                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
1693                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
1694                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
1695                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
1696                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
1697                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
1698                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
1699                         } else {
1700                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1701                                        i,
1702                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
1703                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
1704                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
1705                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
1706                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
1707                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
1708                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
1709                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
1710                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
1711                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
1712                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
1713                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
1714                         }
1715                 }
1716         }
1717
1718         spin_lock_irq(&np->lock);
1719
1720         /* 1) stop tx engine */
1721         nv_stop_tx(dev);
1722
1723         /* 2) check that the packets were not sent already: */
1724         nv_tx_done(dev);
1725
1726         /* 3) if there are dead entries: clear everything */
1727         if (np->next_tx != np->nic_tx) {
1728                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1729                 nv_drain_tx(dev);
1730                 np->next_tx = np->nic_tx = 0;
1731                 setup_hw_rings(dev, NV_SETUP_TX_RING);
1732                 netif_wake_queue(dev);
1733         }
1734
1735         /* 4) restart tx engine */
1736         nv_start_tx(dev);
1737         spin_unlock_irq(&np->lock);
1738 }
1739
1740 /*
1741  * Called when the nic notices a mismatch between the actual data len on the
1742  * wire and the len indicated in the 802 header
1743  */
1744 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1745 {
1746         int hdrlen;     /* length of the 802 header */
1747         int protolen;   /* length as stored in the proto field */
1748
1749         /* 1) calculate len according to header */
1750         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
1751                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1752                 hdrlen = VLAN_HLEN;
1753         } else {
1754                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1755                 hdrlen = ETH_HLEN;
1756         }
1757         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1758                                 dev->name, datalen, protolen, hdrlen);
1759         if (protolen > ETH_DATA_LEN)
1760                 return datalen; /* Value in proto field not a len, no checks possible */
1761
1762         protolen += hdrlen;
1763         /* consistency checks: */
1764         if (datalen > ETH_ZLEN) {
1765                 if (datalen >= protolen) {
1766                         /* more data on wire than in 802 header, trim of
1767                          * additional data.
1768                          */
1769                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1770                                         dev->name, protolen);
1771                         return protolen;
1772                 } else {
1773                         /* less data on wire than mentioned in header.
1774                          * Discard the packet.
1775                          */
1776                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1777                                         dev->name);
1778                         return -1;
1779                 }
1780         } else {
1781                 /* short packet. Accept only if 802 values are also short */
1782                 if (protolen > ETH_ZLEN) {
1783                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1784                                         dev->name);
1785                         return -1;
1786                 }
1787                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1788                                 dev->name, datalen);
1789                 return datalen;
1790         }
1791 }
1792
1793 static int nv_rx_process(struct net_device *dev, int limit)
1794 {
1795         struct fe_priv *np = netdev_priv(dev);
1796         u32 flags;
1797         u32 vlanflags = 0;
1798         int count;
1799
1800         for (count = 0; count < limit; ++count) {
1801                 struct sk_buff *skb;
1802                 int len;
1803                 int i;
1804                 if (np->cur_rx - np->refill_rx >= np->rx_ring_size)
1805                         break;  /* we scanned the whole ring - do not continue */
1806
1807                 i = np->cur_rx % np->rx_ring_size;
1808                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1809                         flags = le32_to_cpu(np->rx_ring.orig[i].flaglen);
1810                         len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1811                 } else {
1812                         flags = le32_to_cpu(np->rx_ring.ex[i].flaglen);
1813                         len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1814                         vlanflags = le32_to_cpu(np->rx_ring.ex[i].buflow);
1815                 }
1816
1817                 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, flags 0x%x.\n",
1818                                         dev->name, np->cur_rx, flags);
1819
1820                 if (flags & NV_RX_AVAIL)
1821                         break;  /* still owned by hardware, */
1822
1823                 /*
1824                  * the packet is for us - immediately tear down the pci mapping.
1825                  * TODO: check if a prefetch of the first cacheline improves
1826                  * the performance.
1827                  */
1828                 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1829                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1830                                 PCI_DMA_FROMDEVICE);
1831
1832                 {
1833                         int j;
1834                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
1835                         for (j=0; j<64; j++) {
1836                                 if ((j%16) == 0)
1837                                         dprintk("\n%03x:", j);
1838                                 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1839                         }
1840                         dprintk("\n");
1841                 }
1842                 /* look at what we actually got: */
1843                 if (np->desc_ver == DESC_VER_1) {
1844                         if (!(flags & NV_RX_DESCRIPTORVALID))
1845                                 goto next_pkt;
1846
1847                         if (flags & NV_RX_ERROR) {
1848                                 if (flags & NV_RX_MISSEDFRAME) {
1849                                         np->stats.rx_missed_errors++;
1850                                         np->stats.rx_errors++;
1851                                         goto next_pkt;
1852                                 }
1853                                 if (flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1854                                         np->stats.rx_errors++;
1855                                         goto next_pkt;
1856                                 }
1857                                 if (flags & NV_RX_CRCERR) {
1858                                         np->stats.rx_crc_errors++;
1859                                         np->stats.rx_errors++;
1860                                         goto next_pkt;
1861                                 }
1862                                 if (flags & NV_RX_OVERFLOW) {
1863                                         np->stats.rx_over_errors++;
1864                                         np->stats.rx_errors++;
1865                                         goto next_pkt;
1866                                 }
1867                                 if (flags & NV_RX_ERROR4) {
1868                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1869                                         if (len < 0) {
1870                                                 np->stats.rx_errors++;
1871                                                 goto next_pkt;
1872                                         }
1873                                 }
1874                                 /* framing errors are soft errors. */
1875                                 if (flags & NV_RX_FRAMINGERR) {
1876                                         if (flags & NV_RX_SUBSTRACT1) {
1877                                                 len--;
1878                                         }
1879                                 }
1880                         }
1881                 } else {
1882                         if (!(flags & NV_RX2_DESCRIPTORVALID))
1883                                 goto next_pkt;
1884
1885                         if (flags & NV_RX2_ERROR) {
1886                                 if (flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1887                                         np->stats.rx_errors++;
1888                                         goto next_pkt;
1889                                 }
1890                                 if (flags & NV_RX2_CRCERR) {
1891                                         np->stats.rx_crc_errors++;
1892                                         np->stats.rx_errors++;
1893                                         goto next_pkt;
1894                                 }
1895                                 if (flags & NV_RX2_OVERFLOW) {
1896                                         np->stats.rx_over_errors++;
1897                                         np->stats.rx_errors++;
1898                                         goto next_pkt;
1899                                 }
1900                                 if (flags & NV_RX2_ERROR4) {
1901                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1902                                         if (len < 0) {
1903                                                 np->stats.rx_errors++;
1904                                                 goto next_pkt;
1905                                         }
1906                                 }
1907                                 /* framing errors are soft errors */
1908                                 if (flags & NV_RX2_FRAMINGERR) {
1909                                         if (flags & NV_RX2_SUBSTRACT1) {
1910                                                 len--;
1911                                         }
1912                                 }
1913                         }
1914                         if (np->rx_csum) {
1915                                 flags &= NV_RX2_CHECKSUMMASK;
1916                                 if (flags == NV_RX2_CHECKSUMOK1 ||
1917                                     flags == NV_RX2_CHECKSUMOK2 ||
1918                                     flags == NV_RX2_CHECKSUMOK3) {
1919                                         dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1920                                         np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1921                                 } else {
1922                                         dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1923                                 }
1924                         }
1925                 }
1926                 /* got a valid packet - forward it to the network core */
1927                 skb = np->rx_skbuff[i];
1928                 np->rx_skbuff[i] = NULL;
1929
1930                 skb_put(skb, len);
1931                 skb->protocol = eth_type_trans(skb, dev);
1932                 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1933                                         dev->name, np->cur_rx, len, skb->protocol);
1934 #ifdef CONFIG_FORCEDETH_NAPI
1935                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
1936                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
1937                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
1938                 else
1939                         netif_receive_skb(skb);
1940 #else
1941                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
1942                         vlan_hwaccel_rx(skb, np->vlangrp,
1943                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
1944                 else
1945                         netif_rx(skb);
1946 #endif
1947                 dev->last_rx = jiffies;
1948                 np->stats.rx_packets++;
1949                 np->stats.rx_bytes += len;
1950 next_pkt:
1951                 np->cur_rx++;
1952         }
1953
1954         return count;
1955 }
1956
1957 static void set_bufsize(struct net_device *dev)
1958 {
1959         struct fe_priv *np = netdev_priv(dev);
1960
1961         if (dev->mtu <= ETH_DATA_LEN)
1962                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1963         else
1964                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1965 }
1966
1967 /*
1968  * nv_change_mtu: dev->change_mtu function
1969  * Called with dev_base_lock held for read.
1970  */
1971 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1972 {
1973         struct fe_priv *np = netdev_priv(dev);
1974         int old_mtu;
1975
1976         if (new_mtu < 64 || new_mtu > np->pkt_limit)
1977                 return -EINVAL;
1978
1979         old_mtu = dev->mtu;
1980         dev->mtu = new_mtu;
1981
1982         /* return early if the buffer sizes will not change */
1983         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1984                 return 0;
1985         if (old_mtu == new_mtu)
1986                 return 0;
1987
1988         /* synchronized against open : rtnl_lock() held by caller */
1989         if (netif_running(dev)) {
1990                 u8 __iomem *base = get_hwbase(dev);
1991                 /*
1992                  * It seems that the nic preloads valid ring entries into an
1993                  * internal buffer. The procedure for flushing everything is
1994                  * guessed, there is probably a simpler approach.
1995                  * Changing the MTU is a rare event, it shouldn't matter.
1996                  */
1997                 nv_disable_irq(dev);
1998                 netif_tx_lock_bh(dev);
1999                 spin_lock(&np->lock);
2000                 /* stop engines */
2001                 nv_stop_rx(dev);
2002                 nv_stop_tx(dev);
2003                 nv_txrx_reset(dev);
2004                 /* drain rx queue */
2005                 nv_drain_rx(dev);
2006                 nv_drain_tx(dev);
2007                 /* reinit driver view of the rx queue */
2008                 set_bufsize(dev);
2009                 if (nv_init_ring(dev)) {
2010                         if (!np->in_shutdown)
2011                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2012                 }
2013                 /* reinit nic view of the rx queue */
2014                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2015                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2016                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2017                         base + NvRegRingSizes);
2018                 pci_push(base);
2019                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2020                 pci_push(base);
2021
2022                 /* restart rx engine */
2023                 nv_start_rx(dev);
2024                 nv_start_tx(dev);
2025                 spin_unlock(&np->lock);
2026                 netif_tx_unlock_bh(dev);
2027                 nv_enable_irq(dev);
2028         }
2029         return 0;
2030 }
2031
2032 static void nv_copy_mac_to_hw(struct net_device *dev)
2033 {
2034         u8 __iomem *base = get_hwbase(dev);
2035         u32 mac[2];
2036
2037         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2038                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2039         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2040
2041         writel(mac[0], base + NvRegMacAddrA);
2042         writel(mac[1], base + NvRegMacAddrB);
2043 }
2044
2045 /*
2046  * nv_set_mac_address: dev->set_mac_address function
2047  * Called with rtnl_lock() held.
2048  */
2049 static int nv_set_mac_address(struct net_device *dev, void *addr)
2050 {
2051         struct fe_priv *np = netdev_priv(dev);
2052         struct sockaddr *macaddr = (struct sockaddr*)addr;
2053
2054         if (!is_valid_ether_addr(macaddr->sa_data))
2055                 return -EADDRNOTAVAIL;
2056
2057         /* synchronized against open : rtnl_lock() held by caller */
2058         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2059
2060         if (netif_running(dev)) {
2061                 netif_tx_lock_bh(dev);
2062                 spin_lock_irq(&np->lock);
2063
2064                 /* stop rx engine */
2065                 nv_stop_rx(dev);
2066
2067                 /* set mac address */
2068                 nv_copy_mac_to_hw(dev);
2069
2070                 /* restart rx engine */
2071                 nv_start_rx(dev);
2072                 spin_unlock_irq(&np->lock);
2073                 netif_tx_unlock_bh(dev);
2074         } else {
2075                 nv_copy_mac_to_hw(dev);
2076         }
2077         return 0;
2078 }
2079
2080 /*
2081  * nv_set_multicast: dev->set_multicast function
2082  * Called with netif_tx_lock held.
2083  */
2084 static void nv_set_multicast(struct net_device *dev)
2085 {
2086         struct fe_priv *np = netdev_priv(dev);
2087         u8 __iomem *base = get_hwbase(dev);
2088         u32 addr[2];
2089         u32 mask[2];
2090         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2091
2092         memset(addr, 0, sizeof(addr));
2093         memset(mask, 0, sizeof(mask));
2094
2095         if (dev->flags & IFF_PROMISC) {
2096                 pff |= NVREG_PFF_PROMISC;
2097         } else {
2098                 pff |= NVREG_PFF_MYADDR;
2099
2100                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2101                         u32 alwaysOff[2];
2102                         u32 alwaysOn[2];
2103
2104                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2105                         if (dev->flags & IFF_ALLMULTI) {
2106                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2107                         } else {
2108                                 struct dev_mc_list *walk;
2109
2110                                 walk = dev->mc_list;
2111                                 while (walk != NULL) {
2112                                         u32 a, b;
2113                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2114                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2115                                         alwaysOn[0] &= a;
2116                                         alwaysOff[0] &= ~a;
2117                                         alwaysOn[1] &= b;
2118                                         alwaysOff[1] &= ~b;
2119                                         walk = walk->next;
2120                                 }
2121                         }
2122                         addr[0] = alwaysOn[0];
2123                         addr[1] = alwaysOn[1];
2124                         mask[0] = alwaysOn[0] | alwaysOff[0];
2125                         mask[1] = alwaysOn[1] | alwaysOff[1];
2126                 }
2127         }
2128         addr[0] |= NVREG_MCASTADDRA_FORCE;
2129         pff |= NVREG_PFF_ALWAYS;
2130         spin_lock_irq(&np->lock);
2131         nv_stop_rx(dev);
2132         writel(addr[0], base + NvRegMulticastAddrA);
2133         writel(addr[1], base + NvRegMulticastAddrB);
2134         writel(mask[0], base + NvRegMulticastMaskA);
2135         writel(mask[1], base + NvRegMulticastMaskB);
2136         writel(pff, base + NvRegPacketFilterFlags);
2137         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2138                 dev->name);
2139         nv_start_rx(dev);
2140         spin_unlock_irq(&np->lock);
2141 }
2142
2143 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2144 {
2145         struct fe_priv *np = netdev_priv(dev);
2146         u8 __iomem *base = get_hwbase(dev);
2147
2148         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2149
2150         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2151                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2152                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2153                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2154                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2155                 } else {
2156                         writel(pff, base + NvRegPacketFilterFlags);
2157                 }
2158         }
2159         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2160                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2161                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2162                         writel(NVREG_TX_PAUSEFRAME_ENABLE,  base + NvRegTxPauseFrame);
2163                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2164                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2165                 } else {
2166                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
2167                         writel(regmisc, base + NvRegMisc1);
2168                 }
2169         }
2170 }
2171
2172 /**
2173  * nv_update_linkspeed: Setup the MAC according to the link partner
2174  * @dev: Network device to be configured
2175  *
2176  * The function queries the PHY and checks if there is a link partner.
2177  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2178  * set to 10 MBit HD.
2179  *
2180  * The function returns 0 if there is no link partner and 1 if there is
2181  * a good link partner.
2182  */
2183 static int nv_update_linkspeed(struct net_device *dev)
2184 {
2185         struct fe_priv *np = netdev_priv(dev);
2186         u8 __iomem *base = get_hwbase(dev);
2187         int adv = 0;
2188         int lpa = 0;
2189         int adv_lpa, adv_pause, lpa_pause;
2190         int newls = np->linkspeed;
2191         int newdup = np->duplex;
2192         int mii_status;
2193         int retval = 0;
2194         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2195
2196         /* BMSR_LSTATUS is latched, read it twice:
2197          * we want the current value.
2198          */
2199         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2200         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2201
2202         if (!(mii_status & BMSR_LSTATUS)) {
2203                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2204                                 dev->name);
2205                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2206                 newdup = 0;
2207                 retval = 0;
2208                 goto set_speed;
2209         }
2210
2211         if (np->autoneg == 0) {
2212                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2213                                 dev->name, np->fixed_mode);
2214                 if (np->fixed_mode & LPA_100FULL) {
2215                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2216                         newdup = 1;
2217                 } else if (np->fixed_mode & LPA_100HALF) {
2218                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2219                         newdup = 0;
2220                 } else if (np->fixed_mode & LPA_10FULL) {
2221                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2222                         newdup = 1;
2223                 } else {
2224                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2225                         newdup = 0;
2226                 }
2227                 retval = 1;
2228                 goto set_speed;
2229         }
2230         /* check auto negotiation is complete */
2231         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2232                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2233                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2234                 newdup = 0;
2235                 retval = 0;
2236                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2237                 goto set_speed;
2238         }
2239
2240         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2241         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2242         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2243                                 dev->name, adv, lpa);
2244
2245         retval = 1;
2246         if (np->gigabit == PHY_GIGABIT) {
2247                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2248                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2249
2250                 if ((control_1000 & ADVERTISE_1000FULL) &&
2251                         (status_1000 & LPA_1000FULL)) {
2252                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2253                                 dev->name);
2254                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2255                         newdup = 1;
2256                         goto set_speed;
2257                 }
2258         }
2259
2260         /* FIXME: handle parallel detection properly */
2261         adv_lpa = lpa & adv;
2262         if (adv_lpa & LPA_100FULL) {
2263                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2264                 newdup = 1;
2265         } else if (adv_lpa & LPA_100HALF) {
2266                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2267                 newdup = 0;
2268         } else if (adv_lpa & LPA_10FULL) {
2269                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2270                 newdup = 1;
2271         } else if (adv_lpa & LPA_10HALF) {
2272                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2273                 newdup = 0;
2274         } else {
2275                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2276                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2277                 newdup = 0;
2278         }
2279
2280 set_speed:
2281         if (np->duplex == newdup && np->linkspeed == newls)
2282                 return retval;
2283
2284         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2285                         dev->name, np->linkspeed, np->duplex, newls, newdup);
2286
2287         np->duplex = newdup;
2288         np->linkspeed = newls;
2289
2290         if (np->gigabit == PHY_GIGABIT) {
2291                 phyreg = readl(base + NvRegRandomSeed);
2292                 phyreg &= ~(0x3FF00);
2293                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2294                         phyreg |= NVREG_RNDSEED_FORCE3;
2295                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2296                         phyreg |= NVREG_RNDSEED_FORCE2;
2297                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2298                         phyreg |= NVREG_RNDSEED_FORCE;
2299                 writel(phyreg, base + NvRegRandomSeed);
2300         }
2301
2302         phyreg = readl(base + NvRegPhyInterface);
2303         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2304         if (np->duplex == 0)
2305                 phyreg |= PHY_HALF;
2306         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2307                 phyreg |= PHY_100;
2308         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2309                 phyreg |= PHY_1000;
2310         writel(phyreg, base + NvRegPhyInterface);
2311
2312         if (phyreg & PHY_RGMII) {
2313                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2314                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2315                 else
2316                         txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2317         } else {
2318                 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2319         }
2320         writel(txreg, base + NvRegTxDeferral);
2321
2322         if (np->desc_ver == DESC_VER_1) {
2323                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2324         } else {
2325                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2326                         txreg = NVREG_TX_WM_DESC2_3_1000;
2327                 else
2328                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2329         }
2330         writel(txreg, base + NvRegTxWatermark);
2331
2332         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2333                 base + NvRegMisc1);
2334         pci_push(base);
2335         writel(np->linkspeed, base + NvRegLinkSpeed);
2336         pci_push(base);
2337
2338         pause_flags = 0;
2339         /* setup pause frame */
2340         if (np->duplex != 0) {
2341                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2342                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2343                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2344
2345                         switch (adv_pause) {
2346                         case ADVERTISE_PAUSE_CAP:
2347                                 if (lpa_pause & LPA_PAUSE_CAP) {
2348                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2349                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2350                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2351                                 }
2352                                 break;
2353                         case ADVERTISE_PAUSE_ASYM:
2354                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2355                                 {
2356                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2357                                 }
2358                                 break;
2359                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2360                                 if (lpa_pause & LPA_PAUSE_CAP)
2361                                 {
2362                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
2363                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2364                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2365                                 }
2366                                 if (lpa_pause == LPA_PAUSE_ASYM)
2367                                 {
2368                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2369                                 }
2370                                 break;
2371                         }
2372                 } else {
2373                         pause_flags = np->pause_flags;
2374                 }
2375         }
2376         nv_update_pause(dev, pause_flags);
2377
2378         return retval;
2379 }
2380
2381 static void nv_linkchange(struct net_device *dev)
2382 {
2383         if (nv_update_linkspeed(dev)) {
2384                 if (!netif_carrier_ok(dev)) {
2385                         netif_carrier_on(dev);
2386                         printk(KERN_INFO "%s: link up.\n", dev->name);
2387                         nv_start_rx(dev);
2388                 }
2389         } else {
2390                 if (netif_carrier_ok(dev)) {
2391                         netif_carrier_off(dev);
2392                         printk(KERN_INFO "%s: link down.\n", dev->name);
2393                         nv_stop_rx(dev);
2394                 }
2395         }
2396 }
2397
2398 static void nv_link_irq(struct net_device *dev)
2399 {
2400         u8 __iomem *base = get_hwbase(dev);
2401         u32 miistat;
2402
2403         miistat = readl(base + NvRegMIIStatus);
2404         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2405         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2406
2407         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2408                 nv_linkchange(dev);
2409         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2410 }
2411
2412 static irqreturn_t nv_nic_irq(int foo, void *data)
2413 {
2414         struct net_device *dev = (struct net_device *) data;
2415         struct fe_priv *np = netdev_priv(dev);
2416         u8 __iomem *base = get_hwbase(dev);
2417         u32 events;
2418         int i;
2419
2420         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2421
2422         for (i=0; ; i++) {
2423                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2424                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2425                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2426                 } else {
2427                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2428                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2429                 }
2430                 pci_push(base);
2431                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2432                 if (!(events & np->irqmask))
2433                         break;
2434
2435                 spin_lock(&np->lock);
2436                 nv_tx_done(dev);
2437                 spin_unlock(&np->lock);
2438
2439                 if (events & NVREG_IRQ_LINK) {
2440                         spin_lock(&np->lock);
2441                         nv_link_irq(dev);
2442                         spin_unlock(&np->lock);
2443                 }
2444                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2445                         spin_lock(&np->lock);
2446                         nv_linkchange(dev);
2447                         spin_unlock(&np->lock);
2448                         np->link_timeout = jiffies + LINK_TIMEOUT;
2449                 }
2450                 if (events & (NVREG_IRQ_TX_ERR)) {
2451                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2452                                                 dev->name, events);
2453                 }
2454                 if (events & (NVREG_IRQ_UNKNOWN)) {
2455                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2456                                                 dev->name, events);
2457                 }
2458 #ifdef CONFIG_FORCEDETH_NAPI
2459                 if (events & NVREG_IRQ_RX_ALL) {
2460                         netif_rx_schedule(dev);
2461
2462                         /* Disable furthur receive irq's */
2463                         spin_lock(&np->lock);
2464                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
2465
2466                         if (np->msi_flags & NV_MSI_X_ENABLED)
2467                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2468                         else
2469                                 writel(np->irqmask, base + NvRegIrqMask);
2470                         spin_unlock(&np->lock);
2471                 }
2472 #else
2473                 nv_rx_process(dev, dev->weight);
2474                 if (nv_alloc_rx(dev)) {
2475                         spin_lock(&np->lock);
2476                         if (!np->in_shutdown)
2477                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2478                         spin_unlock(&np->lock);
2479                 }
2480 #endif
2481                 if (i > max_interrupt_work) {
2482                         spin_lock(&np->lock);
2483                         /* disable interrupts on the nic */
2484                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2485                                 writel(0, base + NvRegIrqMask);
2486                         else
2487                                 writel(np->irqmask, base + NvRegIrqMask);
2488                         pci_push(base);
2489
2490                         if (!np->in_shutdown) {
2491                                 np->nic_poll_irq = np->irqmask;
2492                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2493                         }
2494                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2495                         spin_unlock(&np->lock);
2496                         break;
2497                 }
2498
2499         }
2500         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2501
2502         return IRQ_RETVAL(i);
2503 }
2504
2505 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
2506 {
2507         struct net_device *dev = (struct net_device *) data;
2508         struct fe_priv *np = netdev_priv(dev);
2509         u8 __iomem *base = get_hwbase(dev);
2510         u32 events;
2511         int i;
2512         unsigned long flags;
2513
2514         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
2515
2516         for (i=0; ; i++) {
2517                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
2518                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
2519                 pci_push(base);
2520                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
2521                 if (!(events & np->irqmask))
2522                         break;
2523
2524                 spin_lock_irqsave(&np->lock, flags);
2525                 nv_tx_done(dev);
2526                 spin_unlock_irqrestore(&np->lock, flags);
2527
2528                 if (events & (NVREG_IRQ_TX_ERR)) {
2529                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2530                                                 dev->name, events);
2531                 }
2532                 if (i > max_interrupt_work) {
2533                         spin_lock_irqsave(&np->lock, flags);
2534                         /* disable interrupts on the nic */
2535                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
2536                         pci_push(base);
2537
2538                         if (!np->in_shutdown) {
2539                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
2540                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2541                         }
2542                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
2543                         spin_unlock_irqrestore(&np->lock, flags);
2544                         break;
2545                 }
2546
2547         }
2548         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
2549
2550         return IRQ_RETVAL(i);
2551 }
2552
2553 #ifdef CONFIG_FORCEDETH_NAPI
2554 static int nv_napi_poll(struct net_device *dev, int *budget)
2555 {
2556         int pkts, limit = min(*budget, dev->quota);
2557         struct fe_priv *np = netdev_priv(dev);
2558         u8 __iomem *base = get_hwbase(dev);
2559
2560         pkts = nv_rx_process(dev, limit);
2561
2562         if (nv_alloc_rx(dev)) {
2563                 spin_lock_irq(&np->lock);
2564                 if (!np->in_shutdown)
2565                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2566                 spin_unlock_irq(&np->lock);
2567         }
2568
2569         if (pkts < limit) {
2570                 /* all done, no more packets present */
2571                 netif_rx_complete(dev);
2572
2573                 /* re-enable receive interrupts */
2574                 spin_lock_irq(&np->lock);
2575                 np->irqmask |= NVREG_IRQ_RX_ALL;
2576                 if (np->msi_flags & NV_MSI_X_ENABLED)
2577                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2578                 else
2579                         writel(np->irqmask, base + NvRegIrqMask);
2580                 spin_unlock_irq(&np->lock);
2581                 return 0;
2582         } else {
2583                 /* used up our quantum, so reschedule */
2584                 dev->quota -= pkts;
2585                 *budget -= pkts;
2586                 return 1;
2587         }
2588 }
2589 #endif
2590
2591 #ifdef CONFIG_FORCEDETH_NAPI
2592 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
2593 {
2594         struct net_device *dev = (struct net_device *) data;
2595         u8 __iomem *base = get_hwbase(dev);
2596         u32 events;
2597
2598         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2599         writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2600
2601         if (events) {
2602                 netif_rx_schedule(dev);
2603                 /* disable receive interrupts on the nic */
2604                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2605                 pci_push(base);
2606         }
2607         return IRQ_HANDLED;
2608 }
2609 #else
2610 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
2611 {
2612         struct net_device *dev = (struct net_device *) data;
2613         struct fe_priv *np = netdev_priv(dev);
2614         u8 __iomem *base = get_hwbase(dev);
2615         u32 events;
2616         int i;
2617         unsigned long flags;
2618
2619         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
2620
2621         for (i=0; ; i++) {
2622                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2623                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2624                 pci_push(base);
2625                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
2626                 if (!(events & np->irqmask))
2627                         break;
2628
2629                 nv_rx_process(dev, dev->weight);
2630                 if (nv_alloc_rx(dev)) {
2631                         spin_lock_irqsave(&np->lock, flags);
2632                         if (!np->in_shutdown)
2633                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2634                         spin_unlock_irqrestore(&np->lock, flags);
2635                 }
2636
2637                 if (i > max_interrupt_work) {
2638                         spin_lock_irqsave(&np->lock, flags);
2639                         /* disable interrupts on the nic */
2640                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2641                         pci_push(base);
2642
2643                         if (!np->in_shutdown) {
2644                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
2645                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2646                         }
2647                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
2648                         spin_unlock_irqrestore(&np->lock, flags);
2649                         break;
2650                 }
2651         }
2652         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
2653
2654         return IRQ_RETVAL(i);
2655 }
2656 #endif
2657
2658 static irqreturn_t nv_nic_irq_other(int foo, void *data)
2659 {
2660         struct net_device *dev = (struct net_device *) data;
2661         struct fe_priv *np = netdev_priv(dev);
2662         u8 __iomem *base = get_hwbase(dev);
2663         u32 events;
2664         int i;
2665         unsigned long flags;
2666
2667         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
2668
2669         for (i=0; ; i++) {
2670                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
2671                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
2672                 pci_push(base);
2673                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2674                 if (!(events & np->irqmask))
2675                         break;
2676
2677                 if (events & NVREG_IRQ_LINK) {
2678                         spin_lock_irqsave(&np->lock, flags);
2679                         nv_link_irq(dev);
2680                         spin_unlock_irqrestore(&np->lock, flags);
2681                 }
2682                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2683                         spin_lock_irqsave(&np->lock, flags);
2684                         nv_linkchange(dev);
2685                         spin_unlock_irqrestore(&np->lock, flags);
2686                         np->link_timeout = jiffies + LINK_TIMEOUT;
2687                 }
2688                 if (events & (NVREG_IRQ_UNKNOWN)) {
2689                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2690                                                 dev->name, events);
2691                 }
2692                 if (i > max_interrupt_work) {
2693                         spin_lock_irqsave(&np->lock, flags);
2694                         /* disable interrupts on the nic */
2695                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2696                         pci_push(base);
2697
2698                         if (!np->in_shutdown) {
2699                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2700                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2701                         }
2702                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
2703                         spin_unlock_irqrestore(&np->lock, flags);
2704                         break;
2705                 }
2706
2707         }
2708         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
2709
2710         return IRQ_RETVAL(i);
2711 }
2712
2713 static irqreturn_t nv_nic_irq_test(int foo, void *data)
2714 {
2715         struct net_device *dev = (struct net_device *) data;
2716         struct fe_priv *np = netdev_priv(dev);
2717         u8 __iomem *base = get_hwbase(dev);
2718         u32 events;
2719
2720         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
2721
2722         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2723                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2724                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
2725         } else {
2726                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2727                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
2728         }
2729         pci_push(base);
2730         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2731         if (!(events & NVREG_IRQ_TIMER))
2732                 return IRQ_RETVAL(0);
2733
2734         spin_lock(&np->lock);
2735         np->intr_test = 1;
2736         spin_unlock(&np->lock);
2737
2738         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
2739
2740         return IRQ_RETVAL(1);
2741 }
2742
2743 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
2744 {
2745         u8 __iomem *base = get_hwbase(dev);
2746         int i;
2747         u32 msixmap = 0;
2748
2749         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2750          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2751          * the remaining 8 interrupts.
2752          */
2753         for (i = 0; i < 8; i++) {
2754                 if ((irqmask >> i) & 0x1) {
2755                         msixmap |= vector << (i << 2);
2756                 }
2757         }
2758         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
2759
2760         msixmap = 0;
2761         for (i = 0; i < 8; i++) {
2762                 if ((irqmask >> (i + 8)) & 0x1) {
2763                         msixmap |= vector << (i << 2);
2764                 }
2765         }
2766         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
2767 }
2768
2769 static int nv_request_irq(struct net_device *dev, int intr_test)
2770 {
2771         struct fe_priv *np = get_nvpriv(dev);
2772         u8 __iomem *base = get_hwbase(dev);
2773         int ret = 1;
2774         int i;
2775
2776         if (np->msi_flags & NV_MSI_X_CAPABLE) {
2777                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2778                         np->msi_x_entry[i].entry = i;
2779                 }
2780                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
2781                         np->msi_flags |= NV_MSI_X_ENABLED;
2782                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
2783                                 /* Request irq for rx handling */
2784                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
2785                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
2786                                         pci_disable_msix(np->pci_dev);
2787                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2788                                         goto out_err;
2789                                 }
2790                                 /* Request irq for tx handling */
2791                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
2792                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
2793                                         pci_disable_msix(np->pci_dev);
2794                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2795                                         goto out_free_rx;
2796                                 }
2797                                 /* Request irq for link and timer handling */
2798                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
2799                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
2800                                         pci_disable_msix(np->pci_dev);
2801                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2802                                         goto out_free_tx;
2803                                 }
2804                                 /* map interrupts to their respective vector */
2805                                 writel(0, base + NvRegMSIXMap0);
2806                                 writel(0, base + NvRegMSIXMap1);
2807                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
2808                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
2809                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
2810                         } else {
2811                                 /* Request irq for all interrupts */
2812                                 if ((!intr_test &&
2813                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2814                                     (intr_test &&
2815                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2816                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2817                                         pci_disable_msix(np->pci_dev);
2818                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2819                                         goto out_err;
2820                                 }
2821
2822                                 /* map interrupts to vector 0 */
2823                                 writel(0, base + NvRegMSIXMap0);
2824                                 writel(0, base + NvRegMSIXMap1);
2825                         }
2826                 }
2827         }
2828         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
2829                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
2830                         np->msi_flags |= NV_MSI_ENABLED;
2831                         if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2832                             (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2833                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2834                                 pci_disable_msi(np->pci_dev);
2835                                 np->msi_flags &= ~NV_MSI_ENABLED;
2836                                 goto out_err;
2837                         }
2838
2839                         /* map interrupts to vector 0 */
2840                         writel(0, base + NvRegMSIMap0);
2841                         writel(0, base + NvRegMSIMap1);
2842                         /* enable msi vector 0 */
2843                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
2844                 }
2845         }
2846         if (ret != 0) {
2847                 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2848                     (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0))
2849                         goto out_err;
2850
2851         }
2852
2853         return 0;
2854 out_free_tx:
2855         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
2856 out_free_rx:
2857         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
2858 out_err:
2859         return 1;
2860 }
2861
2862 static void nv_free_irq(struct net_device *dev)
2863 {
2864         struct fe_priv *np = get_nvpriv(dev);
2865         int i;
2866
2867         if (np->msi_flags & NV_MSI_X_ENABLED) {
2868                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2869                         free_irq(np->msi_x_entry[i].vector, dev);
2870                 }
2871                 pci_disable_msix(np->pci_dev);
2872                 np->msi_flags &= ~NV_MSI_X_ENABLED;
2873         } else {
2874                 free_irq(np->pci_dev->irq, dev);
2875                 if (np->msi_flags & NV_MSI_ENABLED) {
2876                         pci_disable_msi(np->pci_dev);
2877                         np->msi_flags &= ~NV_MSI_ENABLED;
2878                 }
2879         }
2880 }
2881
2882 static void nv_do_nic_poll(unsigned long data)
2883 {
2884         struct net_device *dev = (struct net_device *) data;
2885         struct fe_priv *np = netdev_priv(dev);
2886         u8 __iomem *base = get_hwbase(dev);
2887         u32 mask = 0;
2888
2889         /*
2890          * First disable irq(s) and then
2891          * reenable interrupts on the nic, we have to do this before calling
2892          * nv_nic_irq because that may decide to do otherwise
2893          */
2894
2895         if (!using_multi_irqs(dev)) {
2896                 if (np->msi_flags & NV_MSI_X_ENABLED)
2897                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2898                 else
2899                         disable_irq_lockdep(dev->irq);
2900                 mask = np->irqmask;
2901         } else {
2902                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2903                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2904                         mask |= NVREG_IRQ_RX_ALL;
2905                 }
2906                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2907                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2908                         mask |= NVREG_IRQ_TX_ALL;
2909                 }
2910                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2911                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2912                         mask |= NVREG_IRQ_OTHER;
2913                 }
2914         }
2915         np->nic_poll_irq = 0;
2916
2917         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
2918
2919         writel(mask, base + NvRegIrqMask);
2920         pci_push(base);
2921
2922         if (!using_multi_irqs(dev)) {
2923                 nv_nic_irq(0, dev);
2924                 if (np->msi_flags & NV_MSI_X_ENABLED)
2925                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2926                 else
2927                         enable_irq_lockdep(dev->irq);
2928         } else {
2929                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2930                         nv_nic_irq_rx(0, dev);
2931                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2932                 }
2933                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2934                         nv_nic_irq_tx(0, dev);
2935                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2936                 }
2937                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2938                         nv_nic_irq_other(0, dev);
2939                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2940                 }
2941         }
2942 }
2943
2944 #ifdef CONFIG_NET_POLL_CONTROLLER
2945 static void nv_poll_controller(struct net_device *dev)
2946 {
2947         nv_do_nic_poll((unsigned long) dev);
2948 }
2949 #endif
2950
2951 static void nv_do_stats_poll(unsigned long data)
2952 {
2953         struct net_device *dev = (struct net_device *) data;
2954         struct fe_priv *np = netdev_priv(dev);
2955         u8 __iomem *base = get_hwbase(dev);
2956
2957         np->estats.tx_bytes += readl(base + NvRegTxCnt);
2958         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
2959         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
2960         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
2961         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
2962         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
2963         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
2964         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
2965         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
2966         np->estats.tx_deferral += readl(base + NvRegTxDef);
2967         np->estats.tx_packets += readl(base + NvRegTxFrame);
2968         np->estats.tx_pause += readl(base + NvRegTxPause);
2969         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
2970         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
2971         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
2972         np->estats.rx_runt += readl(base + NvRegRxRunt);
2973         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
2974         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
2975         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
2976         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
2977         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
2978         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
2979         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
2980         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
2981         np->estats.rx_bytes += readl(base + NvRegRxCnt);
2982         np->estats.rx_pause += readl(base + NvRegRxPause);
2983         np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
2984         np->estats.rx_packets =
2985                 np->estats.rx_unicast +
2986                 np->estats.rx_multicast +
2987                 np->estats.rx_broadcast;
2988         np->estats.rx_errors_total =
2989                 np->estats.rx_crc_errors +
2990                 np->estats.rx_over_errors +
2991                 np->estats.rx_frame_error +
2992                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
2993                 np->estats.rx_late_collision +
2994                 np->estats.rx_runt +
2995                 np->estats.rx_frame_too_long;
2996
2997         if (!np->in_shutdown)
2998                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
2999 }
3000
3001 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3002 {
3003         struct fe_priv *np = netdev_priv(dev);
3004         strcpy(info->driver, "forcedeth");
3005         strcpy(info->version, FORCEDETH_VERSION);
3006         strcpy(info->bus_info, pci_name(np->pci_dev));
3007 }
3008
3009 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3010 {
3011         struct fe_priv *np = netdev_priv(dev);
3012         wolinfo->supported = WAKE_MAGIC;
3013
3014         spin_lock_irq(&np->lock);
3015         if (np->wolenabled)
3016                 wolinfo->wolopts = WAKE_MAGIC;
3017         spin_unlock_irq(&np->lock);
3018 }
3019
3020 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3021 {
3022         struct fe_priv *np = netdev_priv(dev);
3023         u8 __iomem *base = get_hwbase(dev);
3024         u32 flags = 0;
3025
3026         if (wolinfo->wolopts == 0) {
3027                 np->wolenabled = 0;
3028         } else if (wolinfo->wolopts & WAKE_MAGIC) {
3029                 np->wolenabled = 1;
3030                 flags = NVREG_WAKEUPFLAGS_ENABLE;
3031         }
3032         if (netif_running(dev)) {
3033                 spin_lock_irq(&np->lock);
3034                 writel(flags, base + NvRegWakeUpFlags);
3035                 spin_unlock_irq(&np->lock);
3036         }
3037         return 0;
3038 }
3039
3040 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3041 {
3042         struct fe_priv *np = netdev_priv(dev);
3043         int adv;
3044
3045         spin_lock_irq(&np->lock);
3046         ecmd->port = PORT_MII;
3047         if (!netif_running(dev)) {
3048                 /* We do not track link speed / duplex setting if the
3049                  * interface is disabled. Force a link check */
3050                 if (nv_update_linkspeed(dev)) {
3051                         if (!netif_carrier_ok(dev))
3052                                 netif_carrier_on(dev);
3053                 } else {
3054                         if (netif_carrier_ok(dev))
3055                                 netif_carrier_off(dev);
3056                 }
3057         }
3058
3059         if (netif_carrier_ok(dev)) {
3060                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3061                 case NVREG_LINKSPEED_10:
3062                         ecmd->speed = SPEED_10;
3063                         break;
3064                 case NVREG_LINKSPEED_100:
3065                         ecmd->speed = SPEED_100;
3066                         break;
3067                 case NVREG_LINKSPEED_1000:
3068                         ecmd->speed = SPEED_1000;
3069                         break;
3070                 }
3071                 ecmd->duplex = DUPLEX_HALF;
3072                 if (np->duplex)
3073                         ecmd->duplex = DUPLEX_FULL;
3074         } else {
3075                 ecmd->speed = -1;
3076                 ecmd->duplex = -1;
3077         }
3078
3079         ecmd->autoneg = np->autoneg;
3080
3081         ecmd->advertising = ADVERTISED_MII;
3082         if (np->autoneg) {
3083                 ecmd->advertising |= ADVERTISED_Autoneg;
3084                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3085                 if (adv & ADVERTISE_10HALF)
3086                         ecmd->advertising |= ADVERTISED_10baseT_Half;
3087                 if (adv & ADVERTISE_10FULL)
3088                         ecmd->advertising |= ADVERTISED_10baseT_Full;
3089                 if (adv & ADVERTISE_100HALF)
3090                         ecmd->advertising |= ADVERTISED_100baseT_Half;
3091                 if (adv & ADVERTISE_100FULL)
3092                         ecmd->advertising |= ADVERTISED_100baseT_Full;
3093                 if (np->gigabit == PHY_GIGABIT) {
3094                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3095                         if (adv & ADVERTISE_1000FULL)
3096                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3097                 }
3098         }
3099         ecmd->supported = (SUPPORTED_Autoneg |
3100                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3101                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3102                 SUPPORTED_MII);
3103         if (np->gigabit == PHY_GIGABIT)
3104                 ecmd->supported |= SUPPORTED_1000baseT_Full;
3105
3106         ecmd->phy_address = np->phyaddr;
3107         ecmd->transceiver = XCVR_EXTERNAL;
3108
3109         /* ignore maxtxpkt, maxrxpkt for now */
3110         spin_unlock_irq(&np->lock);
3111         return 0;
3112 }
3113
3114 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3115 {
3116         struct fe_priv *np = netdev_priv(dev);
3117
3118         if (ecmd->port != PORT_MII)
3119                 return -EINVAL;
3120         if (ecmd->transceiver != XCVR_EXTERNAL)
3121                 return -EINVAL;
3122         if (ecmd->phy_address != np->phyaddr) {
3123                 /* TODO: support switching between multiple phys. Should be
3124                  * trivial, but not enabled due to lack of test hardware. */
3125                 return -EINVAL;
3126         }
3127         if (ecmd->autoneg == AUTONEG_ENABLE) {
3128                 u32 mask;
3129
3130                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3131                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3132                 if (np->gigabit == PHY_GIGABIT)
3133                         mask |= ADVERTISED_1000baseT_Full;
3134
3135                 if ((ecmd->advertising & mask) == 0)
3136                         return -EINVAL;
3137
3138         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3139                 /* Note: autonegotiation disable, speed 1000 intentionally
3140                  * forbidden - noone should need that. */
3141
3142                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3143                         return -EINVAL;
3144                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3145                         return -EINVAL;
3146         } else {
3147                 return -EINVAL;
3148         }
3149
3150         netif_carrier_off(dev);
3151         if (netif_running(dev)) {
3152                 nv_disable_irq(dev);
3153                 netif_tx_lock_bh(dev);
3154                 spin_lock(&np->lock);
3155                 /* stop engines */
3156                 nv_stop_rx(dev);
3157                 nv_stop_tx(dev);
3158                 spin_unlock(&np->lock);
3159                 netif_tx_unlock_bh(dev);
3160         }
3161
3162         if (ecmd->autoneg == AUTONEG_ENABLE) {
3163                 int adv, bmcr;
3164
3165                 np->autoneg = 1;
3166
3167                 /* advertise only what has been requested */
3168                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3169                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3170                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3171                         adv |= ADVERTISE_10HALF;
3172                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3173                         adv |= ADVERTISE_10FULL;
3174                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3175                         adv |= ADVERTISE_100HALF;
3176                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3177                         adv |= ADVERTISE_100FULL;
3178                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
3179                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3180                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3181                         adv |=  ADVERTISE_PAUSE_ASYM;
3182                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3183
3184                 if (np->gigabit == PHY_GIGABIT) {
3185                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3186                         adv &= ~ADVERTISE_1000FULL;
3187                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3188                                 adv |= ADVERTISE_1000FULL;
3189                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3190                 }
3191
3192                 if (netif_running(dev))
3193                         printk(KERN_INFO "%s: link down.\n", dev->name);
3194                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3195                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3196                         bmcr |= BMCR_ANENABLE;
3197                         /* reset the phy in order for settings to stick,
3198                          * and cause autoneg to start */
3199                         if (phy_reset(dev, bmcr)) {
3200                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3201                                 return -EINVAL;
3202                         }
3203                 } else {
3204                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3205                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3206                 }
3207         } else {
3208                 int adv, bmcr;
3209
3210                 np->autoneg = 0;
3211
3212                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3213                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3214                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3215                         adv |= ADVERTISE_10HALF;
3216                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3217                         adv |= ADVERTISE_10FULL;
3218                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3219                         adv |= ADVERTISE_100HALF;
3220                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3221                         adv |= ADVERTISE_100FULL;
3222                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3223                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3224                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3225                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3226                 }
3227                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3228                         adv |=  ADVERTISE_PAUSE_ASYM;
3229                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3230                 }
3231                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3232                 np->fixed_mode = adv;
3233
3234                 if (np->gigabit == PHY_GIGABIT) {
3235                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3236                         adv &= ~ADVERTISE_1000FULL;
3237                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3238                 }
3239
3240                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3241                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3242                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3243                         bmcr |= BMCR_FULLDPLX;
3244                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3245                         bmcr |= BMCR_SPEED100;
3246                 if (np->phy_oui == PHY_OUI_MARVELL) {
3247                         /* reset the phy in order for forced mode settings to stick */
3248                         if (phy_reset(dev, bmcr)) {
3249                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3250                                 return -EINVAL;
3251                         }
3252                 } else {
3253                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3254                         if (netif_running(dev)) {
3255                                 /* Wait a bit and then reconfigure the nic. */
3256                                 udelay(10);
3257                                 nv_linkchange(dev);
3258                         }
3259                 }
3260         }
3261
3262         if (netif_running(dev)) {
3263                 nv_start_rx(dev);
3264                 nv_start_tx(dev);
3265                 nv_enable_irq(dev);
3266         }
3267
3268         return 0;
3269 }
3270
3271 #define FORCEDETH_REGS_VER      1
3272
3273 static int nv_get_regs_len(struct net_device *dev)
3274 {
3275         struct fe_priv *np = netdev_priv(dev);
3276         return np->register_size;
3277 }
3278
3279 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3280 {
3281         struct fe_priv *np = netdev_priv(dev);
3282         u8 __iomem *base = get_hwbase(dev);
3283         u32 *rbuf = buf;
3284         int i;
3285
3286         regs->version = FORCEDETH_REGS_VER;
3287         spin_lock_irq(&np->lock);
3288         for (i = 0;i <= np->register_size/sizeof(u32); i++)
3289                 rbuf[i] = readl(base + i*sizeof(u32));
3290         spin_unlock_irq(&np->lock);
3291 }
3292
3293 static int nv_nway_reset(struct net_device *dev)
3294 {
3295         struct fe_priv *np = netdev_priv(dev);
3296         int ret;
3297
3298         if (np->autoneg) {
3299                 int bmcr;
3300
3301                 netif_carrier_off(dev);
3302                 if (netif_running(dev)) {
3303                         nv_disable_irq(dev);
3304                         netif_tx_lock_bh(dev);
3305                         spin_lock(&np->lock);
3306                         /* stop engines */
3307                         nv_stop_rx(dev);
3308                         nv_stop_tx(dev);
3309                         spin_unlock(&np->lock);
3310                         netif_tx_unlock_bh(dev);
3311                         printk(KERN_INFO "%s: link down.\n", dev->name);
3312                 }
3313
3314                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3315                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3316                         bmcr |= BMCR_ANENABLE;
3317                         /* reset the phy in order for settings to stick*/
3318                         if (phy_reset(dev, bmcr)) {
3319                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3320                                 return -EINVAL;
3321                         }
3322                 } else {
3323                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3324                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3325                 }
3326
3327                 if (netif_running(dev)) {
3328                         nv_start_rx(dev);
3329                         nv_start_tx(dev);
3330                         nv_enable_irq(dev);
3331                 }
3332                 ret = 0;
3333         } else {
3334                 ret = -EINVAL;
3335         }
3336
3337         return ret;
3338 }
3339
3340 static int nv_set_tso(struct net_device *dev, u32 value)
3341 {
3342         struct fe_priv *np = netdev_priv(dev);
3343
3344         if ((np->driver_data & DEV_HAS_CHECKSUM))
3345                 return ethtool_op_set_tso(dev, value);
3346         else
3347                 return -EOPNOTSUPP;
3348 }
3349
3350 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3351 {
3352         struct fe_priv *np = netdev_priv(dev);
3353
3354         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3355         ring->rx_mini_max_pending = 0;
3356         ring->rx_jumbo_max_pending = 0;
3357         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3358
3359         ring->rx_pending = np->rx_ring_size;
3360         ring->rx_mini_pending = 0;
3361         ring->rx_jumbo_pending = 0;
3362         ring->tx_pending = np->tx_ring_size;
3363 }
3364
3365 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3366 {
3367         struct fe_priv *np = netdev_priv(dev);
3368         u8 __iomem *base = get_hwbase(dev);
3369         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff, *rx_dma, *tx_dma, *tx_dma_len;
3370         dma_addr_t ring_addr;
3371
3372         if (ring->rx_pending < RX_RING_MIN ||
3373             ring->tx_pending < TX_RING_MIN ||
3374             ring->rx_mini_pending != 0 ||
3375             ring->rx_jumbo_pending != 0 ||
3376             (np->desc_ver == DESC_VER_1 &&
3377              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3378               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3379             (np->desc_ver != DESC_VER_1 &&
3380              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3381               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3382                 return -EINVAL;
3383         }
3384
3385         /* allocate new rings */
3386         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3387                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3388                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3389                                             &ring_addr);
3390         } else {
3391                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3392                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3393                                             &ring_addr);
3394         }
3395         rx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->rx_pending, GFP_KERNEL);
3396         rx_dma = kmalloc(sizeof(dma_addr_t) * ring->rx_pending, GFP_KERNEL);
3397         tx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->tx_pending, GFP_KERNEL);
3398         tx_dma = kmalloc(sizeof(dma_addr_t) * ring->tx_pending, GFP_KERNEL);
3399         tx_dma_len = kmalloc(sizeof(unsigned int) * ring->tx_pending, GFP_KERNEL);
3400         if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) {
3401                 /* fall back to old rings */
3402                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3403                         if (rxtx_ring)
3404                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3405                                                     rxtx_ring, ring_addr);
3406                 } else {
3407                         if (rxtx_ring)
3408                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3409                                                     rxtx_ring, ring_addr);
3410                 }
3411                 if (rx_skbuff)
3412                         kfree(rx_skbuff);
3413                 if (rx_dma)
3414                         kfree(rx_dma);
3415                 if (tx_skbuff)
3416                         kfree(tx_skbuff);
3417                 if (tx_dma)
3418                         kfree(tx_dma);
3419                 if (tx_dma_len)
3420                         kfree(tx_dma_len);
3421                 goto exit;
3422         }
3423
3424         if (netif_running(dev)) {
3425                 nv_disable_irq(dev);
3426                 netif_tx_lock_bh(dev);
3427                 spin_lock(&np->lock);
3428                 /* stop engines */
3429                 nv_stop_rx(dev);
3430                 nv_stop_tx(dev);
3431                 nv_txrx_reset(dev);
3432                 /* drain queues */
3433                 nv_drain_rx(dev);
3434                 nv_drain_tx(dev);
3435                 /* delete queues */
3436                 free_rings(dev);
3437         }
3438
3439         /* set new values */
3440         np->rx_ring_size = ring->rx_pending;
3441         np->tx_ring_size = ring->tx_pending;
3442         np->tx_limit_stop = ring->tx_pending - TX_LIMIT_DIFFERENCE;
3443         np->tx_limit_start = ring->tx_pending - TX_LIMIT_DIFFERENCE - 1;
3444         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3445                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
3446                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
3447         } else {
3448                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
3449                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3450         }
3451         np->rx_skbuff = (struct sk_buff**)rx_skbuff;
3452         np->rx_dma = (dma_addr_t*)rx_dma;
3453         np->tx_skbuff = (struct sk_buff**)tx_skbuff;
3454         np->tx_dma = (dma_addr_t*)tx_dma;
3455         np->tx_dma_len = (unsigned int*)tx_dma_len;
3456         np->ring_addr = ring_addr;
3457
3458         memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
3459         memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
3460         memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
3461         memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
3462         memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
3463
3464         if (netif_running(dev)) {
3465                 /* reinit driver view of the queues */
3466                 set_bufsize(dev);
3467                 if (nv_init_ring(dev)) {
3468                         if (!np->in_shutdown)
3469                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3470                 }
3471
3472                 /* reinit nic view of the queues */
3473                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3474                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3475                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3476                         base + NvRegRingSizes);
3477                 pci_push(base);
3478                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3479                 pci_push(base);
3480
3481                 /* restart engines */
3482                 nv_start_rx(dev);
3483                 nv_start_tx(dev);
3484                 spin_unlock(&np->lock);
3485                 netif_tx_unlock_bh(dev);
3486                 nv_enable_irq(dev);
3487         }
3488         return 0;
3489 exit:
3490         return -ENOMEM;
3491 }
3492
3493 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3494 {
3495         struct fe_priv *np = netdev_priv(dev);
3496
3497         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
3498         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
3499         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
3500 }
3501
3502 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3503 {
3504         struct fe_priv *np = netdev_priv(dev);
3505         int adv, bmcr;
3506
3507         if ((!np->autoneg && np->duplex == 0) ||
3508             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
3509                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
3510                        dev->name);
3511                 return -EINVAL;
3512         }
3513         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
3514                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
3515                 return -EINVAL;
3516         }
3517
3518         netif_carrier_off(dev);
3519         if (netif_running(dev)) {
3520                 nv_disable_irq(dev);
3521                 netif_tx_lock_bh(dev);
3522                 spin_lock(&np->lock);
3523                 /* stop engines */
3524                 nv_stop_rx(dev);
3525                 nv_stop_tx(dev);
3526                 spin_unlock(&np->lock);
3527                 netif_tx_unlock_bh(dev);
3528         }
3529
3530         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
3531         if (pause->rx_pause)
3532                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
3533         if (pause->tx_pause)
3534                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
3535
3536         if (np->autoneg && pause->autoneg) {
3537                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
3538
3539                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3540                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3541                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3542                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3543                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3544                         adv |=  ADVERTISE_PAUSE_ASYM;
3545                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3546
3547                 if (netif_running(dev))
3548                         printk(KERN_INFO "%s: link down.\n", dev->name);
3549                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3550                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3551                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3552         } else {
3553                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3554                 if (pause->rx_pause)
3555                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3556                 if (pause->tx_pause)
3557                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3558
3559                 if (!netif_running(dev))
3560                         nv_update_linkspeed(dev);
3561                 else
3562                         nv_update_pause(dev, np->pause_flags);
3563         }
3564
3565         if (netif_running(dev)) {
3566                 nv_start_rx(dev);
3567                 nv_start_tx(dev);
3568                 nv_enable_irq(dev);
3569         }
3570         return 0;
3571 }
3572
3573 static u32 nv_get_rx_csum(struct net_device *dev)
3574 {
3575         struct fe_priv *np = netdev_priv(dev);
3576         return (np->rx_csum) != 0;
3577 }
3578
3579 static int nv_set_rx_csum(struct net_device *dev, u32 data)
3580 {
3581         struct fe_priv *np = netdev_priv(dev);
3582         u8 __iomem *base = get_hwbase(dev);
3583         int retcode = 0;
3584
3585         if (np->driver_data & DEV_HAS_CHECKSUM) {
3586                 if (data) {
3587                         np->rx_csum = 1;
3588                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
3589                 } else {
3590                         np->rx_csum = 0;
3591                         /* vlan is dependent on rx checksum offload */
3592                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
3593                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3594                 }
3595                 if (netif_running(dev)) {
3596                         spin_lock_irq(&np->lock);
3597                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
3598                         spin_unlock_irq(&np->lock);
3599                 }
3600         } else {
3601                 return -EINVAL;
3602         }
3603
3604         return retcode;
3605 }
3606
3607 static int nv_set_tx_csum(struct net_device *dev, u32 data)
3608 {
3609         struct fe_priv *np = netdev_priv(dev);
3610
3611         if (np->driver_data & DEV_HAS_CHECKSUM)
3612                 return ethtool_op_set_tx_hw_csum(dev, data);
3613         else
3614                 return -EOPNOTSUPP;
3615 }
3616
3617 static int nv_set_sg(struct net_device *dev, u32 data)
3618 {
3619         struct fe_priv *np = netdev_priv(dev);
3620
3621         if (np->driver_data & DEV_HAS_CHECKSUM)
3622                 return ethtool_op_set_sg(dev, data);
3623         else
3624                 return -EOPNOTSUPP;
3625 }
3626
3627 static int nv_get_stats_count(struct net_device *dev)
3628 {
3629         struct fe_priv *np = netdev_priv(dev);
3630
3631         if (np->driver_data & DEV_HAS_STATISTICS)
3632                 return sizeof(struct nv_ethtool_stats)/sizeof(u64);
3633         else
3634                 return 0;
3635 }
3636
3637 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
3638 {
3639         struct fe_priv *np = netdev_priv(dev);
3640
3641         /* update stats */
3642         nv_do_stats_poll((unsigned long)dev);
3643
3644         memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
3645 }
3646
3647 static int nv_self_test_count(struct net_device *dev)
3648 {
3649         struct fe_priv *np = netdev_priv(dev);
3650
3651         if (np->driver_data & DEV_HAS_TEST_EXTENDED)
3652                 return NV_TEST_COUNT_EXTENDED;
3653         else
3654                 return NV_TEST_COUNT_BASE;
3655 }
3656
3657 static int nv_link_test(struct net_device *dev)
3658 {
3659         struct fe_priv *np = netdev_priv(dev);
3660         int mii_status;
3661
3662         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3663         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3664
3665         /* check phy link status */
3666         if (!(mii_status & BMSR_LSTATUS))
3667                 return 0;
3668         else
3669                 return 1;
3670 }
3671
3672 static int nv_register_test(struct net_device *dev)
3673 {
3674         u8 __iomem *base = get_hwbase(dev);
3675         int i = 0;
3676         u32 orig_read, new_read;
3677
3678         do {
3679                 orig_read = readl(base + nv_registers_test[i].reg);
3680
3681                 /* xor with mask to toggle bits */
3682                 orig_read ^= nv_registers_test[i].mask;
3683
3684                 writel(orig_read, base + nv_registers_test[i].reg);
3685
3686                 new_read = readl(base + nv_registers_test[i].reg);
3687
3688                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
3689                         return 0;
3690
3691                 /* restore original value */
3692                 orig_read ^= nv_registers_test[i].mask;
3693                 writel(orig_read, base + nv_registers_test[i].reg);
3694
3695         } while (nv_registers_test[++i].reg != 0);
3696
3697         return 1;
3698 }
3699
3700 static int nv_interrupt_test(struct net_device *dev)
3701 {
3702         struct fe_priv *np = netdev_priv(dev);
3703         u8 __iomem *base = get_hwbase(dev);
3704         int ret = 1;
3705         int testcnt;
3706         u32 save_msi_flags, save_poll_interval = 0;
3707
3708         if (netif_running(dev)) {
3709                 /* free current irq */
3710                 nv_free_irq(dev);
3711                 save_poll_interval = readl(base+NvRegPollingInterval);
3712         }
3713
3714         /* flag to test interrupt handler */
3715         np->intr_test = 0;
3716
3717         /* setup test irq */
3718         save_msi_flags = np->msi_flags;
3719         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
3720         np->msi_flags |= 0x001; /* setup 1 vector */
3721         if (nv_request_irq(dev, 1))
3722                 return 0;
3723
3724         /* setup timer interrupt */
3725         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3726         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3727
3728         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3729
3730         /* wait for at least one interrupt */
3731         msleep(100);
3732
3733         spin_lock_irq(&np->lock);
3734
3735         /* flag should be set within ISR */
3736         testcnt = np->intr_test;
3737         if (!testcnt)
3738                 ret = 2;
3739
3740         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3741         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3742                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3743         else
3744                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3745
3746         spin_unlock_irq(&np->lock);
3747
3748         nv_free_irq(dev);
3749
3750         np->msi_flags = save_msi_flags;
3751
3752         if (netif_running(dev)) {
3753                 writel(save_poll_interval, base + NvRegPollingInterval);
3754                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3755                 /* restore original irq */
3756                 if (nv_request_irq(dev, 0))
3757                         return 0;
3758         }
3759
3760         return ret;
3761 }
3762
3763 static int nv_loopback_test(struct net_device *dev)
3764 {
3765         struct fe_priv *np = netdev_priv(dev);
3766         u8 __iomem *base = get_hwbase(dev);
3767         struct sk_buff *tx_skb, *rx_skb;
3768         dma_addr_t test_dma_addr;
3769         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
3770         u32 flags;
3771         int len, i, pkt_len;
3772         u8 *pkt_data;
3773         u32 filter_flags = 0;
3774         u32 misc1_flags = 0;
3775         int ret = 1;
3776
3777         if (netif_running(dev)) {
3778                 nv_disable_irq(dev);
3779                 filter_flags = readl(base + NvRegPacketFilterFlags);
3780                 misc1_flags = readl(base + NvRegMisc1);
3781         } else {
3782                 nv_txrx_reset(dev);
3783         }
3784
3785         /* reinit driver view of the rx queue */
3786         set_bufsize(dev);
3787         nv_init_ring(dev);
3788
3789         /* setup hardware for loopback */
3790         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
3791         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
3792
3793         /* reinit nic view of the rx queue */
3794         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3795         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3796         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3797                 base + NvRegRingSizes);
3798         pci_push(base);
3799
3800         /* restart rx engine */
3801         nv_start_rx(dev);
3802         nv_start_tx(dev);
3803
3804         /* setup packet for tx */
3805         pkt_len = ETH_DATA_LEN;
3806         tx_skb = dev_alloc_skb(pkt_len);
3807         if (!tx_skb) {
3808                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
3809                          " of %s\n", dev->name);
3810                 ret = 0;
3811                 goto out;
3812         }
3813         pkt_data = skb_put(tx_skb, pkt_len);
3814         for (i = 0; i < pkt_len; i++)
3815                 pkt_data[i] = (u8)(i & 0xff);
3816         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
3817                                        tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
3818
3819         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3820                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
3821                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3822         } else {
3823                 np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
3824                 np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
3825                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3826         }
3827         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3828         pci_push(get_hwbase(dev));
3829
3830         msleep(500);
3831
3832         /* check for rx of the packet */
3833         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3834                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
3835                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
3836
3837         } else {
3838                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
3839                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
3840         }
3841
3842         if (flags & NV_RX_AVAIL) {
3843                 ret = 0;
3844         } else if (np->desc_ver == DESC_VER_1) {
3845                 if (flags & NV_RX_ERROR)
3846                         ret = 0;
3847         } else {
3848                 if (flags & NV_RX2_ERROR) {
3849                         ret = 0;
3850                 }
3851         }
3852
3853         if (ret) {
3854                 if (len != pkt_len) {
3855                         ret = 0;
3856                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
3857                                 dev->name, len, pkt_len);
3858                 } else {
3859                         rx_skb = np->rx_skbuff[0];
3860                         for (i = 0; i < pkt_len; i++) {
3861                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
3862                                         ret = 0;
3863                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
3864                                                 dev->name, i);
3865                                         break;
3866                                 }
3867                         }
3868                 }
3869         } else {
3870                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
3871         }
3872
3873         pci_unmap_page(np->pci_dev, test_dma_addr,
3874                        tx_skb->end-tx_skb->data,
3875                        PCI_DMA_TODEVICE);
3876         dev_kfree_skb_any(tx_skb);
3877  out:
3878         /* stop engines */
3879         nv_stop_rx(dev);
3880         nv_stop_tx(dev);
3881         nv_txrx_reset(dev);
3882         /* drain rx queue */
3883         nv_drain_rx(dev);
3884         nv_drain_tx(dev);
3885
3886         if (netif_running(dev)) {
3887                 writel(misc1_flags, base + NvRegMisc1);
3888                 writel(filter_flags, base + NvRegPacketFilterFlags);
3889                 nv_enable_irq(dev);
3890         }
3891
3892         return ret;
3893 }
3894
3895 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
3896 {
3897         struct fe_priv *np = netdev_priv(dev);
3898         u8 __iomem *base = get_hwbase(dev);
3899         int result;
3900         memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
3901
3902         if (!nv_link_test(dev)) {
3903                 test->flags |= ETH_TEST_FL_FAILED;
3904                 buffer[0] = 1;
3905         }
3906
3907         if (test->flags & ETH_TEST_FL_OFFLINE) {
3908                 if (netif_running(dev)) {
3909                         netif_stop_queue(dev);
3910                         netif_poll_disable(dev);
3911                         netif_tx_lock_bh(dev);
3912                         spin_lock_irq(&np->lock);
3913                         nv_disable_hw_interrupts(dev, np->irqmask);
3914                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3915                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3916                         } else {
3917                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3918                         }
3919                         /* stop engines */
3920                         nv_stop_rx(dev);
3921                         nv_stop_tx(dev);
3922                         nv_txrx_reset(dev);
3923                         /* drain rx queue */
3924                         nv_drain_rx(dev);
3925                         nv_drain_tx(dev);
3926                         spin_unlock_irq(&np->lock);
3927                         netif_tx_unlock_bh(dev);
3928                 }
3929
3930                 if (!nv_register_test(dev)) {
3931                         test->flags |= ETH_TEST_FL_FAILED;
3932                         buffer[1] = 1;
3933                 }
3934
3935                 result = nv_interrupt_test(dev);
3936                 if (result != 1) {
3937                         test->flags |= ETH_TEST_FL_FAILED;
3938                         buffer[2] = 1;
3939                 }
3940                 if (result == 0) {
3941                         /* bail out */
3942                         return;
3943                 }
3944
3945                 if (!nv_loopback_test(dev)) {
3946                         test->flags |= ETH_TEST_FL_FAILED;
3947                         buffer[3] = 1;
3948                 }
3949
3950                 if (netif_running(dev)) {
3951                         /* reinit driver view of the rx queue */
3952                         set_bufsize(dev);
3953                         if (nv_init_ring(dev)) {
3954                                 if (!np->in_shutdown)
3955                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3956                         }
3957                         /* reinit nic view of the rx queue */
3958                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3959                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3960                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3961                                 base + NvRegRingSizes);
3962                         pci_push(base);
3963                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3964                         pci_push(base);
3965                         /* restart rx engine */
3966                         nv_start_rx(dev);
3967                         nv_start_tx(dev);
3968                         netif_start_queue(dev);
3969                         netif_poll_enable(dev);
3970                         nv_enable_hw_interrupts(dev, np->irqmask);
3971                 }
3972         }
3973 }
3974
3975 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
3976 {
3977         switch (stringset) {
3978         case ETH_SS_STATS:
3979                 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
3980                 break;
3981         case ETH_SS_TEST:
3982                 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
3983                 break;
3984         }
3985 }
3986
3987 static const struct ethtool_ops ops = {
3988         .get_drvinfo = nv_get_drvinfo,
3989         .get_link = ethtool_op_get_link,
3990         .get_wol = nv_get_wol,
3991         .set_wol = nv_set_wol,
3992         .get_settings = nv_get_settings,
3993         .set_settings = nv_set_settings,
3994         .get_regs_len = nv_get_regs_len,
3995         .get_regs = nv_get_regs,
3996         .nway_reset = nv_nway_reset,
3997         .get_perm_addr = ethtool_op_get_perm_addr,
3998         .get_tso = ethtool_op_get_tso,
3999         .set_tso = nv_set_tso,
4000         .get_ringparam = nv_get_ringparam,
4001         .set_ringparam = nv_set_ringparam,
4002         .get_pauseparam = nv_get_pauseparam,
4003         .set_pauseparam = nv_set_pauseparam,
4004         .get_rx_csum = nv_get_rx_csum,
4005         .set_rx_csum = nv_set_rx_csum,
4006         .get_tx_csum = ethtool_op_get_tx_csum,
4007         .set_tx_csum = nv_set_tx_csum,
4008         .get_sg = ethtool_op_get_sg,
4009         .set_sg = nv_set_sg,
4010         .get_strings = nv_get_strings,
4011         .get_stats_count = nv_get_stats_count,
4012         .get_ethtool_stats = nv_get_ethtool_stats,
4013         .self_test_count = nv_self_test_count,
4014         .self_test = nv_self_test,
4015 };
4016
4017 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4018 {
4019         struct fe_priv *np = get_nvpriv(dev);
4020
4021         spin_lock_irq(&np->lock);
4022
4023         /* save vlan group */
4024         np->vlangrp = grp;
4025
4026         if (grp) {
4027                 /* enable vlan on MAC */
4028                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4029         } else {
4030                 /* disable vlan on MAC */
4031                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4032                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4033         }
4034
4035         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4036
4037         spin_unlock_irq(&np->lock);
4038 };
4039
4040 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
4041 {
4042         /* nothing to do */
4043 };
4044
4045 /* The mgmt unit and driver use a semaphore to access the phy during init */
4046 static int nv_mgmt_acquire_sema(struct net_device *dev)
4047 {
4048         u8 __iomem *base = get_hwbase(dev);
4049         int i;
4050         u32 tx_ctrl, mgmt_sema;
4051
4052         for (i = 0; i < 10; i++) {
4053                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4054                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4055                         break;
4056                 msleep(500);
4057         }
4058
4059         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4060                 return 0;
4061
4062         for (i = 0; i < 2; i++) {
4063                 tx_ctrl = readl(base + NvRegTransmitterControl);
4064                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4065                 writel(tx_ctrl, base + NvRegTransmitterControl);
4066
4067                 /* verify that semaphore was acquired */
4068                 tx_ctrl = readl(base + NvRegTransmitterControl);
4069                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4070                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4071                         return 1;
4072                 else
4073                         udelay(50);
4074         }
4075
4076         return 0;
4077 }
4078
4079 /* Indicate to mgmt unit whether driver is loaded or not */
4080 static void nv_mgmt_driver_loaded(struct net_device *dev, int loaded)
4081 {
4082         u8 __iomem *base = get_hwbase(dev);
4083         u32 tx_ctrl;
4084
4085         tx_ctrl = readl(base + NvRegTransmitterControl);
4086         if (loaded)
4087                 tx_ctrl |= NVREG_XMITCTL_HOST_LOADED;
4088         else
4089                 tx_ctrl &= ~NVREG_XMITCTL_HOST_LOADED;
4090         writel(tx_ctrl, base + NvRegTransmitterControl);
4091 }
4092
4093 static int nv_open(struct net_device *dev)
4094 {
4095         struct fe_priv *np = netdev_priv(dev);
4096         u8 __iomem *base = get_hwbase(dev);
4097         int ret = 1;
4098         int oom, i;
4099
4100         dprintk(KERN_DEBUG "nv_open: begin\n");
4101
4102         /* erase previous misconfiguration */
4103         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4104                 nv_mac_reset(dev);
4105         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4106         writel(0, base + NvRegMulticastAddrB);
4107         writel(0, base + NvRegMulticastMaskA);
4108         writel(0, base + NvRegMulticastMaskB);
4109         writel(0, base + NvRegPacketFilterFlags);
4110
4111         writel(0, base + NvRegTransmitterControl);
4112         writel(0, base + NvRegReceiverControl);
4113
4114         writel(0, base + NvRegAdapterControl);
4115
4116         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4117                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
4118
4119         /* initialize descriptor rings */
4120         set_bufsize(dev);
4121         oom = nv_init_ring(dev);
4122
4123         writel(0, base + NvRegLinkSpeed);
4124         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4125         nv_txrx_reset(dev);
4126         writel(0, base + NvRegUnknownSetupReg6);
4127
4128         np->in_shutdown = 0;
4129
4130         /* give hw rings */
4131         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4132         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4133                 base + NvRegRingSizes);
4134
4135         writel(np->linkspeed, base + NvRegLinkSpeed);
4136         if (np->desc_ver == DESC_VER_1)
4137                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4138         else
4139                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4140         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4141         writel(np->vlanctl_bits, base + NvRegVlanControl);
4142         pci_push(base);
4143         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4144         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4145                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4146                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4147
4148         writel(0, base + NvRegMIIMask);
4149         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4150         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4151
4152         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4153         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4154         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4155         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4156
4157         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4158         get_random_bytes(&i, sizeof(i));
4159         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4160         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4161         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4162         if (poll_interval == -1) {
4163                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4164                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4165                 else
4166                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4167         }
4168         else
4169                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
4170         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4171         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
4172                         base + NvRegAdapterControl);
4173         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
4174         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
4175         if (np->wolenabled)
4176                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
4177
4178         i = readl(base + NvRegPowerState);
4179         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
4180                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
4181
4182         pci_push(base);
4183         udelay(10);
4184         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
4185
4186         nv_disable_hw_interrupts(dev, np->irqmask);
4187         pci_push(base);
4188         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4189         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4190         pci_push(base);
4191
4192         if (nv_request_irq(dev, 0)) {
4193                 goto out_drain;
4194         }
4195
4196         /* ask for interrupts */
4197         nv_enable_hw_interrupts(dev, np->irqmask);
4198
4199         spin_lock_irq(&np->lock);
4200         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4201         writel(0, base + NvRegMulticastAddrB);
4202         writel(0, base + NvRegMulticastMaskA);
4203         writel(0, base + NvRegMulticastMaskB);
4204         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4205         /* One manual link speed update: Interrupts are enabled, future link
4206          * speed changes cause interrupts and are handled by nv_link_irq().
4207          */
4208         {
4209                 u32 miistat;
4210                 miistat = readl(base + NvRegMIIStatus);
4211                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4212                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4213         }
4214         /* set linkspeed to invalid value, thus force nv_update_linkspeed
4215          * to init hw */
4216         np->linkspeed = 0;
4217         ret = nv_update_linkspeed(dev);
4218         nv_start_rx(dev);
4219         nv_start_tx(dev);
4220         netif_start_queue(dev);
4221         netif_poll_enable(dev);
4222
4223         if (ret) {
4224                 netif_carrier_on(dev);
4225         } else {
4226                 printk("%s: no link during initialization.\n", dev->name);
4227                 netif_carrier_off(dev);
4228         }
4229         if (oom)
4230                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4231
4232         /* start statistics timer */
4233         if (np->driver_data & DEV_HAS_STATISTICS)
4234                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4235
4236         spin_unlock_irq(&np->lock);
4237
4238         return 0;
4239 out_drain:
4240         drain_ring(dev);
4241         return ret;
4242 }
4243
4244 static int nv_close(struct net_device *dev)
4245 {
4246         struct fe_priv *np = netdev_priv(dev);
4247         u8 __iomem *base;
4248
4249         spin_lock_irq(&np->lock);
4250         np->in_shutdown = 1;
4251         spin_unlock_irq(&np->lock);
4252         netif_poll_disable(dev);
4253         synchronize_irq(dev->irq);
4254
4255         del_timer_sync(&np->oom_kick);
4256         del_timer_sync(&np->nic_poll);
4257         del_timer_sync(&np->stats_poll);
4258
4259         netif_stop_queue(dev);
4260         spin_lock_irq(&np->lock);
4261         nv_stop_tx(dev);
4262         nv_stop_rx(dev);
4263         nv_txrx_reset(dev);
4264
4265         /* disable interrupts on the nic or we will lock up */
4266         base = get_hwbase(dev);
4267         nv_disable_hw_interrupts(dev, np->irqmask);
4268         pci_push(base);
4269         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4270
4271         spin_unlock_irq(&np->lock);
4272
4273         nv_free_irq(dev);
4274
4275         drain_ring(dev);
4276
4277         if (np->wolenabled)
4278                 nv_start_rx(dev);
4279
4280         /* FIXME: power down nic */
4281
4282         return 0;
4283 }
4284
4285 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4286 {
4287         struct net_device *dev;
4288         struct fe_priv *np;
4289         unsigned long addr;
4290         u8 __iomem *base;
4291         int err, i;
4292         u32 powerstate, txreg;
4293         u32 phystate_orig = 0, phystate;
4294         int phyinitialized = 0;
4295
4296         dev = alloc_etherdev(sizeof(struct fe_priv));
4297         err = -ENOMEM;
4298         if (!dev)
4299                 goto out;
4300
4301         np = netdev_priv(dev);
4302         np->pci_dev = pci_dev;
4303         spin_lock_init(&np->lock);
4304         SET_MODULE_OWNER(dev);
4305         SET_NETDEV_DEV(dev, &pci_dev->dev);
4306
4307         init_timer(&np->oom_kick);
4308         np->oom_kick.data = (unsigned long) dev;
4309         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
4310         init_timer(&np->nic_poll);
4311         np->nic_poll.data = (unsigned long) dev;
4312         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
4313         init_timer(&np->stats_poll);
4314         np->stats_poll.data = (unsigned long) dev;
4315         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
4316
4317         err = pci_enable_device(pci_dev);
4318         if (err) {
4319                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4320                                 err, pci_name(pci_dev));
4321                 goto out_free;
4322         }
4323
4324         pci_set_master(pci_dev);
4325
4326         err = pci_request_regions(pci_dev, DRV_NAME);
4327         if (err < 0)
4328                 goto out_disable;
4329
4330         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
4331                 np->register_size = NV_PCI_REGSZ_VER2;
4332         else
4333                 np->register_size = NV_PCI_REGSZ_VER1;
4334
4335         err = -EINVAL;
4336         addr = 0;
4337         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4338                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4339                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4340                                 pci_resource_len(pci_dev, i),
4341                                 pci_resource_flags(pci_dev, i));
4342                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4343                                 pci_resource_len(pci_dev, i) >= np->register_size) {
4344                         addr = pci_resource_start(pci_dev, i);
4345                         break;
4346                 }
4347         }
4348         if (i == DEVICE_COUNT_RESOURCE) {
4349                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4350                                         pci_name(pci_dev));
4351                 goto out_relreg;
4352         }
4353
4354         /* copy of driver data */
4355         np->driver_data = id->driver_data;
4356
4357         /* handle different descriptor versions */
4358         if (id->driver_data & DEV_HAS_HIGH_DMA) {
4359                 /* packet format 3: supports 40-bit addressing */
4360                 np->desc_ver = DESC_VER_3;
4361                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4362                 if (dma_64bit) {
4363                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4364                                 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4365                                        pci_name(pci_dev));
4366                         } else {
4367                                 dev->features |= NETIF_F_HIGHDMA;
4368                                 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4369                         }
4370                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4371                                 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4372                                        pci_name(pci_dev));
4373                         }
4374                 }
4375         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4376                 /* packet format 2: supports jumbo frames */
4377                 np->desc_ver = DESC_VER_2;
4378                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4379         } else {
4380                 /* original packet format */
4381                 np->desc_ver = DESC_VER_1;
4382                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4383         }
4384
4385         np->pkt_limit = NV_PKTLIMIT_1;
4386         if (id->driver_data & DEV_HAS_LARGEDESC)
4387                 np->pkt_limit = NV_PKTLIMIT_2;
4388
4389         if (id->driver_data & DEV_HAS_CHECKSUM) {
4390                 np->rx_csum = 1;
4391                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4392                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4393 #ifdef NETIF_F_TSO
4394                 dev->features |= NETIF_F_TSO;
4395 #endif
4396         }
4397
4398         np->vlanctl_bits = 0;
4399         if (id->driver_data & DEV_HAS_VLAN) {
4400                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4401                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4402                 dev->vlan_rx_register = nv_vlan_rx_register;
4403                 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4404         }
4405
4406         np->msi_flags = 0;
4407         if ((id->driver_data & DEV_HAS_MSI) && msi) {
4408                 np->msi_flags |= NV_MSI_CAPABLE;
4409         }
4410         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4411                 np->msi_flags |= NV_MSI_X_CAPABLE;
4412         }
4413
4414         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4415         if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4416                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4417         }
4418
4419
4420         err = -ENOMEM;
4421         np->base = ioremap(addr, np->register_size);
4422         if (!np->base)
4423                 goto out_relreg;
4424         dev->base_addr = (unsigned long)np->base;
4425
4426         dev->irq = pci_dev->irq;
4427
4428         np->rx_ring_size = RX_RING_DEFAULT;
4429         np->tx_ring_size = TX_RING_DEFAULT;
4430         np->tx_limit_stop = np->tx_ring_size - TX_LIMIT_DIFFERENCE;
4431         np->tx_limit_start = np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1;
4432
4433         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4434                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4435                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4436                                         &np->ring_addr);
4437                 if (!np->rx_ring.orig)
4438                         goto out_unmap;
4439                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4440         } else {
4441                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
4442                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
4443                                         &np->ring_addr);
4444                 if (!np->rx_ring.ex)
4445                         goto out_unmap;
4446                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4447         }
4448         np->rx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->rx_ring_size, GFP_KERNEL);
4449         np->rx_dma = kmalloc(sizeof(dma_addr_t) * np->rx_ring_size, GFP_KERNEL);
4450         np->tx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->tx_ring_size, GFP_KERNEL);
4451         np->tx_dma = kmalloc(sizeof(dma_addr_t) * np->tx_ring_size, GFP_KERNEL);
4452         np->tx_dma_len = kmalloc(sizeof(unsigned int) * np->tx_ring_size, GFP_KERNEL);
4453         if (!np->rx_skbuff || !np->rx_dma || !np->tx_skbuff || !np->tx_dma || !np->tx_dma_len)
4454                 goto out_freering;
4455         memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
4456         memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
4457         memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
4458         memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
4459         memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
4460
4461         dev->open = nv_open;
4462         dev->stop = nv_close;
4463         dev->hard_start_xmit = nv_start_xmit;
4464         dev->get_stats = nv_get_stats;
4465         dev->change_mtu = nv_change_mtu;
4466         dev->set_mac_address = nv_set_mac_address;
4467         dev->set_multicast_list = nv_set_multicast;
4468 #ifdef CONFIG_NET_POLL_CONTROLLER
4469         dev->poll_controller = nv_poll_controller;
4470 #endif
4471         dev->weight = 64;
4472 #ifdef CONFIG_FORCEDETH_NAPI
4473         dev->poll = nv_napi_poll;
4474 #endif
4475         SET_ETHTOOL_OPS(dev, &ops);
4476         dev->tx_timeout = nv_tx_timeout;
4477         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
4478
4479         pci_set_drvdata(pci_dev, dev);
4480
4481         /* read the mac address */
4482         base = get_hwbase(dev);
4483         np->orig_mac[0] = readl(base + NvRegMacAddrA);
4484         np->orig_mac[1] = readl(base + NvRegMacAddrB);
4485
4486         /* check the workaround bit for correct mac address order */
4487         txreg = readl(base + NvRegTransmitPoll);
4488         if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
4489                 /* mac address is already in correct order */
4490                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
4491                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
4492                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
4493                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
4494                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
4495                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
4496         } else {
4497                 /* need to reverse mac address to correct order */
4498                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
4499                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
4500                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
4501                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
4502                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
4503                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
4504                 /* set permanent address to be correct aswell */
4505                 np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
4506                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
4507                 np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
4508                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4509         }
4510         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4511
4512         if (!is_valid_ether_addr(dev->perm_addr)) {
4513                 /*
4514                  * Bad mac address. At least one bios sets the mac address
4515                  * to 01:23:45:67:89:ab
4516                  */
4517                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
4518                         pci_name(pci_dev),
4519                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4520                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4521                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
4522                 dev->dev_addr[0] = 0x00;
4523                 dev->dev_addr[1] = 0x00;
4524                 dev->dev_addr[2] = 0x6c;
4525                 get_random_bytes(&dev->dev_addr[3], 3);
4526         }
4527
4528         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
4529                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4530                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4531
4532         /* set mac address */
4533         nv_copy_mac_to_hw(dev);
4534
4535         /* disable WOL */
4536         writel(0, base + NvRegWakeUpFlags);
4537         np->wolenabled = 0;
4538
4539         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
4540                 u8 revision_id;
4541                 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
4542
4543                 /* take phy and nic out of low power mode */
4544                 powerstate = readl(base + NvRegPowerState2);
4545                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
4546                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
4547                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
4548                     revision_id >= 0xA3)
4549                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
4550                 writel(powerstate, base + NvRegPowerState2);
4551         }
4552
4553         if (np->desc_ver == DESC_VER_1) {
4554                 np->tx_flags = NV_TX_VALID;
4555         } else {
4556                 np->tx_flags = NV_TX2_VALID;
4557         }
4558         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
4559                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
4560                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4561                         np->msi_flags |= 0x0003;
4562         } else {
4563                 np->irqmask = NVREG_IRQMASK_CPU;
4564                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4565                         np->msi_flags |= 0x0001;
4566         }
4567
4568         if (id->driver_data & DEV_NEED_TIMERIRQ)
4569                 np->irqmask |= NVREG_IRQ_TIMER;
4570         if (id->driver_data & DEV_NEED_LINKTIMER) {
4571                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
4572                 np->need_linktimer = 1;
4573                 np->link_timeout = jiffies + LINK_TIMEOUT;
4574         } else {
4575                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
4576                 np->need_linktimer = 0;
4577         }
4578
4579         /* clear phy state and temporarily halt phy interrupts */
4580         writel(0, base + NvRegMIIMask);
4581         phystate = readl(base + NvRegAdapterControl);
4582         if (phystate & NVREG_ADAPTCTL_RUNNING) {
4583                 phystate_orig = 1;
4584                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
4585                 writel(phystate, base + NvRegAdapterControl);
4586         }
4587         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4588
4589         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
4590                 writel(0x1, base + 0x204); pci_push(base);
4591                 msleep(500);
4592                 /* management unit running on the mac? */
4593                 np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
4594                 if (np->mac_in_use) {
4595                         u32 mgmt_sync;
4596                         /* management unit setup the phy already? */
4597                         mgmt_sync = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK;
4598                         if (mgmt_sync == NVREG_XMITCTL_SYNC_NOT_READY) {
4599                                 if (!nv_mgmt_acquire_sema(dev)) {
4600                                         for (i = 0; i < 5000; i++) {
4601                                                 msleep(1);
4602                                                 mgmt_sync = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK;
4603                                                 if (mgmt_sync == NVREG_XMITCTL_SYNC_NOT_READY)
4604                                                         continue;
4605                                                 if (mgmt_sync == NVREG_XMITCTL_SYNC_PHY_INIT)
4606                                                         phyinitialized = 1;
4607                                                 break;
4608                                         }
4609                                 } else {
4610                                         /* we need to init the phy */
4611                                 }
4612                         } else if (mgmt_sync == NVREG_XMITCTL_SYNC_PHY_INIT) {
4613                                 /* phy is inited by SMU */
4614                                 phyinitialized = 1;
4615                         } else {
4616                                 /* we need to init the phy */
4617                         }
4618                 }
4619         }
4620
4621         /* find a suitable phy */
4622         for (i = 1; i <= 32; i++) {
4623                 int id1, id2;
4624                 int phyaddr = i & 0x1F;
4625
4626                 spin_lock_irq(&np->lock);
4627                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
4628                 spin_unlock_irq(&np->lock);
4629                 if (id1 < 0 || id1 == 0xffff)
4630                         continue;
4631                 spin_lock_irq(&np->lock);
4632                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
4633                 spin_unlock_irq(&np->lock);
4634                 if (id2 < 0 || id2 == 0xffff)
4635                         continue;
4636
4637                 np->phy_model = id2 & PHYID2_MODEL_MASK;
4638                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
4639                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
4640                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
4641                         pci_name(pci_dev), id1, id2, phyaddr);
4642                 np->phyaddr = phyaddr;
4643                 np->phy_oui = id1 | id2;
4644                 break;
4645         }
4646         if (i == 33) {
4647                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
4648                        pci_name(pci_dev));
4649                 goto out_error;
4650         }
4651
4652         if (!phyinitialized) {
4653                 /* reset it */
4654                 phy_init(dev);
4655         }
4656
4657         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
4658                 nv_mgmt_driver_loaded(dev, 1);
4659         }
4660
4661         /* set default link speed settings */
4662         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
4663         np->duplex = 0;
4664         np->autoneg = 1;
4665
4666         err = register_netdev(dev);
4667         if (err) {
4668                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
4669                 goto out_error;
4670         }
4671         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
4672                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
4673                         pci_name(pci_dev));
4674
4675         return 0;
4676
4677 out_error:
4678         if (phystate_orig)
4679                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
4680         if (np->mac_in_use)
4681                 nv_mgmt_driver_loaded(dev, 0);
4682         pci_set_drvdata(pci_dev, NULL);
4683 out_freering:
4684         free_rings(dev);
4685 out_unmap:
4686         iounmap(get_hwbase(dev));
4687 out_relreg:
4688         pci_release_regions(pci_dev);
4689 out_disable:
4690         pci_disable_device(pci_dev);
4691 out_free:
4692         free_netdev(dev);
4693 out:
4694         return err;
4695 }
4696
4697 static void __devexit nv_remove(struct pci_dev *pci_dev)
4698 {
4699         struct net_device *dev = pci_get_drvdata(pci_dev);
4700         struct fe_priv *np = netdev_priv(dev);
4701         u8 __iomem *base = get_hwbase(dev);
4702
4703         unregister_netdev(dev);
4704
4705         /* special op: write back the misordered MAC address - otherwise
4706          * the next nv_probe would see a wrong address.
4707          */
4708         writel(np->orig_mac[0], base + NvRegMacAddrA);
4709         writel(np->orig_mac[1], base + NvRegMacAddrB);
4710
4711         if (np->mac_in_use)
4712                 nv_mgmt_driver_loaded(dev, 0);
4713
4714         /* free all structures */
4715         free_rings(dev);
4716         iounmap(get_hwbase(dev));
4717         pci_release_regions(pci_dev);
4718         pci_disable_device(pci_dev);
4719         free_netdev(dev);
4720         pci_set_drvdata(pci_dev, NULL);
4721 }
4722
4723 #ifdef CONFIG_PM
4724 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
4725 {
4726         struct net_device *dev = pci_get_drvdata(pdev);
4727         struct fe_priv *np = netdev_priv(dev);
4728
4729         if (!netif_running(dev))
4730                 goto out;
4731
4732         netif_device_detach(dev);
4733
4734         // Gross.
4735         nv_close(dev);
4736
4737         pci_save_state(pdev);
4738         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
4739         pci_set_power_state(pdev, pci_choose_state(pdev, state));
4740 out:
4741         return 0;
4742 }
4743
4744 static int nv_resume(struct pci_dev *pdev)
4745 {
4746         struct net_device *dev = pci_get_drvdata(pdev);
4747         int rc = 0;
4748
4749         if (!netif_running(dev))
4750                 goto out;
4751
4752         netif_device_attach(dev);
4753
4754         pci_set_power_state(pdev, PCI_D0);
4755         pci_restore_state(pdev);
4756         pci_enable_wake(pdev, PCI_D0, 0);
4757
4758         rc = nv_open(dev);
4759 out:
4760         return rc;
4761 }
4762 #else
4763 #define nv_suspend NULL
4764 #define nv_resume NULL
4765 #endif /* CONFIG_PM */
4766
4767 static struct pci_device_id pci_tbl[] = {
4768         {       /* nForce Ethernet Controller */
4769                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
4770                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4771         },
4772         {       /* nForce2 Ethernet Controller */
4773                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
4774                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4775         },
4776         {       /* nForce3 Ethernet Controller */
4777                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
4778                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4779         },
4780         {       /* nForce3 Ethernet Controller */
4781                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
4782                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4783         },
4784         {       /* nForce3 Ethernet Controller */
4785                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
4786                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4787         },
4788         {       /* nForce3 Ethernet Controller */
4789                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
4790                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4791         },
4792         {       /* nForce3 Ethernet Controller */
4793                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
4794                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4795         },
4796         {       /* CK804 Ethernet Controller */
4797                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
4798                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4799         },
4800         {       /* CK804 Ethernet Controller */
4801                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
4802                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4803         },
4804         {       /* MCP04 Ethernet Controller */
4805                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
4806                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4807         },
4808         {       /* MCP04 Ethernet Controller */
4809                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
4810                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4811         },
4812         {       /* MCP51 Ethernet Controller */
4813                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
4814                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4815         },
4816         {       /* MCP51 Ethernet Controller */
4817                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
4818                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4819         },
4820         {       /* MCP55 Ethernet Controller */
4821                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
4822                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4823         },
4824         {       /* MCP55 Ethernet Controller */
4825                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
4826                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4827         },
4828         {       /* MCP61 Ethernet Controller */
4829                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
4830                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4831         },
4832         {       /* MCP61 Ethernet Controller */
4833                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
4834                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4835         },
4836         {       /* MCP61 Ethernet Controller */
4837                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
4838                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4839         },
4840         {       /* MCP61 Ethernet Controller */
4841                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
4842                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4843         },
4844         {       /* MCP65 Ethernet Controller */
4845                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
4846                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4847         },
4848         {       /* MCP65 Ethernet Controller */
4849                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
4850                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4851         },
4852         {       /* MCP65 Ethernet Controller */
4853                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
4854                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4855         },
4856         {       /* MCP65 Ethernet Controller */
4857                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
4858                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4859         },
4860         {0,},
4861 };
4862
4863 static struct pci_driver driver = {
4864         .name = "forcedeth",
4865         .id_table = pci_tbl,
4866         .probe = nv_probe,
4867         .remove = __devexit_p(nv_remove),
4868         .suspend = nv_suspend,
4869         .resume = nv_resume,
4870 };
4871
4872 static int __init init_nic(void)
4873 {
4874         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
4875         return pci_register_driver(&driver);
4876 }
4877
4878 static void __exit exit_nic(void)
4879 {
4880         pci_unregister_driver(&driver);
4881 }
4882
4883 module_param(max_interrupt_work, int, 0);
4884 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
4885 module_param(optimization_mode, int, 0);
4886 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
4887 module_param(poll_interval, int, 0);
4888 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
4889 module_param(msi, int, 0);
4890 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
4891 module_param(msix, int, 0);
4892 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
4893 module_param(dma_64bit, int, 0);
4894 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
4895
4896 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
4897 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
4898 MODULE_LICENSE("GPL");
4899
4900 MODULE_DEVICE_TABLE(pci, pci_tbl);
4901
4902 module_init(init_nic);
4903 module_exit(exit_nic);