Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/rusty/linux...
[linux-2.6] / drivers / net / wireless / rt2x00 / rt2400pci.c
1 /*
2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt2400pci
23         Abstract: rt2400pci device specific routines.
24         Supported chipsets: RT2460.
25  */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00pci.h"
37 #include "rt2400pci.h"
38
39 /*
40  * Register access.
41  * All access to the CSR registers will go through the methods
42  * rt2x00pci_register_read and rt2x00pci_register_write.
43  * BBP and RF register require indirect register access,
44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
45  * These indirect registers work with busy bits,
46  * and we will try maximal REGISTER_BUSY_COUNT times to access
47  * the register while taking a REGISTER_BUSY_DELAY us delay
48  * between each attampt. When the busy bit is still set at that time,
49  * the access attempt is considered to have failed,
50  * and we will print an error.
51  */
52 #define WAIT_FOR_BBP(__dev, __reg) \
53         rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
54 #define WAIT_FOR_RF(__dev, __reg) \
55         rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
56
57 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
58                                 const unsigned int word, const u8 value)
59 {
60         u32 reg;
61
62         mutex_lock(&rt2x00dev->csr_mutex);
63
64         /*
65          * Wait until the BBP becomes available, afterwards we
66          * can safely write the new data into the register.
67          */
68         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
69                 reg = 0;
70                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
71                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
72                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
73                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
74
75                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
76         }
77
78         mutex_unlock(&rt2x00dev->csr_mutex);
79 }
80
81 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
82                                const unsigned int word, u8 *value)
83 {
84         u32 reg;
85
86         mutex_lock(&rt2x00dev->csr_mutex);
87
88         /*
89          * Wait until the BBP becomes available, afterwards we
90          * can safely write the read request into the register.
91          * After the data has been written, we wait until hardware
92          * returns the correct value, if at any time the register
93          * doesn't become available in time, reg will be 0xffffffff
94          * which means we return 0xff to the caller.
95          */
96         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97                 reg = 0;
98                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
99                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
100                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
101
102                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
103
104                 WAIT_FOR_BBP(rt2x00dev, &reg);
105         }
106
107         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
108
109         mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
113                                const unsigned int word, const u32 value)
114 {
115         u32 reg;
116
117         if (!word)
118                 return;
119
120         mutex_lock(&rt2x00dev->csr_mutex);
121
122         /*
123          * Wait until the RF becomes available, afterwards we
124          * can safely write the new data into the register.
125          */
126         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
127                 reg = 0;
128                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
129                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
130                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
131                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
132
133                 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
134                 rt2x00_rf_write(rt2x00dev, word, value);
135         }
136
137         mutex_unlock(&rt2x00dev->csr_mutex);
138 }
139
140 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
141 {
142         struct rt2x00_dev *rt2x00dev = eeprom->data;
143         u32 reg;
144
145         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
146
147         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
148         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
149         eeprom->reg_data_clock =
150             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
151         eeprom->reg_chip_select =
152             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
153 }
154
155 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
156 {
157         struct rt2x00_dev *rt2x00dev = eeprom->data;
158         u32 reg = 0;
159
160         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
161         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
162         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
163                            !!eeprom->reg_data_clock);
164         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
165                            !!eeprom->reg_chip_select);
166
167         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
168 }
169
170 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
171 static const struct rt2x00debug rt2400pci_rt2x00debug = {
172         .owner  = THIS_MODULE,
173         .csr    = {
174                 .read           = rt2x00pci_register_read,
175                 .write          = rt2x00pci_register_write,
176                 .flags          = RT2X00DEBUGFS_OFFSET,
177                 .word_base      = CSR_REG_BASE,
178                 .word_size      = sizeof(u32),
179                 .word_count     = CSR_REG_SIZE / sizeof(u32),
180         },
181         .eeprom = {
182                 .read           = rt2x00_eeprom_read,
183                 .write          = rt2x00_eeprom_write,
184                 .word_base      = EEPROM_BASE,
185                 .word_size      = sizeof(u16),
186                 .word_count     = EEPROM_SIZE / sizeof(u16),
187         },
188         .bbp    = {
189                 .read           = rt2400pci_bbp_read,
190                 .write          = rt2400pci_bbp_write,
191                 .word_base      = BBP_BASE,
192                 .word_size      = sizeof(u8),
193                 .word_count     = BBP_SIZE / sizeof(u8),
194         },
195         .rf     = {
196                 .read           = rt2x00_rf_read,
197                 .write          = rt2400pci_rf_write,
198                 .word_base      = RF_BASE,
199                 .word_size      = sizeof(u32),
200                 .word_count     = RF_SIZE / sizeof(u32),
201         },
202 };
203 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
204
205 #ifdef CONFIG_RT2X00_LIB_RFKILL
206 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
207 {
208         u32 reg;
209
210         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
211         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
212 }
213 #else
214 #define rt2400pci_rfkill_poll   NULL
215 #endif /* CONFIG_RT2X00_LIB_RFKILL */
216
217 #ifdef CONFIG_RT2X00_LIB_LEDS
218 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
219                                      enum led_brightness brightness)
220 {
221         struct rt2x00_led *led =
222             container_of(led_cdev, struct rt2x00_led, led_dev);
223         unsigned int enabled = brightness != LED_OFF;
224         u32 reg;
225
226         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
227
228         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
229                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
230         else if (led->type == LED_TYPE_ACTIVITY)
231                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
232
233         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
234 }
235
236 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
237                                unsigned long *delay_on,
238                                unsigned long *delay_off)
239 {
240         struct rt2x00_led *led =
241             container_of(led_cdev, struct rt2x00_led, led_dev);
242         u32 reg;
243
244         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
245         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
246         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
247         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
248
249         return 0;
250 }
251
252 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
253                                struct rt2x00_led *led,
254                                enum led_type type)
255 {
256         led->rt2x00dev = rt2x00dev;
257         led->type = type;
258         led->led_dev.brightness_set = rt2400pci_brightness_set;
259         led->led_dev.blink_set = rt2400pci_blink_set;
260         led->flags = LED_INITIALIZED;
261 }
262 #endif /* CONFIG_RT2X00_LIB_LEDS */
263
264 /*
265  * Configuration handlers.
266  */
267 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
268                                     const unsigned int filter_flags)
269 {
270         u32 reg;
271
272         /*
273          * Start configuration steps.
274          * Note that the version error will always be dropped
275          * since there is no filter for it at this time.
276          */
277         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
278         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
279                            !(filter_flags & FIF_FCSFAIL));
280         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
281                            !(filter_flags & FIF_PLCPFAIL));
282         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
283                            !(filter_flags & FIF_CONTROL));
284         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
285                            !(filter_flags & FIF_PROMISC_IN_BSS));
286         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
287                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
288                            !rt2x00dev->intf_ap_count);
289         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
290         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
291 }
292
293 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
294                                   struct rt2x00_intf *intf,
295                                   struct rt2x00intf_conf *conf,
296                                   const unsigned int flags)
297 {
298         unsigned int bcn_preload;
299         u32 reg;
300
301         if (flags & CONFIG_UPDATE_TYPE) {
302                 /*
303                  * Enable beacon config
304                  */
305                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
306                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
307                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
308                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
309
310                 /*
311                  * Enable synchronisation.
312                  */
313                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
314                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
315                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
316                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
317                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
318         }
319
320         if (flags & CONFIG_UPDATE_MAC)
321                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
322                                               conf->mac, sizeof(conf->mac));
323
324         if (flags & CONFIG_UPDATE_BSSID)
325                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
326                                               conf->bssid, sizeof(conf->bssid));
327 }
328
329 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
330                                  struct rt2x00lib_erp *erp)
331 {
332         int preamble_mask;
333         u32 reg;
334
335         /*
336          * When short preamble is enabled, we should set bit 0x08
337          */
338         preamble_mask = erp->short_preamble << 3;
339
340         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
341         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
342                            erp->ack_timeout);
343         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
344                            erp->ack_consume_time);
345         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
346
347         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
348         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
349         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
350         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
351         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
352
353         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
354         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
355         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
356         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
357         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
358
359         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
360         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
361         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
362         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
363         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
364
365         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
366         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
367         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
368         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
369         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
370
371         rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
372
373         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
374         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
375         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
376
377         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
378         rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
379         rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
380         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
381
382         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
383         rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
384         rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
385         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
386 }
387
388 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
389                                  struct antenna_setup *ant)
390 {
391         u8 r1;
392         u8 r4;
393
394         /*
395          * We should never come here because rt2x00lib is supposed
396          * to catch this and send us the correct antenna explicitely.
397          */
398         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
399                ant->tx == ANTENNA_SW_DIVERSITY);
400
401         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
402         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
403
404         /*
405          * Configure the TX antenna.
406          */
407         switch (ant->tx) {
408         case ANTENNA_HW_DIVERSITY:
409                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
410                 break;
411         case ANTENNA_A:
412                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
413                 break;
414         case ANTENNA_B:
415         default:
416                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
417                 break;
418         }
419
420         /*
421          * Configure the RX antenna.
422          */
423         switch (ant->rx) {
424         case ANTENNA_HW_DIVERSITY:
425                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
426                 break;
427         case ANTENNA_A:
428                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
429                 break;
430         case ANTENNA_B:
431         default:
432                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
433                 break;
434         }
435
436         rt2400pci_bbp_write(rt2x00dev, 4, r4);
437         rt2400pci_bbp_write(rt2x00dev, 1, r1);
438 }
439
440 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
441                                      struct rf_channel *rf)
442 {
443         /*
444          * Switch on tuning bits.
445          */
446         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
447         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
448
449         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
450         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
451         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
452
453         /*
454          * RF2420 chipset don't need any additional actions.
455          */
456         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
457                 return;
458
459         /*
460          * For the RT2421 chipsets we need to write an invalid
461          * reference clock rate to activate auto_tune.
462          * After that we set the value back to the correct channel.
463          */
464         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
465         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
466         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
467
468         msleep(1);
469
470         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
471         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
472         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
473
474         msleep(1);
475
476         /*
477          * Switch off tuning bits.
478          */
479         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
480         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
481
482         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
483         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
484
485         /*
486          * Clear false CRC during channel switch.
487          */
488         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
489 }
490
491 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
492 {
493         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
494 }
495
496 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
497                                          struct rt2x00lib_conf *libconf)
498 {
499         u32 reg;
500
501         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
502         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
503                            libconf->conf->long_frame_max_tx_count);
504         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
505                            libconf->conf->short_frame_max_tx_count);
506         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
507 }
508
509 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
510                                       struct rt2x00lib_conf *libconf)
511 {
512         u32 reg;
513
514         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
515         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
516         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
517         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
518
519         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
520         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
521                            libconf->conf->beacon_int * 16);
522         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
523                            libconf->conf->beacon_int * 16);
524         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
525 }
526
527 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
528                              struct rt2x00lib_conf *libconf,
529                              const unsigned int flags)
530 {
531         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
532                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
533         if (flags & IEEE80211_CONF_CHANGE_POWER)
534                 rt2400pci_config_txpower(rt2x00dev,
535                                          libconf->conf->power_level);
536         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
537                 rt2400pci_config_retry_limit(rt2x00dev, libconf);
538         if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
539                 rt2400pci_config_duration(rt2x00dev, libconf);
540 }
541
542 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
543                                 const int cw_min, const int cw_max)
544 {
545         u32 reg;
546
547         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
548         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
549         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
550         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
551 }
552
553 /*
554  * Link tuning
555  */
556 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
557                                  struct link_qual *qual)
558 {
559         u32 reg;
560         u8 bbp;
561
562         /*
563          * Update FCS error count from register.
564          */
565         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
566         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
567
568         /*
569          * Update False CCA count from register.
570          */
571         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
572         qual->false_cca = bbp;
573 }
574
575 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
576 {
577         rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
578         rt2x00dev->link.vgc_level = 0x08;
579 }
580
581 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
582 {
583         u8 reg;
584
585         /*
586          * The link tuner should not run longer then 60 seconds,
587          * and should run once every 2 seconds.
588          */
589         if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
590                 return;
591
592         /*
593          * Base r13 link tuning on the false cca count.
594          */
595         rt2400pci_bbp_read(rt2x00dev, 13, &reg);
596
597         if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
598                 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
599                 rt2x00dev->link.vgc_level = reg;
600         } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
601                 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
602                 rt2x00dev->link.vgc_level = reg;
603         }
604 }
605
606 /*
607  * Initialization functions.
608  */
609 static bool rt2400pci_get_entry_state(struct queue_entry *entry)
610 {
611         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
612         u32 word;
613
614         if (entry->queue->qid == QID_RX) {
615                 rt2x00_desc_read(entry_priv->desc, 0, &word);
616
617                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
618         } else {
619                 rt2x00_desc_read(entry_priv->desc, 0, &word);
620
621                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
622                         rt2x00_get_field32(word, TXD_W0_VALID));
623         }
624 }
625
626 static void rt2400pci_clear_entry(struct queue_entry *entry)
627 {
628         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
629         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
630         u32 word;
631
632         if (entry->queue->qid == QID_RX) {
633                 rt2x00_desc_read(entry_priv->desc, 2, &word);
634                 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
635                 rt2x00_desc_write(entry_priv->desc, 2, word);
636
637                 rt2x00_desc_read(entry_priv->desc, 1, &word);
638                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
639                 rt2x00_desc_write(entry_priv->desc, 1, word);
640
641                 rt2x00_desc_read(entry_priv->desc, 0, &word);
642                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
643                 rt2x00_desc_write(entry_priv->desc, 0, word);
644         } else {
645                 rt2x00_desc_read(entry_priv->desc, 0, &word);
646                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
647                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
648                 rt2x00_desc_write(entry_priv->desc, 0, word);
649         }
650 }
651
652 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
653 {
654         struct queue_entry_priv_pci *entry_priv;
655         u32 reg;
656
657         /*
658          * Initialize registers.
659          */
660         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
661         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
662         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
663         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
664         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
665         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
666
667         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
668         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
669         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
670                            entry_priv->desc_dma);
671         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
672
673         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
674         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
675         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
676                            entry_priv->desc_dma);
677         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
678
679         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
680         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
681         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
682                            entry_priv->desc_dma);
683         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
684
685         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
686         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
687         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
688                            entry_priv->desc_dma);
689         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
690
691         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
692         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
693         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
694         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
695
696         entry_priv = rt2x00dev->rx->entries[0].priv_data;
697         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
698         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
699                            entry_priv->desc_dma);
700         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
701
702         return 0;
703 }
704
705 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
706 {
707         u32 reg;
708
709         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
710         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
711         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
712         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
713
714         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
715         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
716         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
717         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
718         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
719
720         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
721         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
722                            (rt2x00dev->rx->data_size / 128));
723         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
724
725         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
726         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
727         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
728         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
729         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
730         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
731         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
732         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
733         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
734         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
735
736         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
737
738         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
739         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
740         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
741         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
742         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
743         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
744
745         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
746         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
747         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
748         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
749         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
750         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
751         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
752         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
753
754         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
755
756         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
757                 return -EBUSY;
758
759         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
760         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
761
762         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
763         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
764         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
765
766         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
767         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
768         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
769         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
770         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
771         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
772
773         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
774         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
775         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
776         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
777         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
778
779         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
780         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
781         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
782         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
783
784         /*
785          * We must clear the FCS and FIFO error count.
786          * These registers are cleared on read,
787          * so we may pass a useless variable to store the value.
788          */
789         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
790         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
791
792         return 0;
793 }
794
795 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
796 {
797         unsigned int i;
798         u8 value;
799
800         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
801                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
802                 if ((value != 0xff) && (value != 0x00))
803                         return 0;
804                 udelay(REGISTER_BUSY_DELAY);
805         }
806
807         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
808         return -EACCES;
809 }
810
811 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
812 {
813         unsigned int i;
814         u16 eeprom;
815         u8 reg_id;
816         u8 value;
817
818         if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
819                 return -EACCES;
820
821         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
822         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
823         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
824         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
825         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
826         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
827         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
828         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
829         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
830         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
831         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
832         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
833         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
834         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
835
836         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
837                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
838
839                 if (eeprom != 0xffff && eeprom != 0x0000) {
840                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
841                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
842                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
843                 }
844         }
845
846         return 0;
847 }
848
849 /*
850  * Device state switch handlers.
851  */
852 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
853                                 enum dev_state state)
854 {
855         u32 reg;
856
857         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
858         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
859                            (state == STATE_RADIO_RX_OFF) ||
860                            (state == STATE_RADIO_RX_OFF_LINK));
861         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
862 }
863
864 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
865                                  enum dev_state state)
866 {
867         int mask = (state == STATE_RADIO_IRQ_OFF);
868         u32 reg;
869
870         /*
871          * When interrupts are being enabled, the interrupt registers
872          * should clear the register to assure a clean state.
873          */
874         if (state == STATE_RADIO_IRQ_ON) {
875                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
876                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
877         }
878
879         /*
880          * Only toggle the interrupts bits we are going to use.
881          * Non-checked interrupt bits are disabled by default.
882          */
883         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
884         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
885         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
886         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
887         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
888         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
889         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
890 }
891
892 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
893 {
894         /*
895          * Initialize all registers.
896          */
897         if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
898                      rt2400pci_init_registers(rt2x00dev) ||
899                      rt2400pci_init_bbp(rt2x00dev)))
900                 return -EIO;
901
902         return 0;
903 }
904
905 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
906 {
907         u32 reg;
908
909         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
910
911         /*
912          * Disable synchronisation.
913          */
914         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
915
916         /*
917          * Cancel RX and TX.
918          */
919         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
920         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
921         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
922 }
923
924 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
925                                enum dev_state state)
926 {
927         u32 reg;
928         unsigned int i;
929         char put_to_sleep;
930         char bbp_state;
931         char rf_state;
932
933         put_to_sleep = (state != STATE_AWAKE);
934
935         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
936         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
937         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
938         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
939         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
940         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
941
942         /*
943          * Device is not guaranteed to be in the requested state yet.
944          * We must wait until the register indicates that the
945          * device has entered the correct state.
946          */
947         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
948                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
949                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
950                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
951                 if (bbp_state == state && rf_state == state)
952                         return 0;
953                 msleep(10);
954         }
955
956         return -EBUSY;
957 }
958
959 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
960                                       enum dev_state state)
961 {
962         int retval = 0;
963
964         switch (state) {
965         case STATE_RADIO_ON:
966                 retval = rt2400pci_enable_radio(rt2x00dev);
967                 break;
968         case STATE_RADIO_OFF:
969                 rt2400pci_disable_radio(rt2x00dev);
970                 break;
971         case STATE_RADIO_RX_ON:
972         case STATE_RADIO_RX_ON_LINK:
973         case STATE_RADIO_RX_OFF:
974         case STATE_RADIO_RX_OFF_LINK:
975                 rt2400pci_toggle_rx(rt2x00dev, state);
976                 break;
977         case STATE_RADIO_IRQ_ON:
978         case STATE_RADIO_IRQ_OFF:
979                 rt2400pci_toggle_irq(rt2x00dev, state);
980                 break;
981         case STATE_DEEP_SLEEP:
982         case STATE_SLEEP:
983         case STATE_STANDBY:
984         case STATE_AWAKE:
985                 retval = rt2400pci_set_state(rt2x00dev, state);
986                 break;
987         default:
988                 retval = -ENOTSUPP;
989                 break;
990         }
991
992         if (unlikely(retval))
993                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
994                       state, retval);
995
996         return retval;
997 }
998
999 /*
1000  * TX descriptor initialization
1001  */
1002 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1003                                     struct sk_buff *skb,
1004                                     struct txentry_desc *txdesc)
1005 {
1006         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1007         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1008         __le32 *txd = skbdesc->desc;
1009         u32 word;
1010
1011         /*
1012          * Start writing the descriptor words.
1013          */
1014         rt2x00_desc_read(entry_priv->desc, 1, &word);
1015         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1016         rt2x00_desc_write(entry_priv->desc, 1, word);
1017
1018         rt2x00_desc_read(txd, 2, &word);
1019         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len);
1020         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len);
1021         rt2x00_desc_write(txd, 2, word);
1022
1023         rt2x00_desc_read(txd, 3, &word);
1024         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1025         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1026         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1027         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1028         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1029         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1030         rt2x00_desc_write(txd, 3, word);
1031
1032         rt2x00_desc_read(txd, 4, &word);
1033         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1034         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1035         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1036         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1037         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1038         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1039         rt2x00_desc_write(txd, 4, word);
1040
1041         rt2x00_desc_read(txd, 0, &word);
1042         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1043         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1044         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1045                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1046         rt2x00_set_field32(&word, TXD_W0_ACK,
1047                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1048         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1049                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1050         rt2x00_set_field32(&word, TXD_W0_RTS,
1051                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1052         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1053         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1054                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1055         rt2x00_desc_write(txd, 0, word);
1056 }
1057
1058 /*
1059  * TX data initialization
1060  */
1061 static void rt2400pci_write_beacon(struct queue_entry *entry)
1062 {
1063         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1064         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1065         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1066         u32 word;
1067         u32 reg;
1068
1069         /*
1070          * Disable beaconing while we are reloading the beacon data,
1071          * otherwise we might be sending out invalid data.
1072          */
1073         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1074         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1075         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1076         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1077         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1078
1079         /*
1080          * Replace rt2x00lib allocated descriptor with the
1081          * pointer to the _real_ hardware descriptor.
1082          * After that, map the beacon to DMA and update the
1083          * descriptor.
1084          */
1085         memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1086         skbdesc->desc = entry_priv->desc;
1087
1088         rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1089
1090         rt2x00_desc_read(entry_priv->desc, 1, &word);
1091         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1092         rt2x00_desc_write(entry_priv->desc, 1, word);
1093 }
1094
1095 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1096                                     const enum data_queue_qid queue)
1097 {
1098         u32 reg;
1099
1100         if (queue == QID_BEACON) {
1101                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1102                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1103                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1104                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1105                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1106                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1107                 }
1108                 return;
1109         }
1110
1111         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1112         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1113         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1114         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1115         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1116 }
1117
1118 /*
1119  * RX control handlers
1120  */
1121 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1122                                   struct rxdone_entry_desc *rxdesc)
1123 {
1124         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1125         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1126         u32 word0;
1127         u32 word2;
1128         u32 word3;
1129         u32 word4;
1130         u64 tsf;
1131         u32 rx_low;
1132         u32 rx_high;
1133
1134         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1135         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1136         rt2x00_desc_read(entry_priv->desc, 3, &word3);
1137         rt2x00_desc_read(entry_priv->desc, 4, &word4);
1138
1139         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1140                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1141         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1142                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1143
1144         /*
1145          * We only get the lower 32bits from the timestamp,
1146          * to get the full 64bits we must complement it with
1147          * the timestamp from get_tsf().
1148          * Note that when a wraparound of the lower 32bits
1149          * has occurred between the frame arrival and the get_tsf()
1150          * call, we must decrease the higher 32bits with 1 to get
1151          * to correct value.
1152          */
1153         tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1154         rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1155         rx_high = upper_32_bits(tsf);
1156
1157         if ((u32)tsf <= rx_low)
1158                 rx_high--;
1159
1160         /*
1161          * Obtain the status about this packet.
1162          * The signal is the PLCP value, and needs to be stripped
1163          * of the preamble bit (0x08).
1164          */
1165         rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1166         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1167         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1168             entry->queue->rt2x00dev->rssi_offset;
1169         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1170
1171         rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1172         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1173                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1174 }
1175
1176 /*
1177  * Interrupt functions.
1178  */
1179 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1180                              const enum data_queue_qid queue_idx)
1181 {
1182         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1183         struct queue_entry_priv_pci *entry_priv;
1184         struct queue_entry *entry;
1185         struct txdone_entry_desc txdesc;
1186         u32 word;
1187
1188         while (!rt2x00queue_empty(queue)) {
1189                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1190                 entry_priv = entry->priv_data;
1191                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1192
1193                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1194                     !rt2x00_get_field32(word, TXD_W0_VALID))
1195                         break;
1196
1197                 /*
1198                  * Obtain the status about this packet.
1199                  */
1200                 txdesc.flags = 0;
1201                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1202                 case 0: /* Success */
1203                 case 1: /* Success with retry */
1204                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1205                         break;
1206                 case 2: /* Failure, excessive retries */
1207                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1208                         /* Don't break, this is a failed frame! */
1209                 default: /* Failure */
1210                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1211                 }
1212                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1213
1214                 rt2x00lib_txdone(entry, &txdesc);
1215         }
1216 }
1217
1218 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1219 {
1220         struct rt2x00_dev *rt2x00dev = dev_instance;
1221         u32 reg;
1222
1223         /*
1224          * Get the interrupt sources & saved to local variable.
1225          * Write register value back to clear pending interrupts.
1226          */
1227         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1228         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1229
1230         if (!reg)
1231                 return IRQ_NONE;
1232
1233         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1234                 return IRQ_HANDLED;
1235
1236         /*
1237          * Handle interrupts, walk through all bits
1238          * and run the tasks, the bits are checked in order of
1239          * priority.
1240          */
1241
1242         /*
1243          * 1 - Beacon timer expired interrupt.
1244          */
1245         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1246                 rt2x00lib_beacondone(rt2x00dev);
1247
1248         /*
1249          * 2 - Rx ring done interrupt.
1250          */
1251         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1252                 rt2x00pci_rxdone(rt2x00dev);
1253
1254         /*
1255          * 3 - Atim ring transmit done interrupt.
1256          */
1257         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1258                 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1259
1260         /*
1261          * 4 - Priority ring transmit done interrupt.
1262          */
1263         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1264                 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1265
1266         /*
1267          * 5 - Tx ring transmit done interrupt.
1268          */
1269         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1270                 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1271
1272         return IRQ_HANDLED;
1273 }
1274
1275 /*
1276  * Device probe functions.
1277  */
1278 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1279 {
1280         struct eeprom_93cx6 eeprom;
1281         u32 reg;
1282         u16 word;
1283         u8 *mac;
1284
1285         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1286
1287         eeprom.data = rt2x00dev;
1288         eeprom.register_read = rt2400pci_eepromregister_read;
1289         eeprom.register_write = rt2400pci_eepromregister_write;
1290         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1291             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1292         eeprom.reg_data_in = 0;
1293         eeprom.reg_data_out = 0;
1294         eeprom.reg_data_clock = 0;
1295         eeprom.reg_chip_select = 0;
1296
1297         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1298                                EEPROM_SIZE / sizeof(u16));
1299
1300         /*
1301          * Start validation of the data that has been read.
1302          */
1303         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1304         if (!is_valid_ether_addr(mac)) {
1305                 random_ether_addr(mac);
1306                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1307         }
1308
1309         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1310         if (word == 0xffff) {
1311                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1312                 return -EINVAL;
1313         }
1314
1315         return 0;
1316 }
1317
1318 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1319 {
1320         u32 reg;
1321         u16 value;
1322         u16 eeprom;
1323
1324         /*
1325          * Read EEPROM word for configuration.
1326          */
1327         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1328
1329         /*
1330          * Identify RF chipset.
1331          */
1332         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1333         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1334         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1335
1336         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1337             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1338                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1339                 return -ENODEV;
1340         }
1341
1342         /*
1343          * Identify default antenna configuration.
1344          */
1345         rt2x00dev->default_ant.tx =
1346             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1347         rt2x00dev->default_ant.rx =
1348             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1349
1350         /*
1351          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1352          * I am not 100% sure about this, but the legacy drivers do not
1353          * indicate antenna swapping in software is required when
1354          * diversity is enabled.
1355          */
1356         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1357                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1358         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1359                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1360
1361         /*
1362          * Store led mode, for correct led behaviour.
1363          */
1364 #ifdef CONFIG_RT2X00_LIB_LEDS
1365         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1366
1367         rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1368         if (value == LED_MODE_TXRX_ACTIVITY)
1369                 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1370                                    LED_TYPE_ACTIVITY);
1371 #endif /* CONFIG_RT2X00_LIB_LEDS */
1372
1373         /*
1374          * Detect if this device has an hardware controlled radio.
1375          */
1376 #ifdef CONFIG_RT2X00_LIB_RFKILL
1377         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1378                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1379 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1380
1381         /*
1382          * Check if the BBP tuning should be enabled.
1383          */
1384         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1385                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1386
1387         return 0;
1388 }
1389
1390 /*
1391  * RF value list for RF2420 & RF2421
1392  * Supports: 2.4 GHz
1393  */
1394 static const struct rf_channel rf_vals_b[] = {
1395         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1396         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1397         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1398         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1399         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1400         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1401         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1402         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1403         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1404         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1405         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1406         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1407         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1408         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1409 };
1410
1411 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1412 {
1413         struct hw_mode_spec *spec = &rt2x00dev->spec;
1414         struct channel_info *info;
1415         char *tx_power;
1416         unsigned int i;
1417
1418         /*
1419          * Initialize all hw fields.
1420          */
1421         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1422                                IEEE80211_HW_SIGNAL_DBM;
1423         rt2x00dev->hw->extra_tx_headroom = 0;
1424
1425         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1426         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1427                                 rt2x00_eeprom_addr(rt2x00dev,
1428                                                    EEPROM_MAC_ADDR_0));
1429
1430         /*
1431          * Initialize hw_mode information.
1432          */
1433         spec->supported_bands = SUPPORT_BAND_2GHZ;
1434         spec->supported_rates = SUPPORT_RATE_CCK;
1435
1436         spec->num_channels = ARRAY_SIZE(rf_vals_b);
1437         spec->channels = rf_vals_b;
1438
1439         /*
1440          * Create channel information array
1441          */
1442         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1443         if (!info)
1444                 return -ENOMEM;
1445
1446         spec->channels_info = info;
1447
1448         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1449         for (i = 0; i < 14; i++)
1450                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1451
1452         return 0;
1453 }
1454
1455 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1456 {
1457         int retval;
1458
1459         /*
1460          * Allocate eeprom data.
1461          */
1462         retval = rt2400pci_validate_eeprom(rt2x00dev);
1463         if (retval)
1464                 return retval;
1465
1466         retval = rt2400pci_init_eeprom(rt2x00dev);
1467         if (retval)
1468                 return retval;
1469
1470         /*
1471          * Initialize hw specifications.
1472          */
1473         retval = rt2400pci_probe_hw_mode(rt2x00dev);
1474         if (retval)
1475                 return retval;
1476
1477         /*
1478          * This device requires the atim queue and DMA-mapped skbs.
1479          */
1480         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1481         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1482
1483         /*
1484          * Set the rssi offset.
1485          */
1486         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1487
1488         return 0;
1489 }
1490
1491 /*
1492  * IEEE80211 stack callback functions.
1493  */
1494 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1495                              const struct ieee80211_tx_queue_params *params)
1496 {
1497         struct rt2x00_dev *rt2x00dev = hw->priv;
1498
1499         /*
1500          * We don't support variating cw_min and cw_max variables
1501          * per queue. So by default we only configure the TX queue,
1502          * and ignore all other configurations.
1503          */
1504         if (queue != 0)
1505                 return -EINVAL;
1506
1507         if (rt2x00mac_conf_tx(hw, queue, params))
1508                 return -EINVAL;
1509
1510         /*
1511          * Write configuration to register.
1512          */
1513         rt2400pci_config_cw(rt2x00dev,
1514                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1515
1516         return 0;
1517 }
1518
1519 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1520 {
1521         struct rt2x00_dev *rt2x00dev = hw->priv;
1522         u64 tsf;
1523         u32 reg;
1524
1525         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1526         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1527         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1528         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1529
1530         return tsf;
1531 }
1532
1533 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1534 {
1535         struct rt2x00_dev *rt2x00dev = hw->priv;
1536         u32 reg;
1537
1538         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1539         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1540 }
1541
1542 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1543         .tx                     = rt2x00mac_tx,
1544         .start                  = rt2x00mac_start,
1545         .stop                   = rt2x00mac_stop,
1546         .add_interface          = rt2x00mac_add_interface,
1547         .remove_interface       = rt2x00mac_remove_interface,
1548         .config                 = rt2x00mac_config,
1549         .config_interface       = rt2x00mac_config_interface,
1550         .configure_filter       = rt2x00mac_configure_filter,
1551         .get_stats              = rt2x00mac_get_stats,
1552         .bss_info_changed       = rt2x00mac_bss_info_changed,
1553         .conf_tx                = rt2400pci_conf_tx,
1554         .get_tx_stats           = rt2x00mac_get_tx_stats,
1555         .get_tsf                = rt2400pci_get_tsf,
1556         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1557 };
1558
1559 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1560         .irq_handler            = rt2400pci_interrupt,
1561         .probe_hw               = rt2400pci_probe_hw,
1562         .initialize             = rt2x00pci_initialize,
1563         .uninitialize           = rt2x00pci_uninitialize,
1564         .get_entry_state        = rt2400pci_get_entry_state,
1565         .clear_entry            = rt2400pci_clear_entry,
1566         .set_device_state       = rt2400pci_set_device_state,
1567         .rfkill_poll            = rt2400pci_rfkill_poll,
1568         .link_stats             = rt2400pci_link_stats,
1569         .reset_tuner            = rt2400pci_reset_tuner,
1570         .link_tuner             = rt2400pci_link_tuner,
1571         .write_tx_desc          = rt2400pci_write_tx_desc,
1572         .write_tx_data          = rt2x00pci_write_tx_data,
1573         .write_beacon           = rt2400pci_write_beacon,
1574         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1575         .fill_rxdone            = rt2400pci_fill_rxdone,
1576         .config_filter          = rt2400pci_config_filter,
1577         .config_intf            = rt2400pci_config_intf,
1578         .config_erp             = rt2400pci_config_erp,
1579         .config_ant             = rt2400pci_config_ant,
1580         .config                 = rt2400pci_config,
1581 };
1582
1583 static const struct data_queue_desc rt2400pci_queue_rx = {
1584         .entry_num              = RX_ENTRIES,
1585         .data_size              = DATA_FRAME_SIZE,
1586         .desc_size              = RXD_DESC_SIZE,
1587         .priv_size              = sizeof(struct queue_entry_priv_pci),
1588 };
1589
1590 static const struct data_queue_desc rt2400pci_queue_tx = {
1591         .entry_num              = TX_ENTRIES,
1592         .data_size              = DATA_FRAME_SIZE,
1593         .desc_size              = TXD_DESC_SIZE,
1594         .priv_size              = sizeof(struct queue_entry_priv_pci),
1595 };
1596
1597 static const struct data_queue_desc rt2400pci_queue_bcn = {
1598         .entry_num              = BEACON_ENTRIES,
1599         .data_size              = MGMT_FRAME_SIZE,
1600         .desc_size              = TXD_DESC_SIZE,
1601         .priv_size              = sizeof(struct queue_entry_priv_pci),
1602 };
1603
1604 static const struct data_queue_desc rt2400pci_queue_atim = {
1605         .entry_num              = ATIM_ENTRIES,
1606         .data_size              = DATA_FRAME_SIZE,
1607         .desc_size              = TXD_DESC_SIZE,
1608         .priv_size              = sizeof(struct queue_entry_priv_pci),
1609 };
1610
1611 static const struct rt2x00_ops rt2400pci_ops = {
1612         .name           = KBUILD_MODNAME,
1613         .max_sta_intf   = 1,
1614         .max_ap_intf    = 1,
1615         .eeprom_size    = EEPROM_SIZE,
1616         .rf_size        = RF_SIZE,
1617         .tx_queues      = NUM_TX_QUEUES,
1618         .rx             = &rt2400pci_queue_rx,
1619         .tx             = &rt2400pci_queue_tx,
1620         .bcn            = &rt2400pci_queue_bcn,
1621         .atim           = &rt2400pci_queue_atim,
1622         .lib            = &rt2400pci_rt2x00_ops,
1623         .hw             = &rt2400pci_mac80211_ops,
1624 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1625         .debugfs        = &rt2400pci_rt2x00debug,
1626 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1627 };
1628
1629 /*
1630  * RT2400pci module information.
1631  */
1632 static struct pci_device_id rt2400pci_device_table[] = {
1633         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1634         { 0, }
1635 };
1636
1637 MODULE_AUTHOR(DRV_PROJECT);
1638 MODULE_VERSION(DRV_VERSION);
1639 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1640 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1641 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1642 MODULE_LICENSE("GPL");
1643
1644 static struct pci_driver rt2400pci_driver = {
1645         .name           = KBUILD_MODNAME,
1646         .id_table       = rt2400pci_device_table,
1647         .probe          = rt2x00pci_probe,
1648         .remove         = __devexit_p(rt2x00pci_remove),
1649         .suspend        = rt2x00pci_suspend,
1650         .resume         = rt2x00pci_resume,
1651 };
1652
1653 static int __init rt2400pci_init(void)
1654 {
1655         return pci_register_driver(&rt2400pci_driver);
1656 }
1657
1658 static void __exit rt2400pci_exit(void)
1659 {
1660         pci_unregister_driver(&rt2400pci_driver);
1661 }
1662
1663 module_init(rt2400pci_init);
1664 module_exit(rt2400pci_exit);