git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/iwlwifi/iwl-5000.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  23  *
  24  *****************************************************************************/
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/version.h>
  29 #include <linux/init.h>
  30 #include <linux/pci.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/delay.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <net/mac80211.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39
  40 #include "iwl-eeprom.h"
  41 #include "iwl-dev.h"
  42 #include "iwl-core.h"
  43 #include "iwl-io.h"
  44 #include "iwl-helpers.h"
  45 #include "iwl-5000-hw.h"
  46
  47 #define IWL5000_UCODE_API  "-1"
  48
  49 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
  50         IWL_TX_FIFO_AC3,
  51         IWL_TX_FIFO_AC2,
  52         IWL_TX_FIFO_AC1,
  53         IWL_TX_FIFO_AC0,
  54         IWL50_CMD_FIFO_NUM,
  55         IWL_TX_FIFO_HCCA_1,
  56         IWL_TX_FIFO_HCCA_2
  57 };
  58
  59 static int iwl5000_apm_init(struct iwl_priv *priv)
  60 {
  61         int ret = 0;
  62
  63         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  64                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  65
  66         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
  67         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  68                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  69
  70         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
  71
  72         /* set "initialization complete" bit to move adapter
  73          * D0U* --> D0A* state */
  74         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  75
  76         /* wait for clock stabilization */
  77         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
  78                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  79                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  80         if (ret < 0) {
  81                 IWL_DEBUG_INFO("Failed to init the card\n");
  82                 return ret;
  83         }
  84
  85         ret = iwl_grab_nic_access(priv);
  86         if (ret)
  87                 return ret;
  88
  89         /* enable DMA */
  90         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  91
  92         udelay(20);
  93
  94         /* disable L1-Active */
  95         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  96                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  97
  98         iwl_release_nic_access(priv);
  99
 100         return ret;
 101 }
 102
 103 static int iwl5000_apm_reset(struct iwl_priv *priv)
 104 {
 105         int ret = 0;
 106         unsigned long flags;
 107
 108         iwl4965_hw_nic_stop_master(priv);
 109
 110         spin_lock_irqsave(&priv->lock, flags);
 111
 112         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 113
 114         udelay(10);
 115
 116
 117         /* FIXME: put here L1A -L0S w/a */
 118
 119         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 120
 121         /* set "initialization complete" bit to move adapter
 122          * D0U* --> D0A* state */
 123         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 124
 125         /* wait for clock stabilization */
 126         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
 127                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 128                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 129         if (ret < 0) {
 130                 IWL_DEBUG_INFO("Failed to init the card\n");
 131                 goto out;
 132         }
 133
 134         ret = iwl_grab_nic_access(priv);
 135         if (ret)
 136                 goto out;
 137
 138         /* enable DMA */
 139         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 140
 141         udelay(20);
 142
 143         /* disable L1-Active */
 144         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 145                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 146
 147         iwl_release_nic_access(priv);
 148
 149 out:
 150         spin_unlock_irqrestore(&priv->lock, flags);
 151
 152         return ret;
 153 }
 154
 155
 156 static void iwl5000_nic_config(struct iwl_priv *priv)
 157 {
 158         unsigned long flags;
 159         u16 radio_cfg;
 160         u8 val_link;
 161
 162         spin_lock_irqsave(&priv->lock, flags);
 163
 164         pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
 165
 166         /* L1 is enabled by BIOS */
 167         if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
 168                 /* diable L0S disabled L1A enabled */
 169                 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 170         else
 171                 /* L0S enabled L1A disabled */
 172                 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 173
 174         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
 175
 176         /* write radio config values to register */
 177         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
 178                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 179                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
 180                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
 181                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
 182
 183         /* set CSR_HW_CONFIG_REG for uCode use */
 184         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 185                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
 186                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
 187
 188         spin_unlock_irqrestore(&priv->lock, flags);
 189 }
 190
 191
 192
 193 /*
 194  * EEPROM
 195  */
 196 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 197 {
 198         u16 offset = 0;
 199
 200         if ((address & INDIRECT_ADDRESS) == 0)
 201                 return address;
 202
 203         switch (address & INDIRECT_TYPE_MSK) {
 204         case INDIRECT_HOST:
 205                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
 206                 break;
 207         case INDIRECT_GENERAL:
 208                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
 209                 break;
 210         case INDIRECT_REGULATORY:
 211                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
 212                 break;
 213         case INDIRECT_CALIBRATION:
 214                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
 215                 break;
 216         case INDIRECT_PROCESS_ADJST:
 217                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
 218                 break;
 219         case INDIRECT_OTHERS:
 220                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
 221                 break;
 222         default:
 223                 IWL_ERROR("illegal indirect type: 0x%X\n",
 224                 address & INDIRECT_TYPE_MSK);
 225                 break;
 226         }
 227
 228         /* translate the offset from words to byte */
 229         return (address & ADDRESS_MSK) + (offset << 1);
 230 }
 231
 232 static int iwl5000_eeprom_check_version(struct iwl_priv *priv)
 233 {
 234         u16 eeprom_ver;
 235         struct iwl_eeprom_calib_hdr {
 236                 u8 version;
 237                 u8 pa_type;
 238                 u16 voltage;
 239         } *hdr;
 240
 241         eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
 242
 243         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 244                                                         EEPROM_5000_CALIB_ALL);
 245
 246         if (eeprom_ver < EEPROM_5000_EEPROM_VERSION ||
 247             hdr->version < EEPROM_5000_TX_POWER_VERSION)
 248                 goto err;
 249
 250         return 0;
 251 err:
 252         IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
 253                   eeprom_ver, EEPROM_5000_EEPROM_VERSION,
 254                   hdr->version, EEPROM_5000_TX_POWER_VERSION);
 255         return -EINVAL;
 256
 257 }
 258
 259 #ifdef CONFIG_IWL5000_RUN_TIME_CALIB
 260
 261 static void iwl5000_gain_computation(struct iwl_priv *priv,
 262                 u32 average_noise[NUM_RX_CHAINS],
 263                 u16 min_average_noise_antenna_i,
 264                 u32 min_average_noise)
 265 {
 266         int i;
 267         s32 delta_g;
 268         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 269
 270         /* Find Gain Code for the antennas B and C */
 271         for (i = 1; i < NUM_RX_CHAINS; i++) {
 272                 if ((data->disconn_array[i])) {
 273                         data->delta_gain_code[i] = 0;
 274                         continue;
 275                 }
 276                 delta_g = (1000 * ((s32)average_noise[0] -
 277                         (s32)average_noise[i])) / 1500;
 278                 /* bound gain by 2 bits value max, 3rd bit is sign */
 279                 data->delta_gain_code[i] =
 280                         min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
 281
 282                 if (delta_g < 0)
 283                         /* set negative sign */
 284                         data->delta_gain_code[i] |= (1 << 2);
 285         }
 286
 287         IWL_DEBUG_CALIB("Delta gains: ANT_B = %d  ANT_C = %d\n",
 288                         data->delta_gain_code[1], data->delta_gain_code[2]);
 289
 290         if (!data->radio_write) {
 291                 struct iwl5000_calibration_chain_noise_gain_cmd cmd;
 292                 memset(&cmd, 0, sizeof(cmd));
 293
 294                 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
 295                 cmd.delta_gain_1 = data->delta_gain_code[1];
 296                 cmd.delta_gain_2 = data->delta_gain_code[2];
 297                 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
 298                         sizeof(cmd), &cmd, NULL);
 299
 300                 data->radio_write = 1;
 301                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
 302         }
 303
 304         data->chain_noise_a = 0;
 305         data->chain_noise_b = 0;
 306         data->chain_noise_c = 0;
 307         data->chain_signal_a = 0;
 308         data->chain_signal_b = 0;
 309         data->chain_signal_c = 0;
 310         data->beacon_count = 0;
 311 }
 312
 313
 314 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
 315 {
 316         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 317
 318         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
 319                 struct iwl5000_calibration_chain_noise_reset_cmd cmd;
 320
 321                 memset(&cmd, 0, sizeof(cmd));
 322                 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
 323                 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 324                         sizeof(cmd), &cmd))
 325                         IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
 326                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
 327                 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
 328         }
 329 }
 330
 331 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
 332         .min_nrg_cck = 95,
 333         .max_nrg_cck = 0,
 334         .auto_corr_min_ofdm = 90,
 335         .auto_corr_min_ofdm_mrc = 170,
 336         .auto_corr_min_ofdm_x1 = 120,
 337         .auto_corr_min_ofdm_mrc_x1 = 240,
 338
 339         .auto_corr_max_ofdm = 120,
 340         .auto_corr_max_ofdm_mrc = 210,
 341         .auto_corr_max_ofdm_x1 = 155,
 342         .auto_corr_max_ofdm_mrc_x1 = 290,
 343
 344         .auto_corr_min_cck = 125,
 345         .auto_corr_max_cck = 200,
 346         .auto_corr_min_cck_mrc = 170,
 347         .auto_corr_max_cck_mrc = 400,
 348         .nrg_th_cck = 95,
 349         .nrg_th_ofdm = 95,
 350 };
 351
 352 #endif /* CONFIG_IWL5000_RUN_TIME_CALIB */
 353
 354 static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
 355                                            size_t offset)
 356 {
 357         u32 address = eeprom_indirect_address(priv, offset);
 358         BUG_ON(address >= priv->cfg->eeprom_size);
 359         return &priv->eeprom[address];
 360 }
 361
 362 /*
 363  * ucode
 364  */
 365 static int iwl5000_load_section(struct iwl_priv *priv,
 366                                 struct fw_desc *image,
 367                                 u32 dst_addr)
 368 {
 369         int ret = 0;
 370         unsigned long flags;
 371
 372         dma_addr_t phy_addr = image->p_addr;
 373         u32 byte_cnt = image->len;
 374
 375         spin_lock_irqsave(&priv->lock, flags);
 376         ret = iwl_grab_nic_access(priv);
 377         if (ret) {
 378                 spin_unlock_irqrestore(&priv->lock, flags);
 379                 return ret;
 380         }
 381
 382         iwl_write_direct32(priv,
 383                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 384                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 385
 386         iwl_write_direct32(priv,
 387                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 388
 389         iwl_write_direct32(priv,
 390                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 391                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 392
 393         /* FIME: write the MSB of the phy_addr in CTRL1
 394          * iwl_write_direct32(priv,
 395                 IWL_FH_TFDIB_CTRL1_REG(IWL_FH_SRVC_CHNL),
 396                 ((phy_addr & MSB_MSK)
 397                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_count);
 398          */
 399         iwl_write_direct32(priv,
 400                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), byte_cnt);
 401         iwl_write_direct32(priv,
 402                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 403                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 404                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 405                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 406
 407         iwl_write_direct32(priv,
 408                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 409                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 410                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL |
 411                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 412
 413         iwl_release_nic_access(priv);
 414         spin_unlock_irqrestore(&priv->lock, flags);
 415         return 0;
 416 }
 417
 418 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
 419                 struct fw_desc *inst_image,
 420                 struct fw_desc *data_image)
 421 {
 422         int ret = 0;
 423
 424         ret = iwl5000_load_section(
 425                 priv, inst_image, RTC_INST_LOWER_BOUND);
 426         if (ret)
 427                 return ret;
 428
 429         IWL_DEBUG_INFO("INST uCode section being loaded...\n");
 430         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 431                                 priv->ucode_write_complete, 5 * HZ);
 432         if (ret == -ERESTARTSYS) {
 433                 IWL_ERROR("Could not load the INST uCode section due "
 434                         "to interrupt\n");
 435                 return ret;
 436         }
 437         if (!ret) {
 438                 IWL_ERROR("Could not load the INST uCode section\n");
 439                 return -ETIMEDOUT;
 440         }
 441
 442         priv->ucode_write_complete = 0;
 443
 444         ret = iwl5000_load_section(
 445                 priv, data_image, RTC_DATA_LOWER_BOUND);
 446         if (ret)
 447                 return ret;
 448
 449         IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
 450
 451         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 452                                 priv->ucode_write_complete, 5 * HZ);
 453         if (ret == -ERESTARTSYS) {
 454                 IWL_ERROR("Could not load the INST uCode section due "
 455                         "to interrupt\n");
 456                 return ret;
 457         } else if (!ret) {
 458                 IWL_ERROR("Could not load the DATA uCode section\n");
 459                 return -ETIMEDOUT;
 460         } else
 461                 ret = 0;
 462
 463         priv->ucode_write_complete = 0;
 464
 465         return ret;
 466 }
 467
 468 static int iwl5000_load_ucode(struct iwl_priv *priv)
 469 {
 470         int ret = 0;
 471
 472         /* check whether init ucode should be loaded, or rather runtime ucode */
 473         if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
 474                 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
 475                 ret = iwl5000_load_given_ucode(priv,
 476                         &priv->ucode_init, &priv->ucode_init_data);
 477                 if (!ret) {
 478                         IWL_DEBUG_INFO("Init ucode load complete.\n");
 479                         priv->ucode_type = UCODE_INIT;
 480                 }
 481         } else {
 482                 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
 483                         "Loading runtime ucode...\n");
 484                 ret = iwl5000_load_given_ucode(priv,
 485                         &priv->ucode_code, &priv->ucode_data);
 486                 if (!ret) {
 487                         IWL_DEBUG_INFO("Runtime ucode load complete.\n");
 488                         priv->ucode_type = UCODE_RT;
 489                 }
 490         }
 491
 492         return ret;
 493 }
 494
 495 static void iwl5000_init_alive_start(struct iwl_priv *priv)
 496 {
 497         int ret = 0;
 498
 499         /* Check alive response for "valid" sign from uCode */
 500         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
 501                 /* We had an error bringing up the hardware, so take it
 502                  * all the way back down so we can try again */
 503                 IWL_DEBUG_INFO("Initialize Alive failed.\n");
 504                 goto restart;
 505         }
 506
 507         /* initialize uCode was loaded... verify inst image.
 508          * This is a paranoid check, because we would not have gotten the
 509          * "initialize" alive if code weren't properly loaded.  */
 510         if (iwl_verify_ucode(priv)) {
 511                 /* Runtime instruction load was bad;
 512                  * take it all the way back down so we can try again */
 513                 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
 514                 goto restart;
 515         }
 516
 517         iwlcore_clear_stations_table(priv);
 518         ret = priv->cfg->ops->lib->alive_notify(priv);
 519         if (ret) {
 520                 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
 521                 goto restart;
 522         }
 523
 524         return;
 525
 526 restart:
 527         /* real restart (first load init_ucode) */
 528         queue_work(priv->workqueue, &priv->restart);
 529 }
 530
 531 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
 532                                 int txq_id, u32 index)
 533 {
 534         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
 535                         (index & 0xff) | (txq_id << 8));
 536         iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
 537 }
 538
 539 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
 540                                         struct iwl_tx_queue *txq,
 541                                         int tx_fifo_id, int scd_retry)
 542 {
 543         int txq_id = txq->q.id;
 544         int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
 545
 546         iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 547                         (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 548                         (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
 549                         (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
 550                         IWL50_SCD_QUEUE_STTS_REG_MSK);
 551
 552         txq->sched_retry = scd_retry;
 553
 554         IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
 555                        active ? "Activate" : "Deactivate",
 556                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
 557 }
 558
 559 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
 560 {
 561         struct iwl_wimax_coex_cmd coex_cmd;
 562
 563         memset(&coex_cmd, 0, sizeof(coex_cmd));
 564
 565         return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
 566                                 sizeof(coex_cmd), &coex_cmd);
 567 }
 568
 569 static int iwl5000_alive_notify(struct iwl_priv *priv)
 570 {
 571         u32 a;
 572         int i = 0;
 573         unsigned long flags;
 574         int ret;
 575
 576         spin_lock_irqsave(&priv->lock, flags);
 577
 578         ret = iwl_grab_nic_access(priv);
 579         if (ret) {
 580                 spin_unlock_irqrestore(&priv->lock, flags);
 581                 return ret;
 582         }
 583
 584         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
 585         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
 586         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
 587                 a += 4)
 588                 iwl_write_targ_mem(priv, a, 0);
 589         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
 590                 a += 4)
 591                 iwl_write_targ_mem(priv, a, 0);
 592         for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
 593                 iwl_write_targ_mem(priv, a, 0);
 594
 595         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
 596                 (priv->shared_phys +
 597                  offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10);
 598         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
 599                 IWL50_SCD_QUEUECHAIN_SEL_ALL(
 600                         priv->hw_params.max_txq_num));
 601         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
 602
 603         /* initiate the queues */
 604         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 605                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
 606                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 607                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 608                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 609                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 610                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
 611                                 sizeof(u32),
 612                                 ((SCD_WIN_SIZE <<
 613                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 614                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 615                                 ((SCD_FRAME_LIMIT <<
 616                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 617                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 618         }
 619
 620         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
 621                                  (1 << priv->hw_params.max_txq_num) - 1);
 622
 623         iwl_write_prph(priv, IWL50_SCD_TXFACT,
 624                                  SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
 625
 626         iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
 627         /* map qos queues to fifos one-to-one */
 628         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
 629                 int ac = iwl5000_default_queue_to_tx_fifo[i];
 630                 iwl_txq_ctx_activate(priv, i);
 631                 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
 632         }
 633         /* TODO - need to initialize those FIFOs inside the loop above,
 634          * not only mark them as active */
 635         iwl_txq_ctx_activate(priv, 4);
 636         iwl_txq_ctx_activate(priv, 7);
 637         iwl_txq_ctx_activate(priv, 8);
 638         iwl_txq_ctx_activate(priv, 9);
 639
 640         iwl_release_nic_access(priv);
 641         spin_unlock_irqrestore(&priv->lock, flags);
 642
 643         iwl5000_send_wimax_coex(priv);
 644
 645         return 0;
 646 }
 647
 648 static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
 649 {
 650         if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
 651             (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
 652                 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
 653                           IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
 654                 return -EINVAL;
 655         }
 656
 657         priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
 658         priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
 659         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
 660         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
 661         if (priv->cfg->mod_params->amsdu_size_8K)
 662                 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
 663         else
 664                 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
 665         priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
 666         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
 667         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
 668         priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
 669         priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
 670         priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
 671         priv->hw_params.fat_channel =  BIT(IEEE80211_BAND_2GHZ) |
 672                                         BIT(IEEE80211_BAND_5GHZ);
 673 #ifdef CONFIG_IWL5000_RUN_TIME_CALIB
 674         priv->hw_params.sens = &iwl5000_sensitivity;
 675 #endif
 676
 677         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 678         case CSR_HW_REV_TYPE_5100:
 679         case CSR_HW_REV_TYPE_5150:
 680                 priv->hw_params.tx_chains_num = 1;
 681                 priv->hw_params.rx_chains_num = 2;
 682                 /* FIXME: move to ANT_A, ANT_B, ANT_C enum */
 683                 priv->hw_params.valid_tx_ant = ANT_A;
 684                 priv->hw_params.valid_rx_ant = ANT_AB;
 685                 break;
 686         case CSR_HW_REV_TYPE_5300:
 687         case CSR_HW_REV_TYPE_5350:
 688                 priv->hw_params.tx_chains_num = 3;
 689                 priv->hw_params.rx_chains_num = 3;
 690                 priv->hw_params.valid_tx_ant = ANT_ABC;
 691                 priv->hw_params.valid_rx_ant = ANT_ABC;
 692                 break;
 693         }
 694
 695         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 696         case CSR_HW_REV_TYPE_5100:
 697         case CSR_HW_REV_TYPE_5300:
 698                 /* 5X00 wants in Celsius */
 699                 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
 700                 break;
 701         case CSR_HW_REV_TYPE_5150:
 702         case CSR_HW_REV_TYPE_5350:
 703                 /* 5X50 wants in Kelvin */
 704                 priv->hw_params.ct_kill_threshold =
 705                                 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
 706                 break;
 707         }
 708
 709         return 0;
 710 }
 711
 712 static int iwl5000_alloc_shared_mem(struct iwl_priv *priv)
 713 {
 714         priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
 715                                         sizeof(struct iwl5000_shared),
 716                                         &priv->shared_phys);
 717         if (!priv->shared_virt)
 718                 return -ENOMEM;
 719
 720         memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared));
 721
 722         priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed);
 723
 724         return 0;
 725 }
 726
 727 static void iwl5000_free_shared_mem(struct iwl_priv *priv)
 728 {
 729         if (priv->shared_virt)
 730                 pci_free_consistent(priv->pci_dev,
 731                                     sizeof(struct iwl5000_shared),
 732                                     priv->shared_virt,
 733                                     priv->shared_phys);
 734 }
 735
 736 static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv)
 737 {
 738         struct iwl5000_shared *s = priv->shared_virt;
 739         return le32_to_cpu(s->rb_closed) & 0xFFF;
 740 }
 741
 742 /**
 743  * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 744  */
 745 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
 746                                             struct iwl_tx_queue *txq,
 747                                             u16 byte_cnt)
 748 {
 749         struct iwl5000_shared *shared_data = priv->shared_virt;
 750         int txq_id = txq->q.id;
 751         u8 sec_ctl = 0;
 752         u8 sta = 0;
 753         int len;
 754
 755         len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 756
 757         if (txq_id != IWL_CMD_QUEUE_NUM) {
 758                 sta = txq->cmd[txq->q.write_ptr].cmd.tx.sta_id;
 759                 sec_ctl = txq->cmd[txq->q.write_ptr].cmd.tx.sec_ctl;
 760
 761                 switch (sec_ctl & TX_CMD_SEC_MSK) {
 762                 case TX_CMD_SEC_CCM:
 763                         len += CCMP_MIC_LEN;
 764                         break;
 765                 case TX_CMD_SEC_TKIP:
 766                         len += TKIP_ICV_LEN;
 767                         break;
 768                 case TX_CMD_SEC_WEP:
 769                         len += WEP_IV_LEN + WEP_ICV_LEN;
 770                         break;
 771                 }
 772         }
 773
 774         IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 775                        tfd_offset[txq->q.write_ptr], byte_cnt, len);
 776
 777         IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 778                        tfd_offset[txq->q.write_ptr], sta_id, sta);
 779
 780         if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
 781                 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 782                         tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
 783                         byte_cnt, len);
 784                 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 785                         tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
 786                         sta_id, sta);
 787         }
 788 }
 789
 790 static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
 791 {
 792         u16 size = (u16)sizeof(struct iwl_addsta_cmd);
 793         memcpy(data, cmd, size);
 794         return size;
 795 }
 796
 797
 798 static int iwl5000_disable_tx_fifo(struct iwl_priv *priv)
 799 {
 800         unsigned long flags;
 801         int ret;
 802
 803         spin_lock_irqsave(&priv->lock, flags);
 804
 805         ret = iwl_grab_nic_access(priv);
 806         if (unlikely(ret)) {
 807                 IWL_ERROR("Tx fifo reset failed");
 808                 spin_unlock_irqrestore(&priv->lock, flags);
 809                 return ret;
 810         }
 811
 812         iwl_write_prph(priv, IWL50_SCD_TXFACT, 0);
 813         iwl_release_nic_access(priv);
 814         spin_unlock_irqrestore(&priv->lock, flags);
 815
 816         return 0;
 817 }
 818
 819 /* Currently 5000 is the supperset of everything */
 820 static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
 821 {
 822         return len;
 823 }
 824
 825 static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
 826 {
 827 }
 828
 829 static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
 830 {
 831         return (addr >= RTC_DATA_LOWER_BOUND) &&
 832                 (addr < IWL50_RTC_DATA_UPPER_BOUND);
 833 }
 834
 835 static struct iwl_hcmd_ops iwl5000_hcmd = {
 836 };
 837
 838 static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
 839         .get_hcmd_size = iwl5000_get_hcmd_size,
 840         .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
 841 #ifdef CONFIG_IWL5000_RUN_TIME_CALIB
 842         .gain_computation = iwl5000_gain_computation,
 843         .chain_noise_reset = iwl5000_chain_noise_reset,
 844 #endif
 845 };
 846
 847 static struct iwl_lib_ops iwl5000_lib = {
 848         .set_hw_params = iwl5000_hw_set_hw_params,
 849         .alloc_shared_mem = iwl5000_alloc_shared_mem,
 850         .free_shared_mem = iwl5000_free_shared_mem,
 851         .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx,
 852         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
 853         .disable_tx_fifo = iwl5000_disable_tx_fifo,
 854         .rx_handler_setup = iwl5000_rx_handler_setup,
 855         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
 856         .load_ucode = iwl5000_load_ucode,
 857         .init_alive_start = iwl5000_init_alive_start,
 858         .alive_notify = iwl5000_alive_notify,
 859         .apm_ops = {
 860                 .init = iwl5000_apm_init,
 861                 .reset = iwl5000_apm_reset,
 862                 .config = iwl5000_nic_config,
 863                 .set_pwr_src = iwl4965_set_pwr_src,
 864         },
 865         .eeprom_ops = {
 866                 .regulatory_bands = {
 867                         EEPROM_5000_REG_BAND_1_CHANNELS,
 868                         EEPROM_5000_REG_BAND_2_CHANNELS,
 869                         EEPROM_5000_REG_BAND_3_CHANNELS,
 870                         EEPROM_5000_REG_BAND_4_CHANNELS,
 871                         EEPROM_5000_REG_BAND_5_CHANNELS,
 872                         EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
 873                         EEPROM_5000_REG_BAND_52_FAT_CHANNELS
 874                 },
 875                 .verify_signature  = iwlcore_eeprom_verify_signature,
 876                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
 877                 .release_semaphore = iwlcore_eeprom_release_semaphore,
 878                 .check_version  = iwl5000_eeprom_check_version,
 879                 .query_addr = iwl5000_eeprom_query_addr,
 880         },
 881 };
 882
 883 static struct iwl_ops iwl5000_ops = {
 884         .lib = &iwl5000_lib,
 885         .hcmd = &iwl5000_hcmd,
 886         .utils = &iwl5000_hcmd_utils,
 887 };
 888
 889 static struct iwl_mod_params iwl50_mod_params = {
 890         .num_of_queues = IWL50_NUM_QUEUES,
 891         .enable_qos = 1,
 892         .amsdu_size_8K = 1,
 893         .restart_fw = 1,
 894         /* the rest are 0 by default */
 895 };
 896
 897
 898 struct iwl_cfg iwl5300_agn_cfg = {
 899         .name = "5300AGN",
 900         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
 901         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
 902         .ops = &iwl5000_ops,
 903         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
 904         .mod_params = &iwl50_mod_params,
 905 };
 906
 907 struct iwl_cfg iwl5100_agn_cfg = {
 908         .name = "5100AGN",
 909         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
 910         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
 911         .ops = &iwl5000_ops,
 912         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
 913         .mod_params = &iwl50_mod_params,
 914 };
 915
 916 struct iwl_cfg iwl5350_agn_cfg = {
 917         .name = "5350AGN",
 918         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
 919         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
 920         .ops = &iwl5000_ops,
 921         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
 922         .mod_params = &iwl50_mod_params,
 923 };
 924
 925 module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
 926 MODULE_PARM_DESC(disable50,
 927                   "manually disable the 50XX radio (default 0 [radio on])");
 928 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
 929 MODULE_PARM_DESC(swcrypto50,
 930                   "using software crypto engine (default 0 [hardware])\n");
 931 module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
 932 MODULE_PARM_DESC(debug50, "50XX debug output mask");
 933 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
 934 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
 935 module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
 936 MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
 937 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
 938 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
 939 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
 940 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");