Merge branch 'linus' of master.kernel.org:/pub/scm/linux/kernel/git/perex/alsa
[linux-2.6] / drivers / usb / host / ehci-sched.c
1 /*
2  * Copyright (c) 2001-2004 by David Brownell
3  * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License as published by the
7  * Free Software Foundation; either version 2 of the License, or (at your
8  * option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
13  * for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software Foundation,
17  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18  */
19
20 /* this file is part of ehci-hcd.c */
21
22 /*-------------------------------------------------------------------------*/
23
24 /*
25  * EHCI scheduled transaction support:  interrupt, iso, split iso
26  * These are called "periodic" transactions in the EHCI spec.
27  *
28  * Note that for interrupt transfers, the QH/QTD manipulation is shared
29  * with the "asynchronous" transaction support (control/bulk transfers).
30  * The only real difference is in how interrupt transfers are scheduled.
31  *
32  * For ISO, we make an "iso_stream" head to serve the same role as a QH.
33  * It keeps track of every ITD (or SITD) that's linked, and holds enough
34  * pre-calculated schedule data to make appending to the queue be quick.
35  */
36
37 static int ehci_get_frame (struct usb_hcd *hcd);
38
39 /*-------------------------------------------------------------------------*/
40
41 /*
42  * periodic_next_shadow - return "next" pointer on shadow list
43  * @periodic: host pointer to qh/itd/sitd
44  * @tag: hardware tag for type of this record
45  */
46 static union ehci_shadow *
47 periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic,
48                 __hc32 tag)
49 {
50         switch (hc32_to_cpu(ehci, tag)) {
51         case Q_TYPE_QH:
52                 return &periodic->qh->qh_next;
53         case Q_TYPE_FSTN:
54                 return &periodic->fstn->fstn_next;
55         case Q_TYPE_ITD:
56                 return &periodic->itd->itd_next;
57         // case Q_TYPE_SITD:
58         default:
59                 return &periodic->sitd->sitd_next;
60         }
61 }
62
63 /* caller must hold ehci->lock */
64 static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
65 {
66         union ehci_shadow       *prev_p = &ehci->pshadow[frame];
67         __hc32                  *hw_p = &ehci->periodic[frame];
68         union ehci_shadow       here = *prev_p;
69
70         /* find predecessor of "ptr"; hw and shadow lists are in sync */
71         while (here.ptr && here.ptr != ptr) {
72                 prev_p = periodic_next_shadow(ehci, prev_p,
73                                 Q_NEXT_TYPE(ehci, *hw_p));
74                 hw_p = here.hw_next;
75                 here = *prev_p;
76         }
77         /* an interrupt entry (at list end) could have been shared */
78         if (!here.ptr)
79                 return;
80
81         /* update shadow and hardware lists ... the old "next" pointers
82          * from ptr may still be in use, the caller updates them.
83          */
84         *prev_p = *periodic_next_shadow(ehci, &here,
85                         Q_NEXT_TYPE(ehci, *hw_p));
86         *hw_p = *here.hw_next;
87 }
88
89 /* how many of the uframe's 125 usecs are allocated? */
90 static unsigned short
91 periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
92 {
93         __hc32                  *hw_p = &ehci->periodic [frame];
94         union ehci_shadow       *q = &ehci->pshadow [frame];
95         unsigned                usecs = 0;
96
97         while (q->ptr) {
98                 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
99                 case Q_TYPE_QH:
100                         /* is it in the S-mask? */
101                         if (q->qh->hw_info2 & cpu_to_hc32(ehci, 1 << uframe))
102                                 usecs += q->qh->usecs;
103                         /* ... or C-mask? */
104                         if (q->qh->hw_info2 & cpu_to_hc32(ehci,
105                                         1 << (8 + uframe)))
106                                 usecs += q->qh->c_usecs;
107                         hw_p = &q->qh->hw_next;
108                         q = &q->qh->qh_next;
109                         break;
110                 // case Q_TYPE_FSTN:
111                 default:
112                         /* for "save place" FSTNs, count the relevant INTR
113                          * bandwidth from the previous frame
114                          */
115                         if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) {
116                                 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
117                         }
118                         hw_p = &q->fstn->hw_next;
119                         q = &q->fstn->fstn_next;
120                         break;
121                 case Q_TYPE_ITD:
122                         usecs += q->itd->usecs [uframe];
123                         hw_p = &q->itd->hw_next;
124                         q = &q->itd->itd_next;
125                         break;
126                 case Q_TYPE_SITD:
127                         /* is it in the S-mask?  (count SPLIT, DATA) */
128                         if (q->sitd->hw_uframe & cpu_to_hc32(ehci,
129                                         1 << uframe)) {
130                                 if (q->sitd->hw_fullspeed_ep &
131                                                 cpu_to_hc32(ehci, 1<<31))
132                                         usecs += q->sitd->stream->usecs;
133                                 else    /* worst case for OUT start-split */
134                                         usecs += HS_USECS_ISO (188);
135                         }
136
137                         /* ... C-mask?  (count CSPLIT, DATA) */
138                         if (q->sitd->hw_uframe &
139                                         cpu_to_hc32(ehci, 1 << (8 + uframe))) {
140                                 /* worst case for IN complete-split */
141                                 usecs += q->sitd->stream->c_usecs;
142                         }
143
144                         hw_p = &q->sitd->hw_next;
145                         q = &q->sitd->sitd_next;
146                         break;
147                 }
148         }
149 #ifdef  DEBUG
150         if (usecs > 100)
151                 ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
152                         frame * 8 + uframe, usecs);
153 #endif
154         return usecs;
155 }
156
157 /*-------------------------------------------------------------------------*/
158
159 static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
160 {
161         if (!dev1->tt || !dev2->tt)
162                 return 0;
163         if (dev1->tt != dev2->tt)
164                 return 0;
165         if (dev1->tt->multi)
166                 return dev1->ttport == dev2->ttport;
167         else
168                 return 1;
169 }
170
171 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
172
173 /* Which uframe does the low/fullspeed transfer start in?
174  *
175  * The parameter is the mask of ssplits in "H-frame" terms
176  * and this returns the transfer start uframe in "B-frame" terms,
177  * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
178  * will cause a transfer in "B-frame" uframe 0.  "B-frames" lag
179  * "H-frames" by 1 uframe.  See the EHCI spec sec 4.5 and figure 4.7.
180  */
181 static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
182 {
183         unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask);
184         if (!smask) {
185                 ehci_err(ehci, "invalid empty smask!\n");
186                 /* uframe 7 can't have bw so this will indicate failure */
187                 return 7;
188         }
189         return ffs(smask) - 1;
190 }
191
192 static const unsigned char
193 max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
194
195 /* carryover low/fullspeed bandwidth that crosses uframe boundries */
196 static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
197 {
198         int i;
199         for (i=0; i<7; i++) {
200                 if (max_tt_usecs[i] < tt_usecs[i]) {
201                         tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i];
202                         tt_usecs[i] = max_tt_usecs[i];
203                 }
204         }
205 }
206
207 /* How many of the tt's periodic downstream 1000 usecs are allocated?
208  *
209  * While this measures the bandwidth in terms of usecs/uframe,
210  * the low/fullspeed bus has no notion of uframes, so any particular
211  * low/fullspeed transfer can "carry over" from one uframe to the next,
212  * since the TT just performs downstream transfers in sequence.
213  *
214  * For example two seperate 100 usec transfers can start in the same uframe,
215  * and the second one would "carry over" 75 usecs into the next uframe.
216  */
217 static void
218 periodic_tt_usecs (
219         struct ehci_hcd *ehci,
220         struct usb_device *dev,
221         unsigned frame,
222         unsigned short tt_usecs[8]
223 )
224 {
225         __hc32                  *hw_p = &ehci->periodic [frame];
226         union ehci_shadow       *q = &ehci->pshadow [frame];
227         unsigned char           uf;
228
229         memset(tt_usecs, 0, 16);
230
231         while (q->ptr) {
232                 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
233                 case Q_TYPE_ITD:
234                         hw_p = &q->itd->hw_next;
235                         q = &q->itd->itd_next;
236                         continue;
237                 case Q_TYPE_QH:
238                         if (same_tt(dev, q->qh->dev)) {
239                                 uf = tt_start_uframe(ehci, q->qh->hw_info2);
240                                 tt_usecs[uf] += q->qh->tt_usecs;
241                         }
242                         hw_p = &q->qh->hw_next;
243                         q = &q->qh->qh_next;
244                         continue;
245                 case Q_TYPE_SITD:
246                         if (same_tt(dev, q->sitd->urb->dev)) {
247                                 uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
248                                 tt_usecs[uf] += q->sitd->stream->tt_usecs;
249                         }
250                         hw_p = &q->sitd->hw_next;
251                         q = &q->sitd->sitd_next;
252                         continue;
253                 // case Q_TYPE_FSTN:
254                 default:
255                         ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n",
256                                         frame);
257                         hw_p = &q->fstn->hw_next;
258                         q = &q->fstn->fstn_next;
259                 }
260         }
261
262         carryover_tt_bandwidth(tt_usecs);
263
264         if (max_tt_usecs[7] < tt_usecs[7])
265                 ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n",
266                         frame, tt_usecs[7] - max_tt_usecs[7]);
267 }
268
269 /*
270  * Return true if the device's tt's downstream bus is available for a
271  * periodic transfer of the specified length (usecs), starting at the
272  * specified frame/uframe.  Note that (as summarized in section 11.19
273  * of the usb 2.0 spec) TTs can buffer multiple transactions for each
274  * uframe.
275  *
276  * The uframe parameter is when the fullspeed/lowspeed transfer
277  * should be executed in "B-frame" terms, which is the same as the
278  * highspeed ssplit's uframe (which is in "H-frame" terms).  For example
279  * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0.
280  * See the EHCI spec sec 4.5 and fig 4.7.
281  *
282  * This checks if the full/lowspeed bus, at the specified starting uframe,
283  * has the specified bandwidth available, according to rules listed
284  * in USB 2.0 spec section 11.18.1 fig 11-60.
285  *
286  * This does not check if the transfer would exceed the max ssplit
287  * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4,
288  * since proper scheduling limits ssplits to less than 16 per uframe.
289  */
290 static int tt_available (
291         struct ehci_hcd         *ehci,
292         unsigned                period,
293         struct usb_device       *dev,
294         unsigned                frame,
295         unsigned                uframe,
296         u16                     usecs
297 )
298 {
299         if ((period == 0) || (uframe >= 7))     /* error */
300                 return 0;
301
302         for (; frame < ehci->periodic_size; frame += period) {
303                 unsigned short tt_usecs[8];
304
305                 periodic_tt_usecs (ehci, dev, frame, tt_usecs);
306
307                 ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in"
308                         " schedule %d/%d/%d/%d/%d/%d/%d/%d\n",
309                         frame, usecs, uframe,
310                         tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3],
311                         tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]);
312
313                 if (max_tt_usecs[uframe] <= tt_usecs[uframe]) {
314                         ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n",
315                                 frame, uframe);
316                         return 0;
317                 }
318
319                 /* special case for isoc transfers larger than 125us:
320                  * the first and each subsequent fully used uframe
321                  * must be empty, so as to not illegally delay
322                  * already scheduled transactions
323                  */
324                 if (125 < usecs) {
325                         int ufs = (usecs / 125) - 1;
326                         int i;
327                         for (i = uframe; i < (uframe + ufs) && i < 8; i++)
328                                 if (0 < tt_usecs[i]) {
329                                         ehci_vdbg(ehci,
330                                                 "multi-uframe xfer can't fit "
331                                                 "in frame %d uframe %d\n",
332                                                 frame, i);
333                                         return 0;
334                                 }
335                 }
336
337                 tt_usecs[uframe] += usecs;
338
339                 carryover_tt_bandwidth(tt_usecs);
340
341                 /* fail if the carryover pushed bw past the last uframe's limit */
342                 if (max_tt_usecs[7] < tt_usecs[7]) {
343                         ehci_vdbg(ehci,
344                                 "tt unavailable usecs %d frame %d uframe %d\n",
345                                 usecs, frame, uframe);
346                         return 0;
347                 }
348         }
349
350         return 1;
351 }
352
353 #else
354
355 /* return true iff the device's transaction translator is available
356  * for a periodic transfer starting at the specified frame, using
357  * all the uframes in the mask.
358  */
359 static int tt_no_collision (
360         struct ehci_hcd         *ehci,
361         unsigned                period,
362         struct usb_device       *dev,
363         unsigned                frame,
364         u32                     uf_mask
365 )
366 {
367         if (period == 0)        /* error */
368                 return 0;
369
370         /* note bandwidth wastage:  split never follows csplit
371          * (different dev or endpoint) until the next uframe.
372          * calling convention doesn't make that distinction.
373          */
374         for (; frame < ehci->periodic_size; frame += period) {
375                 union ehci_shadow       here;
376                 __hc32                  type;
377
378                 here = ehci->pshadow [frame];
379                 type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]);
380                 while (here.ptr) {
381                         switch (hc32_to_cpu(ehci, type)) {
382                         case Q_TYPE_ITD:
383                                 type = Q_NEXT_TYPE(ehci, here.itd->hw_next);
384                                 here = here.itd->itd_next;
385                                 continue;
386                         case Q_TYPE_QH:
387                                 if (same_tt (dev, here.qh->dev)) {
388                                         u32             mask;
389
390                                         mask = hc32_to_cpu(ehci,
391                                                         here.qh->hw_info2);
392                                         /* "knows" no gap is needed */
393                                         mask |= mask >> 8;
394                                         if (mask & uf_mask)
395                                                 break;
396                                 }
397                                 type = Q_NEXT_TYPE(ehci, here.qh->hw_next);
398                                 here = here.qh->qh_next;
399                                 continue;
400                         case Q_TYPE_SITD:
401                                 if (same_tt (dev, here.sitd->urb->dev)) {
402                                         u16             mask;
403
404                                         mask = hc32_to_cpu(ehci, here.sitd
405                                                                 ->hw_uframe);
406                                         /* FIXME assumes no gap for IN! */
407                                         mask |= mask >> 8;
408                                         if (mask & uf_mask)
409                                                 break;
410                                 }
411                                 type = Q_NEXT_TYPE(ehci, here.sitd->hw_next);
412                                 here = here.sitd->sitd_next;
413                                 continue;
414                         // case Q_TYPE_FSTN:
415                         default:
416                                 ehci_dbg (ehci,
417                                         "periodic frame %d bogus type %d\n",
418                                         frame, type);
419                         }
420
421                         /* collision or error */
422                         return 0;
423                 }
424         }
425
426         /* no collision */
427         return 1;
428 }
429
430 #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */
431
432 /*-------------------------------------------------------------------------*/
433
434 static int enable_periodic (struct ehci_hcd *ehci)
435 {
436         u32     cmd;
437         int     status;
438
439         /* did clearing PSE did take effect yet?
440          * takes effect only at frame boundaries...
441          */
442         status = handshake(ehci, &ehci->regs->status, STS_PSS, 0, 9 * 125);
443         if (status != 0) {
444                 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
445                 return status;
446         }
447
448         cmd = ehci_readl(ehci, &ehci->regs->command) | CMD_PSE;
449         ehci_writel(ehci, cmd, &ehci->regs->command);
450         /* posted write ... PSS happens later */
451         ehci_to_hcd(ehci)->state = HC_STATE_RUNNING;
452
453         /* make sure ehci_work scans these */
454         ehci->next_uframe = ehci_readl(ehci, &ehci->regs->frame_index)
455                 % (ehci->periodic_size << 3);
456         return 0;
457 }
458
459 static int disable_periodic (struct ehci_hcd *ehci)
460 {
461         u32     cmd;
462         int     status;
463
464         /* did setting PSE not take effect yet?
465          * takes effect only at frame boundaries...
466          */
467         status = handshake(ehci, &ehci->regs->status, STS_PSS, STS_PSS, 9 * 125);
468         if (status != 0) {
469                 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
470                 return status;
471         }
472
473         cmd = ehci_readl(ehci, &ehci->regs->command) & ~CMD_PSE;
474         ehci_writel(ehci, cmd, &ehci->regs->command);
475         /* posted write ... */
476
477         ehci->next_uframe = -1;
478         return 0;
479 }
480
481 /*-------------------------------------------------------------------------*/
482 #ifdef CONFIG_CPU_FREQ
483
484 static int safe_to_modify_i (struct ehci_hcd *ehci, struct ehci_qh *qh)
485 {
486         int now; /* current (frame * 8) + uframe */
487         int prev_start, next_start; /* uframes from/to split start */
488         int start_uframe = ffs(le32_to_cpup (&qh->hw_info2) & QH_SMASK);
489         int end_uframe = fls((le32_to_cpup (&qh->hw_info2) & QH_CMASK) >> 8);
490         int split_duration = end_uframe - start_uframe;
491
492         now = readl(&ehci->regs->frame_index) % (ehci->periodic_size << 3);
493
494         next_start = ((1024 << 3) + (qh->start << 3) + start_uframe - now)
495                         % (qh->period << 3);
496         prev_start = (qh->period << 3) - next_start;
497
498         /*
499          * Make sure there will be at least one uframe when qh is safe.
500          */
501         if ((qh->period << 3) <= (ehci->i_thresh + 2 + split_duration))
502                 /* never safe */
503                 return -EINVAL;
504
505         /*
506          * Wait 1 uframe after transaction should have started, to make
507          * sure controller has time to write back overlay, so we can
508          * check QTD_STS_STS to see if transaction is in progress.
509          */
510         if ((next_start > ehci->i_thresh) && (prev_start > 1))
511                 /* safe to set "i" bit if split isn't in progress */
512                 return (qh->hw_token & STATUS_BIT(ehci)) ? 0 : 1;
513         else
514                 return 0;
515 }
516
517 /* Set inactivate bit for all the split interrupt QHs. */
518 static void qh_inactivate_split_intr_qhs (struct ehci_hcd *ehci)
519 {
520         struct ehci_qh  *qh;
521         int             not_done, safe;
522         u32             inactivate = INACTIVATE_BIT(ehci);
523         u32             active = ACTIVE_BIT(ehci);
524
525         do {
526                 not_done = 0;
527                 list_for_each_entry(qh, &ehci->split_intr_qhs,
528                                 split_intr_qhs) {
529                         if (qh->hw_info1 & inactivate)
530                                 /* already off */
531                                 continue;
532                         /*
533                          * To avoid setting "I" after the start split happens,
534                          * don't set it if the QH might be cached in the
535                          * controller.  Some HCs (Broadcom/ServerWorks HT1000)
536                          * will stop in the middle of a split transaction when
537                          * the "I" bit is set.
538                          */
539                         safe = safe_to_modify_i(ehci, qh);
540                         if (safe == 0) {
541                                 not_done = 1;
542                         } else if (safe > 0) {
543                                 qh->was_active = qh->hw_token & active;
544                                 qh->hw_info1 |= inactivate;
545                         }
546                 }
547         } while (not_done);
548         wmb();
549 }
550
551 static void qh_reactivate_split_intr_qhs (struct ehci_hcd *ehci)
552 {
553         struct ehci_qh  *qh;
554         u32             token;
555         int             not_done, safe;
556         u32             inactivate = INACTIVATE_BIT(ehci);
557         u32             active = ACTIVE_BIT(ehci);
558         u32             halt = HALT_BIT(ehci);
559
560         do {
561                 not_done = 0;
562                 list_for_each_entry(qh, &ehci->split_intr_qhs, split_intr_qhs) {
563                         if (!(qh->hw_info1 & inactivate)) /* already on */
564                                 continue;
565                         /*
566                          * Don't reactivate if cached, or controller might
567                          * overwrite overlay after we modify it!
568                          */
569                         safe = safe_to_modify_i(ehci, qh);
570                         if (safe == 0) {
571                                 not_done = 1;
572                         } else if (safe > 0) {
573                                 /* See EHCI 1.0 section 4.15.2.4. */
574                                 token = qh->hw_token;
575                                 qh->hw_token = (token | halt) & ~active;
576                                 wmb();
577                                 qh->hw_info1 &= ~inactivate;
578                                 wmb();
579                                 qh->hw_token = (token & ~halt) | qh->was_active;
580                         }
581                 }
582         } while (not_done);
583 }
584 #endif
585
586 /* periodic schedule slots have iso tds (normal or split) first, then a
587  * sparse tree for active interrupt transfers.
588  *
589  * this just links in a qh; caller guarantees uframe masks are set right.
590  * no FSTN support (yet; ehci 0.96+)
591  */
592 static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
593 {
594         unsigned        i;
595         unsigned        period = qh->period;
596
597         dev_dbg (&qh->dev->dev,
598                 "link qh%d-%04x/%p start %d [%d/%d us]\n",
599                 period, hc32_to_cpup(ehci, &qh->hw_info2) & (QH_CMASK | QH_SMASK),
600                 qh, qh->start, qh->usecs, qh->c_usecs);
601
602 #ifdef CONFIG_CPU_FREQ
603         /*
604          * If low/full speed interrupt QHs are inactive (because of
605          * cpufreq changing processor speeds), start QH with I flag set--
606          * it will automatically be cleared when cpufreq is done.
607          */
608         if (ehci->cpufreq_changing)
609                 if (!(qh->hw_info1 & (cpu_to_le32(1 << 13))))
610                         qh->hw_info1 |= INACTIVATE_BIT(ehci);
611 #endif
612
613         /* high bandwidth, or otherwise every microframe */
614         if (period == 0)
615                 period = 1;
616
617         for (i = qh->start; i < ehci->periodic_size; i += period) {
618                 union ehci_shadow       *prev = &ehci->pshadow[i];
619                 __hc32                  *hw_p = &ehci->periodic[i];
620                 union ehci_shadow       here = *prev;
621                 __hc32                  type = 0;
622
623                 /* skip the iso nodes at list head */
624                 while (here.ptr) {
625                         type = Q_NEXT_TYPE(ehci, *hw_p);
626                         if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
627                                 break;
628                         prev = periodic_next_shadow(ehci, prev, type);
629                         hw_p = &here.qh->hw_next;
630                         here = *prev;
631                 }
632
633                 /* sorting each branch by period (slow-->fast)
634                  * enables sharing interior tree nodes
635                  */
636                 while (here.ptr && qh != here.qh) {
637                         if (qh->period > here.qh->period)
638                                 break;
639                         prev = &here.qh->qh_next;
640                         hw_p = &here.qh->hw_next;
641                         here = *prev;
642                 }
643                 /* link in this qh, unless some earlier pass did that */
644                 if (qh != here.qh) {
645                         qh->qh_next = here;
646                         if (here.qh)
647                                 qh->hw_next = *hw_p;
648                         wmb ();
649                         prev->qh = qh;
650                         *hw_p = QH_NEXT (ehci, qh->qh_dma);
651                 }
652         }
653         qh->qh_state = QH_STATE_LINKED;
654         qh_get (qh);
655
656         /* update per-qh bandwidth for usbfs */
657         ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
658                 ? ((qh->usecs + qh->c_usecs) / qh->period)
659                 : (qh->usecs * 8);
660
661 #ifdef CONFIG_CPU_FREQ
662         /* add qh to list of low/full speed interrupt QHs, if applicable */
663         if (!(qh->hw_info1 & (cpu_to_le32(1 << 13)))) {
664                 list_add(&qh->split_intr_qhs, &ehci->split_intr_qhs);
665         }
666 #endif
667         /* maybe enable periodic schedule processing */
668         if (!ehci->periodic_sched++)
669                 return enable_periodic (ehci);
670
671         return 0;
672 }
673
674 static void qh_unlink_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
675 {
676         unsigned        i;
677         unsigned        period;
678
679         // FIXME:
680         // IF this isn't high speed
681         //   and this qh is active in the current uframe
682         //   (and overlay token SplitXstate is false?)
683         // THEN
684         //   qh->hw_info1 |= __constant_cpu_to_hc32(1 << 7 /* "ignore" */);
685
686 #ifdef CONFIG_CPU_FREQ
687         /* remove qh from list of low/full speed interrupt QHs */
688         if (!(qh->hw_info1 & (cpu_to_le32(1 << 13)))) {
689                 list_del_init(&qh->split_intr_qhs);
690         }
691 #endif
692
693         /* high bandwidth, or otherwise part of every microframe */
694         if ((period = qh->period) == 0)
695                 period = 1;
696
697         for (i = qh->start; i < ehci->periodic_size; i += period)
698                 periodic_unlink (ehci, i, qh);
699
700         /* update per-qh bandwidth for usbfs */
701         ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
702                 ? ((qh->usecs + qh->c_usecs) / qh->period)
703                 : (qh->usecs * 8);
704
705         dev_dbg (&qh->dev->dev,
706                 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
707                 qh->period,
708                 hc32_to_cpup(ehci, &qh->hw_info2) & (QH_CMASK | QH_SMASK),
709                 qh, qh->start, qh->usecs, qh->c_usecs);
710
711         /* qh->qh_next still "live" to HC */
712         qh->qh_state = QH_STATE_UNLINK;
713         qh->qh_next.ptr = NULL;
714         qh_put (qh);
715
716         /* maybe turn off periodic schedule */
717         ehci->periodic_sched--;
718         if (!ehci->periodic_sched)
719                 (void) disable_periodic (ehci);
720 }
721
722 static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
723 {
724         unsigned        wait;
725
726         qh_unlink_periodic (ehci, qh);
727
728         /* simple/paranoid:  always delay, expecting the HC needs to read
729          * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
730          * expect khubd to clean up after any CSPLITs we won't issue.
731          * active high speed queues may need bigger delays...
732          */
733         if (list_empty (&qh->qtd_list)
734                         || (cpu_to_hc32(ehci, QH_CMASK)
735                                         & qh->hw_info2) != 0)
736                 wait = 2;
737         else
738                 wait = 55;      /* worst case: 3 * 1024 */
739
740         udelay (wait);
741         qh->qh_state = QH_STATE_IDLE;
742         qh->hw_next = EHCI_LIST_END(ehci);
743         wmb ();
744 }
745
746 /*-------------------------------------------------------------------------*/
747
748 static int check_period (
749         struct ehci_hcd *ehci,
750         unsigned        frame,
751         unsigned        uframe,
752         unsigned        period,
753         unsigned        usecs
754 ) {
755         int             claimed;
756
757         /* complete split running into next frame?
758          * given FSTN support, we could sometimes check...
759          */
760         if (uframe >= 8)
761                 return 0;
762
763         /*
764          * 80% periodic == 100 usec/uframe available
765          * convert "usecs we need" to "max already claimed"
766          */
767         usecs = 100 - usecs;
768
769         /* we "know" 2 and 4 uframe intervals were rejected; so
770          * for period 0, check _every_ microframe in the schedule.
771          */
772         if (unlikely (period == 0)) {
773                 do {
774                         for (uframe = 0; uframe < 7; uframe++) {
775                                 claimed = periodic_usecs (ehci, frame, uframe);
776                                 if (claimed > usecs)
777                                         return 0;
778                         }
779                 } while ((frame += 1) < ehci->periodic_size);
780
781         /* just check the specified uframe, at that period */
782         } else {
783                 do {
784                         claimed = periodic_usecs (ehci, frame, uframe);
785                         if (claimed > usecs)
786                                 return 0;
787                 } while ((frame += period) < ehci->periodic_size);
788         }
789
790         // success!
791         return 1;
792 }
793
794 static int check_intr_schedule (
795         struct ehci_hcd         *ehci,
796         unsigned                frame,
797         unsigned                uframe,
798         const struct ehci_qh    *qh,
799         __hc32                  *c_maskp
800 )
801 {
802         int             retval = -ENOSPC;
803         u8              mask = 0;
804
805         if (qh->c_usecs && uframe >= 6)         /* FSTN territory? */
806                 goto done;
807
808         if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
809                 goto done;
810         if (!qh->c_usecs) {
811                 retval = 0;
812                 *c_maskp = 0;
813                 goto done;
814         }
815
816 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
817         if (tt_available (ehci, qh->period, qh->dev, frame, uframe,
818                                 qh->tt_usecs)) {
819                 unsigned i;
820
821                 /* TODO : this may need FSTN for SSPLIT in uframe 5. */
822                 for (i=uframe+1; i<8 && i<uframe+4; i++)
823                         if (!check_period (ehci, frame, i,
824                                                 qh->period, qh->c_usecs))
825                                 goto done;
826                         else
827                                 mask |= 1 << i;
828
829                 retval = 0;
830
831                 *c_maskp = cpu_to_hc32(ehci, mask << 8);
832         }
833 #else
834         /* Make sure this tt's buffer is also available for CSPLITs.
835          * We pessimize a bit; probably the typical full speed case
836          * doesn't need the second CSPLIT.
837          *
838          * NOTE:  both SPLIT and CSPLIT could be checked in just
839          * one smart pass...
840          */
841         mask = 0x03 << (uframe + qh->gap_uf);
842         *c_maskp = cpu_to_hc32(ehci, mask << 8);
843
844         mask |= 1 << uframe;
845         if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
846                 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
847                                         qh->period, qh->c_usecs))
848                         goto done;
849                 if (!check_period (ehci, frame, uframe + qh->gap_uf,
850                                         qh->period, qh->c_usecs))
851                         goto done;
852                 retval = 0;
853         }
854 #endif
855 done:
856         return retval;
857 }
858
859 /* "first fit" scheduling policy used the first time through,
860  * or when the previous schedule slot can't be re-used.
861  */
862 static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
863 {
864         int             status;
865         unsigned        uframe;
866         __hc32          c_mask;
867         unsigned        frame;          /* 0..(qh->period - 1), or NO_FRAME */
868
869         qh_refresh(ehci, qh);
870         qh->hw_next = EHCI_LIST_END(ehci);
871         frame = qh->start;
872
873         /* reuse the previous schedule slots, if we can */
874         if (frame < qh->period) {
875                 uframe = ffs(hc32_to_cpup(ehci, &qh->hw_info2) & QH_SMASK);
876                 status = check_intr_schedule (ehci, frame, --uframe,
877                                 qh, &c_mask);
878         } else {
879                 uframe = 0;
880                 c_mask = 0;
881                 status = -ENOSPC;
882         }
883
884         /* else scan the schedule to find a group of slots such that all
885          * uframes have enough periodic bandwidth available.
886          */
887         if (status) {
888                 /* "normal" case, uframing flexible except with splits */
889                 if (qh->period) {
890                         frame = qh->period - 1;
891                         do {
892                                 for (uframe = 0; uframe < 8; uframe++) {
893                                         status = check_intr_schedule (ehci,
894                                                         frame, uframe, qh,
895                                                         &c_mask);
896                                         if (status == 0)
897                                                 break;
898                                 }
899                         } while (status && frame--);
900
901                 /* qh->period == 0 means every uframe */
902                 } else {
903                         frame = 0;
904                         status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
905                 }
906                 if (status)
907                         goto done;
908                 qh->start = frame;
909
910                 /* reset S-frame and (maybe) C-frame masks */
911                 qh->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK));
912                 qh->hw_info2 |= qh->period
913                         ? cpu_to_hc32(ehci, 1 << uframe)
914                         : cpu_to_hc32(ehci, QH_SMASK);
915                 qh->hw_info2 |= c_mask;
916         } else
917                 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
918
919         /* stuff into the periodic schedule */
920         status = qh_link_periodic (ehci, qh);
921 done:
922         return status;
923 }
924
925 static int intr_submit (
926         struct ehci_hcd         *ehci,
927         struct usb_host_endpoint *ep,
928         struct urb              *urb,
929         struct list_head        *qtd_list,
930         gfp_t                   mem_flags
931 ) {
932         unsigned                epnum;
933         unsigned long           flags;
934         struct ehci_qh          *qh;
935         int                     status = 0;
936         struct list_head        empty;
937
938         /* get endpoint and transfer/schedule data */
939         epnum = ep->desc.bEndpointAddress;
940
941         spin_lock_irqsave (&ehci->lock, flags);
942
943         if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
944                         &ehci_to_hcd(ehci)->flags))) {
945                 status = -ESHUTDOWN;
946                 goto done;
947         }
948
949         /* get qh and force any scheduling errors */
950         INIT_LIST_HEAD (&empty);
951         qh = qh_append_tds (ehci, urb, &empty, epnum, &ep->hcpriv);
952         if (qh == NULL) {
953                 status = -ENOMEM;
954                 goto done;
955         }
956         if (qh->qh_state == QH_STATE_IDLE) {
957                 if ((status = qh_schedule (ehci, qh)) != 0)
958                         goto done;
959         }
960
961         /* then queue the urb's tds to the qh */
962         qh = qh_append_tds (ehci, urb, qtd_list, epnum, &ep->hcpriv);
963         BUG_ON (qh == NULL);
964
965         /* ... update usbfs periodic stats */
966         ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
967
968 done:
969         spin_unlock_irqrestore (&ehci->lock, flags);
970         if (status)
971                 qtd_list_free (ehci, urb, qtd_list);
972
973         return status;
974 }
975
976 /*-------------------------------------------------------------------------*/
977
978 /* ehci_iso_stream ops work with both ITD and SITD */
979
980 static struct ehci_iso_stream *
981 iso_stream_alloc (gfp_t mem_flags)
982 {
983         struct ehci_iso_stream *stream;
984
985         stream = kzalloc(sizeof *stream, mem_flags);
986         if (likely (stream != NULL)) {
987                 INIT_LIST_HEAD(&stream->td_list);
988                 INIT_LIST_HEAD(&stream->free_list);
989                 stream->next_uframe = -1;
990                 stream->refcount = 1;
991         }
992         return stream;
993 }
994
995 static void
996 iso_stream_init (
997         struct ehci_hcd         *ehci,
998         struct ehci_iso_stream  *stream,
999         struct usb_device       *dev,
1000         int                     pipe,
1001         unsigned                interval
1002 )
1003 {
1004         static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
1005
1006         u32                     buf1;
1007         unsigned                epnum, maxp;
1008         int                     is_input;
1009         long                    bandwidth;
1010
1011         /*
1012          * this might be a "high bandwidth" highspeed endpoint,
1013          * as encoded in the ep descriptor's wMaxPacket field
1014          */
1015         epnum = usb_pipeendpoint (pipe);
1016         is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
1017         maxp = usb_maxpacket(dev, pipe, !is_input);
1018         if (is_input) {
1019                 buf1 = (1 << 11);
1020         } else {
1021                 buf1 = 0;
1022         }
1023
1024         /* knows about ITD vs SITD */
1025         if (dev->speed == USB_SPEED_HIGH) {
1026                 unsigned multi = hb_mult(maxp);
1027
1028                 stream->highspeed = 1;
1029
1030                 maxp = max_packet(maxp);
1031                 buf1 |= maxp;
1032                 maxp *= multi;
1033
1034                 stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum);
1035                 stream->buf1 = cpu_to_hc32(ehci, buf1);
1036                 stream->buf2 = cpu_to_hc32(ehci, multi);
1037
1038                 /* usbfs wants to report the average usecs per frame tied up
1039                  * when transfers on this endpoint are scheduled ...
1040                  */
1041                 stream->usecs = HS_USECS_ISO (maxp);
1042                 bandwidth = stream->usecs * 8;
1043                 bandwidth /= 1 << (interval - 1);
1044
1045         } else {
1046                 u32             addr;
1047                 int             think_time;
1048                 int             hs_transfers;
1049
1050                 addr = dev->ttport << 24;
1051                 if (!ehci_is_TDI(ehci)
1052                                 || (dev->tt->hub !=
1053                                         ehci_to_hcd(ehci)->self.root_hub))
1054                         addr |= dev->tt->hub->devnum << 16;
1055                 addr |= epnum << 8;
1056                 addr |= dev->devnum;
1057                 stream->usecs = HS_USECS_ISO (maxp);
1058                 think_time = dev->tt ? dev->tt->think_time : 0;
1059                 stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
1060                                 dev->speed, is_input, 1, maxp));
1061                 hs_transfers = max (1u, (maxp + 187) / 188);
1062                 if (is_input) {
1063                         u32     tmp;
1064
1065                         addr |= 1 << 31;
1066                         stream->c_usecs = stream->usecs;
1067                         stream->usecs = HS_USECS_ISO (1);
1068                         stream->raw_mask = 1;
1069
1070                         /* c-mask as specified in USB 2.0 11.18.4 3.c */
1071                         tmp = (1 << (hs_transfers + 2)) - 1;
1072                         stream->raw_mask |= tmp << (8 + 2);
1073                 } else
1074                         stream->raw_mask = smask_out [hs_transfers - 1];
1075                 bandwidth = stream->usecs + stream->c_usecs;
1076                 bandwidth /= 1 << (interval + 2);
1077
1078                 /* stream->splits gets created from raw_mask later */
1079                 stream->address = cpu_to_hc32(ehci, addr);
1080         }
1081         stream->bandwidth = bandwidth;
1082
1083         stream->udev = dev;
1084
1085         stream->bEndpointAddress = is_input | epnum;
1086         stream->interval = interval;
1087         stream->maxp = maxp;
1088 }
1089
1090 static void
1091 iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
1092 {
1093         stream->refcount--;
1094
1095         /* free whenever just a dev->ep reference remains.
1096          * not like a QH -- no persistent state (toggle, halt)
1097          */
1098         if (stream->refcount == 1) {
1099                 int             is_in;
1100
1101                 // BUG_ON (!list_empty(&stream->td_list));
1102
1103                 while (!list_empty (&stream->free_list)) {
1104                         struct list_head        *entry;
1105
1106                         entry = stream->free_list.next;
1107                         list_del (entry);
1108
1109                         /* knows about ITD vs SITD */
1110                         if (stream->highspeed) {
1111                                 struct ehci_itd         *itd;
1112
1113                                 itd = list_entry (entry, struct ehci_itd,
1114                                                 itd_list);
1115                                 dma_pool_free (ehci->itd_pool, itd,
1116                                                 itd->itd_dma);
1117                         } else {
1118                                 struct ehci_sitd        *sitd;
1119
1120                                 sitd = list_entry (entry, struct ehci_sitd,
1121                                                 sitd_list);
1122                                 dma_pool_free (ehci->sitd_pool, sitd,
1123                                                 sitd->sitd_dma);
1124                         }
1125                 }
1126
1127                 is_in = (stream->bEndpointAddress & USB_DIR_IN) ? 0x10 : 0;
1128                 stream->bEndpointAddress &= 0x0f;
1129                 stream->ep->hcpriv = NULL;
1130
1131                 if (stream->rescheduled) {
1132                         ehci_info (ehci, "ep%d%s-iso rescheduled "
1133                                 "%lu times in %lu seconds\n",
1134                                 stream->bEndpointAddress, is_in ? "in" : "out",
1135                                 stream->rescheduled,
1136                                 ((jiffies - stream->start)/HZ)
1137                                 );
1138                 }
1139
1140                 kfree(stream);
1141         }
1142 }
1143
1144 static inline struct ehci_iso_stream *
1145 iso_stream_get (struct ehci_iso_stream *stream)
1146 {
1147         if (likely (stream != NULL))
1148                 stream->refcount++;
1149         return stream;
1150 }
1151
1152 static struct ehci_iso_stream *
1153 iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
1154 {
1155         unsigned                epnum;
1156         struct ehci_iso_stream  *stream;
1157         struct usb_host_endpoint *ep;
1158         unsigned long           flags;
1159
1160         epnum = usb_pipeendpoint (urb->pipe);
1161         if (usb_pipein(urb->pipe))
1162                 ep = urb->dev->ep_in[epnum];
1163         else
1164                 ep = urb->dev->ep_out[epnum];
1165
1166         spin_lock_irqsave (&ehci->lock, flags);
1167         stream = ep->hcpriv;
1168
1169         if (unlikely (stream == NULL)) {
1170                 stream = iso_stream_alloc(GFP_ATOMIC);
1171                 if (likely (stream != NULL)) {
1172                         /* dev->ep owns the initial refcount */
1173                         ep->hcpriv = stream;
1174                         stream->ep = ep;
1175                         iso_stream_init(ehci, stream, urb->dev, urb->pipe,
1176                                         urb->interval);
1177                 }
1178
1179         /* if dev->ep [epnum] is a QH, info1.maxpacket is nonzero */
1180         } else if (unlikely (stream->hw_info1 != 0)) {
1181                 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
1182                         urb->dev->devpath, epnum,
1183                         usb_pipein(urb->pipe) ? "in" : "out");
1184                 stream = NULL;
1185         }
1186
1187         /* caller guarantees an eventual matching iso_stream_put */
1188         stream = iso_stream_get (stream);
1189
1190         spin_unlock_irqrestore (&ehci->lock, flags);
1191         return stream;
1192 }
1193
1194 /*-------------------------------------------------------------------------*/
1195
1196 /* ehci_iso_sched ops can be ITD-only or SITD-only */
1197
1198 static struct ehci_iso_sched *
1199 iso_sched_alloc (unsigned packets, gfp_t mem_flags)
1200 {
1201         struct ehci_iso_sched   *iso_sched;
1202         int                     size = sizeof *iso_sched;
1203
1204         size += packets * sizeof (struct ehci_iso_packet);
1205         iso_sched = kzalloc(size, mem_flags);
1206         if (likely (iso_sched != NULL)) {
1207                 INIT_LIST_HEAD (&iso_sched->td_list);
1208         }
1209         return iso_sched;
1210 }
1211
1212 static inline void
1213 itd_sched_init(
1214         struct ehci_hcd         *ehci,
1215         struct ehci_iso_sched   *iso_sched,
1216         struct ehci_iso_stream  *stream,
1217         struct urb              *urb
1218 )
1219 {
1220         unsigned        i;
1221         dma_addr_t      dma = urb->transfer_dma;
1222
1223         /* how many uframes are needed for these transfers */
1224         iso_sched->span = urb->number_of_packets * stream->interval;
1225
1226         /* figure out per-uframe itd fields that we'll need later
1227          * when we fit new itds into the schedule.
1228          */
1229         for (i = 0; i < urb->number_of_packets; i++) {
1230                 struct ehci_iso_packet  *uframe = &iso_sched->packet [i];
1231                 unsigned                length;
1232                 dma_addr_t              buf;
1233                 u32                     trans;
1234
1235                 length = urb->iso_frame_desc [i].length;
1236                 buf = dma + urb->iso_frame_desc [i].offset;
1237
1238                 trans = EHCI_ISOC_ACTIVE;
1239                 trans |= buf & 0x0fff;
1240                 if (unlikely (((i + 1) == urb->number_of_packets))
1241                                 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1242                         trans |= EHCI_ITD_IOC;
1243                 trans |= length << 16;
1244                 uframe->transaction = cpu_to_hc32(ehci, trans);
1245
1246                 /* might need to cross a buffer page within a uframe */
1247                 uframe->bufp = (buf & ~(u64)0x0fff);
1248                 buf += length;
1249                 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
1250                         uframe->cross = 1;
1251         }
1252 }
1253
1254 static void
1255 iso_sched_free (
1256         struct ehci_iso_stream  *stream,
1257         struct ehci_iso_sched   *iso_sched
1258 )
1259 {
1260         if (!iso_sched)
1261                 return;
1262         // caller must hold ehci->lock!
1263         list_splice (&iso_sched->td_list, &stream->free_list);
1264         kfree (iso_sched);
1265 }
1266
1267 static int
1268 itd_urb_transaction (
1269         struct ehci_iso_stream  *stream,
1270         struct ehci_hcd         *ehci,
1271         struct urb              *urb,
1272         gfp_t                   mem_flags
1273 )
1274 {
1275         struct ehci_itd         *itd;
1276         dma_addr_t              itd_dma;
1277         int                     i;
1278         unsigned                num_itds;
1279         struct ehci_iso_sched   *sched;
1280         unsigned long           flags;
1281
1282         sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1283         if (unlikely (sched == NULL))
1284                 return -ENOMEM;
1285
1286         itd_sched_init(ehci, sched, stream, urb);
1287
1288         if (urb->interval < 8)
1289                 num_itds = 1 + (sched->span + 7) / 8;
1290         else
1291                 num_itds = urb->number_of_packets;
1292
1293         /* allocate/init ITDs */
1294         spin_lock_irqsave (&ehci->lock, flags);
1295         for (i = 0; i < num_itds; i++) {
1296
1297                 /* free_list.next might be cache-hot ... but maybe
1298                  * the HC caches it too. avoid that issue for now.
1299                  */
1300
1301                 /* prefer previously-allocated itds */
1302                 if (likely (!list_empty(&stream->free_list))) {
1303                         itd = list_entry (stream->free_list.prev,
1304                                         struct ehci_itd, itd_list);
1305                         list_del (&itd->itd_list);
1306                         itd_dma = itd->itd_dma;
1307                 } else
1308                         itd = NULL;
1309
1310                 if (!itd) {
1311                         spin_unlock_irqrestore (&ehci->lock, flags);
1312                         itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
1313                                         &itd_dma);
1314                         spin_lock_irqsave (&ehci->lock, flags);
1315                 }
1316
1317                 if (unlikely (NULL == itd)) {
1318                         iso_sched_free (stream, sched);
1319                         spin_unlock_irqrestore (&ehci->lock, flags);
1320                         return -ENOMEM;
1321                 }
1322                 memset (itd, 0, sizeof *itd);
1323                 itd->itd_dma = itd_dma;
1324                 list_add (&itd->itd_list, &sched->td_list);
1325         }
1326         spin_unlock_irqrestore (&ehci->lock, flags);
1327
1328         /* temporarily store schedule info in hcpriv */
1329         urb->hcpriv = sched;
1330         urb->error_count = 0;
1331         return 0;
1332 }
1333
1334 /*-------------------------------------------------------------------------*/
1335
1336 static inline int
1337 itd_slot_ok (
1338         struct ehci_hcd         *ehci,
1339         u32                     mod,
1340         u32                     uframe,
1341         u8                      usecs,
1342         u32                     period
1343 )
1344 {
1345         uframe %= period;
1346         do {
1347                 /* can't commit more than 80% periodic == 100 usec */
1348                 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
1349                                 > (100 - usecs))
1350                         return 0;
1351
1352                 /* we know urb->interval is 2^N uframes */
1353                 uframe += period;
1354         } while (uframe < mod);
1355         return 1;
1356 }
1357
1358 static inline int
1359 sitd_slot_ok (
1360         struct ehci_hcd         *ehci,
1361         u32                     mod,
1362         struct ehci_iso_stream  *stream,
1363         u32                     uframe,
1364         struct ehci_iso_sched   *sched,
1365         u32                     period_uframes
1366 )
1367 {
1368         u32                     mask, tmp;
1369         u32                     frame, uf;
1370
1371         mask = stream->raw_mask << (uframe & 7);
1372
1373         /* for IN, don't wrap CSPLIT into the next frame */
1374         if (mask & ~0xffff)
1375                 return 0;
1376
1377         /* this multi-pass logic is simple, but performance may
1378          * suffer when the schedule data isn't cached.
1379          */
1380
1381         /* check bandwidth */
1382         uframe %= period_uframes;
1383         do {
1384                 u32             max_used;
1385
1386                 frame = uframe >> 3;
1387                 uf = uframe & 7;
1388
1389 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
1390                 /* The tt's fullspeed bus bandwidth must be available.
1391                  * tt_available scheduling guarantees 10+% for control/bulk.
1392                  */
1393                 if (!tt_available (ehci, period_uframes << 3,
1394                                 stream->udev, frame, uf, stream->tt_usecs))
1395                         return 0;
1396 #else
1397                 /* tt must be idle for start(s), any gap, and csplit.
1398                  * assume scheduling slop leaves 10+% for control/bulk.
1399                  */
1400                 if (!tt_no_collision (ehci, period_uframes << 3,
1401                                 stream->udev, frame, mask))
1402                         return 0;
1403 #endif
1404
1405                 /* check starts (OUT uses more than one) */
1406                 max_used = 100 - stream->usecs;
1407                 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
1408                         if (periodic_usecs (ehci, frame, uf) > max_used)
1409                                 return 0;
1410                 }
1411
1412                 /* for IN, check CSPLIT */
1413                 if (stream->c_usecs) {
1414                         uf = uframe & 7;
1415                         max_used = 100 - stream->c_usecs;
1416                         do {
1417                                 tmp = 1 << uf;
1418                                 tmp <<= 8;
1419                                 if ((stream->raw_mask & tmp) == 0)
1420                                         continue;
1421                                 if (periodic_usecs (ehci, frame, uf)
1422                                                 > max_used)
1423                                         return 0;
1424                         } while (++uf < 8);
1425                 }
1426
1427                 /* we know urb->interval is 2^N uframes */
1428                 uframe += period_uframes;
1429         } while (uframe < mod);
1430
1431         stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7));
1432         return 1;
1433 }
1434
1435 /*
1436  * This scheduler plans almost as far into the future as it has actual
1437  * periodic schedule slots.  (Affected by TUNE_FLS, which defaults to
1438  * "as small as possible" to be cache-friendlier.)  That limits the size
1439  * transfers you can stream reliably; avoid more than 64 msec per urb.
1440  * Also avoid queue depths of less than ehci's worst irq latency (affected
1441  * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1442  * and other factors); or more than about 230 msec total (for portability,
1443  * given EHCI_TUNE_FLS and the slop).  Or, write a smarter scheduler!
1444  */
1445
1446 #define SCHEDULE_SLOP   10      /* frames */
1447
1448 static int
1449 iso_stream_schedule (
1450         struct ehci_hcd         *ehci,
1451         struct urb              *urb,
1452         struct ehci_iso_stream  *stream
1453 )
1454 {
1455         u32                     now, start, max, period;
1456         int                     status;
1457         unsigned                mod = ehci->periodic_size << 3;
1458         struct ehci_iso_sched   *sched = urb->hcpriv;
1459
1460         if (sched->span > (mod - 8 * SCHEDULE_SLOP)) {
1461                 ehci_dbg (ehci, "iso request %p too long\n", urb);
1462                 status = -EFBIG;
1463                 goto fail;
1464         }
1465
1466         if ((stream->depth + sched->span) > mod) {
1467                 ehci_dbg (ehci, "request %p would overflow (%d+%d>%d)\n",
1468                         urb, stream->depth, sched->span, mod);
1469                 status = -EFBIG;
1470                 goto fail;
1471         }
1472
1473         now = ehci_readl(ehci, &ehci->regs->frame_index) % mod;
1474
1475         /* when's the last uframe this urb could start? */
1476         max = now + mod;
1477
1478         /* typical case: reuse current schedule. stream is still active,
1479          * and no gaps from host falling behind (irq delays etc)
1480          */
1481         if (likely (!list_empty (&stream->td_list))) {
1482                 start = stream->next_uframe;
1483                 if (start < now)
1484                         start += mod;
1485                 if (likely ((start + sched->span) < max))
1486                         goto ready;
1487                 /* else fell behind; someday, try to reschedule */
1488                 status = -EL2NSYNC;
1489                 goto fail;
1490         }
1491
1492         /* need to schedule; when's the next (u)frame we could start?
1493          * this is bigger than ehci->i_thresh allows; scheduling itself
1494          * isn't free, the slop should handle reasonably slow cpus.  it
1495          * can also help high bandwidth if the dma and irq loads don't
1496          * jump until after the queue is primed.
1497          */
1498         start = SCHEDULE_SLOP * 8 + (now & ~0x07);
1499         start %= mod;
1500         stream->next_uframe = start;
1501
1502         /* NOTE:  assumes URB_ISO_ASAP, to limit complexity/bugs */
1503
1504         period = urb->interval;
1505         if (!stream->highspeed)
1506                 period <<= 3;
1507
1508         /* find a uframe slot with enough bandwidth */
1509         for (; start < (stream->next_uframe + period); start++) {
1510                 int             enough_space;
1511
1512                 /* check schedule: enough space? */
1513                 if (stream->highspeed)
1514                         enough_space = itd_slot_ok (ehci, mod, start,
1515                                         stream->usecs, period);
1516                 else {
1517                         if ((start % 8) >= 6)
1518                                 continue;
1519                         enough_space = sitd_slot_ok (ehci, mod, stream,
1520                                         start, sched, period);
1521                 }
1522
1523                 /* schedule it here if there's enough bandwidth */
1524                 if (enough_space) {
1525                         stream->next_uframe = start % mod;
1526                         goto ready;
1527                 }
1528         }
1529
1530         /* no room in the schedule */
1531         ehci_dbg (ehci, "iso %ssched full %p (now %d max %d)\n",
1532                 list_empty (&stream->td_list) ? "" : "re",
1533                 urb, now, max);
1534         status = -ENOSPC;
1535
1536 fail:
1537         iso_sched_free (stream, sched);
1538         urb->hcpriv = NULL;
1539         return status;
1540
1541 ready:
1542         /* report high speed start in uframes; full speed, in frames */
1543         urb->start_frame = stream->next_uframe;
1544         if (!stream->highspeed)
1545                 urb->start_frame >>= 3;
1546         return 0;
1547 }
1548
1549 /*-------------------------------------------------------------------------*/
1550
1551 static inline void
1552 itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream,
1553                 struct ehci_itd *itd)
1554 {
1555         int i;
1556
1557         /* it's been recently zeroed */
1558         itd->hw_next = EHCI_LIST_END(ehci);
1559         itd->hw_bufp [0] = stream->buf0;
1560         itd->hw_bufp [1] = stream->buf1;
1561         itd->hw_bufp [2] = stream->buf2;
1562
1563         for (i = 0; i < 8; i++)
1564                 itd->index[i] = -1;
1565
1566         /* All other fields are filled when scheduling */
1567 }
1568
1569 static inline void
1570 itd_patch(
1571         struct ehci_hcd         *ehci,
1572         struct ehci_itd         *itd,
1573         struct ehci_iso_sched   *iso_sched,
1574         unsigned                index,
1575         u16                     uframe
1576 )
1577 {
1578         struct ehci_iso_packet  *uf = &iso_sched->packet [index];
1579         unsigned                pg = itd->pg;
1580
1581         // BUG_ON (pg == 6 && uf->cross);
1582
1583         uframe &= 0x07;
1584         itd->index [uframe] = index;
1585
1586         itd->hw_transaction[uframe] = uf->transaction;
1587         itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12);
1588         itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0);
1589         itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32));
1590
1591         /* iso_frame_desc[].offset must be strictly increasing */
1592         if (unlikely (uf->cross)) {
1593                 u64     bufp = uf->bufp + 4096;
1594
1595                 itd->pg = ++pg;
1596                 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0);
1597                 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32));
1598         }
1599 }
1600
1601 static inline void
1602 itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1603 {
1604         /* always prepend ITD/SITD ... only QH tree is order-sensitive */
1605         itd->itd_next = ehci->pshadow [frame];
1606         itd->hw_next = ehci->periodic [frame];
1607         ehci->pshadow [frame].itd = itd;
1608         itd->frame = frame;
1609         wmb ();
1610         ehci->periodic[frame] = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
1611 }
1612
1613 /* fit urb's itds into the selected schedule slot; activate as needed */
1614 static int
1615 itd_link_urb (
1616         struct ehci_hcd         *ehci,
1617         struct urb              *urb,
1618         unsigned                mod,
1619         struct ehci_iso_stream  *stream
1620 )
1621 {
1622         int                     packet;
1623         unsigned                next_uframe, uframe, frame;
1624         struct ehci_iso_sched   *iso_sched = urb->hcpriv;
1625         struct ehci_itd         *itd;
1626
1627         next_uframe = stream->next_uframe % mod;
1628
1629         if (unlikely (list_empty(&stream->td_list))) {
1630                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1631                                 += stream->bandwidth;
1632                 ehci_vdbg (ehci,
1633                         "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1634                         urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1635                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1636                         urb->interval,
1637                         next_uframe >> 3, next_uframe & 0x7);
1638                 stream->start = jiffies;
1639         }
1640         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1641
1642         /* fill iTDs uframe by uframe */
1643         for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1644                 if (itd == NULL) {
1645                         /* ASSERT:  we have all necessary itds */
1646                         // BUG_ON (list_empty (&iso_sched->td_list));
1647
1648                         /* ASSERT:  no itds for this endpoint in this uframe */
1649
1650                         itd = list_entry (iso_sched->td_list.next,
1651                                         struct ehci_itd, itd_list);
1652                         list_move_tail (&itd->itd_list, &stream->td_list);
1653                         itd->stream = iso_stream_get (stream);
1654                         itd->urb = usb_get_urb (urb);
1655                         itd_init (ehci, stream, itd);
1656                 }
1657
1658                 uframe = next_uframe & 0x07;
1659                 frame = next_uframe >> 3;
1660
1661                 itd->usecs [uframe] = stream->usecs;
1662                 itd_patch(ehci, itd, iso_sched, packet, uframe);
1663
1664                 next_uframe += stream->interval;
1665                 stream->depth += stream->interval;
1666                 next_uframe %= mod;
1667                 packet++;
1668
1669                 /* link completed itds into the schedule */
1670                 if (((next_uframe >> 3) != frame)
1671                                 || packet == urb->number_of_packets) {
1672                         itd_link (ehci, frame % ehci->periodic_size, itd);
1673                         itd = NULL;
1674                 }
1675         }
1676         stream->next_uframe = next_uframe;
1677
1678         /* don't need that schedule data any more */
1679         iso_sched_free (stream, iso_sched);
1680         urb->hcpriv = NULL;
1681
1682         timer_action (ehci, TIMER_IO_WATCHDOG);
1683         if (unlikely (!ehci->periodic_sched++))
1684                 return enable_periodic (ehci);
1685         return 0;
1686 }
1687
1688 #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1689
1690 static unsigned
1691 itd_complete (
1692         struct ehci_hcd *ehci,
1693         struct ehci_itd *itd
1694 ) {
1695         struct urb                              *urb = itd->urb;
1696         struct usb_iso_packet_descriptor        *desc;
1697         u32                                     t;
1698         unsigned                                uframe;
1699         int                                     urb_index = -1;
1700         struct ehci_iso_stream                  *stream = itd->stream;
1701         struct usb_device                       *dev;
1702
1703         /* for each uframe with a packet */
1704         for (uframe = 0; uframe < 8; uframe++) {
1705                 if (likely (itd->index[uframe] == -1))
1706                         continue;
1707                 urb_index = itd->index[uframe];
1708                 desc = &urb->iso_frame_desc [urb_index];
1709
1710                 t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]);
1711                 itd->hw_transaction [uframe] = 0;
1712                 stream->depth -= stream->interval;
1713
1714                 /* report transfer status */
1715                 if (unlikely (t & ISO_ERRS)) {
1716                         urb->error_count++;
1717                         if (t & EHCI_ISOC_BUF_ERR)
1718                                 desc->status = usb_pipein (urb->pipe)
1719                                         ? -ENOSR  /* hc couldn't read */
1720                                         : -ECOMM; /* hc couldn't write */
1721                         else if (t & EHCI_ISOC_BABBLE)
1722                                 desc->status = -EOVERFLOW;
1723                         else /* (t & EHCI_ISOC_XACTERR) */
1724                                 desc->status = -EPROTO;
1725
1726                         /* HC need not update length with this error */
1727                         if (!(t & EHCI_ISOC_BABBLE))
1728                                 desc->actual_length = EHCI_ITD_LENGTH (t);
1729                 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1730                         desc->status = 0;
1731                         desc->actual_length = EHCI_ITD_LENGTH (t);
1732                 }
1733         }
1734
1735         usb_put_urb (urb);
1736         itd->urb = NULL;
1737         itd->stream = NULL;
1738         list_move (&itd->itd_list, &stream->free_list);
1739         iso_stream_put (ehci, stream);
1740
1741         /* handle completion now? */
1742         if (likely ((urb_index + 1) != urb->number_of_packets))
1743                 return 0;
1744
1745         /* ASSERT: it's really the last itd for this urb
1746         list_for_each_entry (itd, &stream->td_list, itd_list)
1747                 BUG_ON (itd->urb == urb);
1748          */
1749
1750         /* give urb back to the driver ... can be out-of-order */
1751         dev = urb->dev;
1752         ehci_urb_done (ehci, urb);
1753         urb = NULL;
1754
1755         /* defer stopping schedule; completion can submit */
1756         ehci->periodic_sched--;
1757         if (unlikely (!ehci->periodic_sched))
1758                 (void) disable_periodic (ehci);
1759         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1760
1761         if (unlikely (list_empty (&stream->td_list))) {
1762                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1763                                 -= stream->bandwidth;
1764                 ehci_vdbg (ehci,
1765                         "deschedule devp %s ep%d%s-iso\n",
1766                         dev->devpath, stream->bEndpointAddress & 0x0f,
1767                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1768         }
1769         iso_stream_put (ehci, stream);
1770
1771         return 1;
1772 }
1773
1774 /*-------------------------------------------------------------------------*/
1775
1776 static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
1777         gfp_t mem_flags)
1778 {
1779         int                     status = -EINVAL;
1780         unsigned long           flags;
1781         struct ehci_iso_stream  *stream;
1782
1783         /* Get iso_stream head */
1784         stream = iso_stream_find (ehci, urb);
1785         if (unlikely (stream == NULL)) {
1786                 ehci_dbg (ehci, "can't get iso stream\n");
1787                 return -ENOMEM;
1788         }
1789         if (unlikely (urb->interval != stream->interval)) {
1790                 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1791                         stream->interval, urb->interval);
1792                 goto done;
1793         }
1794
1795 #ifdef EHCI_URB_TRACE
1796         ehci_dbg (ehci,
1797                 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
1798                 __FUNCTION__, urb->dev->devpath, urb,
1799                 usb_pipeendpoint (urb->pipe),
1800                 usb_pipein (urb->pipe) ? "in" : "out",
1801                 urb->transfer_buffer_length,
1802                 urb->number_of_packets, urb->interval,
1803                 stream);
1804 #endif
1805
1806         /* allocate ITDs w/o locking anything */
1807         status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1808         if (unlikely (status < 0)) {
1809                 ehci_dbg (ehci, "can't init itds\n");
1810                 goto done;
1811         }
1812
1813         /* schedule ... need to lock */
1814         spin_lock_irqsave (&ehci->lock, flags);
1815         if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
1816                                &ehci_to_hcd(ehci)->flags)))
1817                 status = -ESHUTDOWN;
1818         else
1819                 status = iso_stream_schedule (ehci, urb, stream);
1820         if (likely (status == 0))
1821                 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1822         spin_unlock_irqrestore (&ehci->lock, flags);
1823
1824 done:
1825         if (unlikely (status < 0))
1826                 iso_stream_put (ehci, stream);
1827         return status;
1828 }
1829
1830 #ifdef CONFIG_USB_EHCI_SPLIT_ISO
1831
1832 /*-------------------------------------------------------------------------*/
1833
1834 /*
1835  * "Split ISO TDs" ... used for USB 1.1 devices going through the
1836  * TTs in USB 2.0 hubs.  These need microframe scheduling.
1837  */
1838
1839 static inline void
1840 sitd_sched_init(
1841         struct ehci_hcd         *ehci,
1842         struct ehci_iso_sched   *iso_sched,
1843         struct ehci_iso_stream  *stream,
1844         struct urb              *urb
1845 )
1846 {
1847         unsigned        i;
1848         dma_addr_t      dma = urb->transfer_dma;
1849
1850         /* how many frames are needed for these transfers */
1851         iso_sched->span = urb->number_of_packets * stream->interval;
1852
1853         /* figure out per-frame sitd fields that we'll need later
1854          * when we fit new sitds into the schedule.
1855          */
1856         for (i = 0; i < urb->number_of_packets; i++) {
1857                 struct ehci_iso_packet  *packet = &iso_sched->packet [i];
1858                 unsigned                length;
1859                 dma_addr_t              buf;
1860                 u32                     trans;
1861
1862                 length = urb->iso_frame_desc [i].length & 0x03ff;
1863                 buf = dma + urb->iso_frame_desc [i].offset;
1864
1865                 trans = SITD_STS_ACTIVE;
1866                 if (((i + 1) == urb->number_of_packets)
1867                                 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1868                         trans |= SITD_IOC;
1869                 trans |= length << 16;
1870                 packet->transaction = cpu_to_hc32(ehci, trans);
1871
1872                 /* might need to cross a buffer page within a td */
1873                 packet->bufp = buf;
1874                 packet->buf1 = (buf + length) & ~0x0fff;
1875                 if (packet->buf1 != (buf & ~(u64)0x0fff))
1876                         packet->cross = 1;
1877
1878                 /* OUT uses multiple start-splits */
1879                 if (stream->bEndpointAddress & USB_DIR_IN)
1880                         continue;
1881                 length = (length + 187) / 188;
1882                 if (length > 1) /* BEGIN vs ALL */
1883                         length |= 1 << 3;
1884                 packet->buf1 |= length;
1885         }
1886 }
1887
1888 static int
1889 sitd_urb_transaction (
1890         struct ehci_iso_stream  *stream,
1891         struct ehci_hcd         *ehci,
1892         struct urb              *urb,
1893         gfp_t                   mem_flags
1894 )
1895 {
1896         struct ehci_sitd        *sitd;
1897         dma_addr_t              sitd_dma;
1898         int                     i;
1899         struct ehci_iso_sched   *iso_sched;
1900         unsigned long           flags;
1901
1902         iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1903         if (iso_sched == NULL)
1904                 return -ENOMEM;
1905
1906         sitd_sched_init(ehci, iso_sched, stream, urb);
1907
1908         /* allocate/init sITDs */
1909         spin_lock_irqsave (&ehci->lock, flags);
1910         for (i = 0; i < urb->number_of_packets; i++) {
1911
1912                 /* NOTE:  for now, we don't try to handle wraparound cases
1913                  * for IN (using sitd->hw_backpointer, like a FSTN), which
1914                  * means we never need two sitds for full speed packets.
1915                  */
1916
1917                 /* free_list.next might be cache-hot ... but maybe
1918                  * the HC caches it too. avoid that issue for now.
1919                  */
1920
1921                 /* prefer previously-allocated sitds */
1922                 if (!list_empty(&stream->free_list)) {
1923                         sitd = list_entry (stream->free_list.prev,
1924                                          struct ehci_sitd, sitd_list);
1925                         list_del (&sitd->sitd_list);
1926                         sitd_dma = sitd->sitd_dma;
1927                 } else
1928                         sitd = NULL;
1929
1930                 if (!sitd) {
1931                         spin_unlock_irqrestore (&ehci->lock, flags);
1932                         sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
1933                                         &sitd_dma);
1934                         spin_lock_irqsave (&ehci->lock, flags);
1935                 }
1936
1937                 if (!sitd) {
1938                         iso_sched_free (stream, iso_sched);
1939                         spin_unlock_irqrestore (&ehci->lock, flags);
1940                         return -ENOMEM;
1941                 }
1942                 memset (sitd, 0, sizeof *sitd);
1943                 sitd->sitd_dma = sitd_dma;
1944                 list_add (&sitd->sitd_list, &iso_sched->td_list);
1945         }
1946
1947         /* temporarily store schedule info in hcpriv */
1948         urb->hcpriv = iso_sched;
1949         urb->error_count = 0;
1950
1951         spin_unlock_irqrestore (&ehci->lock, flags);
1952         return 0;
1953 }
1954
1955 /*-------------------------------------------------------------------------*/
1956
1957 static inline void
1958 sitd_patch(
1959         struct ehci_hcd         *ehci,
1960         struct ehci_iso_stream  *stream,
1961         struct ehci_sitd        *sitd,
1962         struct ehci_iso_sched   *iso_sched,
1963         unsigned                index
1964 )
1965 {
1966         struct ehci_iso_packet  *uf = &iso_sched->packet [index];
1967         u64                     bufp = uf->bufp;
1968
1969         sitd->hw_next = EHCI_LIST_END(ehci);
1970         sitd->hw_fullspeed_ep = stream->address;
1971         sitd->hw_uframe = stream->splits;
1972         sitd->hw_results = uf->transaction;
1973         sitd->hw_backpointer = EHCI_LIST_END(ehci);
1974
1975         bufp = uf->bufp;
1976         sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp);
1977         sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32);
1978
1979         sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1);
1980         if (uf->cross)
1981                 bufp += 4096;
1982         sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32);
1983         sitd->index = index;
1984 }
1985
1986 static inline void
1987 sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
1988 {
1989         /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
1990         sitd->sitd_next = ehci->pshadow [frame];
1991         sitd->hw_next = ehci->periodic [frame];
1992         ehci->pshadow [frame].sitd = sitd;
1993         sitd->frame = frame;
1994         wmb ();
1995         ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD);
1996 }
1997
1998 /* fit urb's sitds into the selected schedule slot; activate as needed */
1999 static int
2000 sitd_link_urb (
2001         struct ehci_hcd         *ehci,
2002         struct urb              *urb,
2003         unsigned                mod,
2004         struct ehci_iso_stream  *stream
2005 )
2006 {
2007         int                     packet;
2008         unsigned                next_uframe;
2009         struct ehci_iso_sched   *sched = urb->hcpriv;
2010         struct ehci_sitd        *sitd;
2011
2012         next_uframe = stream->next_uframe;
2013
2014         if (list_empty(&stream->td_list)) {
2015                 /* usbfs ignores TT bandwidth */
2016                 ehci_to_hcd(ehci)->self.bandwidth_allocated
2017                                 += stream->bandwidth;
2018                 ehci_vdbg (ehci,
2019                         "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
2020                         urb->dev->devpath, stream->bEndpointAddress & 0x0f,
2021                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
2022                         (next_uframe >> 3) % ehci->periodic_size,
2023                         stream->interval, hc32_to_cpu(ehci, stream->splits));
2024                 stream->start = jiffies;
2025         }
2026         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
2027
2028         /* fill sITDs frame by frame */
2029         for (packet = 0, sitd = NULL;
2030                         packet < urb->number_of_packets;
2031                         packet++) {
2032
2033                 /* ASSERT:  we have all necessary sitds */
2034                 BUG_ON (list_empty (&sched->td_list));
2035
2036                 /* ASSERT:  no itds for this endpoint in this frame */
2037
2038                 sitd = list_entry (sched->td_list.next,
2039                                 struct ehci_sitd, sitd_list);
2040                 list_move_tail (&sitd->sitd_list, &stream->td_list);
2041                 sitd->stream = iso_stream_get (stream);
2042                 sitd->urb = usb_get_urb (urb);
2043
2044                 sitd_patch(ehci, stream, sitd, sched, packet);
2045                 sitd_link (ehci, (next_uframe >> 3) % ehci->periodic_size,
2046                                 sitd);
2047
2048                 next_uframe += stream->interval << 3;
2049                 stream->depth += stream->interval << 3;
2050         }
2051         stream->next_uframe = next_uframe % mod;
2052
2053         /* don't need that schedule data any more */
2054         iso_sched_free (stream, sched);
2055         urb->hcpriv = NULL;
2056
2057         timer_action (ehci, TIMER_IO_WATCHDOG);
2058         if (!ehci->periodic_sched++)
2059                 return enable_periodic (ehci);
2060         return 0;
2061 }
2062
2063 /*-------------------------------------------------------------------------*/
2064
2065 #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
2066                                 | SITD_STS_XACT | SITD_STS_MMF)
2067
2068 static unsigned
2069 sitd_complete (
2070         struct ehci_hcd         *ehci,
2071         struct ehci_sitd        *sitd
2072 ) {
2073         struct urb                              *urb = sitd->urb;
2074         struct usb_iso_packet_descriptor        *desc;
2075         u32                                     t;
2076         int                                     urb_index = -1;
2077         struct ehci_iso_stream                  *stream = sitd->stream;
2078         struct usb_device                       *dev;
2079
2080         urb_index = sitd->index;
2081         desc = &urb->iso_frame_desc [urb_index];
2082         t = hc32_to_cpup(ehci, &sitd->hw_results);
2083
2084         /* report transfer status */
2085         if (t & SITD_ERRS) {
2086                 urb->error_count++;
2087                 if (t & SITD_STS_DBE)
2088                         desc->status = usb_pipein (urb->pipe)
2089                                 ? -ENOSR  /* hc couldn't read */
2090                                 : -ECOMM; /* hc couldn't write */
2091                 else if (t & SITD_STS_BABBLE)
2092                         desc->status = -EOVERFLOW;
2093                 else /* XACT, MMF, etc */
2094                         desc->status = -EPROTO;
2095         } else {
2096                 desc->status = 0;
2097                 desc->actual_length = desc->length - SITD_LENGTH (t);
2098         }
2099
2100         usb_put_urb (urb);
2101         sitd->urb = NULL;
2102         sitd->stream = NULL;
2103         list_move (&sitd->sitd_list, &stream->free_list);
2104         stream->depth -= stream->interval << 3;
2105         iso_stream_put (ehci, stream);
2106
2107         /* handle completion now? */
2108         if ((urb_index + 1) != urb->number_of_packets)
2109                 return 0;
2110
2111         /* ASSERT: it's really the last sitd for this urb
2112         list_for_each_entry (sitd, &stream->td_list, sitd_list)
2113                 BUG_ON (sitd->urb == urb);
2114          */
2115
2116         /* give urb back to the driver */
2117         dev = urb->dev;
2118         ehci_urb_done (ehci, urb);
2119         urb = NULL;
2120
2121         /* defer stopping schedule; completion can submit */
2122         ehci->periodic_sched--;
2123         if (!ehci->periodic_sched)
2124                 (void) disable_periodic (ehci);
2125         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
2126
2127         if (list_empty (&stream->td_list)) {
2128                 ehci_to_hcd(ehci)->self.bandwidth_allocated
2129                                 -= stream->bandwidth;
2130                 ehci_vdbg (ehci,
2131                         "deschedule devp %s ep%d%s-iso\n",
2132                         dev->devpath, stream->bEndpointAddress & 0x0f,
2133                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
2134         }
2135         iso_stream_put (ehci, stream);
2136
2137         return 1;
2138 }
2139
2140
2141 static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
2142         gfp_t mem_flags)
2143 {
2144         int                     status = -EINVAL;
2145         unsigned long           flags;
2146         struct ehci_iso_stream  *stream;
2147
2148         /* Get iso_stream head */
2149         stream = iso_stream_find (ehci, urb);
2150         if (stream == NULL) {
2151                 ehci_dbg (ehci, "can't get iso stream\n");
2152                 return -ENOMEM;
2153         }
2154         if (urb->interval != stream->interval) {
2155                 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
2156                         stream->interval, urb->interval);
2157                 goto done;
2158         }
2159
2160 #ifdef EHCI_URB_TRACE
2161         ehci_dbg (ehci,
2162                 "submit %p dev%s ep%d%s-iso len %d\n",
2163                 urb, urb->dev->devpath,
2164                 usb_pipeendpoint (urb->pipe),
2165                 usb_pipein (urb->pipe) ? "in" : "out",
2166                 urb->transfer_buffer_length);
2167 #endif
2168
2169         /* allocate SITDs */
2170         status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
2171         if (status < 0) {
2172                 ehci_dbg (ehci, "can't init sitds\n");
2173                 goto done;
2174         }
2175
2176         /* schedule ... need to lock */
2177         spin_lock_irqsave (&ehci->lock, flags);
2178         if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
2179                                &ehci_to_hcd(ehci)->flags)))
2180                 status = -ESHUTDOWN;
2181         else
2182                 status = iso_stream_schedule (ehci, urb, stream);
2183         if (status == 0)
2184                 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
2185         spin_unlock_irqrestore (&ehci->lock, flags);
2186
2187 done:
2188         if (status < 0)
2189                 iso_stream_put (ehci, stream);
2190         return status;
2191 }
2192
2193 #else
2194
2195 static inline int
2196 sitd_submit (struct ehci_hcd *ehci, struct urb *urb, gfp_t mem_flags)
2197 {
2198         ehci_dbg (ehci, "split iso support is disabled\n");
2199         return -ENOSYS;
2200 }
2201
2202 static inline unsigned
2203 sitd_complete (
2204         struct ehci_hcd         *ehci,
2205         struct ehci_sitd        *sitd
2206 ) {
2207         ehci_err (ehci, "sitd_complete %p?\n", sitd);
2208         return 0;
2209 }
2210
2211 #endif /* USB_EHCI_SPLIT_ISO */
2212
2213 /*-------------------------------------------------------------------------*/
2214
2215 static void
2216 scan_periodic (struct ehci_hcd *ehci)
2217 {
2218         unsigned        frame, clock, now_uframe, mod;
2219         unsigned        modified;
2220
2221         mod = ehci->periodic_size << 3;
2222
2223         /*
2224          * When running, scan from last scan point up to "now"
2225          * else clean up by scanning everything that's left.
2226          * Touches as few pages as possible:  cache-friendly.
2227          */
2228         now_uframe = ehci->next_uframe;
2229         if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
2230                 clock = ehci_readl(ehci, &ehci->regs->frame_index);
2231         else
2232                 clock = now_uframe + mod - 1;
2233         clock %= mod;
2234
2235         for (;;) {
2236                 union ehci_shadow       q, *q_p;
2237                 __hc32                  type, *hw_p;
2238                 unsigned                uframes;
2239
2240                 /* don't scan past the live uframe */
2241                 frame = now_uframe >> 3;
2242                 if (frame == (clock >> 3))
2243                         uframes = now_uframe & 0x07;
2244                 else {
2245                         /* safe to scan the whole frame at once */
2246                         now_uframe |= 0x07;
2247                         uframes = 8;
2248                 }
2249
2250 restart:
2251                 /* scan each element in frame's queue for completions */
2252                 q_p = &ehci->pshadow [frame];
2253                 hw_p = &ehci->periodic [frame];
2254                 q.ptr = q_p->ptr;
2255                 type = Q_NEXT_TYPE(ehci, *hw_p);
2256                 modified = 0;
2257
2258                 while (q.ptr != NULL) {
2259                         unsigned                uf;
2260                         union ehci_shadow       temp;
2261                         int                     live;
2262
2263                         live = HC_IS_RUNNING (ehci_to_hcd(ehci)->state);
2264                         switch (hc32_to_cpu(ehci, type)) {
2265                         case Q_TYPE_QH:
2266                                 /* handle any completions */
2267                                 temp.qh = qh_get (q.qh);
2268                                 type = Q_NEXT_TYPE(ehci, q.qh->hw_next);
2269                                 q = q.qh->qh_next;
2270                                 modified = qh_completions (ehci, temp.qh);
2271                                 if (unlikely (list_empty (&temp.qh->qtd_list)))
2272                                         intr_deschedule (ehci, temp.qh);
2273                                 qh_put (temp.qh);
2274                                 break;
2275                         case Q_TYPE_FSTN:
2276                                 /* for "save place" FSTNs, look at QH entries
2277                                  * in the previous frame for completions.
2278                                  */
2279                                 if (q.fstn->hw_prev != EHCI_LIST_END(ehci)) {
2280                                         dbg ("ignoring completions from FSTNs");
2281                                 }
2282                                 type = Q_NEXT_TYPE(ehci, q.fstn->hw_next);
2283                                 q = q.fstn->fstn_next;
2284                                 break;
2285                         case Q_TYPE_ITD:
2286                                 /* skip itds for later in the frame */
2287                                 rmb ();
2288                                 for (uf = live ? uframes : 8; uf < 8; uf++) {
2289                                         if (0 == (q.itd->hw_transaction [uf]
2290                                                         & ITD_ACTIVE(ehci)))
2291                                                 continue;
2292                                         q_p = &q.itd->itd_next;
2293                                         hw_p = &q.itd->hw_next;
2294                                         type = Q_NEXT_TYPE(ehci,
2295                                                         q.itd->hw_next);
2296                                         q = *q_p;
2297                                         break;
2298                                 }
2299                                 if (uf != 8)
2300                                         break;
2301
2302                                 /* this one's ready ... HC won't cache the
2303                                  * pointer for much longer, if at all.
2304                                  */
2305                                 *q_p = q.itd->itd_next;
2306                                 *hw_p = q.itd->hw_next;
2307                                 type = Q_NEXT_TYPE(ehci, q.itd->hw_next);
2308                                 wmb();
2309                                 modified = itd_complete (ehci, q.itd);
2310                                 q = *q_p;
2311                                 break;
2312                         case Q_TYPE_SITD:
2313                                 if ((q.sitd->hw_results & SITD_ACTIVE(ehci))
2314                                                 && live) {
2315                                         q_p = &q.sitd->sitd_next;
2316                                         hw_p = &q.sitd->hw_next;
2317                                         type = Q_NEXT_TYPE(ehci,
2318                                                         q.sitd->hw_next);
2319                                         q = *q_p;
2320                                         break;
2321                                 }
2322                                 *q_p = q.sitd->sitd_next;
2323                                 *hw_p = q.sitd->hw_next;
2324                                 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next);
2325                                 wmb();
2326                                 modified = sitd_complete (ehci, q.sitd);
2327                                 q = *q_p;
2328                                 break;
2329                         default:
2330                                 dbg ("corrupt type %d frame %d shadow %p",
2331                                         type, frame, q.ptr);
2332                                 // BUG ();
2333                                 q.ptr = NULL;
2334                         }
2335
2336                         /* assume completion callbacks modify the queue */
2337                         if (unlikely (modified))
2338                                 goto restart;
2339                 }
2340
2341                 /* stop when we catch up to the HC */
2342
2343                 // FIXME:  this assumes we won't get lapped when
2344                 // latencies climb; that should be rare, but...
2345                 // detect it, and just go all the way around.
2346                 // FLR might help detect this case, so long as latencies
2347                 // don't exceed periodic_size msec (default 1.024 sec).
2348
2349                 // FIXME:  likewise assumes HC doesn't halt mid-scan
2350
2351                 if (now_uframe == clock) {
2352                         unsigned        now;
2353
2354                         if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
2355                                 break;
2356                         ehci->next_uframe = now_uframe;
2357                         now = ehci_readl(ehci, &ehci->regs->frame_index) % mod;
2358                         if (now_uframe == now)
2359                                 break;
2360
2361                         /* rescan the rest of this frame, then ... */
2362                         clock = now;
2363                 } else {
2364                         now_uframe++;
2365                         now_uframe %= mod;
2366                 }
2367         }
2368 }