2 * Copyright (C) 2003 - 2006 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
30 * Source file for NIC routines to access the Phantom hardware
34 #include "netxen_nic.h"
35 #include "netxen_nic_hw.h"
36 #include "netxen_nic_phan_reg.h"
41 #define MASK(n) ((1ULL<<(n))-1)
42 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
43 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
44 #define MS_WIN(addr) (addr & 0x0ffc0000)
46 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
48 #define CRB_BLK(off) ((off >> 20) & 0x3f)
49 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
50 #define CRB_WINDOW_2M (0x130060)
51 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
52 #define CRB_INDIRECT_2M (0x1e0000UL)
54 #define CRB_WIN_LOCK_TIMEOUT 100000000
55 static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {
56 {{{0, 0, 0, 0} } }, /* 0: PCI */
57 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
58 {1, 0x0110000, 0x0120000, 0x130000},
59 {1, 0x0120000, 0x0122000, 0x124000},
60 {1, 0x0130000, 0x0132000, 0x126000},
61 {1, 0x0140000, 0x0142000, 0x128000},
62 {1, 0x0150000, 0x0152000, 0x12a000},
63 {1, 0x0160000, 0x0170000, 0x110000},
64 {1, 0x0170000, 0x0172000, 0x12e000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {1, 0x01e0000, 0x01e0800, 0x122000},
72 {0, 0x0000000, 0x0000000, 0x000000} } },
73 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
74 {{{0, 0, 0, 0} } }, /* 3: */
75 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
76 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
77 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
78 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
79 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {1, 0x08f0000, 0x08f2000, 0x172000} } },
95 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {1, 0x09f0000, 0x09f2000, 0x176000} } },
111 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
127 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
143 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
144 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
145 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
146 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
147 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
148 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
149 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
150 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
151 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
152 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
153 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
154 {{{0, 0, 0, 0} } }, /* 23: */
155 {{{0, 0, 0, 0} } }, /* 24: */
156 {{{0, 0, 0, 0} } }, /* 25: */
157 {{{0, 0, 0, 0} } }, /* 26: */
158 {{{0, 0, 0, 0} } }, /* 27: */
159 {{{0, 0, 0, 0} } }, /* 28: */
160 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
161 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
162 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
163 {{{0} } }, /* 32: PCI */
164 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
165 {1, 0x2110000, 0x2120000, 0x130000},
166 {1, 0x2120000, 0x2122000, 0x124000},
167 {1, 0x2130000, 0x2132000, 0x126000},
168 {1, 0x2140000, 0x2142000, 0x128000},
169 {1, 0x2150000, 0x2152000, 0x12a000},
170 {1, 0x2160000, 0x2170000, 0x110000},
171 {1, 0x2170000, 0x2172000, 0x12e000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000} } },
180 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
186 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
187 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
188 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
189 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
190 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
191 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
192 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
193 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
194 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
195 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
196 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
197 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
199 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
200 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
201 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
202 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
203 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
204 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
205 {{{0} } }, /* 59: I2C0 */
206 {{{0} } }, /* 60: I2C1 */
207 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
208 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
209 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
213 * top 12 bits of crb internal address (hub, agent)
215 static unsigned crb_hub_agt[64] =
218 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
219 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
220 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
222 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
223 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
224 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
225 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
226 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
227 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
228 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
229 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
230 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
231 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
232 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
233 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
234 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
235 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
236 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
237 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
238 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
239 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
240 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
241 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
242 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
243 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
245 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
246 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
248 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
250 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
251 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
257 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
259 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
260 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
261 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
262 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
263 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
264 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
265 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
266 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
267 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
268 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
270 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
272 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
273 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
275 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
276 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
277 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
283 /* PCI Windowing for DDR regions. */
285 #define ADDR_IN_RANGE(addr, low, high) \
286 (((addr) <= (high)) && ((addr) >= (low)))
288 #define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE
289 #define NETXEN_MIN_MTU 64
290 #define NETXEN_ETH_FCS_SIZE 4
291 #define NETXEN_ENET_HEADER_SIZE 14
292 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
293 #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
294 #define NETXEN_NIU_HDRSIZE (0x1 << 6)
295 #define NETXEN_NIU_TLRSIZE (0x1 << 5)
297 #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
298 #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
299 #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
300 #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
302 #define NETXEN_NIC_WINDOW_MARGIN 0x100000
304 int netxen_nic_set_mac(struct net_device *netdev, void *p)
306 struct netxen_adapter *adapter = netdev_priv(netdev);
307 struct sockaddr *addr = p;
309 if (netif_running(netdev))
312 if (!is_valid_ether_addr(addr->sa_data))
313 return -EADDRNOTAVAIL;
315 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
317 /* For P3, MAC addr is not set in NIU */
318 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
319 if (adapter->macaddr_set)
320 adapter->macaddr_set(adapter, addr->sa_data);
325 #define NETXEN_UNICAST_ADDR(port, index) \
326 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
327 #define NETXEN_MCAST_ADDR(port, index) \
328 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
329 #define MAC_HI(addr) \
330 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
331 #define MAC_LO(addr) \
332 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
335 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
338 u16 port = adapter->physical_port;
339 u8 *addr = adapter->netdev->dev_addr;
341 if (adapter->mc_enabled)
344 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
345 val |= (1UL << (28+port));
346 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
348 /* add broadcast addr to filter */
350 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
351 netxen_crb_writelit_adapter(adapter,
352 NETXEN_UNICAST_ADDR(port, 0)+4, val);
354 /* add station addr to filter */
356 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
358 netxen_crb_writelit_adapter(adapter,
359 NETXEN_UNICAST_ADDR(port, 1)+4, val);
361 adapter->mc_enabled = 1;
366 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
369 u16 port = adapter->physical_port;
370 u8 *addr = adapter->netdev->dev_addr;
372 if (!adapter->mc_enabled)
375 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
376 val &= ~(1UL << (28+port));
377 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
380 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
382 netxen_crb_writelit_adapter(adapter,
383 NETXEN_UNICAST_ADDR(port, 0)+4, val);
385 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
386 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
388 adapter->mc_enabled = 0;
393 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
397 u16 port = adapter->physical_port;
402 netxen_crb_writelit_adapter(adapter,
403 NETXEN_MCAST_ADDR(port, index), hi);
404 netxen_crb_writelit_adapter(adapter,
405 NETXEN_MCAST_ADDR(port, index)+4, lo);
410 void netxen_p2_nic_set_multi(struct net_device *netdev)
412 struct netxen_adapter *adapter = netdev_priv(netdev);
413 struct dev_mc_list *mc_ptr;
417 memset(null_addr, 0, 6);
419 if (netdev->flags & IFF_PROMISC) {
421 adapter->set_promisc(adapter,
422 NETXEN_NIU_PROMISC_MODE);
424 /* Full promiscuous mode */
425 netxen_nic_disable_mcast_filter(adapter);
430 if (netdev->mc_count == 0) {
431 adapter->set_promisc(adapter,
432 NETXEN_NIU_NON_PROMISC_MODE);
433 netxen_nic_disable_mcast_filter(adapter);
437 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
438 if (netdev->flags & IFF_ALLMULTI ||
439 netdev->mc_count > adapter->max_mc_count) {
440 netxen_nic_disable_mcast_filter(adapter);
444 netxen_nic_enable_mcast_filter(adapter);
446 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
447 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
449 if (index != netdev->mc_count)
450 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
451 netxen_nic_driver_name, netdev->name);
453 /* Clear out remaining addresses */
454 for (; index < adapter->max_mc_count; index++)
455 netxen_nic_set_mcast_addr(adapter, index, null_addr);
458 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
459 u8 *addr, nx_mac_list_t **add_list, nx_mac_list_t **del_list)
461 nx_mac_list_t *cur, *prev;
463 /* if in del_list, move it to adapter->mac_list */
464 for (cur = *del_list, prev = NULL; cur;) {
465 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
467 *del_list = cur->next;
469 prev->next = cur->next;
470 cur->next = adapter->mac_list;
471 adapter->mac_list = cur;
478 /* make sure to add each mac address only once */
479 for (cur = adapter->mac_list; cur; cur = cur->next) {
480 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
483 /* not in del_list, create new entry and add to add_list */
484 cur = kmalloc(sizeof(*cur), in_atomic()? GFP_ATOMIC : GFP_KERNEL);
486 printk(KERN_ERR "%s: cannot allocate memory. MAC filtering may"
487 "not work properly from now.\n", __func__);
491 memcpy(cur->mac_addr, addr, ETH_ALEN);
492 cur->next = *add_list;
498 netxen_send_cmd_descs(struct netxen_adapter *adapter,
499 struct cmd_desc_type0 *cmd_desc_arr, int nr_elements)
501 uint32_t i, producer;
502 struct netxen_cmd_buffer *pbuf;
503 struct cmd_desc_type0 *cmd_desc;
505 if (nr_elements > MAX_PENDING_DESC_BLOCK_SIZE || nr_elements == 0) {
506 printk(KERN_WARNING "%s: Too many command descriptors in a "
507 "request\n", __func__);
513 producer = adapter->cmd_producer;
515 cmd_desc = &cmd_desc_arr[i];
517 pbuf = &adapter->cmd_buf_arr[producer];
519 pbuf->total_length = 0;
522 pbuf->frag_count = 0;
525 /* adapter->ahw.cmd_desc_head[producer] = *cmd_desc; */
526 memcpy(&adapter->ahw.cmd_desc_head[producer],
527 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
529 producer = get_next_index(producer,
530 adapter->max_tx_desc_count);
533 } while (i != nr_elements);
535 adapter->cmd_producer = producer;
537 /* write producer index to start the xmit */
539 netxen_nic_update_cmd_producer(adapter, adapter->cmd_producer);
544 #define NIC_REQUEST 0x14
545 #define NETXEN_MAC_EVENT 0x1
547 static int nx_p3_sre_macaddr_change(struct net_device *dev,
548 u8 *addr, unsigned op)
550 struct netxen_adapter *adapter = (struct netxen_adapter *)dev->priv;
552 nx_mac_req_t mac_req;
555 memset(&req, 0, sizeof(nx_nic_req_t));
556 req.qhdr |= (NIC_REQUEST << 23);
557 req.req_hdr |= NETXEN_MAC_EVENT;
558 req.req_hdr |= ((u64)adapter->portnum << 16);
560 memcpy(&mac_req.mac_addr, addr, 6);
561 req.words[0] = cpu_to_le64(*(u64 *)&mac_req);
563 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
565 printk(KERN_ERR "ERROR. Could not send mac update\n");
572 void netxen_p3_nic_set_multi(struct net_device *netdev)
574 struct netxen_adapter *adapter = netdev_priv(netdev);
575 nx_mac_list_t *cur, *next, *del_list, *add_list = NULL;
576 struct dev_mc_list *mc_ptr;
577 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
579 adapter->set_promisc(adapter, NETXEN_NIU_PROMISC_MODE);
582 * Programming mac addresses will automaticly enabling L2 filtering.
583 * HW will replace timestamp with L2 conid when L2 filtering is
584 * enabled. This causes problem for LSA. Do not enabling L2 filtering
585 * until that problem is fixed.
587 if ((netdev->flags & IFF_PROMISC) ||
588 (netdev->mc_count > adapter->max_mc_count))
591 del_list = adapter->mac_list;
592 adapter->mac_list = NULL;
594 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &add_list, &del_list);
595 if (netdev->mc_count > 0) {
596 nx_p3_nic_add_mac(adapter, bcast_addr, &add_list, &del_list);
597 for (mc_ptr = netdev->mc_list; mc_ptr;
598 mc_ptr = mc_ptr->next) {
599 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr,
600 &add_list, &del_list);
603 for (cur = del_list; cur;) {
604 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_DEL);
609 for (cur = add_list; cur;) {
610 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_ADD);
612 cur->next = adapter->mac_list;
613 adapter->mac_list = cur;
618 #define NETXEN_CONFIG_INTR_COALESCE 3
621 * Send the interrupt coalescing parameter set by ethtool to the card.
623 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
628 memset(&req, 0, sizeof(nx_nic_req_t));
630 req.qhdr |= (NIC_REQUEST << 23);
631 req.req_hdr |= NETXEN_CONFIG_INTR_COALESCE;
632 req.req_hdr |= ((u64)adapter->portnum << 16);
634 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
636 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
638 printk(KERN_ERR "ERROR. Could not send "
639 "interrupt coalescing parameters\n");
646 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
647 * @returns 0 on success, negative on failure
650 #define MTU_FUDGE_FACTOR 100
652 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
654 struct netxen_adapter *adapter = netdev_priv(netdev);
657 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
658 max_mtu = P3_MAX_MTU;
660 max_mtu = P2_MAX_MTU;
663 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
664 netdev->name, max_mtu);
668 if (adapter->set_mtu)
669 adapter->set_mtu(adapter, mtu);
672 mtu += MTU_FUDGE_FACTOR;
673 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
674 nx_fw_cmd_set_mtu(adapter, mtu);
675 else if (adapter->set_mtu)
676 adapter->set_mtu(adapter, mtu);
681 int netxen_is_flash_supported(struct netxen_adapter *adapter)
683 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
684 int addr, val01, val02, i, j;
686 /* if the flash size less than 4Mb, make huge war cry and die */
687 for (j = 1; j < 4; j++) {
688 addr = j * NETXEN_NIC_WINDOW_MARGIN;
689 for (i = 0; i < ARRAY_SIZE(locs); i++) {
690 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
691 && netxen_rom_fast_read(adapter, (addr + locs[i]),
703 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
704 int size, __le32 * buf)
712 for (i = 0; i < size / sizeof(u32); i++) {
713 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
715 *ptr32 = cpu_to_le32(v);
719 if ((char *)buf + size > (char *)ptr32) {
721 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
723 local = cpu_to_le32(v);
724 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
730 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[])
732 __le32 *pmac = (__le32 *) & mac[0];
734 if (netxen_get_flash_block(adapter,
736 offsetof(struct netxen_new_user_info,
738 FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
741 if (*mac == cpu_to_le64(~0ULL)) {
742 if (netxen_get_flash_block(adapter,
743 NETXEN_USER_START_OLD +
744 offsetof(struct netxen_user_old_info,
746 FLASH_NUM_PORTS * sizeof(u64),
749 if (*mac == cpu_to_le64(~0ULL))
755 #define CRB_WIN_LOCK_TIMEOUT 100000000
757 static int crb_win_lock(struct netxen_adapter *adapter)
759 int done = 0, timeout = 0;
762 /* acquire semaphore3 from PCI HW block */
763 adapter->hw_read_wx(adapter,
764 NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4);
767 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
772 netxen_crb_writelit_adapter(adapter,
773 NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
777 static void crb_win_unlock(struct netxen_adapter *adapter)
781 adapter->hw_read_wx(adapter,
782 NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4);
786 * Changes the CRB window to the specified window.
789 netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
791 void __iomem *offset;
794 uint8_t func = adapter->ahw.pci_func;
796 if (adapter->curr_window == wndw)
799 * Move the CRB window.
800 * We need to write to the "direct access" region of PCI
801 * to avoid a race condition where the window register has
802 * not been successfully written across CRB before the target
803 * register address is received by PCI. The direct region bypasses
806 offset = PCI_OFFSET_SECOND_RANGE(adapter,
807 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
810 wndw = NETXEN_WINDOW_ONE;
812 writel(wndw, offset);
814 /* MUST make sure window is set before we forge on... */
815 while ((tmp = readl(offset)) != wndw) {
816 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
817 "registered properly: 0x%08x.\n",
818 netxen_nic_driver_name, __func__, tmp);
825 if (wndw == NETXEN_WINDOW_ONE)
826 adapter->curr_window = 1;
828 adapter->curr_window = 0;
832 * Return -1 if off is not valid,
833 * 1 if window access is needed. 'off' is set to offset from
834 * CRB space in 128M pci map
835 * 0 if no window access is needed. 'off' is set to 2M addr
836 * In: 'off' is offset from base in 128M pci map
839 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
842 unsigned long end = *off + len;
843 crb_128M_2M_sub_block_map_t *m;
846 if (*off >= NETXEN_CRB_MAX)
849 if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) {
850 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
851 (ulong)adapter->ahw.pci_base0;
855 if (*off < NETXEN_PCI_CRBSPACE)
858 *off -= NETXEN_PCI_CRBSPACE;
864 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
866 if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) {
867 *off = *off + m->start_2M - m->start_128M +
868 (ulong)adapter->ahw.pci_base0;
873 * Not in direct map, use crb window
879 * In: 'off' is offset from CRB space in 128M pci map
880 * Out: 'off' is 2M pci map addr
881 * side effect: lock crb window
884 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
888 adapter->crb_win = CRB_HI(*off);
889 writel(adapter->crb_win, (void *)(CRB_WINDOW_2M +
890 adapter->ahw.pci_base0));
892 * Read back value to make sure write has gone through before trying
895 win_read = readl((void *)(CRB_WINDOW_2M + adapter->ahw.pci_base0));
896 if (win_read != adapter->crb_win) {
897 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
898 "Read crbwin (0x%x), off=0x%lx\n",
899 __func__, adapter->crb_win, win_read, *off);
901 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
902 (ulong)adapter->ahw.pci_base0;
905 int netxen_load_firmware(struct netxen_adapter *adapter)
909 u32 flashaddr = NETXEN_BOOTLD_START, memaddr = NETXEN_BOOTLD_START;
911 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START)/4;
913 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
914 adapter->pci_write_normalize(adapter,
915 NETXEN_ROMUSB_GLB_CAS_RST, 1);
917 for (i = 0; i < size; i++) {
918 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0)
921 adapter->pci_mem_write(adapter, memaddr, &data, 4);
928 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
929 adapter->pci_write_normalize(adapter,
930 NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
932 adapter->pci_write_normalize(adapter,
933 NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
934 adapter->pci_write_normalize(adapter,
935 NETXEN_ROMUSB_GLB_CAS_RST, 0);
942 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
943 ulong off, void *data, int len)
947 if (ADDR_IN_WINDOW1(off)) {
948 addr = NETXEN_CRB_NORMALIZE(adapter, off);
949 } else { /* Window 0 */
950 addr = pci_base_offset(adapter, off);
951 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
954 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
955 " data %llx len %d\n",
956 pci_base(adapter, off), off, addr,
957 *(unsigned long long *)data, len);
959 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
965 writeb(*(u8 *) data, addr);
968 writew(*(u16 *) data, addr);
971 writel(*(u32 *) data, addr);
974 writeq(*(u64 *) data, addr);
978 "writing data %lx to offset %llx, num words=%d\n",
979 *(unsigned long *)data, off, (len >> 3));
981 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
985 if (!ADDR_IN_WINDOW1(off))
986 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
992 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
993 ulong off, void *data, int len)
997 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
998 addr = NETXEN_CRB_NORMALIZE(adapter, off);
999 } else { /* Window 0 */
1000 addr = pci_base_offset(adapter, off);
1001 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1004 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
1005 pci_base(adapter, off), off, addr);
1007 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1012 *(u8 *) data = readb(addr);
1015 *(u16 *) data = readw(addr);
1018 *(u32 *) data = readl(addr);
1021 *(u64 *) data = readq(addr);
1024 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
1028 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
1030 if (!ADDR_IN_WINDOW1(off))
1031 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1037 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1038 ulong off, void *data, int len)
1040 unsigned long flags = 0;
1043 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1046 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1053 write_lock_irqsave(&adapter->adapter_lock, flags);
1054 crb_win_lock(adapter);
1055 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1058 DPRINTK(1, INFO, "write data %lx to offset %llx, len=%d\n",
1059 *(unsigned long *)data, off, len);
1063 writeb(*(uint8_t *)data, (void *)off);
1066 writew(*(uint16_t *)data, (void *)off);
1069 writel(*(uint32_t *)data, (void *)off);
1072 writeq(*(uint64_t *)data, (void *)off);
1076 "writing data %lx to offset %llx, num words=%d\n",
1077 *(unsigned long *)data, off, (len>>3));
1081 crb_win_unlock(adapter);
1082 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1089 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1090 ulong off, void *data, int len)
1092 unsigned long flags = 0;
1095 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1098 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1105 write_lock_irqsave(&adapter->adapter_lock, flags);
1106 crb_win_lock(adapter);
1107 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1110 DPRINTK(1, INFO, "read from offset %lx, len=%d\n", off, len);
1114 *(uint8_t *)data = readb((void *)off);
1117 *(uint16_t *)data = readw((void *)off);
1120 *(uint32_t *)data = readl((void *)off);
1123 *(uint64_t *)data = readq((void *)off);
1129 DPRINTK(1, INFO, "read %lx\n", *(unsigned long *)data);
1132 crb_win_unlock(adapter);
1133 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1139 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
1141 adapter->hw_write_wx(adapter, off, &val, 4);
1144 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
1147 adapter->hw_read_wx(adapter, off, &val, 4);
1151 /* Change the window to 0, write and change back to window 1. */
1152 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
1154 adapter->hw_write_wx(adapter, index, &value, 4);
1157 /* Change the window to 0, read and change back to window 1. */
1158 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value)
1160 adapter->hw_read_wx(adapter, index, value, 4);
1163 void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value)
1165 adapter->hw_write_wx(adapter, index, &value, 4);
1168 void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value)
1170 adapter->hw_read_wx(adapter, index, value, 4);
1174 * check memory access boundary.
1175 * used by test agent. support ddr access only for now
1177 static unsigned long
1178 netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1179 unsigned long long addr, int size)
1181 if (!ADDR_IN_RANGE(addr,
1182 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1183 !ADDR_IN_RANGE(addr+size-1,
1184 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1185 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1192 static int netxen_pci_set_window_warning_count;
1195 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1196 unsigned long long addr)
1198 void __iomem *offset;
1200 unsigned long long qdr_max;
1201 uint8_t func = adapter->ahw.pci_func;
1203 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1204 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1206 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1209 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1210 /* DDR network side */
1211 addr -= NETXEN_ADDR_DDR_NET;
1212 window = (addr >> 25) & 0x3ff;
1213 if (adapter->ahw.ddr_mn_window != window) {
1214 adapter->ahw.ddr_mn_window = window;
1215 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1216 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1217 writel(window, offset);
1218 /* MUST make sure window is set before we forge on... */
1221 addr -= (window * NETXEN_WINDOW_ONE);
1222 addr += NETXEN_PCI_DDR_NET;
1223 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1224 addr -= NETXEN_ADDR_OCM0;
1225 addr += NETXEN_PCI_OCM0;
1226 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1227 addr -= NETXEN_ADDR_OCM1;
1228 addr += NETXEN_PCI_OCM1;
1229 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1230 /* QDR network side */
1231 addr -= NETXEN_ADDR_QDR_NET;
1232 window = (addr >> 22) & 0x3f;
1233 if (adapter->ahw.qdr_sn_window != window) {
1234 adapter->ahw.qdr_sn_window = window;
1235 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1236 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1237 writel((window << 22), offset);
1238 /* MUST make sure window is set before we forge on... */
1241 addr -= (window * 0x400000);
1242 addr += NETXEN_PCI_QDR_NET;
1245 * peg gdb frequently accesses memory that doesn't exist,
1246 * this limits the chit chat so debugging isn't slowed down.
1248 if ((netxen_pci_set_window_warning_count++ < 8)
1249 || (netxen_pci_set_window_warning_count % 64 == 0))
1250 printk("%s: Warning:netxen_nic_pci_set_window()"
1251 " Unknown address range!\n",
1252 netxen_nic_driver_name);
1259 * Note : only 32-bit writes!
1261 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1264 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1268 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1270 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1273 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1276 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1279 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off)
1281 return readl(NETXEN_CRB_NORMALIZE(adapter, off));
1285 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1286 unsigned long long addr)
1291 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1292 /* DDR network side */
1293 window = MN_WIN(addr);
1294 adapter->ahw.ddr_mn_window = window;
1295 adapter->hw_write_wx(adapter,
1296 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1298 adapter->hw_read_wx(adapter,
1299 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1301 if ((win_read << 17) != window) {
1302 printk(KERN_INFO "Written MNwin (0x%x) != "
1303 "Read MNwin (0x%x)\n", window, win_read);
1305 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1306 } else if (ADDR_IN_RANGE(addr,
1307 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1308 if ((addr & 0x00ff800) == 0xff800) {
1309 printk("%s: QM access not handled.\n", __func__);
1313 window = OCM_WIN(addr);
1314 adapter->ahw.ddr_mn_window = window;
1315 adapter->hw_write_wx(adapter,
1316 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1318 adapter->hw_read_wx(adapter,
1319 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1321 if ((win_read >> 7) != window) {
1322 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1323 "Read OCMwin (0x%x)\n",
1324 __func__, window, win_read);
1326 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1328 } else if (ADDR_IN_RANGE(addr,
1329 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1330 /* QDR network side */
1331 window = MS_WIN(addr);
1332 adapter->ahw.qdr_sn_window = window;
1333 adapter->hw_write_wx(adapter,
1334 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1336 adapter->hw_read_wx(adapter,
1337 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1339 if (win_read != window) {
1340 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1341 "Read MSwin (0x%x)\n",
1342 __func__, window, win_read);
1344 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1348 * peg gdb frequently accesses memory that doesn't exist,
1349 * this limits the chit chat so debugging isn't slowed down.
1351 if ((netxen_pci_set_window_warning_count++ < 8)
1352 || (netxen_pci_set_window_warning_count%64 == 0)) {
1353 printk("%s: Warning:%s Unknown address range!\n",
1354 __func__, netxen_nic_driver_name);
1361 static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1362 unsigned long long addr)
1365 unsigned long long qdr_max;
1367 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1368 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1370 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1372 if (ADDR_IN_RANGE(addr,
1373 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1374 /* DDR network side */
1375 BUG(); /* MN access can not come here */
1376 } else if (ADDR_IN_RANGE(addr,
1377 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1379 } else if (ADDR_IN_RANGE(addr,
1380 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1382 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1383 /* QDR network side */
1384 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1385 if (adapter->ahw.qdr_sn_window == window)
1392 static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1393 u64 off, void *data, int size)
1395 unsigned long flags;
1399 uint8_t *mem_ptr = NULL;
1400 unsigned long mem_base;
1401 unsigned long mem_page;
1403 write_lock_irqsave(&adapter->adapter_lock, flags);
1406 * If attempting to access unknown address or straddle hw windows,
1409 start = adapter->pci_set_window(adapter, off);
1410 if ((start == -1UL) ||
1411 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1412 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1413 printk(KERN_ERR "%s out of bound pci memory access. "
1414 "offset is 0x%llx\n", netxen_nic_driver_name, off);
1418 addr = (void *)(pci_base_offset(adapter, start));
1420 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1421 mem_base = pci_resource_start(adapter->pdev, 0);
1422 mem_page = start & PAGE_MASK;
1423 /* Map two pages whenever user tries to access addresses in two
1426 if (mem_page != ((start + size - 1) & PAGE_MASK))
1427 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1429 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1430 if (mem_ptr == 0UL) {
1431 *(uint8_t *)data = 0;
1435 addr += start & (PAGE_SIZE - 1);
1436 write_lock_irqsave(&adapter->adapter_lock, flags);
1441 *(uint8_t *)data = readb(addr);
1444 *(uint16_t *)data = readw(addr);
1447 *(uint32_t *)data = readl(addr);
1450 *(uint64_t *)data = readq(addr);
1456 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1457 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1465 netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1466 void *data, int size)
1468 unsigned long flags;
1472 uint8_t *mem_ptr = NULL;
1473 unsigned long mem_base;
1474 unsigned long mem_page;
1476 write_lock_irqsave(&adapter->adapter_lock, flags);
1479 * If attempting to access unknown address or straddle hw windows,
1482 start = adapter->pci_set_window(adapter, off);
1483 if ((start == -1UL) ||
1484 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1485 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1486 printk(KERN_ERR "%s out of bound pci memory access. "
1487 "offset is 0x%llx\n", netxen_nic_driver_name, off);
1491 addr = (void *)(pci_base_offset(adapter, start));
1493 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1494 mem_base = pci_resource_start(adapter->pdev, 0);
1495 mem_page = start & PAGE_MASK;
1496 /* Map two pages whenever user tries to access addresses in two
1497 * consecutive pages.
1499 if (mem_page != ((start + size - 1) & PAGE_MASK))
1500 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1502 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1506 addr += start & (PAGE_SIZE - 1);
1507 write_lock_irqsave(&adapter->adapter_lock, flags);
1512 writeb(*(uint8_t *)data, addr);
1515 writew(*(uint16_t *)data, addr);
1518 writel(*(uint32_t *)data, addr);
1521 writeq(*(uint64_t *)data, addr);
1527 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1528 DPRINTK(1, INFO, "writing data %llx to offset %llx\n",
1529 *(unsigned long long *)data, start);
1535 #define MAX_CTL_CHECK 1000
1538 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1539 u64 off, void *data, int size)
1541 unsigned long flags, mem_crb;
1542 int i, j, ret = 0, loop, sz[2], off0;
1544 uint64_t off8, tmpw, word[2] = {0, 0};
1547 * If not MN, go check for MS or invalid.
1549 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1550 return netxen_nic_pci_mem_write_direct(adapter,
1553 off8 = off & 0xfffffff8;
1555 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1556 sz[1] = size - sz[0];
1557 loop = ((off0 + size - 1) >> 3) + 1;
1558 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1560 if ((size != 8) || (off0 != 0)) {
1561 for (i = 0; i < loop; i++) {
1562 if (adapter->pci_mem_read(adapter,
1563 off8 + (i << 3), &word[i], 8))
1570 tmpw = *((uint8_t *)data);
1573 tmpw = *((uint16_t *)data);
1576 tmpw = *((uint32_t *)data);
1580 tmpw = *((uint64_t *)data);
1583 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1584 word[0] |= tmpw << (off0 * 8);
1587 word[1] &= ~(~0ULL << (sz[1] * 8));
1588 word[1] |= tmpw >> (sz[0] * 8);
1591 write_lock_irqsave(&adapter->adapter_lock, flags);
1592 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1594 for (i = 0; i < loop; i++) {
1595 writel((uint32_t)(off8 + (i << 3)),
1596 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1598 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1599 writel(word[i] & 0xffffffff,
1600 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_LO));
1601 writel((word[i] >> 32) & 0xffffffff,
1602 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_HI));
1603 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1604 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1605 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1606 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1608 for (j = 0; j < MAX_CTL_CHECK; j++) {
1610 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1611 if ((temp & MIU_TA_CTL_BUSY) == 0)
1615 if (j >= MAX_CTL_CHECK) {
1616 printk("%s: %s Fail to write through agent\n",
1617 __func__, netxen_nic_driver_name);
1623 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1624 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1629 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1630 u64 off, void *data, int size)
1632 unsigned long flags, mem_crb;
1633 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1635 uint64_t off8, val, word[2] = {0, 0};
1639 * If not MN, go check for MS or invalid.
1641 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1642 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1644 off8 = off & 0xfffffff8;
1645 off0[0] = off & 0x7;
1647 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1648 sz[1] = size - sz[0];
1649 loop = ((off0[0] + size - 1) >> 3) + 1;
1650 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1652 write_lock_irqsave(&adapter->adapter_lock, flags);
1653 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1655 for (i = 0; i < loop; i++) {
1656 writel((uint32_t)(off8 + (i << 3)),
1657 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1659 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1660 writel(MIU_TA_CTL_ENABLE,
1661 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1662 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1663 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1665 for (j = 0; j < MAX_CTL_CHECK; j++) {
1667 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1668 if ((temp & MIU_TA_CTL_BUSY) == 0)
1672 if (j >= MAX_CTL_CHECK) {
1673 printk(KERN_ERR "%s: %s Fail to read through agent\n",
1674 __func__, netxen_nic_driver_name);
1678 start = off0[i] >> 2;
1679 end = (off0[i] + sz[i] - 1) >> 2;
1680 for (k = start; k <= end; k++) {
1681 word[i] |= ((uint64_t) readl(
1683 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1687 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1688 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1690 if (j >= MAX_CTL_CHECK)
1696 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1697 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1702 *(uint8_t *)data = val;
1705 *(uint16_t *)data = val;
1708 *(uint32_t *)data = val;
1711 *(uint64_t *)data = val;
1714 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1719 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1720 u64 off, void *data, int size)
1722 int i, j, ret = 0, loop, sz[2], off0;
1724 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1727 * If not MN, go check for MS or invalid.
1729 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1730 mem_crb = NETXEN_CRB_QDR_NET;
1732 mem_crb = NETXEN_CRB_DDR_NET;
1733 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1734 return netxen_nic_pci_mem_write_direct(adapter,
1738 off8 = off & 0xfffffff8;
1740 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1741 sz[1] = size - sz[0];
1742 loop = ((off0 + size - 1) >> 3) + 1;
1744 if ((size != 8) || (off0 != 0)) {
1745 for (i = 0; i < loop; i++) {
1746 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1754 tmpw = *((uint8_t *)data);
1757 tmpw = *((uint16_t *)data);
1760 tmpw = *((uint32_t *)data);
1764 tmpw = *((uint64_t *)data);
1768 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1769 word[0] |= tmpw << (off0 * 8);
1772 word[1] &= ~(~0ULL << (sz[1] * 8));
1773 word[1] |= tmpw >> (sz[0] * 8);
1777 * don't lock here - write_wx gets the lock if each time
1778 * write_lock_irqsave(&adapter->adapter_lock, flags);
1779 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1782 for (i = 0; i < loop; i++) {
1783 temp = off8 + (i << 3);
1784 adapter->hw_write_wx(adapter,
1785 mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4);
1787 adapter->hw_write_wx(adapter,
1788 mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4);
1789 temp = word[i] & 0xffffffff;
1790 adapter->hw_write_wx(adapter,
1791 mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4);
1792 temp = (word[i] >> 32) & 0xffffffff;
1793 adapter->hw_write_wx(adapter,
1794 mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4);
1795 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1796 adapter->hw_write_wx(adapter,
1797 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1798 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1799 adapter->hw_write_wx(adapter,
1800 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1802 for (j = 0; j < MAX_CTL_CHECK; j++) {
1803 adapter->hw_read_wx(adapter,
1804 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1805 if ((temp & MIU_TA_CTL_BUSY) == 0)
1809 if (j >= MAX_CTL_CHECK) {
1810 printk(KERN_ERR "%s: Fail to write through agent\n",
1811 netxen_nic_driver_name);
1818 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1819 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1825 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1826 u64 off, void *data, int size)
1828 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1830 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1833 * If not MN, go check for MS or invalid.
1836 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1837 mem_crb = NETXEN_CRB_QDR_NET;
1839 mem_crb = NETXEN_CRB_DDR_NET;
1840 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1841 return netxen_nic_pci_mem_read_direct(adapter,
1845 off8 = off & 0xfffffff8;
1846 off0[0] = off & 0x7;
1848 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1849 sz[1] = size - sz[0];
1850 loop = ((off0[0] + size - 1) >> 3) + 1;
1853 * don't lock here - write_wx gets the lock if each time
1854 * write_lock_irqsave(&adapter->adapter_lock, flags);
1855 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1858 for (i = 0; i < loop; i++) {
1859 temp = off8 + (i << 3);
1860 adapter->hw_write_wx(adapter,
1861 mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4);
1863 adapter->hw_write_wx(adapter,
1864 mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4);
1865 temp = MIU_TA_CTL_ENABLE;
1866 adapter->hw_write_wx(adapter,
1867 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1868 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1869 adapter->hw_write_wx(adapter,
1870 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1872 for (j = 0; j < MAX_CTL_CHECK; j++) {
1873 adapter->hw_read_wx(adapter,
1874 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1875 if ((temp & MIU_TA_CTL_BUSY) == 0)
1879 if (j >= MAX_CTL_CHECK) {
1880 printk(KERN_ERR "%s: Fail to read through agent\n",
1881 netxen_nic_driver_name);
1885 start = off0[i] >> 2;
1886 end = (off0[i] + sz[i] - 1) >> 2;
1887 for (k = start; k <= end; k++) {
1888 adapter->hw_read_wx(adapter,
1889 mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4);
1890 word[i] |= ((uint64_t)temp << (32 * k));
1895 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1896 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1899 if (j >= MAX_CTL_CHECK)
1905 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1906 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1911 *(uint8_t *)data = val;
1914 *(uint16_t *)data = val;
1917 *(uint32_t *)data = val;
1920 *(uint64_t *)data = val;
1923 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1928 * Note : only 32-bit writes!
1930 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1933 adapter->hw_write_wx(adapter, off, &data, 4);
1938 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
1941 adapter->hw_read_wx(adapter, off, &temp, 4);
1945 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1948 adapter->hw_write_wx(adapter, off, &data, 4);
1951 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off)
1954 adapter->hw_read_wx(adapter, off, &temp, 4);
1960 netxen_nic_erase_pxe(struct netxen_adapter *adapter)
1962 if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) {
1963 printk(KERN_ERR "%s: erase pxe failed\n",
1964 netxen_nic_driver_name);
1971 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1974 int addr = NETXEN_BRDCFG_START;
1975 struct netxen_board_info *boardinfo;
1979 boardinfo = &adapter->ahw.boardcfg;
1980 ptr32 = (u32 *) boardinfo;
1982 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
1984 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
1988 addr += sizeof(u32);
1990 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
1991 printk("%s: ERROR reading %s board config."
1992 " Read %x, expected %x\n", netxen_nic_driver_name,
1993 netxen_nic_driver_name,
1994 boardinfo->magic, NETXEN_BDINFO_MAGIC);
1997 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
1998 printk("%s: Unknown board config version."
1999 " Read %x, expected %x\n", netxen_nic_driver_name,
2000 boardinfo->header_version, NETXEN_BDINFO_VERSION);
2004 DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
2005 switch ((netxen_brdtype_t) boardinfo->board_type) {
2006 case NETXEN_BRDTYPE_P2_SB35_4G:
2007 adapter->ahw.board_type = NETXEN_NIC_GBE;
2009 case NETXEN_BRDTYPE_P2_SB31_10G:
2010 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
2011 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
2012 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
2013 case NETXEN_BRDTYPE_P3_HMEZ:
2014 case NETXEN_BRDTYPE_P3_XG_LOM:
2015 case NETXEN_BRDTYPE_P3_10G_CX4:
2016 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
2017 case NETXEN_BRDTYPE_P3_IMEZ:
2018 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
2019 case NETXEN_BRDTYPE_P3_10G_XFP:
2020 case NETXEN_BRDTYPE_P3_10000_BASE_T:
2022 adapter->ahw.board_type = NETXEN_NIC_XGBE;
2024 case NETXEN_BRDTYPE_P1_BD:
2025 case NETXEN_BRDTYPE_P1_SB:
2026 case NETXEN_BRDTYPE_P1_SMAX:
2027 case NETXEN_BRDTYPE_P1_SOCK:
2028 case NETXEN_BRDTYPE_P3_REF_QG:
2029 case NETXEN_BRDTYPE_P3_4_GB:
2030 case NETXEN_BRDTYPE_P3_4_GB_MM:
2032 adapter->ahw.board_type = NETXEN_NIC_GBE;
2035 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
2036 boardinfo->board_type);
2043 /* NIU access sections */
2045 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
2047 netxen_nic_write_w0(adapter,
2048 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2053 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
2055 new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
2056 if (adapter->physical_port == 0)
2057 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
2060 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
2066 netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
2067 unsigned long off, int data)
2069 adapter->hw_write_wx(adapter, off, &data, 4);
2072 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2078 netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
2079 if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
2080 if (adapter->phy_read
2083 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2085 if (netxen_get_phy_link(status)) {
2086 switch (netxen_get_phy_speed(status)) {
2088 adapter->link_speed = SPEED_10;
2091 adapter->link_speed = SPEED_100;
2094 adapter->link_speed = SPEED_1000;
2097 adapter->link_speed = -1;
2100 switch (netxen_get_phy_duplex(status)) {
2102 adapter->link_duplex = DUPLEX_HALF;
2105 adapter->link_duplex = DUPLEX_FULL;
2108 adapter->link_duplex = -1;
2111 if (adapter->phy_read
2114 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
2116 adapter->link_autoneg = autoneg;
2121 adapter->link_speed = -1;
2122 adapter->link_duplex = -1;
2127 void netxen_nic_flash_print(struct netxen_adapter *adapter)
2132 char brd_name[NETXEN_MAX_SHORT_NAME];
2133 char serial_num[32];
2137 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
2139 adapter->driver_mismatch = 0;
2141 ptr32 = (u32 *)&serial_num;
2142 addr = NETXEN_USER_START +
2143 offsetof(struct netxen_new_user_info, serial_num);
2144 for (i = 0; i < 8; i++) {
2145 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
2146 printk("%s: ERROR reading %s board userarea.\n",
2147 netxen_nic_driver_name,
2148 netxen_nic_driver_name);
2149 adapter->driver_mismatch = 1;
2153 addr += sizeof(u32);
2156 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4);
2157 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4);
2158 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4);
2160 adapter->fw_major = fw_major;
2162 if (adapter->portnum == 0) {
2163 get_brd_name_by_type(board_info->board_type, brd_name);
2165 printk("NetXen %s Board S/N %s Chip id 0x%x\n",
2166 brd_name, serial_num, board_info->chip_id);
2167 printk("NetXen Firmware version %d.%d.%d\n", fw_major,
2168 fw_minor, fw_build);
2171 if (NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build) <
2172 NETXEN_VERSION_CODE(3, 4, 216)) {
2173 adapter->driver_mismatch = 1;
2174 printk(KERN_ERR "%s: firmware version %d.%d.%d unsupported\n",
2175 netxen_nic_driver_name,
2176 fw_major, fw_minor, fw_build);