2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
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11 * without modification, are permitted provided that the following
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15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 AEL100X_TX_CONFIG1 = 0xc002,
37 AEL1002_PWR_DOWN_HI = 0xc011,
38 AEL1002_PWR_DOWN_LO = 0xc012,
39 AEL1002_XFI_EQL = 0xc015,
40 AEL1002_LB_EN = 0xc017,
41 AEL_OPT_SETTINGS = 0xc017,
42 AEL_I2C_CTRL = 0xc30a,
43 AEL_I2C_DATA = 0xc30b,
44 AEL_I2C_STAT = 0xc30c,
45 AEL2005_GPIO_CTRL = 0xc214,
46 AEL2005_GPIO_STAT = 0xc215,
48 AEL2020_GPIO_INTR = 0xc103, /* Latch High (LH) */
49 AEL2020_GPIO_CTRL = 0xc108, /* Store Clear (SC) */
50 AEL2020_GPIO_STAT = 0xc10c, /* Read Only (RO) */
51 AEL2020_GPIO_CFG = 0xc110, /* Read Write (RW) */
53 AEL2020_GPIO_SDA = 0, /* IN: i2c serial data */
54 AEL2020_GPIO_MODDET = 1, /* IN: Module Detect */
55 AEL2020_GPIO_0 = 3, /* IN: unassigned */
56 AEL2020_GPIO_1 = 2, /* OUT: unassigned */
57 AEL2020_GPIO_LSTAT = AEL2020_GPIO_1, /* wired to link status LED */
60 enum { edc_none, edc_sr, edc_twinax };
62 /* PHY module I2C device address */
64 MODULE_DEV_ADDR = 0xa0,
68 /* PHY transceiver type */
70 phy_transtype_unknown = 0,
71 phy_transtype_sfp = 3,
72 phy_transtype_xfp = 6,
75 #define AEL2005_MODDET_IRQ 4
78 unsigned short mmd_addr;
79 unsigned short reg_addr;
80 unsigned short clear_bits;
81 unsigned short set_bits;
84 static int set_phy_regs(struct cphy *phy, const struct reg_val *rv)
88 for (err = 0; rv->mmd_addr && !err; rv++) {
89 if (rv->clear_bits == 0xffff)
90 err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr,
93 err = t3_mdio_change_bits(phy, rv->mmd_addr,
94 rv->reg_addr, rv->clear_bits,
100 static void ael100x_txon(struct cphy *phy)
103 phy->mdio.prtad == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL;
106 t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio);
111 * Read an 8-bit word from a device attached to the PHY's i2c bus.
113 static int ael_i2c_rd(struct cphy *phy, int dev_addr, int word_addr)
116 unsigned int stat, data;
118 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL_I2C_CTRL,
119 (dev_addr << 8) | (1 << 8) | word_addr);
123 for (i = 0; i < 200; i++) {
125 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_STAT, &stat);
128 if ((stat & 3) == 1) {
129 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_DATA,
136 CH_WARN(phy->adapter, "PHY %u i2c read of dev.addr %#x.%#x timed out\n",
137 phy->mdio.prtad, dev_addr, word_addr);
141 static int ael1002_power_down(struct cphy *phy, int enable)
145 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, !!enable);
147 err = mdio_set_flag(&phy->mdio, phy->mdio.prtad,
148 MDIO_MMD_PMAPMD, MDIO_CTRL1,
149 MDIO_CTRL1_LPOWER, enable);
153 static int ael1002_reset(struct cphy *phy, int wait)
157 if ((err = ael1002_power_down(phy, 0)) ||
158 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL100X_TX_CONFIG1, 1)) ||
159 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_HI, 0)) ||
160 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_LO, 0)) ||
161 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_XFI_EQL, 0x18)) ||
162 (err = t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL1002_LB_EN,
168 static int ael1002_intr_noop(struct cphy *phy)
174 * Get link status for a 10GBASE-R device.
176 static int get_link_status_r(struct cphy *phy, int *link_ok, int *speed,
177 int *duplex, int *fc)
180 unsigned int stat0, stat1, stat2;
181 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD,
182 MDIO_PMA_RXDET, &stat0);
185 err = t3_mdio_read(phy, MDIO_MMD_PCS,
186 MDIO_PCS_10GBRT_STAT1, &stat1);
188 err = t3_mdio_read(phy, MDIO_MMD_PHYXS,
189 MDIO_PHYXS_LNSTAT, &stat2);
192 *link_ok = (stat0 & stat1 & (stat2 >> 12)) & 1;
195 *speed = SPEED_10000;
197 *duplex = DUPLEX_FULL;
201 static struct cphy_ops ael1002_ops = {
202 .reset = ael1002_reset,
203 .intr_enable = ael1002_intr_noop,
204 .intr_disable = ael1002_intr_noop,
205 .intr_clear = ael1002_intr_noop,
206 .intr_handler = ael1002_intr_noop,
207 .get_link_status = get_link_status_r,
208 .power_down = ael1002_power_down,
209 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
212 int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter,
213 int phy_addr, const struct mdio_ops *mdio_ops)
215 cphy_init(phy, adapter, phy_addr, &ael1002_ops, mdio_ops,
216 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE,
222 static int ael1006_reset(struct cphy *phy, int wait)
224 return t3_phy_reset(phy, MDIO_MMD_PMAPMD, wait);
227 static int ael1006_power_down(struct cphy *phy, int enable)
229 return mdio_set_flag(&phy->mdio, phy->mdio.prtad, MDIO_MMD_PMAPMD,
230 MDIO_CTRL1, MDIO_CTRL1_LPOWER, enable);
233 static struct cphy_ops ael1006_ops = {
234 .reset = ael1006_reset,
235 .intr_enable = t3_phy_lasi_intr_enable,
236 .intr_disable = t3_phy_lasi_intr_disable,
237 .intr_clear = t3_phy_lasi_intr_clear,
238 .intr_handler = t3_phy_lasi_intr_handler,
239 .get_link_status = get_link_status_r,
240 .power_down = ael1006_power_down,
241 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
244 int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter,
245 int phy_addr, const struct mdio_ops *mdio_ops)
247 cphy_init(phy, adapter, phy_addr, &ael1006_ops, mdio_ops,
248 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE,
255 * Decode our module type.
257 static int ael2xxx_get_module_type(struct cphy *phy, int delay_ms)
264 /* see SFF-8472 for below */
265 v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 3);
270 return phy_modtype_sr;
272 return phy_modtype_lr;
274 return phy_modtype_lrm;
276 v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 6);
282 v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 10);
287 v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 0x12);
290 return v > 10 ? phy_modtype_twinax_long : phy_modtype_twinax;
293 return phy_modtype_unknown;
297 * Code to support the Aeluros/NetLogic 2005 10Gb PHY.
299 static int ael2005_setup_sr_edc(struct cphy *phy)
301 static struct reg_val regs[] = {
302 { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x181 },
303 { MDIO_MMD_PMAPMD, 0xc010, 0xffff, 0x448a },
304 { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5200 },
307 static u16 sr_edc[] = {
582 err = set_phy_regs(phy, regs);
588 for (i = 0; i < ARRAY_SIZE(sr_edc) && !err; i += 2)
589 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, sr_edc[i],
596 static int ael2005_setup_twinax_edc(struct cphy *phy, int modtype)
598 static struct reg_val regs[] = {
599 { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5a00 },
602 static struct reg_val preemphasis[] = {
603 { MDIO_MMD_PMAPMD, 0xc014, 0xffff, 0xfe16 },
604 { MDIO_MMD_PMAPMD, 0xc015, 0xffff, 0xa000 },
607 static u16 twinax_edc[] = {
977 err = set_phy_regs(phy, regs);
978 if (!err && modtype == phy_modtype_twinax_long)
979 err = set_phy_regs(phy, preemphasis);
985 for (i = 0; i < ARRAY_SIZE(twinax_edc) && !err; i += 2)
986 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, twinax_edc[i],
989 phy->priv = edc_twinax;
993 static int ael2005_get_module_type(struct cphy *phy, int delay_ms)
998 v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, &stat);
1002 if (stat & (1 << 8)) /* module absent */
1003 return phy_modtype_none;
1005 return ael2xxx_get_module_type(phy, delay_ms);
1008 static int ael2005_intr_enable(struct cphy *phy)
1010 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x200);
1011 return err ? err : t3_phy_lasi_intr_enable(phy);
1014 static int ael2005_intr_disable(struct cphy *phy)
1016 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x100);
1017 return err ? err : t3_phy_lasi_intr_disable(phy);
1020 static int ael2005_intr_clear(struct cphy *phy)
1022 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0xd00);
1023 return err ? err : t3_phy_lasi_intr_clear(phy);
1026 static int ael2005_reset(struct cphy *phy, int wait)
1028 static struct reg_val regs0[] = {
1029 { MDIO_MMD_PMAPMD, 0xc001, 0, 1 << 5 },
1030 { MDIO_MMD_PMAPMD, 0xc017, 0, 1 << 5 },
1031 { MDIO_MMD_PMAPMD, 0xc013, 0xffff, 0xf341 },
1032 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 },
1033 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8100 },
1034 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 },
1035 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0 },
1038 static struct reg_val regs1[] = {
1039 { MDIO_MMD_PMAPMD, 0xca00, 0xffff, 0x0080 },
1040 { MDIO_MMD_PMAPMD, 0xca12, 0xffff, 0 },
1045 unsigned int lasi_ctrl;
1047 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
1052 err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 0);
1057 phy->priv = edc_none;
1058 err = set_phy_regs(phy, regs0);
1064 err = ael2005_get_module_type(phy, 0);
1069 if (err == phy_modtype_twinax || err == phy_modtype_twinax_long)
1070 err = ael2005_setup_twinax_edc(phy, err);
1072 err = ael2005_setup_sr_edc(phy);
1076 err = set_phy_regs(phy, regs1);
1080 /* reset wipes out interrupts, reenable them if they were on */
1082 err = ael2005_intr_enable(phy);
1086 static int ael2005_intr_handler(struct cphy *phy)
1089 int ret, edc_needed, cause = 0;
1091 ret = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_STAT, &stat);
1095 if (stat & AEL2005_MODDET_IRQ) {
1096 ret = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL,
1101 /* modules have max 300 ms init time after hot plug */
1102 ret = ael2005_get_module_type(phy, 300);
1107 if (ret == phy_modtype_none)
1108 edc_needed = phy->priv; /* on unplug retain EDC */
1109 else if (ret == phy_modtype_twinax ||
1110 ret == phy_modtype_twinax_long)
1111 edc_needed = edc_twinax;
1113 edc_needed = edc_sr;
1115 if (edc_needed != phy->priv) {
1116 ret = ael2005_reset(phy, 0);
1117 return ret ? ret : cphy_cause_module_change;
1119 cause = cphy_cause_module_change;
1122 ret = t3_phy_lasi_intr_handler(phy);
1127 return ret ? ret : cphy_cause_link_change;
1130 static struct cphy_ops ael2005_ops = {
1131 .reset = ael2005_reset,
1132 .intr_enable = ael2005_intr_enable,
1133 .intr_disable = ael2005_intr_disable,
1134 .intr_clear = ael2005_intr_clear,
1135 .intr_handler = ael2005_intr_handler,
1136 .get_link_status = get_link_status_r,
1137 .power_down = ael1002_power_down,
1138 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
1141 int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter,
1142 int phy_addr, const struct mdio_ops *mdio_ops)
1144 cphy_init(phy, adapter, phy_addr, &ael2005_ops, mdio_ops,
1145 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE |
1146 SUPPORTED_IRQ, "10GBASE-R");
1148 return t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL_OPT_SETTINGS, 0,
1153 * Setup EDC and other parameters for operation with an optical module.
1155 static int ael2020_setup_sr_edc(struct cphy *phy)
1157 static struct reg_val regs[] = {
1158 /* set CDR offset to 10 */
1159 { MDIO_MMD_PMAPMD, 0xcc01, 0xffff, 0x488a },
1161 /* adjust 10G RX bias current */
1162 { MDIO_MMD_PMAPMD, 0xcb1b, 0xffff, 0x0200 },
1163 { MDIO_MMD_PMAPMD, 0xcb1c, 0xffff, 0x00f0 },
1164 { MDIO_MMD_PMAPMD, 0xcc06, 0xffff, 0x00e0 },
1171 err = set_phy_regs(phy, regs);
1181 * Setup EDC and other parameters for operation with an TWINAX module.
1183 static int ael2020_setup_twinax_edc(struct cphy *phy, int modtype)
1185 /* set uC to 40MHz */
1186 static struct reg_val uCclock40MHz[] = {
1187 { MDIO_MMD_PMAPMD, 0xff28, 0xffff, 0x4001 },
1188 { MDIO_MMD_PMAPMD, 0xff2a, 0xffff, 0x0002 },
1192 /* activate uC clock */
1193 static struct reg_val uCclockActivate[] = {
1194 { MDIO_MMD_PMAPMD, 0xd000, 0xffff, 0x5200 },
1198 /* set PC to start of SRAM and activate uC */
1199 static struct reg_val uCactivate[] = {
1200 { MDIO_MMD_PMAPMD, 0xd080, 0xffff, 0x0100 },
1201 { MDIO_MMD_PMAPMD, 0xd092, 0xffff, 0x0000 },
1205 /* TWINAX EDC firmware */
1206 static u16 twinax_edc[] = {
1605 /* set uC clock and activate it */
1606 err = set_phy_regs(phy, uCclock40MHz);
1610 err = set_phy_regs(phy, uCclockActivate);
1615 /* write TWINAX EDC firmware into PHY */
1616 for (i = 0; i < ARRAY_SIZE(twinax_edc) && !err; i += 2)
1617 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, twinax_edc[i],
1620 err = set_phy_regs(phy, uCactivate);
1622 phy->priv = edc_twinax;
1627 * Return Module Type.
1629 static int ael2020_get_module_type(struct cphy *phy, int delay_ms)
1634 v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_STAT, &stat);
1638 if (stat & (0x1 << (AEL2020_GPIO_MODDET*4))) {
1640 return phy_modtype_none;
1643 return ael2xxx_get_module_type(phy, delay_ms);
1647 * Enable PHY interrupts. We enable "Module Detection" interrupts (on any
1648 * state transition) and then generic Link Alarm Status Interrupt (LASI).
1650 static int ael2020_intr_enable(struct cphy *phy)
1652 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
1653 0x2 << (AEL2020_GPIO_MODDET*4));
1654 return err ? err : t3_phy_lasi_intr_enable(phy);
1658 * Disable PHY interrupts. The mirror of the above ...
1660 static int ael2020_intr_disable(struct cphy *phy)
1662 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
1663 0x1 << (AEL2020_GPIO_MODDET*4));
1664 return err ? err : t3_phy_lasi_intr_disable(phy);
1668 * Clear PHY interrupt state.
1670 static int ael2020_intr_clear(struct cphy *phy)
1673 * The GPIO Interrupt register on the AEL2020 is a "Latching High"
1674 * (LH) register which is cleared to the current state when it's read.
1675 * Thus, we simply read the register and discard the result.
1678 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_INTR, &stat);
1679 return err ? err : t3_phy_lasi_intr_clear(phy);
1683 * Reset the PHY and put it into a canonical operating state.
1685 static int ael2020_reset(struct cphy *phy, int wait)
1687 static struct reg_val regs0[] = {
1688 /* Erratum #2: CDRLOL asserted, causing PMA link down status */
1689 { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x3101 },
1691 /* force XAUI to send LF when RX_LOS is asserted */
1692 { MDIO_MMD_PMAPMD, 0xcd40, 0xffff, 0x0001 },
1694 /* RX_LOS pin is active high */
1695 { MDIO_MMD_PMAPMD, AEL_OPT_SETTINGS,
1698 /* output Module's Loss Of Signal (LOS) to LED */
1699 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CFG+AEL2020_GPIO_LSTAT,
1701 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
1702 0xffff, 0x8 << (AEL2020_GPIO_LSTAT*4) },
1708 unsigned int lasi_ctrl;
1710 /* grab current interrupt state */
1711 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
1716 err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 125);
1721 /* basic initialization for all module types */
1722 phy->priv = edc_none;
1723 err = set_phy_regs(phy, regs0);
1727 /* determine module type and perform appropriate initialization */
1728 err = ael2020_get_module_type(phy, 0);
1731 phy->modtype = (u8)err;
1732 if (err == phy_modtype_twinax || err == phy_modtype_twinax_long)
1733 err = ael2020_setup_twinax_edc(phy, err);
1735 err = ael2020_setup_sr_edc(phy);
1739 /* reset wipes out interrupts, reenable them if they were on */
1741 err = ael2005_intr_enable(phy);
1746 * Handle a PHY interrupt.
1748 static int ael2020_intr_handler(struct cphy *phy)
1751 int ret, edc_needed, cause = 0;
1753 ret = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_INTR, &stat);
1757 if (stat & (0x1 << AEL2020_GPIO_MODDET)) {
1758 /* modules have max 300 ms init time after hot plug */
1759 ret = ael2020_get_module_type(phy, 300);
1763 phy->modtype = (u8)ret;
1764 if (ret == phy_modtype_none)
1765 edc_needed = phy->priv; /* on unplug retain EDC */
1766 else if (ret == phy_modtype_twinax ||
1767 ret == phy_modtype_twinax_long)
1768 edc_needed = edc_twinax;
1770 edc_needed = edc_sr;
1772 if (edc_needed != phy->priv) {
1773 ret = ael2020_reset(phy, 0);
1774 return ret ? ret : cphy_cause_module_change;
1776 cause = cphy_cause_module_change;
1779 ret = t3_phy_lasi_intr_handler(phy);
1784 return ret ? ret : cphy_cause_link_change;
1787 static struct cphy_ops ael2020_ops = {
1788 .reset = ael2020_reset,
1789 .intr_enable = ael2020_intr_enable,
1790 .intr_disable = ael2020_intr_disable,
1791 .intr_clear = ael2020_intr_clear,
1792 .intr_handler = ael2020_intr_handler,
1793 .get_link_status = get_link_status_r,
1794 .power_down = ael1002_power_down,
1795 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
1798 int t3_ael2020_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr,
1799 const struct mdio_ops *mdio_ops)
1801 cphy_init(phy, adapter, phy_addr, &ael2020_ops, mdio_ops,
1802 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE |
1803 SUPPORTED_IRQ, "10GBASE-R");
1809 * Get link status for a 10GBASE-X device.
1811 static int get_link_status_x(struct cphy *phy, int *link_ok, int *speed,
1812 int *duplex, int *fc)
1815 unsigned int stat0, stat1, stat2;
1816 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD,
1817 MDIO_PMA_RXDET, &stat0);
1820 err = t3_mdio_read(phy, MDIO_MMD_PCS,
1821 MDIO_PCS_10GBX_STAT1, &stat1);
1823 err = t3_mdio_read(phy, MDIO_MMD_PHYXS,
1824 MDIO_PHYXS_LNSTAT, &stat2);
1827 *link_ok = (stat0 & (stat1 >> 12) & (stat2 >> 12)) & 1;
1830 *speed = SPEED_10000;
1832 *duplex = DUPLEX_FULL;
1836 static struct cphy_ops qt2045_ops = {
1837 .reset = ael1006_reset,
1838 .intr_enable = t3_phy_lasi_intr_enable,
1839 .intr_disable = t3_phy_lasi_intr_disable,
1840 .intr_clear = t3_phy_lasi_intr_clear,
1841 .intr_handler = t3_phy_lasi_intr_handler,
1842 .get_link_status = get_link_status_x,
1843 .power_down = ael1006_power_down,
1844 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
1847 int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter,
1848 int phy_addr, const struct mdio_ops *mdio_ops)
1852 cphy_init(phy, adapter, phy_addr, &qt2045_ops, mdio_ops,
1853 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_TP,
1857 * Some cards where the PHY is supposed to be at address 0 actually
1861 !t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_STAT1, &stat) &&
1863 phy->mdio.prtad = 1;
1867 static int xaui_direct_reset(struct cphy *phy, int wait)
1872 static int xaui_direct_get_link_status(struct cphy *phy, int *link_ok,
1873 int *speed, int *duplex, int *fc)
1876 unsigned int status;
1877 int prtad = phy->mdio.prtad;
1879 status = t3_read_reg(phy->adapter,
1880 XGM_REG(A_XGM_SERDES_STAT0, prtad)) |
1881 t3_read_reg(phy->adapter,
1882 XGM_REG(A_XGM_SERDES_STAT1, prtad)) |
1883 t3_read_reg(phy->adapter,
1884 XGM_REG(A_XGM_SERDES_STAT2, prtad)) |
1885 t3_read_reg(phy->adapter,
1886 XGM_REG(A_XGM_SERDES_STAT3, prtad));
1887 *link_ok = !(status & F_LOWSIG0);
1890 *speed = SPEED_10000;
1892 *duplex = DUPLEX_FULL;
1896 static int xaui_direct_power_down(struct cphy *phy, int enable)
1901 static struct cphy_ops xaui_direct_ops = {
1902 .reset = xaui_direct_reset,
1903 .intr_enable = ael1002_intr_noop,
1904 .intr_disable = ael1002_intr_noop,
1905 .intr_clear = ael1002_intr_noop,
1906 .intr_handler = ael1002_intr_noop,
1907 .get_link_status = xaui_direct_get_link_status,
1908 .power_down = xaui_direct_power_down,
1911 int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter,
1912 int phy_addr, const struct mdio_ops *mdio_ops)
1914 cphy_init(phy, adapter, MDIO_PRTAD_NONE, &xaui_direct_ops, mdio_ops,
1915 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_TP,