Merge commit 'v2.6.28-rc6' into core/debug
[linux-2.6] / arch / x86 / oprofile / op_model_amd.c
1 /*
2  * @file op_model_amd.c
3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
4  *
5  * @remark Copyright 2002-2008 OProfile authors
6  * @remark Read the file COPYING
7  *
8  * @author John Levon
9  * @author Philippe Elie
10  * @author Graydon Hoare
11  * @author Robert Richter <robert.richter@amd.com>
12  * @author Barry Kasindorf
13 */
14
15 #include <linux/oprofile.h>
16 #include <linux/device.h>
17 #include <linux/pci.h>
18
19 #include <asm/ptrace.h>
20 #include <asm/msr.h>
21 #include <asm/nmi.h>
22
23 #include "op_x86_model.h"
24 #include "op_counter.h"
25
26 #define NUM_COUNTERS 4
27 #define NUM_CONTROLS 4
28
29 #define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
30 #define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0)
31 #define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1); } while (0)
32 #define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))
33
34 #define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
35 #define CTRL_READ(l, h, msrs, c) do {rdmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
36 #define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
37 #define CTRL_SET_ACTIVE(n) (n |= (1<<22))
38 #define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))
39 #define CTRL_CLEAR_LO(x) (x &= (1<<21))
40 #define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0)
41 #define CTRL_SET_ENABLE(val) (val |= 1<<20)
42 #define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16))
43 #define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17))
44 #define CTRL_SET_UM(val, m) (val |= (m << 8))
45 #define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff))
46 #define CTRL_SET_EVENT_HIGH(val, e) (val |= ((e >> 8) & 0xf))
47 #define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))
48 #define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
49
50 static unsigned long reset_value[NUM_COUNTERS];
51
52 #ifdef CONFIG_OPROFILE_IBS
53
54 /* IbsFetchCtl bits/masks */
55 #define IBS_FETCH_HIGH_VALID_BIT        (1UL << 17)     /* bit 49 */
56 #define IBS_FETCH_HIGH_ENABLE           (1UL << 16)     /* bit 48 */
57 #define IBS_FETCH_LOW_MAX_CNT_MASK      0x0000FFFFUL    /* MaxCnt mask */
58
59 /*IbsOpCtl bits */
60 #define IBS_OP_LOW_VALID_BIT            (1ULL<<18)      /* bit 18 */
61 #define IBS_OP_LOW_ENABLE               (1ULL<<17)      /* bit 17 */
62
63 /* Codes used in cpu_buffer.c */
64 /* This produces duplicate code, need to be fixed */
65 #define IBS_FETCH_BEGIN 3
66 #define IBS_OP_BEGIN    4
67
68 /* The function interface needs to be fixed, something like add
69    data. Should then be added to linux/oprofile.h. */
70 extern void
71 oprofile_add_ibs_sample(struct pt_regs *const regs,
72                         unsigned int *const ibs_sample, int ibs_code);
73
74 struct ibs_fetch_sample {
75         /* MSRC001_1031 IBS Fetch Linear Address Register */
76         unsigned int ibs_fetch_lin_addr_low;
77         unsigned int ibs_fetch_lin_addr_high;
78         /* MSRC001_1030 IBS Fetch Control Register */
79         unsigned int ibs_fetch_ctl_low;
80         unsigned int ibs_fetch_ctl_high;
81         /* MSRC001_1032 IBS Fetch Physical Address Register */
82         unsigned int ibs_fetch_phys_addr_low;
83         unsigned int ibs_fetch_phys_addr_high;
84 };
85
86 struct ibs_op_sample {
87         /* MSRC001_1034 IBS Op Logical Address Register (IbsRIP) */
88         unsigned int ibs_op_rip_low;
89         unsigned int ibs_op_rip_high;
90         /* MSRC001_1035 IBS Op Data Register */
91         unsigned int ibs_op_data1_low;
92         unsigned int ibs_op_data1_high;
93         /* MSRC001_1036 IBS Op Data 2 Register */
94         unsigned int ibs_op_data2_low;
95         unsigned int ibs_op_data2_high;
96         /* MSRC001_1037 IBS Op Data 3 Register */
97         unsigned int ibs_op_data3_low;
98         unsigned int ibs_op_data3_high;
99         /* MSRC001_1038 IBS DC Linear Address Register (IbsDcLinAd) */
100         unsigned int ibs_dc_linear_low;
101         unsigned int ibs_dc_linear_high;
102         /* MSRC001_1039 IBS DC Physical Address Register (IbsDcPhysAd) */
103         unsigned int ibs_dc_phys_low;
104         unsigned int ibs_dc_phys_high;
105 };
106
107 /*
108  * unitialize the APIC for the IBS interrupts if needed on AMD Family10h+
109 */
110 static void clear_ibs_nmi(void);
111
112 static int ibs_allowed; /* AMD Family10h and later */
113
114 struct op_ibs_config {
115         unsigned long op_enabled;
116         unsigned long fetch_enabled;
117         unsigned long max_cnt_fetch;
118         unsigned long max_cnt_op;
119         unsigned long rand_en;
120         unsigned long dispatched_ops;
121 };
122
123 static struct op_ibs_config ibs_config;
124
125 #endif
126
127 /* functions for op_amd_spec */
128
129 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
130 {
131         int i;
132
133         for (i = 0; i < NUM_COUNTERS; i++) {
134                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
135                         msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
136                 else
137                         msrs->counters[i].addr = 0;
138         }
139
140         for (i = 0; i < NUM_CONTROLS; i++) {
141                 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
142                         msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
143                 else
144                         msrs->controls[i].addr = 0;
145         }
146 }
147
148
149 static void op_amd_setup_ctrs(struct op_msrs const * const msrs)
150 {
151         unsigned int low, high;
152         int i;
153
154         /* clear all counters */
155         for (i = 0 ; i < NUM_CONTROLS; ++i) {
156                 if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
157                         continue;
158                 CTRL_READ(low, high, msrs, i);
159                 CTRL_CLEAR_LO(low);
160                 CTRL_CLEAR_HI(high);
161                 CTRL_WRITE(low, high, msrs, i);
162         }
163
164         /* avoid a false detection of ctr overflows in NMI handler */
165         for (i = 0; i < NUM_COUNTERS; ++i) {
166                 if (unlikely(!CTR_IS_RESERVED(msrs, i)))
167                         continue;
168                 CTR_WRITE(1, msrs, i);
169         }
170
171         /* enable active counters */
172         for (i = 0; i < NUM_COUNTERS; ++i) {
173                 if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
174                         reset_value[i] = counter_config[i].count;
175
176                         CTR_WRITE(counter_config[i].count, msrs, i);
177
178                         CTRL_READ(low, high, msrs, i);
179                         CTRL_CLEAR_LO(low);
180                         CTRL_CLEAR_HI(high);
181                         CTRL_SET_ENABLE(low);
182                         CTRL_SET_USR(low, counter_config[i].user);
183                         CTRL_SET_KERN(low, counter_config[i].kernel);
184                         CTRL_SET_UM(low, counter_config[i].unit_mask);
185                         CTRL_SET_EVENT_LOW(low, counter_config[i].event);
186                         CTRL_SET_EVENT_HIGH(high, counter_config[i].event);
187                         CTRL_SET_HOST_ONLY(high, 0);
188                         CTRL_SET_GUEST_ONLY(high, 0);
189
190                         CTRL_WRITE(low, high, msrs, i);
191                 } else {
192                         reset_value[i] = 0;
193                 }
194         }
195 }
196
197 #ifdef CONFIG_OPROFILE_IBS
198
199 static inline int
200 op_amd_handle_ibs(struct pt_regs * const regs,
201                   struct op_msrs const * const msrs)
202 {
203         unsigned int low, high;
204         struct ibs_fetch_sample ibs_fetch;
205         struct ibs_op_sample ibs_op;
206
207         if (!ibs_allowed)
208                 return 1;
209
210         if (ibs_config.fetch_enabled) {
211                 rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
212                 if (high & IBS_FETCH_HIGH_VALID_BIT) {
213                         ibs_fetch.ibs_fetch_ctl_high = high;
214                         ibs_fetch.ibs_fetch_ctl_low = low;
215                         rdmsr(MSR_AMD64_IBSFETCHLINAD, low, high);
216                         ibs_fetch.ibs_fetch_lin_addr_high = high;
217                         ibs_fetch.ibs_fetch_lin_addr_low = low;
218                         rdmsr(MSR_AMD64_IBSFETCHPHYSAD, low, high);
219                         ibs_fetch.ibs_fetch_phys_addr_high = high;
220                         ibs_fetch.ibs_fetch_phys_addr_low = low;
221
222                         oprofile_add_ibs_sample(regs,
223                                                 (unsigned int *)&ibs_fetch,
224                                                 IBS_FETCH_BEGIN);
225
226                         /*reenable the IRQ */
227                         rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
228                         high &= ~IBS_FETCH_HIGH_VALID_BIT;
229                         high |= IBS_FETCH_HIGH_ENABLE;
230                         low &= IBS_FETCH_LOW_MAX_CNT_MASK;
231                         wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
232                 }
233         }
234
235         if (ibs_config.op_enabled) {
236                 rdmsr(MSR_AMD64_IBSOPCTL, low, high);
237                 if (low & IBS_OP_LOW_VALID_BIT) {
238                         rdmsr(MSR_AMD64_IBSOPRIP, low, high);
239                         ibs_op.ibs_op_rip_low = low;
240                         ibs_op.ibs_op_rip_high = high;
241                         rdmsr(MSR_AMD64_IBSOPDATA, low, high);
242                         ibs_op.ibs_op_data1_low = low;
243                         ibs_op.ibs_op_data1_high = high;
244                         rdmsr(MSR_AMD64_IBSOPDATA2, low, high);
245                         ibs_op.ibs_op_data2_low = low;
246                         ibs_op.ibs_op_data2_high = high;
247                         rdmsr(MSR_AMD64_IBSOPDATA3, low, high);
248                         ibs_op.ibs_op_data3_low = low;
249                         ibs_op.ibs_op_data3_high = high;
250                         rdmsr(MSR_AMD64_IBSDCLINAD, low, high);
251                         ibs_op.ibs_dc_linear_low = low;
252                         ibs_op.ibs_dc_linear_high = high;
253                         rdmsr(MSR_AMD64_IBSDCPHYSAD, low, high);
254                         ibs_op.ibs_dc_phys_low = low;
255                         ibs_op.ibs_dc_phys_high = high;
256
257                         /* reenable the IRQ */
258                         oprofile_add_ibs_sample(regs,
259                                                 (unsigned int *)&ibs_op,
260                                                 IBS_OP_BEGIN);
261                         rdmsr(MSR_AMD64_IBSOPCTL, low, high);
262                         high = 0;
263                         low &= ~IBS_OP_LOW_VALID_BIT;
264                         low |= IBS_OP_LOW_ENABLE;
265                         wrmsr(MSR_AMD64_IBSOPCTL, low, high);
266                 }
267         }
268
269         return 1;
270 }
271
272 #endif
273
274 static int op_amd_check_ctrs(struct pt_regs * const regs,
275                              struct op_msrs const * const msrs)
276 {
277         unsigned int low, high;
278         int i;
279
280         for (i = 0 ; i < NUM_COUNTERS; ++i) {
281                 if (!reset_value[i])
282                         continue;
283                 CTR_READ(low, high, msrs, i);
284                 if (CTR_OVERFLOWED(low)) {
285                         oprofile_add_sample(regs, i);
286                         CTR_WRITE(reset_value[i], msrs, i);
287                 }
288         }
289
290 #ifdef CONFIG_OPROFILE_IBS
291         op_amd_handle_ibs(regs, msrs);
292 #endif
293
294         /* See op_model_ppro.c */
295         return 1;
296 }
297
298 static void op_amd_start(struct op_msrs const * const msrs)
299 {
300         unsigned int low, high;
301         int i;
302         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
303                 if (reset_value[i]) {
304                         CTRL_READ(low, high, msrs, i);
305                         CTRL_SET_ACTIVE(low);
306                         CTRL_WRITE(low, high, msrs, i);
307                 }
308         }
309
310 #ifdef CONFIG_OPROFILE_IBS
311         if (ibs_allowed && ibs_config.fetch_enabled) {
312                 low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
313                 high = ((ibs_config.rand_en & 0x1) << 25) /* bit 57 */
314                         + IBS_FETCH_HIGH_ENABLE;
315                 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
316         }
317
318         if (ibs_allowed && ibs_config.op_enabled) {
319                 low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF)
320                         + ((ibs_config.dispatched_ops & 0x1) << 19) /* bit 19 */
321                         + IBS_OP_LOW_ENABLE;
322                 high = 0;
323                 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
324         }
325 #endif
326 }
327
328
329 static void op_amd_stop(struct op_msrs const * const msrs)
330 {
331         unsigned int low, high;
332         int i;
333
334         /* Subtle: stop on all counters to avoid race with
335          * setting our pm callback */
336         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
337                 if (!reset_value[i])
338                         continue;
339                 CTRL_READ(low, high, msrs, i);
340                 CTRL_SET_INACTIVE(low);
341                 CTRL_WRITE(low, high, msrs, i);
342         }
343
344 #ifdef CONFIG_OPROFILE_IBS
345         if (ibs_allowed && ibs_config.fetch_enabled) {
346                 low = 0;                /* clear max count and enable */
347                 high = 0;
348                 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
349         }
350
351         if (ibs_allowed && ibs_config.op_enabled) {
352                 low = 0;                /* clear max count and enable */
353                 high = 0;
354                 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
355         }
356 #endif
357 }
358
359 static void op_amd_shutdown(struct op_msrs const * const msrs)
360 {
361         int i;
362
363         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
364                 if (CTR_IS_RESERVED(msrs, i))
365                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
366         }
367         for (i = 0 ; i < NUM_CONTROLS ; ++i) {
368                 if (CTRL_IS_RESERVED(msrs, i))
369                         release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
370         }
371 }
372
373 #ifndef CONFIG_OPROFILE_IBS
374
375 /* no IBS support */
376
377 static int op_amd_init(struct oprofile_operations *ops)
378 {
379         return 0;
380 }
381
382 static void op_amd_exit(void) {}
383
384 #else
385
386 static u8 ibs_eilvt_off;
387
388 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
389 {
390         ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
391 }
392
393 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
394 {
395         setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
396 }
397
398 static int pfm_amd64_setup_eilvt(void)
399 {
400 #define IBSCTL_LVTOFFSETVAL             (1 << 8)
401 #define IBSCTL                          0x1cc
402         struct pci_dev *cpu_cfg;
403         int nodes;
404         u32 value = 0;
405
406         /* per CPU setup */
407         on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
408
409         nodes = 0;
410         cpu_cfg = NULL;
411         do {
412                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
413                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
414                                          cpu_cfg);
415                 if (!cpu_cfg)
416                         break;
417                 ++nodes;
418                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
419                                        | IBSCTL_LVTOFFSETVAL);
420                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
421                 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
422                         printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
423                                 "IBSCTL = 0x%08x", value);
424                         return 1;
425                 }
426         } while (1);
427
428         if (!nodes) {
429                 printk(KERN_DEBUG "No CPU node configured for IBS");
430                 return 1;
431         }
432
433 #ifdef CONFIG_NUMA
434         /* Sanity check */
435         /* Works only for 64bit with proper numa implementation. */
436         if (nodes != num_possible_nodes()) {
437                 printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, "
438                         "found: %d, expected %d",
439                         nodes, num_possible_nodes());
440                 return 1;
441         }
442 #endif
443         return 0;
444 }
445
446 /*
447  * initialize the APIC for the IBS interrupts
448  * if available (AMD Family10h rev B0 and later)
449  */
450 static void setup_ibs(void)
451 {
452         ibs_allowed = boot_cpu_has(X86_FEATURE_IBS);
453
454         if (!ibs_allowed)
455                 return;
456
457         if (pfm_amd64_setup_eilvt()) {
458                 ibs_allowed = 0;
459                 return;
460         }
461
462         printk(KERN_INFO "oprofile: AMD IBS detected\n");
463 }
464
465
466 /*
467  * unitialize the APIC for the IBS interrupts if needed on AMD Family10h
468  * rev B0 and later */
469 static void clear_ibs_nmi(void)
470 {
471         if (ibs_allowed)
472                 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
473 }
474
475 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
476
477 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
478 {
479         struct dentry *dir;
480         int ret = 0;
481
482         /* architecture specific files */
483         if (create_arch_files)
484                 ret = create_arch_files(sb, root);
485
486         if (ret)
487                 return ret;
488
489         if (!ibs_allowed)
490                 return ret;
491
492         /* model specific files */
493
494         /* setup some reasonable defaults */
495         ibs_config.max_cnt_fetch = 250000;
496         ibs_config.fetch_enabled = 0;
497         ibs_config.max_cnt_op = 250000;
498         ibs_config.op_enabled = 0;
499         ibs_config.dispatched_ops = 1;
500
501         dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
502         oprofilefs_create_ulong(sb, dir, "enable",
503                                 &ibs_config.fetch_enabled);
504         oprofilefs_create_ulong(sb, dir, "max_count",
505                                 &ibs_config.max_cnt_fetch);
506         oprofilefs_create_ulong(sb, dir, "rand_enable",
507                                 &ibs_config.rand_en);
508
509         dir = oprofilefs_mkdir(sb, root, "ibs_op");
510         oprofilefs_create_ulong(sb, dir, "enable",
511                                 &ibs_config.op_enabled);
512         oprofilefs_create_ulong(sb, dir, "max_count",
513                                 &ibs_config.max_cnt_op);
514         oprofilefs_create_ulong(sb, dir, "dispatched_ops",
515                                 &ibs_config.dispatched_ops);
516
517         return 0;
518 }
519
520 static int op_amd_init(struct oprofile_operations *ops)
521 {
522         setup_ibs();
523         create_arch_files = ops->create_files;
524         ops->create_files = setup_ibs_files;
525         return 0;
526 }
527
528 static void op_amd_exit(void)
529 {
530         clear_ibs_nmi();
531 }
532
533 #endif
534
535 struct op_x86_model_spec const op_amd_spec = {
536         .init                   = op_amd_init,
537         .exit                   = op_amd_exit,
538         .num_counters           = NUM_COUNTERS,
539         .num_controls           = NUM_CONTROLS,
540         .fill_in_addresses      = &op_amd_fill_in_addresses,
541         .setup_ctrs             = &op_amd_setup_ctrs,
542         .check_ctrs             = &op_amd_check_ctrs,
543         .start                  = &op_amd_start,
544         .stop                   = &op_amd_stop,
545         .shutdown               = &op_amd_shutdown
546 };