Merge commit 'v2.6.28-rc6' into core/debug
[linux-2.6] / drivers / gpu / drm / i915 / i915_suspend.c
1 /*
2  *
3  * Copyright 2008 (c) Intel Corporation
4  *   Jesse Barnes <jbarnes@virtuousgeek.org>
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the
15  * next paragraph) shall be included in all copies or substantial portions
16  * of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  */
26
27 #include "drmP.h"
28 #include "drm.h"
29 #include "i915_drm.h"
30 #include "i915_drv.h"
31
32 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
33 {
34         struct drm_i915_private *dev_priv = dev->dev_private;
35
36         if (pipe == PIPE_A)
37                 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
38         else
39                 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
40 }
41
42 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
43 {
44         struct drm_i915_private *dev_priv = dev->dev_private;
45         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
46         u32 *array;
47         int i;
48
49         if (!i915_pipe_enabled(dev, pipe))
50                 return;
51
52         if (pipe == PIPE_A)
53                 array = dev_priv->save_palette_a;
54         else
55                 array = dev_priv->save_palette_b;
56
57         for(i = 0; i < 256; i++)
58                 array[i] = I915_READ(reg + (i << 2));
59 }
60
61 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
62 {
63         struct drm_i915_private *dev_priv = dev->dev_private;
64         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
65         u32 *array;
66         int i;
67
68         if (!i915_pipe_enabled(dev, pipe))
69                 return;
70
71         if (pipe == PIPE_A)
72                 array = dev_priv->save_palette_a;
73         else
74                 array = dev_priv->save_palette_b;
75
76         for(i = 0; i < 256; i++)
77                 I915_WRITE(reg + (i << 2), array[i]);
78 }
79
80 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
81 {
82         struct drm_i915_private *dev_priv = dev->dev_private;
83
84         I915_WRITE8(index_port, reg);
85         return I915_READ8(data_port);
86 }
87
88 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
89 {
90         struct drm_i915_private *dev_priv = dev->dev_private;
91
92         I915_READ8(st01);
93         I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
94         return I915_READ8(VGA_AR_DATA_READ);
95 }
96
97 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
98 {
99         struct drm_i915_private *dev_priv = dev->dev_private;
100
101         I915_READ8(st01);
102         I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
103         I915_WRITE8(VGA_AR_DATA_WRITE, val);
104 }
105
106 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
107 {
108         struct drm_i915_private *dev_priv = dev->dev_private;
109
110         I915_WRITE8(index_port, reg);
111         I915_WRITE8(data_port, val);
112 }
113
114 static void i915_save_vga(struct drm_device *dev)
115 {
116         struct drm_i915_private *dev_priv = dev->dev_private;
117         int i;
118         u16 cr_index, cr_data, st01;
119
120         /* VGA color palette registers */
121         dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
122         /* DACCRX automatically increments during read */
123         I915_WRITE8(VGA_DACRX, 0);
124         /* Read 3 bytes of color data from each index */
125         for (i = 0; i < 256 * 3; i++)
126                 dev_priv->saveDACDATA[i] = I915_READ8(VGA_DACDATA);
127
128         /* MSR bits */
129         dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
130         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
131                 cr_index = VGA_CR_INDEX_CGA;
132                 cr_data = VGA_CR_DATA_CGA;
133                 st01 = VGA_ST01_CGA;
134         } else {
135                 cr_index = VGA_CR_INDEX_MDA;
136                 cr_data = VGA_CR_DATA_MDA;
137                 st01 = VGA_ST01_MDA;
138         }
139
140         /* CRT controller regs */
141         i915_write_indexed(dev, cr_index, cr_data, 0x11,
142                            i915_read_indexed(dev, cr_index, cr_data, 0x11) &
143                            (~0x80));
144         for (i = 0; i <= 0x24; i++)
145                 dev_priv->saveCR[i] =
146                         i915_read_indexed(dev, cr_index, cr_data, i);
147         /* Make sure we don't turn off CR group 0 writes */
148         dev_priv->saveCR[0x11] &= ~0x80;
149
150         /* Attribute controller registers */
151         I915_READ8(st01);
152         dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
153         for (i = 0; i <= 0x14; i++)
154                 dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
155         I915_READ8(st01);
156         I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX);
157         I915_READ8(st01);
158
159         /* Graphics controller registers */
160         for (i = 0; i < 9; i++)
161                 dev_priv->saveGR[i] =
162                         i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
163
164         dev_priv->saveGR[0x10] =
165                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
166         dev_priv->saveGR[0x11] =
167                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
168         dev_priv->saveGR[0x18] =
169                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
170
171         /* Sequencer registers */
172         for (i = 0; i < 8; i++)
173                 dev_priv->saveSR[i] =
174                         i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
175 }
176
177 static void i915_restore_vga(struct drm_device *dev)
178 {
179         struct drm_i915_private *dev_priv = dev->dev_private;
180         int i;
181         u16 cr_index, cr_data, st01;
182
183         /* MSR bits */
184         I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR);
185         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
186                 cr_index = VGA_CR_INDEX_CGA;
187                 cr_data = VGA_CR_DATA_CGA;
188                 st01 = VGA_ST01_CGA;
189         } else {
190                 cr_index = VGA_CR_INDEX_MDA;
191                 cr_data = VGA_CR_DATA_MDA;
192                 st01 = VGA_ST01_MDA;
193         }
194
195         /* Sequencer registers, don't write SR07 */
196         for (i = 0; i < 7; i++)
197                 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
198                                    dev_priv->saveSR[i]);
199
200         /* CRT controller regs */
201         /* Enable CR group 0 writes */
202         i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
203         for (i = 0; i <= 0x24; i++)
204                 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);
205
206         /* Graphics controller regs */
207         for (i = 0; i < 9; i++)
208                 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
209                                    dev_priv->saveGR[i]);
210
211         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
212                            dev_priv->saveGR[0x10]);
213         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
214                            dev_priv->saveGR[0x11]);
215         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
216                            dev_priv->saveGR[0x18]);
217
218         /* Attribute controller registers */
219         I915_READ8(st01); /* switch back to index mode */
220         for (i = 0; i <= 0x14; i++)
221                 i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
222         I915_READ8(st01); /* switch back to index mode */
223         I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);
224         I915_READ8(st01);
225
226         /* VGA color palette registers */
227         I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
228         /* DACCRX automatically increments during read */
229         I915_WRITE8(VGA_DACWX, 0);
230         /* Read 3 bytes of color data from each index */
231         for (i = 0; i < 256 * 3; i++)
232                 I915_WRITE8(VGA_DACDATA, dev_priv->saveDACDATA[i]);
233
234 }
235
236 int i915_save_state(struct drm_device *dev)
237 {
238         struct drm_i915_private *dev_priv = dev->dev_private;
239         int i;
240
241         pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
242
243         /* Render Standby */
244         if (IS_I965G(dev) && IS_MOBILE(dev))
245                 dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
246
247         /* Display arbitration control */
248         dev_priv->saveDSPARB = I915_READ(DSPARB);
249
250         /* Pipe & plane A info */
251         dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
252         dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
253         dev_priv->saveFPA0 = I915_READ(FPA0);
254         dev_priv->saveFPA1 = I915_READ(FPA1);
255         dev_priv->saveDPLL_A = I915_READ(DPLL_A);
256         if (IS_I965G(dev))
257                 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
258         dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
259         dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
260         dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
261         dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
262         dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
263         dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
264         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
265
266         dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
267         dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
268         dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
269         dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
270         dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
271         if (IS_I965G(dev)) {
272                 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
273                 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
274         }
275         i915_save_palette(dev, PIPE_A);
276         dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
277
278         /* Pipe & plane B info */
279         dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
280         dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
281         dev_priv->saveFPB0 = I915_READ(FPB0);
282         dev_priv->saveFPB1 = I915_READ(FPB1);
283         dev_priv->saveDPLL_B = I915_READ(DPLL_B);
284         if (IS_I965G(dev))
285                 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
286         dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
287         dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
288         dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
289         dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
290         dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
291         dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
292         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
293
294         dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
295         dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
296         dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
297         dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
298         dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
299         if (IS_I965GM(dev) || IS_GM45(dev)) {
300                 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
301                 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
302         }
303         i915_save_palette(dev, PIPE_B);
304         dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
305
306         /* CRT state */
307         dev_priv->saveADPA = I915_READ(ADPA);
308
309         /* LVDS state */
310         dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
311         dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
312         dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
313         if (IS_I965G(dev))
314                 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
315         if (IS_MOBILE(dev) && !IS_I830(dev))
316                 dev_priv->saveLVDS = I915_READ(LVDS);
317         if (!IS_I830(dev) && !IS_845G(dev))
318                 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
319         dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
320         dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
321         dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
322
323         /* FIXME: save TV & SDVO state */
324
325         /* FBC state */
326         dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
327         dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
328         dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
329         dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
330
331         /* Interrupt state */
332         dev_priv->saveIIR = I915_READ(IIR);
333         dev_priv->saveIER = I915_READ(IER);
334         dev_priv->saveIMR = I915_READ(IMR);
335
336         /* VGA state */
337         dev_priv->saveVGA0 = I915_READ(VGA0);
338         dev_priv->saveVGA1 = I915_READ(VGA1);
339         dev_priv->saveVGA_PD = I915_READ(VGA_PD);
340         dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
341
342         /* Clock gating state */
343         dev_priv->saveD_STATE = I915_READ(D_STATE);
344         dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS);
345
346         /* Cache mode state */
347         dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
348
349         /* Memory Arbitration state */
350         dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
351
352         /* Scratch space */
353         for (i = 0; i < 16; i++) {
354                 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
355                 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
356         }
357         for (i = 0; i < 3; i++)
358                 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
359
360         i915_save_vga(dev);
361
362         return 0;
363 }
364
365 int i915_restore_state(struct drm_device *dev)
366 {
367         struct drm_i915_private *dev_priv = dev->dev_private;
368         int i;
369
370         pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
371
372         /* Render Standby */
373         if (IS_I965G(dev) && IS_MOBILE(dev))
374                 I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
375
376         /* Display arbitration */
377         I915_WRITE(DSPARB, dev_priv->saveDSPARB);
378
379         /* Pipe & plane A info */
380         /* Prime the clock */
381         if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
382                 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
383                            ~DPLL_VCO_ENABLE);
384                 DRM_UDELAY(150);
385         }
386         I915_WRITE(FPA0, dev_priv->saveFPA0);
387         I915_WRITE(FPA1, dev_priv->saveFPA1);
388         /* Actually enable it */
389         I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
390         DRM_UDELAY(150);
391         if (IS_I965G(dev))
392                 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
393         DRM_UDELAY(150);
394
395         /* Restore mode */
396         I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
397         I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
398         I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
399         I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
400         I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
401         I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
402         I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
403
404         /* Restore plane info */
405         I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
406         I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
407         I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
408         I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
409         I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
410         if (IS_I965G(dev)) {
411                 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
412                 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
413         }
414
415         I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
416
417         i915_restore_palette(dev, PIPE_A);
418         /* Enable the plane */
419         I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
420         I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
421
422         /* Pipe & plane B info */
423         if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
424                 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
425                            ~DPLL_VCO_ENABLE);
426                 DRM_UDELAY(150);
427         }
428         I915_WRITE(FPB0, dev_priv->saveFPB0);
429         I915_WRITE(FPB1, dev_priv->saveFPB1);
430         /* Actually enable it */
431         I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
432         DRM_UDELAY(150);
433         if (IS_I965G(dev))
434                 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
435         DRM_UDELAY(150);
436
437         /* Restore mode */
438         I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
439         I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
440         I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
441         I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
442         I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
443         I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
444         I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
445
446         /* Restore plane info */
447         I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
448         I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
449         I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
450         I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
451         I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
452         if (IS_I965G(dev)) {
453                 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
454                 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
455         }
456
457         I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
458
459         i915_restore_palette(dev, PIPE_B);
460         /* Enable the plane */
461         I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
462         I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
463
464         /* CRT state */
465         I915_WRITE(ADPA, dev_priv->saveADPA);
466
467         /* LVDS state */
468         if (IS_I965G(dev))
469                 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
470         if (IS_MOBILE(dev) && !IS_I830(dev))
471                 I915_WRITE(LVDS, dev_priv->saveLVDS);
472         if (!IS_I830(dev) && !IS_845G(dev))
473                 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
474
475         I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
476         I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
477         I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
478         I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
479         I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
480         I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
481
482         /* FIXME: restore TV & SDVO state */
483
484         /* FBC info */
485         I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
486         I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
487         I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
488         I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
489
490         /* VGA state */
491         I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
492         I915_WRITE(VGA0, dev_priv->saveVGA0);
493         I915_WRITE(VGA1, dev_priv->saveVGA1);
494         I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
495         DRM_UDELAY(150);
496
497         /* Clock gating state */
498         I915_WRITE (D_STATE, dev_priv->saveD_STATE);
499         I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS);
500
501         /* Cache mode state */
502         I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
503
504         /* Memory arbitration state */
505         I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
506
507         for (i = 0; i < 16; i++) {
508                 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
509                 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
510         }
511         for (i = 0; i < 3; i++)
512                 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
513
514         i915_restore_vga(dev);
515
516         return 0;
517 }
518