2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/radeon_drm.h>
32 #include "radeon_reg.h"
34 #include "radeon_asic.h"
38 * GPU scratch registers helpers function.
40 static void radeon_scratch_init(struct radeon_device *rdev)
44 /* FIXME: check this out */
45 if (rdev->family < CHIP_R300) {
46 rdev->scratch.num_reg = 5;
48 rdev->scratch.num_reg = 7;
50 for (i = 0; i < rdev->scratch.num_reg; i++) {
51 rdev->scratch.free[i] = true;
52 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
56 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
60 for (i = 0; i < rdev->scratch.num_reg; i++) {
61 if (rdev->scratch.free[i]) {
62 rdev->scratch.free[i] = false;
63 *reg = rdev->scratch.reg[i];
70 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
74 for (i = 0; i < rdev->scratch.num_reg; i++) {
75 if (rdev->scratch.reg[i] == reg) {
76 rdev->scratch.free[i] = true;
85 int radeon_mc_setup(struct radeon_device *rdev)
89 /* Some chips have an "issue" with the memory controller, the
90 * location must be aligned to the size. We just align it down,
91 * too bad if we walk over the top of system memory, we don't
92 * use DMA without a remapped anyway.
93 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
95 /* FGLRX seems to setup like this, VRAM a 0, then GART.
98 * Note: from R6xx the address space is 40bits but here we only
99 * use 32bits (still have to see a card which would exhaust 4G
102 if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
103 /* vram location was already setup try to put gtt after
105 tmp = rdev->mc.vram_location + rdev->mc.vram_size;
106 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
107 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
108 rdev->mc.gtt_location = tmp;
110 if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
111 printk(KERN_ERR "[drm] GTT too big to fit "
112 "before or after vram location.\n");
115 rdev->mc.gtt_location = 0;
117 } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
118 /* gtt location was already setup try to put vram before
120 if (rdev->mc.vram_size < rdev->mc.gtt_location) {
121 rdev->mc.vram_location = 0;
123 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
124 tmp += (rdev->mc.vram_size - 1);
125 tmp &= ~(rdev->mc.vram_size - 1);
126 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) {
127 rdev->mc.vram_location = tmp;
129 printk(KERN_ERR "[drm] vram too big to fit "
130 "before or after GTT location.\n");
135 rdev->mc.vram_location = 0;
136 rdev->mc.gtt_location = rdev->mc.vram_size;
138 DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20);
139 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
140 rdev->mc.vram_location,
141 rdev->mc.vram_location + rdev->mc.vram_size - 1);
142 DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20);
143 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
144 rdev->mc.gtt_location,
145 rdev->mc.gtt_location + rdev->mc.gtt_size - 1);
151 * GPU helpers function.
153 static bool radeon_card_posted(struct radeon_device *rdev)
157 /* first check CRTCs */
158 if (ASIC_IS_AVIVO(rdev)) {
159 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
160 RREG32(AVIVO_D2CRTC_CONTROL);
161 if (reg & AVIVO_CRTC_EN) {
165 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
166 RREG32(RADEON_CRTC2_GEN_CNTL);
167 if (reg & RADEON_CRTC_EN) {
172 /* then check MEM_SIZE, in case the crtcs are off */
173 if (rdev->family >= CHIP_R600)
174 reg = RREG32(R600_CONFIG_MEMSIZE);
176 reg = RREG32(RADEON_CONFIG_MEMSIZE);
187 * Registers accessors functions.
189 uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
191 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
196 void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
198 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
203 void radeon_register_accessor_init(struct radeon_device *rdev)
205 rdev->mm_rreg = &r100_mm_rreg;
206 rdev->mm_wreg = &r100_mm_wreg;
207 rdev->mc_rreg = &radeon_invalid_rreg;
208 rdev->mc_wreg = &radeon_invalid_wreg;
209 rdev->pll_rreg = &radeon_invalid_rreg;
210 rdev->pll_wreg = &radeon_invalid_wreg;
211 rdev->pcie_rreg = &radeon_invalid_rreg;
212 rdev->pcie_wreg = &radeon_invalid_wreg;
213 rdev->pciep_rreg = &radeon_invalid_rreg;
214 rdev->pciep_wreg = &radeon_invalid_wreg;
216 /* Don't change order as we are overridding accessor. */
217 if (rdev->family < CHIP_RV515) {
218 rdev->pcie_rreg = &rv370_pcie_rreg;
219 rdev->pcie_wreg = &rv370_pcie_wreg;
221 if (rdev->family >= CHIP_RV515) {
222 rdev->pcie_rreg = &rv515_pcie_rreg;
223 rdev->pcie_wreg = &rv515_pcie_wreg;
225 /* FIXME: not sure here */
226 if (rdev->family <= CHIP_R580) {
227 rdev->pll_rreg = &r100_pll_rreg;
228 rdev->pll_wreg = &r100_pll_wreg;
230 if (rdev->family >= CHIP_RV515) {
231 rdev->mc_rreg = &rv515_mc_rreg;
232 rdev->mc_wreg = &rv515_mc_wreg;
234 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
235 rdev->mc_rreg = &rs400_mc_rreg;
236 rdev->mc_wreg = &rs400_mc_wreg;
238 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
239 rdev->mc_rreg = &rs690_mc_rreg;
240 rdev->mc_wreg = &rs690_mc_wreg;
242 if (rdev->family == CHIP_RS600) {
243 rdev->mc_rreg = &rs600_mc_rreg;
244 rdev->mc_wreg = &rs600_mc_wreg;
246 if (rdev->family >= CHIP_R600) {
247 rdev->pciep_rreg = &r600_pciep_rreg;
248 rdev->pciep_wreg = &r600_pciep_wreg;
256 int radeon_asic_init(struct radeon_device *rdev)
258 radeon_register_accessor_init(rdev);
259 switch (rdev->family) {
269 rdev->asic = &r100_asic;
275 rdev->asic = &r300_asic;
280 rdev->asic = &r420_asic;
284 rdev->asic = &rs400_asic;
287 rdev->asic = &rs600_asic;
291 rdev->asic = &rs690_asic;
294 rdev->asic = &rv515_asic;
301 rdev->asic = &r520_asic;
314 /* FIXME: not supported yet */
322 * Wrapper around modesetting bits.
324 int radeon_clocks_init(struct radeon_device *rdev)
328 radeon_get_clock_info(rdev->ddev);
329 r = radeon_static_clocks_init(rdev->ddev);
333 DRM_INFO("Clocks initialized !\n");
337 void radeon_clocks_fini(struct radeon_device *rdev)
341 /* ATOM accessor methods */
342 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
344 struct radeon_device *rdev = info->dev->dev_private;
347 r = rdev->pll_rreg(rdev, reg);
351 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
353 struct radeon_device *rdev = info->dev->dev_private;
355 rdev->pll_wreg(rdev, reg, val);
358 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
360 struct radeon_device *rdev = info->dev->dev_private;
363 r = rdev->mc_rreg(rdev, reg);
367 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
369 struct radeon_device *rdev = info->dev->dev_private;
371 rdev->mc_wreg(rdev, reg, val);
374 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
376 struct radeon_device *rdev = info->dev->dev_private;
381 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
383 struct radeon_device *rdev = info->dev->dev_private;
390 static struct card_info atom_card_info = {
392 .reg_read = cail_reg_read,
393 .reg_write = cail_reg_write,
394 .mc_read = cail_mc_read,
395 .mc_write = cail_mc_write,
396 .pll_read = cail_pll_read,
397 .pll_write = cail_pll_write,
400 int radeon_atombios_init(struct radeon_device *rdev)
402 atom_card_info.dev = rdev->ddev;
403 rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
404 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
408 void radeon_atombios_fini(struct radeon_device *rdev)
410 kfree(rdev->mode_info.atom_context);
413 int radeon_combios_init(struct radeon_device *rdev)
415 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
419 void radeon_combios_fini(struct radeon_device *rdev)
423 int radeon_modeset_init(struct radeon_device *rdev);
424 void radeon_modeset_fini(struct radeon_device *rdev);
430 int radeon_device_init(struct radeon_device *rdev,
431 struct drm_device *ddev,
432 struct pci_dev *pdev,
437 DRM_INFO("radeon: Initializing kernel modesetting.\n");
438 rdev->shutdown = false;
442 rdev->family = flags & RADEON_FAMILY_MASK;
443 rdev->is_atom_bios = false;
444 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
445 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
446 rdev->gpu_lockup = false;
447 /* mutex initialization are all done here so we
448 * can recall function without having locking issues */
449 mutex_init(&rdev->cs_mutex);
450 mutex_init(&rdev->ib_pool.mutex);
451 mutex_init(&rdev->cp.mutex);
452 rwlock_init(&rdev->fence_drv.lock);
454 if (radeon_agpmode == -1) {
455 rdev->flags &= ~RADEON_IS_AGP;
456 if (rdev->family > CHIP_RV515 ||
457 rdev->family == CHIP_RV380 ||
458 rdev->family == CHIP_RV410 ||
459 rdev->family == CHIP_R423) {
460 DRM_INFO("Forcing AGP to PCIE mode\n");
461 rdev->flags |= RADEON_IS_PCIE;
463 DRM_INFO("Forcing AGP to PCI mode\n");
464 rdev->flags |= RADEON_IS_PCI;
468 /* Set asic functions */
469 r = radeon_asic_init(rdev);
473 r = radeon_init(rdev);
478 /* Report DMA addressing limitation */
479 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
481 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
484 /* Registers mapping */
485 /* TODO: block userspace mapping of io register */
486 rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
487 rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
488 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
489 if (rdev->rmmio == NULL) {
492 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
493 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
495 /* Setup errata flags */
497 /* Initialize scratch registers */
498 radeon_scratch_init(rdev);
500 /* TODO: disable VGA need to use VGA request */
502 if (!radeon_get_bios(rdev)) {
503 if (ASIC_IS_AVIVO(rdev))
506 if (rdev->is_atom_bios) {
507 r = radeon_atombios_init(rdev);
512 r = radeon_combios_init(rdev);
517 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
518 if (radeon_gpu_reset(rdev)) {
519 /* FIXME: what do we want to do here ? */
521 /* check if cards are posted or not */
522 if (!radeon_card_posted(rdev) && rdev->bios) {
523 DRM_INFO("GPU not posted. posting now...\n");
524 if (rdev->is_atom_bios) {
525 atom_asic_init(rdev->mode_info.atom_context);
527 radeon_combios_asic_init(rdev->ddev);
530 /* Get vram informations */
531 radeon_vram_info(rdev);
532 /* Device is severly broken if aper size > vram size.
533 * for RN50/M6/M7 - Novell bug 204882 ?
535 if (rdev->mc.vram_size < rdev->mc.aper_size) {
536 rdev->mc.aper_size = rdev->mc.vram_size;
538 /* Add an MTRR for the VRAM */
539 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
540 MTRR_TYPE_WRCOMB, 1);
541 DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
542 rdev->mc.vram_size >> 20,
543 (unsigned)rdev->mc.aper_size >> 20);
544 DRM_INFO("RAM width %dbits %cDR\n",
545 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
546 /* Initialize clocks */
547 r = radeon_clocks_init(rdev);
551 /* Initialize memory controller (also test AGP) */
552 r = radeon_mc_init(rdev);
557 r = radeon_fence_driver_init(rdev);
561 r = radeon_irq_kms_init(rdev);
566 r = radeon_object_init(rdev);
570 /* Initialize GART (initialize after TTM so we can allocate
571 * memory through TTM but finalize after TTM) */
572 r = radeon_gart_enable(rdev);
574 r = radeon_gem_init(rdev);
579 r = radeon_cp_init(rdev, 1024 * 1024);
582 r = radeon_wb_init(rdev);
584 DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
589 r = radeon_ib_pool_init(rdev);
591 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
596 r = radeon_ib_test(rdev);
598 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
603 r = radeon_modeset_init(rdev);
607 if (rdev->fbdev_rfb && rdev->fbdev_rfb->obj) {
608 rdev->fbdev_robj = rdev->fbdev_rfb->obj->driver_private;
611 DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
613 if (radeon_benchmarking) {
614 radeon_benchmark(rdev);
619 void radeon_device_fini(struct radeon_device *rdev)
621 if (rdev == NULL || rdev->rmmio == NULL) {
624 DRM_INFO("radeon: finishing device.\n");
625 rdev->shutdown = true;
626 /* Order matter so becarefull if you rearrange anythings */
627 radeon_modeset_fini(rdev);
628 radeon_ib_pool_fini(rdev);
629 radeon_cp_fini(rdev);
630 radeon_wb_fini(rdev);
631 radeon_gem_fini(rdev);
632 radeon_object_fini(rdev);
633 /* mc_fini must be after object_fini */
634 radeon_mc_fini(rdev);
636 radeon_agp_fini(rdev);
638 radeon_irq_kms_fini(rdev);
639 radeon_fence_driver_fini(rdev);
640 radeon_clocks_fini(rdev);
641 if (rdev->is_atom_bios) {
642 radeon_atombios_fini(rdev);
644 radeon_combios_fini(rdev);
648 iounmap(rdev->rmmio);
656 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
658 struct radeon_device *rdev = dev->dev_private;
659 struct drm_crtc *crtc;
661 if (dev == NULL || rdev == NULL) {
664 if (state.event == PM_EVENT_PRETHAW) {
667 /* unpin the front buffers */
668 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
669 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
670 struct radeon_object *robj;
672 if (rfb == NULL || rfb->obj == NULL) {
675 robj = rfb->obj->driver_private;
676 if (robj != rdev->fbdev_robj) {
677 radeon_object_unpin(robj);
680 /* evict vram memory */
681 radeon_object_evict_vram(rdev);
682 /* wait for gpu to finish processing current batch */
683 radeon_fence_wait_last(rdev);
685 radeon_cp_disable(rdev);
686 radeon_gart_disable(rdev);
688 /* evict remaining vram memory */
689 radeon_object_evict_vram(rdev);
691 rdev->irq.sw_int = false;
692 radeon_irq_set(rdev);
694 pci_save_state(dev->pdev);
695 if (state.event == PM_EVENT_SUSPEND) {
696 /* Shut down the device */
697 pci_disable_device(dev->pdev);
698 pci_set_power_state(dev->pdev, PCI_D3hot);
700 acquire_console_sem();
701 fb_set_suspend(rdev->fbdev_info, 1);
702 release_console_sem();
706 int radeon_resume_kms(struct drm_device *dev)
708 struct radeon_device *rdev = dev->dev_private;
711 acquire_console_sem();
712 pci_set_power_state(dev->pdev, PCI_D0);
713 pci_restore_state(dev->pdev);
714 if (pci_enable_device(dev->pdev)) {
715 release_console_sem();
718 pci_set_master(dev->pdev);
719 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
720 if (radeon_gpu_reset(rdev)) {
721 /* FIXME: what do we want to do here ? */
724 if (rdev->is_atom_bios) {
725 atom_asic_init(rdev->mode_info.atom_context);
727 radeon_combios_asic_init(rdev->ddev);
729 /* Initialize clocks */
730 r = radeon_clocks_init(rdev);
732 release_console_sem();
736 rdev->irq.sw_int = true;
737 radeon_irq_set(rdev);
738 /* Initialize GPU Memory Controller */
739 r = radeon_mc_init(rdev);
743 r = radeon_gart_enable(rdev);
747 r = radeon_cp_init(rdev, rdev->cp.ring_size);
752 fb_set_suspend(rdev->fbdev_info, 0);
753 release_console_sem();
755 /* blat the mode back in */
756 drm_helper_resume_force_mode(dev);
764 struct radeon_debugfs {
765 struct drm_info_list *files;
768 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
769 static unsigned _radeon_debugfs_count = 0;
771 int radeon_debugfs_add_files(struct radeon_device *rdev,
772 struct drm_info_list *files,
777 for (i = 0; i < _radeon_debugfs_count; i++) {
778 if (_radeon_debugfs[i].files == files) {
779 /* Already registered */
783 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
784 DRM_ERROR("Reached maximum number of debugfs files.\n");
785 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
788 _radeon_debugfs[_radeon_debugfs_count].files = files;
789 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
790 _radeon_debugfs_count++;
791 #if defined(CONFIG_DEBUG_FS)
792 drm_debugfs_create_files(files, nfiles,
793 rdev->ddev->control->debugfs_root,
794 rdev->ddev->control);
795 drm_debugfs_create_files(files, nfiles,
796 rdev->ddev->primary->debugfs_root,
797 rdev->ddev->primary);
802 #if defined(CONFIG_DEBUG_FS)
803 int radeon_debugfs_init(struct drm_minor *minor)
808 void radeon_debugfs_cleanup(struct drm_minor *minor)
812 for (i = 0; i < _radeon_debugfs_count; i++) {
813 drm_debugfs_remove_files(_radeon_debugfs[i].files,
814 _radeon_debugfs[i].num_files, minor);