git.oblomov.eu Git - linux-2.6/blob - drivers/infiniband/hw/ipath/ipath_iba6110.c

   1 /*
   2  * Copyright (c) 2006 QLogic, Inc. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 /*
  35  * This file contains all of the code that is specific to the InfiniPath
  36  * HT chip.
  37  */
  38
  39 #include <linux/pci.h>
  40 #include <linux/delay.h>
  41
  42 #include "ipath_kernel.h"
  43 #include "ipath_registers.h"
  44
  45 /*
  46  * This lists the InfiniPath registers, in the actual chip layout.
  47  * This structure should never be directly accessed.
  48  *
  49  * The names are in InterCap form because they're taken straight from
  50  * the chip specification.  Since they're only used in this file, they
  51  * don't pollute the rest of the source.
  52 */
  53
  54 struct _infinipath_do_not_use_kernel_regs {
  55         unsigned long long Revision;
  56         unsigned long long Control;
  57         unsigned long long PageAlign;
  58         unsigned long long PortCnt;
  59         unsigned long long DebugPortSelect;
  60         unsigned long long DebugPort;
  61         unsigned long long SendRegBase;
  62         unsigned long long UserRegBase;
  63         unsigned long long CounterRegBase;
  64         unsigned long long Scratch;
  65         unsigned long long ReservedMisc1;
  66         unsigned long long InterruptConfig;
  67         unsigned long long IntBlocked;
  68         unsigned long long IntMask;
  69         unsigned long long IntStatus;
  70         unsigned long long IntClear;
  71         unsigned long long ErrorMask;
  72         unsigned long long ErrorStatus;
  73         unsigned long long ErrorClear;
  74         unsigned long long HwErrMask;
  75         unsigned long long HwErrStatus;
  76         unsigned long long HwErrClear;
  77         unsigned long long HwDiagCtrl;
  78         unsigned long long MDIO;
  79         unsigned long long IBCStatus;
  80         unsigned long long IBCCtrl;
  81         unsigned long long ExtStatus;
  82         unsigned long long ExtCtrl;
  83         unsigned long long GPIOOut;
  84         unsigned long long GPIOMask;
  85         unsigned long long GPIOStatus;
  86         unsigned long long GPIOClear;
  87         unsigned long long RcvCtrl;
  88         unsigned long long RcvBTHQP;
  89         unsigned long long RcvHdrSize;
  90         unsigned long long RcvHdrCnt;
  91         unsigned long long RcvHdrEntSize;
  92         unsigned long long RcvTIDBase;
  93         unsigned long long RcvTIDCnt;
  94         unsigned long long RcvEgrBase;
  95         unsigned long long RcvEgrCnt;
  96         unsigned long long RcvBufBase;
  97         unsigned long long RcvBufSize;
  98         unsigned long long RxIntMemBase;
  99         unsigned long long RxIntMemSize;
 100         unsigned long long RcvPartitionKey;
 101         unsigned long long ReservedRcv[10];
 102         unsigned long long SendCtrl;
 103         unsigned long long SendPIOBufBase;
 104         unsigned long long SendPIOSize;
 105         unsigned long long SendPIOBufCnt;
 106         unsigned long long SendPIOAvailAddr;
 107         unsigned long long TxIntMemBase;
 108         unsigned long long TxIntMemSize;
 109         unsigned long long ReservedSend[9];
 110         unsigned long long SendBufferError;
 111         unsigned long long SendBufferErrorCONT1;
 112         unsigned long long SendBufferErrorCONT2;
 113         unsigned long long SendBufferErrorCONT3;
 114         unsigned long long ReservedSBE[4];
 115         unsigned long long RcvHdrAddr0;
 116         unsigned long long RcvHdrAddr1;
 117         unsigned long long RcvHdrAddr2;
 118         unsigned long long RcvHdrAddr3;
 119         unsigned long long RcvHdrAddr4;
 120         unsigned long long RcvHdrAddr5;
 121         unsigned long long RcvHdrAddr6;
 122         unsigned long long RcvHdrAddr7;
 123         unsigned long long RcvHdrAddr8;
 124         unsigned long long ReservedRHA[7];
 125         unsigned long long RcvHdrTailAddr0;
 126         unsigned long long RcvHdrTailAddr1;
 127         unsigned long long RcvHdrTailAddr2;
 128         unsigned long long RcvHdrTailAddr3;
 129         unsigned long long RcvHdrTailAddr4;
 130         unsigned long long RcvHdrTailAddr5;
 131         unsigned long long RcvHdrTailAddr6;
 132         unsigned long long RcvHdrTailAddr7;
 133         unsigned long long RcvHdrTailAddr8;
 134         unsigned long long ReservedRHTA[7];
 135         unsigned long long Sync;        /* Software only */
 136         unsigned long long Dump;        /* Software only */
 137         unsigned long long SimVer;      /* Software only */
 138         unsigned long long ReservedSW[5];
 139         unsigned long long SerdesConfig0;
 140         unsigned long long SerdesConfig1;
 141         unsigned long long SerdesStatus;
 142         unsigned long long XGXSConfig;
 143         unsigned long long ReservedSW2[4];
 144 };
 145
 146 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
 147     _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
 148 #define IPATH_CREG_OFFSET(field) (offsetof( \
 149     struct infinipath_counters, field) / sizeof(u64))
 150
 151 static const struct ipath_kregs ipath_ht_kregs = {
 152         .kr_control = IPATH_KREG_OFFSET(Control),
 153         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
 154         .kr_debugport = IPATH_KREG_OFFSET(DebugPort),
 155         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
 156         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
 157         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
 158         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
 159         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
 160         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
 161         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
 162         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
 163         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
 164         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
 165         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
 166         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
 167         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
 168         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
 169         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
 170         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
 171         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
 172         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
 173         .kr_interruptconfig = IPATH_KREG_OFFSET(InterruptConfig),
 174         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
 175         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
 176         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
 177         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
 178         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
 179         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
 180         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
 181         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
 182         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
 183         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
 184         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
 185         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
 186         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
 187         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
 188         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
 189         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
 190         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
 191         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
 192         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
 193         .kr_revision = IPATH_KREG_OFFSET(Revision),
 194         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
 195         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
 196         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
 197         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
 198         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
 199         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
 200         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
 201         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
 202         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
 203         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
 204         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
 205         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
 206         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
 207         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
 208         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
 209         /*
 210          * These should not be used directly via ipath_read_kreg64(),
 211          * use them with ipath_read_kreg64_port(),
 212          */
 213         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
 214         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0)
 215 };
 216
 217 static const struct ipath_cregs ipath_ht_cregs = {
 218         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
 219         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
 220         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
 221         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
 222         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
 223         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
 224         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
 225         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
 226         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
 227         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
 228         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
 229         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
 230         /* calc from Reg_CounterRegBase + offset */
 231         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
 232         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
 233         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
 234         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
 235         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
 236         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
 237         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
 238         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
 239         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
 240         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
 241         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
 242         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
 243         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
 244         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
 245         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
 246         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
 247         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
 248         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
 249         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
 250         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
 251         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
 252 };
 253
 254 /* kr_intstatus, kr_intclear, kr_intmask bits */
 255 #define INFINIPATH_I_RCVURG_MASK ((1U<<9)-1)
 256 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<9)-1)
 257
 258 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
 259 #define INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT 0
 260 #define INFINIPATH_HWE_HTCMEMPARITYERR_MASK 0x3FFFFFULL
 261 #define INFINIPATH_HWE_HTCLNKABYTE0CRCERR   0x0000000000800000ULL
 262 #define INFINIPATH_HWE_HTCLNKABYTE1CRCERR   0x0000000001000000ULL
 263 #define INFINIPATH_HWE_HTCLNKBBYTE0CRCERR   0x0000000002000000ULL
 264 #define INFINIPATH_HWE_HTCLNKBBYTE1CRCERR   0x0000000004000000ULL
 265 #define INFINIPATH_HWE_HTCMISCERR4          0x0000000008000000ULL
 266 #define INFINIPATH_HWE_HTCMISCERR5          0x0000000010000000ULL
 267 #define INFINIPATH_HWE_HTCMISCERR6          0x0000000020000000ULL
 268 #define INFINIPATH_HWE_HTCMISCERR7          0x0000000040000000ULL
 269 #define INFINIPATH_HWE_HTCBUSTREQPARITYERR  0x0000000080000000ULL
 270 #define INFINIPATH_HWE_HTCBUSTRESPPARITYERR 0x0000000100000000ULL
 271 #define INFINIPATH_HWE_HTCBUSIREQPARITYERR  0x0000000200000000ULL
 272 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
 273 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
 274 #define INFINIPATH_HWE_HTBPLL_FBSLIP        0x0200000000000000ULL
 275 #define INFINIPATH_HWE_HTBPLL_RFSLIP        0x0400000000000000ULL
 276 #define INFINIPATH_HWE_HTAPLL_FBSLIP        0x0800000000000000ULL
 277 #define INFINIPATH_HWE_HTAPLL_RFSLIP        0x1000000000000000ULL
 278 #define INFINIPATH_HWE_SERDESPLLFAILED      0x2000000000000000ULL
 279
 280 /* kr_extstatus bits */
 281 #define INFINIPATH_EXTS_FREQSEL 0x2
 282 #define INFINIPATH_EXTS_SERDESSEL 0x4
 283 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
 284 #define INFINIPATH_EXTS_MEMBIST_CORRECT     0x0000000000008000
 285
 286 /*
 287  * masks and bits that are different in different chips, or present only
 288  * in one
 289  */
 290 static const ipath_err_t infinipath_hwe_htcmemparityerr_mask =
 291     INFINIPATH_HWE_HTCMEMPARITYERR_MASK;
 292 static const ipath_err_t infinipath_hwe_htcmemparityerr_shift =
 293     INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT;
 294
 295 static const ipath_err_t infinipath_hwe_htclnkabyte0crcerr =
 296     INFINIPATH_HWE_HTCLNKABYTE0CRCERR;
 297 static const ipath_err_t infinipath_hwe_htclnkabyte1crcerr =
 298     INFINIPATH_HWE_HTCLNKABYTE1CRCERR;
 299 static const ipath_err_t infinipath_hwe_htclnkbbyte0crcerr =
 300     INFINIPATH_HWE_HTCLNKBBYTE0CRCERR;
 301 static const ipath_err_t infinipath_hwe_htclnkbbyte1crcerr =
 302     INFINIPATH_HWE_HTCLNKBBYTE1CRCERR;
 303
 304 #define _IPATH_GPIO_SDA_NUM 1
 305 #define _IPATH_GPIO_SCL_NUM 0
 306
 307 #define IPATH_GPIO_SDA \
 308         (1ULL << (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 309 #define IPATH_GPIO_SCL \
 310         (1ULL << (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 311
 312 /* keep the code below somewhat more readonable; not used elsewhere */
 313 #define _IPATH_HTLINK0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
 314                                 infinipath_hwe_htclnkabyte1crcerr)
 315 #define _IPATH_HTLINK1_CRCBITS (infinipath_hwe_htclnkbbyte0crcerr |     \
 316                                 infinipath_hwe_htclnkbbyte1crcerr)
 317 #define _IPATH_HTLANE0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
 318                                 infinipath_hwe_htclnkbbyte0crcerr)
 319 #define _IPATH_HTLANE1_CRCBITS (infinipath_hwe_htclnkabyte1crcerr |     \
 320                                 infinipath_hwe_htclnkbbyte1crcerr)
 321
 322 static void hwerr_crcbits(struct ipath_devdata *dd, ipath_err_t hwerrs,
 323                           char *msg, size_t msgl)
 324 {
 325         char bitsmsg[64];
 326         ipath_err_t crcbits = hwerrs &
 327                 (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS);
 328         /* don't check if 8bit HT */
 329         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
 330                 crcbits &= ~infinipath_hwe_htclnkabyte1crcerr;
 331         /* don't check if 8bit HT */
 332         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
 333                 crcbits &= ~infinipath_hwe_htclnkbbyte1crcerr;
 334         /*
 335          * we'll want to ignore link errors on link that is
 336          * not in use, if any.  For now, complain about both
 337          */
 338         if (crcbits) {
 339                 u16 ctrl0, ctrl1;
 340                 snprintf(bitsmsg, sizeof bitsmsg,
 341                          "[HT%s lane %s CRC (%llx); powercycle to completely clear]",
 342                          !(crcbits & _IPATH_HTLINK1_CRCBITS) ?
 343                          "0 (A)" : (!(crcbits & _IPATH_HTLINK0_CRCBITS)
 344                                     ? "1 (B)" : "0+1 (A+B)"),
 345                          !(crcbits & _IPATH_HTLANE1_CRCBITS) ? "0"
 346                          : (!(crcbits & _IPATH_HTLANE0_CRCBITS) ? "1" :
 347                             "0+1"), (unsigned long long) crcbits);
 348                 strlcat(msg, bitsmsg, msgl);
 349
 350                 /*
 351                  * print extra info for debugging.  slave/primary
 352                  * config word 4, 8 (link control 0, 1)
 353                  */
 354
 355                 if (pci_read_config_word(dd->pcidev,
 356                                          dd->ipath_ht_slave_off + 0x4,
 357                                          &ctrl0))
 358                         dev_info(&dd->pcidev->dev, "Couldn't read "
 359                                  "linkctrl0 of slave/primary "
 360                                  "config block\n");
 361                 else if (!(ctrl0 & 1 << 6))
 362                         /* not if EOC bit set */
 363                         ipath_dbg("HT linkctrl0 0x%x%s%s\n", ctrl0,
 364                                   ((ctrl0 >> 8) & 7) ? " CRC" : "",
 365                                   ((ctrl0 >> 4) & 1) ? "linkfail" :
 366                                   "");
 367                 if (pci_read_config_word(dd->pcidev,
 368                                          dd->ipath_ht_slave_off + 0x8,
 369                                          &ctrl1))
 370                         dev_info(&dd->pcidev->dev, "Couldn't read "
 371                                  "linkctrl1 of slave/primary "
 372                                  "config block\n");
 373                 else if (!(ctrl1 & 1 << 6))
 374                         /* not if EOC bit set */
 375                         ipath_dbg("HT linkctrl1 0x%x%s%s\n", ctrl1,
 376                                   ((ctrl1 >> 8) & 7) ? " CRC" : "",
 377                                   ((ctrl1 >> 4) & 1) ? "linkfail" :
 378                                   "");
 379
 380                 /* disable until driver reloaded */
 381                 dd->ipath_hwerrmask &= ~crcbits;
 382                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 383                                  dd->ipath_hwerrmask);
 384                 ipath_dbg("HT crc errs: %s\n", msg);
 385         } else
 386                 ipath_dbg("ignoring HT crc errors 0x%llx, "
 387                           "not in use\n", (unsigned long long)
 388                           (hwerrs & (_IPATH_HTLINK0_CRCBITS |
 389                                      _IPATH_HTLINK1_CRCBITS)));
 390 }
 391
 392 /* 6110 specific hardware errors... */
 393 static const struct ipath_hwerror_msgs ipath_6110_hwerror_msgs[] = {
 394         INFINIPATH_HWE_MSG(HTCBUSIREQPARITYERR, "HTC Ireq Parity"),
 395         INFINIPATH_HWE_MSG(HTCBUSTREQPARITYERR, "HTC Treq Parity"),
 396         INFINIPATH_HWE_MSG(HTCBUSTRESPPARITYERR, "HTC Tresp Parity"),
 397         INFINIPATH_HWE_MSG(HTCMISCERR5, "HT core Misc5"),
 398         INFINIPATH_HWE_MSG(HTCMISCERR6, "HT core Misc6"),
 399         INFINIPATH_HWE_MSG(HTCMISCERR7, "HT core Misc7"),
 400         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
 401         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
 402 };
 403
 404 /**
 405  * ipath_ht_handle_hwerrors - display hardware errors.
 406  * @dd: the infinipath device
 407  * @msg: the output buffer
 408  * @msgl: the size of the output buffer
 409  *
 410  * Use same msg buffer as regular errors to avoid excessive stack
 411  * use.  Most hardware errors are catastrophic, but for right now,
 412  * we'll print them and continue.  We reuse the same message buffer as
 413  * ipath_handle_errors() to avoid excessive stack usage.
 414  */
 415 static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
 416                                      size_t msgl)
 417 {
 418         ipath_err_t hwerrs;
 419         u32 bits, ctrl;
 420         int isfatal = 0;
 421         char bitsmsg[64];
 422
 423         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
 424
 425         if (!hwerrs) {
 426                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
 427                 /*
 428                  * better than printing cofusing messages
 429                  * This seems to be related to clearing the crc error, or
 430                  * the pll error during init.
 431                  */
 432                 goto bail;
 433         } else if (hwerrs == -1LL) {
 434                 ipath_dev_err(dd, "Read of hardware error status failed "
 435                               "(all bits set); ignoring\n");
 436                 goto bail;
 437         }
 438         ipath_stats.sps_hwerrs++;
 439
 440         /* Always clear the error status register, except MEMBISTFAIL,
 441          * regardless of whether we continue or stop using the chip.
 442          * We want that set so we know it failed, even across driver reload.
 443          * We'll still ignore it in the hwerrmask.  We do this partly for
 444          * diagnostics, but also for support */
 445         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 446                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
 447
 448         hwerrs &= dd->ipath_hwerrmask;
 449
 450         /*
 451          * make sure we get this much out, unless told to be quiet,
 452          * or it's occurred within the last 5 seconds
 453          */
 454         if ((hwerrs & ~(dd->ipath_lasthwerror |
 455                         ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
 456                           INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
 457                         << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT))) ||
 458             (ipath_debug & __IPATH_VERBDBG))
 459                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
 460                          "(cleared)\n", (unsigned long long) hwerrs);
 461         dd->ipath_lasthwerror |= hwerrs;
 462
 463         if (hwerrs & ~dd->ipath_hwe_bitsextant)
 464                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
 465                               "%llx set\n", (unsigned long long)
 466                               (hwerrs & ~dd->ipath_hwe_bitsextant));
 467
 468         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
 469         if (ctrl & INFINIPATH_C_FREEZEMODE) {
 470                 /*
 471                  * parity errors in send memory are recoverable,
 472                  * just cancel the send (if indicated in * sendbuffererror),
 473                  * count the occurrence, unfreeze (if no other handled
 474                  * hardware error bits are set), and continue. They can
 475                  * occur if a processor speculative read is done to the PIO
 476                  * buffer while we are sending a packet, for example.
 477                  */
 478                 if (hwerrs & ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
 479                                INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
 480                               << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)) {
 481                         ipath_stats.sps_txeparity++;
 482                         ipath_dbg("Recovering from TXE parity error (%llu), "
 483                                   "hwerrstatus=%llx\n",
 484                                   (unsigned long long) ipath_stats.sps_txeparity,
 485                                   (unsigned long long) hwerrs);
 486                         ipath_disarm_senderrbufs(dd);
 487                         hwerrs &= ~((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
 488                                      INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
 489                                     << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT);
 490                         if (!hwerrs) { /* else leave in freeze mode */
 491                                 ipath_write_kreg(dd,
 492                                                  dd->ipath_kregs->kr_control,
 493                                                  dd->ipath_control);
 494                                 return;
 495                         }
 496                 }
 497                 if (hwerrs) {
 498                         /*
 499                          * if any set that we aren't ignoring; only
 500                          * make the complaint once, in case it's stuck
 501                          * or recurring, and we get here multiple
 502                          * times.
 503                          */
 504                         if (dd->ipath_flags & IPATH_INITTED) {
 505                                 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
 506                                               "mode), no longer usable, SN %.16s\n",
 507                                                   dd->ipath_serial);
 508                                 isfatal = 1;
 509                         }
 510                         *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
 511                         /* mark as having had error */
 512                         *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 513                         /*
 514                          * mark as not usable, at a minimum until driver
 515                          * is reloaded, probably until reboot, since no
 516                          * other reset is possible.
 517                          */
 518                         dd->ipath_flags &= ~IPATH_INITTED;
 519                 } else {
 520                         ipath_dbg("Clearing freezemode on ignored hardware "
 521                                   "error\n");
 522                         ctrl &= ~INFINIPATH_C_FREEZEMODE;
 523                         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 524                                          ctrl);
 525                 }
 526         }
 527
 528         *msg = '\0';
 529
 530         /*
 531          * may someday want to decode into which bits are which
 532          * functional area for parity errors, etc.
 533          */
 534         if (hwerrs & (infinipath_hwe_htcmemparityerr_mask
 535                       << INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT)) {
 536                 bits = (u32) ((hwerrs >>
 537                                INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) &
 538                               INFINIPATH_HWE_HTCMEMPARITYERR_MASK);
 539                 snprintf(bitsmsg, sizeof bitsmsg, "[HTC Parity Errs %x] ",
 540                          bits);
 541                 strlcat(msg, bitsmsg, msgl);
 542         }
 543
 544         ipath_format_hwerrors(hwerrs,
 545                               ipath_6110_hwerror_msgs,
 546                               sizeof(ipath_6110_hwerror_msgs) /
 547                               sizeof(ipath_6110_hwerror_msgs[0]),
 548                               msg, msgl);
 549
 550         if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS))
 551                 hwerr_crcbits(dd, hwerrs, msg, msgl);
 552
 553         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
 554                 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
 555                         msgl);
 556                 /* ignore from now on, so disable until driver reloaded */
 557                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
 558                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 559                                  dd->ipath_hwerrmask);
 560         }
 561 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
 562                          INFINIPATH_HWE_COREPLL_RFSLIP |        \
 563                          INFINIPATH_HWE_HTBPLL_FBSLIP |         \
 564                          INFINIPATH_HWE_HTBPLL_RFSLIP |         \
 565                          INFINIPATH_HWE_HTAPLL_FBSLIP |         \
 566                          INFINIPATH_HWE_HTAPLL_RFSLIP)
 567
 568         if (hwerrs & _IPATH_PLL_FAIL) {
 569                 snprintf(bitsmsg, sizeof bitsmsg,
 570                          "[PLL failed (%llx), InfiniPath hardware unusable]",
 571                          (unsigned long long) (hwerrs & _IPATH_PLL_FAIL));
 572                 strlcat(msg, bitsmsg, msgl);
 573                 /* ignore from now on, so disable until driver reloaded */
 574                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
 575                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 576                                  dd->ipath_hwerrmask);
 577         }
 578
 579         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
 580                 /*
 581                  * If it occurs, it is left masked since the eternal
 582                  * interface is unused
 583                  */
 584                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 585                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 586                                  dd->ipath_hwerrmask);
 587         }
 588
 589         ipath_dev_err(dd, "%s hardware error\n", msg);
 590         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
 591                 /*
 592                  * for status file; if no trailing brace is copied,
 593                  * we'll know it was truncated.
 594                  */
 595                 snprintf(dd->ipath_freezemsg,
 596                          dd->ipath_freezelen, "{%s}", msg);
 597
 598 bail:;
 599 }
 600
 601 /**
 602  * ipath_ht_boardname - fill in the board name
 603  * @dd: the infinipath device
 604  * @name: the output buffer
 605  * @namelen: the size of the output buffer
 606  *
 607  * fill in the board name, based on the board revision register
 608  */
 609 static int ipath_ht_boardname(struct ipath_devdata *dd, char *name,
 610                               size_t namelen)
 611 {
 612         char *n = NULL;
 613         u8 boardrev = dd->ipath_boardrev;
 614         int ret;
 615
 616         switch (boardrev) {
 617         case 4:         /* Ponderosa is one of the bringup boards */
 618                 n = "Ponderosa";
 619                 break;
 620         case 5:
 621                 /*
 622                  * original production board; two production levels, with
 623                  * different serial number ranges.   See ipath_ht_early_init() for
 624                  * case where we enable IPATH_GPIO_INTR for later serial # range.
 625                  */
 626                 n = "InfiniPath_QHT7040";
 627                 break;
 628         case 6:
 629                 n = "OEM_Board_3";
 630                 break;
 631         case 7:
 632                 /* small form factor production board */
 633                 n = "InfiniPath_QHT7140";
 634                 break;
 635         case 8:
 636                 n = "LS/X-1";
 637                 break;
 638         case 9:         /* Comstock bringup test board */
 639                 n = "Comstock";
 640                 break;
 641         case 10:
 642                 n = "OEM_Board_2";
 643                 break;
 644         case 11:
 645                 n = "InfiniPath_HT-470"; /* obsoleted */
 646                 break;
 647         case 12:
 648                 n = "OEM_Board_4";
 649                 break;
 650         default:                /* don't know, just print the number */
 651                 ipath_dev_err(dd, "Don't yet know about board "
 652                               "with ID %u\n", boardrev);
 653                 snprintf(name, namelen, "Unknown_InfiniPath_QHT7xxx_%u",
 654                          boardrev);
 655                 break;
 656         }
 657         if (n)
 658                 snprintf(name, namelen, "%s", n);
 659
 660         if (dd->ipath_majrev != 3 || (dd->ipath_minrev < 2 || dd->ipath_minrev > 3)) {
 661                 /*
 662                  * This version of the driver only supports Rev 3.2 and 3.3
 663                  */
 664                 ipath_dev_err(dd,
 665                               "Unsupported InfiniPath hardware revision %u.%u!\n",
 666                               dd->ipath_majrev, dd->ipath_minrev);
 667                 ret = 1;
 668                 goto bail;
 669         }
 670         /*
 671          * pkt/word counters are 32 bit, and therefore wrap fast enough
 672          * that we snapshot them from a timer, and maintain 64 bit shadow
 673          * copies
 674          */
 675         dd->ipath_flags |= IPATH_32BITCOUNTERS;
 676         if (dd->ipath_htspeed != 800)
 677                 ipath_dev_err(dd,
 678                               "Incorrectly configured for HT @ %uMHz\n",
 679                               dd->ipath_htspeed);
 680         if (dd->ipath_boardrev == 7 || dd->ipath_boardrev == 11 ||
 681             dd->ipath_boardrev == 6)
 682                 dd->ipath_flags |= IPATH_GPIO_INTR;
 683         else
 684                 dd->ipath_flags |= IPATH_POLL_RX_INTR;
 685         if (dd->ipath_boardrev == 8) {  /* LS/X-1 */
 686                 u64 val;
 687                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
 688                 if (val & INFINIPATH_EXTS_SERDESSEL) {
 689                         /*
 690                          * hardware disabled
 691                          *
 692                          * This means that the chip is hardware disabled,
 693                          * and will not be able to bring up the link,
 694                          * in any case.  We special case this and abort
 695                          * early, to avoid later messages.  We also set
 696                          * the DISABLED status bit
 697                          */
 698                         ipath_dbg("Unit %u is hardware-disabled\n",
 699                                   dd->ipath_unit);
 700                         *dd->ipath_statusp |= IPATH_STATUS_DISABLED;
 701                         /* this value is handled differently */
 702                         ret = 2;
 703                         goto bail;
 704                 }
 705         }
 706         ret = 0;
 707
 708 bail:
 709         return ret;
 710 }
 711
 712 static void ipath_check_htlink(struct ipath_devdata *dd)
 713 {
 714         u8 linkerr, link_off, i;
 715
 716         for (i = 0; i < 2; i++) {
 717                 link_off = dd->ipath_ht_slave_off + i * 4 + 0xd;
 718                 if (pci_read_config_byte(dd->pcidev, link_off, &linkerr))
 719                         dev_info(&dd->pcidev->dev, "Couldn't read "
 720                                  "linkerror%d of HT slave/primary block\n",
 721                                  i);
 722                 else if (linkerr & 0xf0) {
 723                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
 724                                    "clearing\n", linkerr >> 4, i);
 725                         /*
 726                          * writing the linkerr bits that are set should
 727                          * clear them
 728                          */
 729                         if (pci_write_config_byte(dd->pcidev, link_off,
 730                                                   linkerr))
 731                                 ipath_dbg("Failed write to clear HT "
 732                                           "linkerror%d\n", i);
 733                         if (pci_read_config_byte(dd->pcidev, link_off,
 734                                                  &linkerr))
 735                                 dev_info(&dd->pcidev->dev,
 736                                          "Couldn't reread linkerror%d of "
 737                                          "HT slave/primary block\n", i);
 738                         else if (linkerr & 0xf0)
 739                                 dev_info(&dd->pcidev->dev,
 740                                          "HT linkerror%d bits 0x%x "
 741                                          "couldn't be cleared\n",
 742                                          i, linkerr >> 4);
 743                 }
 744         }
 745 }
 746
 747 static int ipath_setup_ht_reset(struct ipath_devdata *dd)
 748 {
 749         ipath_dbg("No reset possible for this InfiniPath hardware\n");
 750         return 0;
 751 }
 752
 753 #define HT_INTR_DISC_CONFIG  0x80       /* HT interrupt and discovery cap */
 754 #define HT_INTR_REG_INDEX    2  /* intconfig requires indirect accesses */
 755
 756 /*
 757  * Bits 13-15 of command==0 is slave/primary block.  Clear any HT CRC
 758  * errors.  We only bother to do this at load time, because it's OK if
 759  * it happened before we were loaded (first time after boot/reset),
 760  * but any time after that, it's fatal anyway.  Also need to not check
 761  * for for upper byte errors if we are in 8 bit mode, so figure out
 762  * our width.  For now, at least, also complain if it's 8 bit.
 763  */
 764 static void slave_or_pri_blk(struct ipath_devdata *dd, struct pci_dev *pdev,
 765                              int pos, u8 cap_type)
 766 {
 767         u8 linkwidth = 0, linkerr, link_a_b_off, link_off;
 768         u16 linkctrl = 0;
 769         int i;
 770
 771         dd->ipath_ht_slave_off = pos;
 772         /* command word, master_host bit */
 773         /* master host || slave */
 774         if ((cap_type >> 2) & 1)
 775                 link_a_b_off = 4;
 776         else
 777                 link_a_b_off = 0;
 778         ipath_cdbg(VERBOSE, "HT%u (Link %c) connected to processor\n",
 779                    link_a_b_off ? 1 : 0,
 780                    link_a_b_off ? 'B' : 'A');
 781
 782         link_a_b_off += pos;
 783
 784         /*
 785          * check both link control registers; clear both HT CRC sets if
 786          * necessary.
 787          */
 788         for (i = 0; i < 2; i++) {
 789                 link_off = pos + i * 4 + 0x4;
 790                 if (pci_read_config_word(pdev, link_off, &linkctrl))
 791                         ipath_dev_err(dd, "Couldn't read HT link control%d "
 792                                       "register\n", i);
 793                 else if (linkctrl & (0xf << 8)) {
 794                         ipath_cdbg(VERBOSE, "Clear linkctrl%d CRC Error "
 795                                    "bits %x\n", i, linkctrl & (0xf << 8));
 796                         /*
 797                          * now write them back to clear the error.
 798                          */
 799                         pci_write_config_byte(pdev, link_off,
 800                                               linkctrl & (0xf << 8));
 801                 }
 802         }
 803
 804         /*
 805          * As with HT CRC bits, same for protocol errors that might occur
 806          * during boot.
 807          */
 808         for (i = 0; i < 2; i++) {
 809                 link_off = pos + i * 4 + 0xd;
 810                 if (pci_read_config_byte(pdev, link_off, &linkerr))
 811                         dev_info(&pdev->dev, "Couldn't read linkerror%d "
 812                                  "of HT slave/primary block\n", i);
 813                 else if (linkerr & 0xf0) {
 814                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
 815                                    "clearing\n", linkerr >> 4, i);
 816                         /*
 817                          * writing the linkerr bits that are set will clear
 818                          * them
 819                          */
 820                         if (pci_write_config_byte
 821                             (pdev, link_off, linkerr))
 822                                 ipath_dbg("Failed write to clear HT "
 823                                           "linkerror%d\n", i);
 824                         if (pci_read_config_byte(pdev, link_off, &linkerr))
 825                                 dev_info(&pdev->dev, "Couldn't reread "
 826                                          "linkerror%d of HT slave/primary "
 827                                          "block\n", i);
 828                         else if (linkerr & 0xf0)
 829                                 dev_info(&pdev->dev, "HT linkerror%d bits "
 830                                          "0x%x couldn't be cleared\n",
 831                                          i, linkerr >> 4);
 832                 }
 833         }
 834
 835         /*
 836          * this is just for our link to the host, not devices connected
 837          * through tunnel.
 838          */
 839
 840         if (pci_read_config_byte(pdev, link_a_b_off + 7, &linkwidth))
 841                 ipath_dev_err(dd, "Couldn't read HT link width "
 842                               "config register\n");
 843         else {
 844                 u32 width;
 845                 switch (linkwidth & 7) {
 846                 case 5:
 847                         width = 4;
 848                         break;
 849                 case 4:
 850                         width = 2;
 851                         break;
 852                 case 3:
 853                         width = 32;
 854                         break;
 855                 case 1:
 856                         width = 16;
 857                         break;
 858                 case 0:
 859                 default:        /* if wrong, assume 8 bit */
 860                         width = 8;
 861                         break;
 862                 }
 863
 864                 dd->ipath_htwidth = width;
 865
 866                 if (linkwidth != 0x11) {
 867                         ipath_dev_err(dd, "Not configured for 16 bit HT "
 868                                       "(%x)\n", linkwidth);
 869                         if (!(linkwidth & 0xf)) {
 870                                 ipath_dbg("Will ignore HT lane1 errors\n");
 871                                 dd->ipath_flags |= IPATH_8BIT_IN_HT0;
 872                         }
 873                 }
 874         }
 875
 876         /*
 877          * this is just for our link to the host, not devices connected
 878          * through tunnel.
 879          */
 880         if (pci_read_config_byte(pdev, link_a_b_off + 0xd, &linkwidth))
 881                 ipath_dev_err(dd, "Couldn't read HT link frequency "
 882                               "config register\n");
 883         else {
 884                 u32 speed;
 885                 switch (linkwidth & 0xf) {
 886                 case 6:
 887                         speed = 1000;
 888                         break;
 889                 case 5:
 890                         speed = 800;
 891                         break;
 892                 case 4:
 893                         speed = 600;
 894                         break;
 895                 case 3:
 896                         speed = 500;
 897                         break;
 898                 case 2:
 899                         speed = 400;
 900                         break;
 901                 case 1:
 902                         speed = 300;
 903                         break;
 904                 default:
 905                         /*
 906                          * assume reserved and vendor-specific are 200...
 907                          */
 908                 case 0:
 909                         speed = 200;
 910                         break;
 911                 }
 912                 dd->ipath_htspeed = speed;
 913         }
 914 }
 915
 916 static int set_int_handler(struct ipath_devdata *dd, struct pci_dev *pdev,
 917                             int pos)
 918 {
 919         u32 int_handler_addr_lower;
 920         u32 int_handler_addr_upper;
 921         u64 ihandler;
 922         u32 intvec;
 923
 924         /* use indirection register to get the intr handler */
 925         pci_write_config_byte(pdev, pos + HT_INTR_REG_INDEX, 0x10);
 926         pci_read_config_dword(pdev, pos + 4, &int_handler_addr_lower);
 927         pci_write_config_byte(pdev, pos + HT_INTR_REG_INDEX, 0x11);
 928         pci_read_config_dword(pdev, pos + 4, &int_handler_addr_upper);
 929
 930         ihandler = (u64) int_handler_addr_lower |
 931                 ((u64) int_handler_addr_upper << 32);
 932
 933         /*
 934          * kernels with CONFIG_PCI_MSI set the vector in the irq field of
 935          * struct pci_device, so we use that to program the internal
 936          * interrupt register (not config space) with that value. The BIOS
 937          * must still have done the basic MSI setup.
 938          */
 939         intvec = pdev->irq;
 940         /*
 941          * clear any vector bits there; normally not set but we'll overload
 942          * this for some debug purposes (setting the HTC debug register
 943          * value from software, rather than GPIOs), so it might be set on a
 944          * driver reload.
 945          */
 946         ihandler &= ~0xff0000;
 947         /* x86 vector goes in intrinfo[23:16] */
 948         ihandler |= intvec << 16;
 949         ipath_cdbg(VERBOSE, "ihandler lower %x, upper %x, intvec %x, "
 950                    "interruptconfig %llx\n", int_handler_addr_lower,
 951                    int_handler_addr_upper, intvec,
 952                    (unsigned long long) ihandler);
 953
 954         /* can't program yet, so save for interrupt setup */
 955         dd->ipath_intconfig = ihandler;
 956         /* keep going, so we find link control stuff also */
 957
 958         return ihandler != 0;
 959 }
 960
 961 /**
 962  * ipath_setup_ht_config - setup the interruptconfig register
 963  * @dd: the infinipath device
 964  * @pdev: the PCI device
 965  *
 966  * setup the interruptconfig register from the HT config info.
 967  * Also clear CRC errors in HT linkcontrol, if necessary.
 968  * This is done only for the real hardware.  It is done before
 969  * chip address space is initted, so can't touch infinipath registers
 970  */
 971 static int ipath_setup_ht_config(struct ipath_devdata *dd,
 972                                  struct pci_dev *pdev)
 973 {
 974         int pos, ret = 0;
 975         int ihandler = 0;
 976
 977         /*
 978          * Read the capability info to find the interrupt info, and also
 979          * handle clearing CRC errors in linkctrl register if necessary.  We
 980          * do this early, before we ever enable errors or hardware errors,
 981          * mostly to avoid causing the chip to enter freeze mode.
 982          */
 983         pos = pci_find_capability(pdev, PCI_CAP_ID_HT);
 984         if (!pos) {
 985                 ipath_dev_err(dd, "Couldn't find HyperTransport "
 986                               "capability; no interrupts\n");
 987                 ret = -ENODEV;
 988                 goto bail;
 989         }
 990         do {
 991                 u8 cap_type;
 992
 993                 /* the HT capability type byte is 3 bytes after the
 994                  * capability byte.
 995                  */
 996                 if (pci_read_config_byte(pdev, pos + 3, &cap_type)) {
 997                         dev_info(&pdev->dev, "Couldn't read config "
 998                                  "command @ %d\n", pos);
 999                         continue;
1000                 }
1001                 if (!(cap_type & 0xE0))
1002                         slave_or_pri_blk(dd, pdev, pos, cap_type);
1003                 else if (cap_type == HT_INTR_DISC_CONFIG)
1004                         ihandler = set_int_handler(dd, pdev, pos);
1005         } while ((pos = pci_find_next_capability(pdev, pos,
1006                                                  PCI_CAP_ID_HT)));
1007
1008         if (!ihandler) {
1009                 ipath_dev_err(dd, "Couldn't find interrupt handler in "
1010                               "config space\n");
1011                 ret = -ENODEV;
1012         }
1013
1014 bail:
1015         return ret;
1016 }
1017
1018 /**
1019  * ipath_setup_ht_cleanup - clean up any per-chip chip-specific stuff
1020  * @dd: the infinipath device
1021  *
1022  * Called during driver unload.
1023  * This is currently a nop for the HT chip, not for all chips
1024  */
1025 static void ipath_setup_ht_cleanup(struct ipath_devdata *dd)
1026 {
1027 }
1028
1029 /**
1030  * ipath_setup_ht_setextled - set the state of the two external LEDs
1031  * @dd: the infinipath device
1032  * @lst: the L state
1033  * @ltst: the LT state
1034  *
1035  * Set the state of the two external LEDs, to indicate physical and
1036  * logical state of IB link.   For this chip (at least with recommended
1037  * board pinouts), LED1 is Green (physical state), and LED2 is Yellow
1038  * (logical state)
1039  *
1040  * Note:  We try to match the Mellanox HCA LED behavior as best
1041  * we can.  Green indicates physical link state is OK (something is
1042  * plugged in, and we can train).
1043  * Amber indicates the link is logically up (ACTIVE).
1044  * Mellanox further blinks the amber LED to indicate data packet
1045  * activity, but we have no hardware support for that, so it would
1046  * require waking up every 10-20 msecs and checking the counters
1047  * on the chip, and then turning the LED off if appropriate.  That's
1048  * visible overhead, so not something we will do.
1049  *
1050  */
1051 static void ipath_setup_ht_setextled(struct ipath_devdata *dd,
1052                                      u64 lst, u64 ltst)
1053 {
1054         u64 extctl;
1055
1056         /* the diags use the LED to indicate diag info, so we leave
1057          * the external LED alone when the diags are running */
1058         if (ipath_diag_inuse)
1059                 return;
1060
1061         /*
1062          * start by setting both LED control bits to off, then turn
1063          * on the appropriate bit(s).
1064          */
1065         if (dd->ipath_boardrev == 8) { /* LS/X-1 uses different pins */
1066                 /*
1067                  * major difference is that INFINIPATH_EXTC_LEDGBLERR_OFF
1068                  * is inverted,  because it is normally used to indicate
1069                  * a hardware fault at reset, if there were errors
1070                  */
1071                 extctl = (dd->ipath_extctrl & ~INFINIPATH_EXTC_LEDGBLOK_ON)
1072                         | INFINIPATH_EXTC_LEDGBLERR_OFF;
1073                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1074                         extctl &= ~INFINIPATH_EXTC_LEDGBLERR_OFF;
1075                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1076                         extctl |= INFINIPATH_EXTC_LEDGBLOK_ON;
1077         }
1078         else {
1079                 extctl = dd->ipath_extctrl &
1080                         ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1081                           INFINIPATH_EXTC_LED2PRIPORT_ON);
1082                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1083                         extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1084                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1085                         extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1086         }
1087         dd->ipath_extctrl = extctl;
1088         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1089 }
1090
1091 static void ipath_init_ht_variables(struct ipath_devdata *dd)
1092 {
1093         dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1094         dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1095         dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1096         dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1097
1098         dd->ipath_i_bitsextant =
1099                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1100                 (INFINIPATH_I_RCVAVAIL_MASK <<
1101                  INFINIPATH_I_RCVAVAIL_SHIFT) |
1102                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1103                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1104
1105         dd->ipath_e_bitsextant =
1106                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1107                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1108                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1109                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1110                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1111                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1112                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1113                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1114                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1115                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1116                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1117                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1118                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1119                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1120                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1121                 INFINIPATH_E_HARDWARE;
1122
1123         dd->ipath_hwe_bitsextant =
1124                 (INFINIPATH_HWE_HTCMEMPARITYERR_MASK <<
1125                  INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) |
1126                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1127                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1128                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1129                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1130                 INFINIPATH_HWE_HTCLNKABYTE0CRCERR |
1131                 INFINIPATH_HWE_HTCLNKABYTE1CRCERR |
1132                 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR |
1133                 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR |
1134                 INFINIPATH_HWE_HTCMISCERR4 |
1135                 INFINIPATH_HWE_HTCMISCERR5 | INFINIPATH_HWE_HTCMISCERR6 |
1136                 INFINIPATH_HWE_HTCMISCERR7 |
1137                 INFINIPATH_HWE_HTCBUSTREQPARITYERR |
1138                 INFINIPATH_HWE_HTCBUSTRESPPARITYERR |
1139                 INFINIPATH_HWE_HTCBUSIREQPARITYERR |
1140                 INFINIPATH_HWE_RXDSYNCMEMPARITYERR |
1141                 INFINIPATH_HWE_MEMBISTFAILED |
1142                 INFINIPATH_HWE_COREPLL_FBSLIP |
1143                 INFINIPATH_HWE_COREPLL_RFSLIP |
1144                 INFINIPATH_HWE_HTBPLL_FBSLIP |
1145                 INFINIPATH_HWE_HTBPLL_RFSLIP |
1146                 INFINIPATH_HWE_HTAPLL_FBSLIP |
1147                 INFINIPATH_HWE_HTAPLL_RFSLIP |
1148                 INFINIPATH_HWE_SERDESPLLFAILED |
1149                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1150                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1151
1152         dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1153         dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1154 }
1155
1156 /**
1157  * ipath_ht_init_hwerrors - enable hardware errors
1158  * @dd: the infinipath device
1159  *
1160  * now that we have finished initializing everything that might reasonably
1161  * cause a hardware error, and cleared those errors bits as they occur,
1162  * we can enable hardware errors in the mask (potentially enabling
1163  * freeze mode), and enable hardware errors as errors (along with
1164  * everything else) in errormask
1165  */
1166 static void ipath_ht_init_hwerrors(struct ipath_devdata *dd)
1167 {
1168         ipath_err_t val;
1169         u64 extsval;
1170
1171         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
1172
1173         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
1174                 ipath_dev_err(dd, "MemBIST did not complete!\n");
1175
1176         ipath_check_htlink(dd);
1177
1178         /* barring bugs, all hwerrors become interrupts, which can */
1179         val = -1LL;
1180         /* don't look at crc lane1 if 8 bit */
1181         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
1182                 val &= ~infinipath_hwe_htclnkabyte1crcerr;
1183         /* don't look at crc lane1 if 8 bit */
1184         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
1185                 val &= ~infinipath_hwe_htclnkbbyte1crcerr;
1186
1187         /*
1188          * disable RXDSYNCMEMPARITY because external serdes is unused,
1189          * and therefore the logic will never be used or initialized,
1190          * and uninitialized state will normally result in this error
1191          * being asserted.  Similarly for the external serdess pll
1192          * lock signal.
1193          */
1194         val &= ~(INFINIPATH_HWE_SERDESPLLFAILED |
1195                  INFINIPATH_HWE_RXDSYNCMEMPARITYERR);
1196
1197         /*
1198          * Disable MISCERR4 because of an inversion in the HT core
1199          * logic checking for errors that cause this bit to be set.
1200          * The errata can also cause the protocol error bit to be set
1201          * in the HT config space linkerror register(s).
1202          */
1203         val &= ~INFINIPATH_HWE_HTCMISCERR4;
1204
1205         /*
1206          * PLL ignored because MDIO interface has a logic problem
1207          * for reads, on Comstock and Ponderosa.  BRINGUP
1208          */
1209         if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9)
1210                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
1211         dd->ipath_hwerrmask = val;
1212 }
1213
1214 /**
1215  * ipath_ht_bringup_serdes - bring up the serdes
1216  * @dd: the infinipath device
1217  */
1218 static int ipath_ht_bringup_serdes(struct ipath_devdata *dd)
1219 {
1220         u64 val, config1;
1221         int ret = 0, change = 0;
1222
1223         ipath_dbg("Trying to bringup serdes\n");
1224
1225         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
1226             INFINIPATH_HWE_SERDESPLLFAILED)
1227         {
1228                 ipath_dbg("At start, serdes PLL failed bit set in "
1229                           "hwerrstatus, clearing and continuing\n");
1230                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1231                                  INFINIPATH_HWE_SERDESPLLFAILED);
1232         }
1233
1234         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1235         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
1236
1237         ipath_cdbg(VERBOSE, "Initial serdes status is config0=%llx "
1238                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1239                    (unsigned long long) val, (unsigned long long) config1,
1240                    (unsigned long long)
1241                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1242                    (unsigned long long)
1243                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1244
1245         /* force reset on */
1246         val |= INFINIPATH_SERDC0_RESET_PLL
1247                 /* | INFINIPATH_SERDC0_RESET_MASK */
1248                 ;
1249         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1250         udelay(15);             /* need pll reset set at least for a bit */
1251
1252         if (val & INFINIPATH_SERDC0_RESET_PLL) {
1253                 u64 val2 = val &= ~INFINIPATH_SERDC0_RESET_PLL;
1254                 /* set lane resets, and tx idle, during pll reset */
1255                 val2 |= INFINIPATH_SERDC0_RESET_MASK |
1256                         INFINIPATH_SERDC0_TXIDLE;
1257                 ipath_cdbg(VERBOSE, "Clearing serdes PLL reset (writing "
1258                            "%llx)\n", (unsigned long long) val2);
1259                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1260                                  val2);
1261                 /*
1262                  * be sure chip saw it
1263                  */
1264                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1265                 /*
1266                  * need pll reset clear at least 11 usec before lane
1267                  * resets cleared; give it a few more
1268                  */
1269                 udelay(15);
1270                 val = val2;     /* for check below */
1271         }
1272
1273         if (val & (INFINIPATH_SERDC0_RESET_PLL |
1274                    INFINIPATH_SERDC0_RESET_MASK |
1275                    INFINIPATH_SERDC0_TXIDLE)) {
1276                 val &= ~(INFINIPATH_SERDC0_RESET_PLL |
1277                          INFINIPATH_SERDC0_RESET_MASK |
1278                          INFINIPATH_SERDC0_TXIDLE);
1279                 /* clear them */
1280                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1281                                  val);
1282         }
1283
1284         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1285         if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
1286              INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
1287                 val &= ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
1288                          INFINIPATH_XGXS_MDIOADDR_SHIFT);
1289                 /*
1290                  * we use address 3
1291                  */
1292                 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
1293                 change = 1;
1294         }
1295         if (val & INFINIPATH_XGXS_RESET) {
1296                 /* normally true after boot */
1297                 val &= ~INFINIPATH_XGXS_RESET;
1298                 change = 1;
1299         }
1300         if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
1301              INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
1302                 /* need to compensate for Tx inversion in partner */
1303                 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
1304                          INFINIPATH_XGXS_RX_POL_SHIFT);
1305                 val |= dd->ipath_rx_pol_inv <<
1306                         INFINIPATH_XGXS_RX_POL_SHIFT;
1307                 change = 1;
1308         }
1309         if (change)
1310                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1311
1312         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1313
1314         /* clear current and de-emphasis bits */
1315         config1 &= ~0x0ffffffff00ULL;
1316         /* set current to 20ma */
1317         config1 |= 0x00000000000ULL;
1318         /* set de-emphasis to -5.68dB */
1319         config1 |= 0x0cccc000000ULL;
1320         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
1321
1322         ipath_cdbg(VERBOSE, "After setup: serdes status is config0=%llx "
1323                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1324                    (unsigned long long) val, (unsigned long long) config1,
1325                    (unsigned long long)
1326                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1327                    (unsigned long long)
1328                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1329
1330         if (!ipath_waitfor_mdio_cmdready(dd)) {
1331                 ipath_write_kreg(dd, dd->ipath_kregs->kr_mdio,
1332                                  ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
1333                                                 IPATH_MDIO_CTRL_XGXS_REG_8,
1334                                                 0));
1335                 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
1336                                            IPATH_MDIO_DATAVALID, &val))
1337                         ipath_dbg("Never got MDIO data for XGXS status "
1338                                   "read\n");
1339                 else
1340                         ipath_cdbg(VERBOSE, "MDIO Read reg8, "
1341                                    "'bank' 31 %x\n", (u32) val);
1342         } else
1343                 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
1344
1345         return ret;             /* for now, say we always succeeded */
1346 }
1347
1348 /**
1349  * ipath_ht_quiet_serdes - set serdes to txidle
1350  * @dd: the infinipath device
1351  * driver is being unloaded
1352  */
1353 static void ipath_ht_quiet_serdes(struct ipath_devdata *dd)
1354 {
1355         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1356
1357         val |= INFINIPATH_SERDC0_TXIDLE;
1358         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
1359                   (unsigned long long) val);
1360         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1361 }
1362
1363 static int ipath_ht_intconfig(struct ipath_devdata *dd)
1364 {
1365         int ret;
1366
1367         if (!dd->ipath_intconfig) {
1368                 ipath_dev_err(dd, "No interrupts enabled, couldn't setup "
1369                               "interrupt address\n");
1370                 ret = 1;
1371                 goto bail;
1372         }
1373
1374         ipath_write_kreg(dd, dd->ipath_kregs->kr_interruptconfig,
1375                          dd->ipath_intconfig);  /* interrupt address */
1376         ret = 0;
1377
1378 bail:
1379         return ret;
1380 }
1381
1382 /**
1383  * ipath_pe_put_tid - write a TID in chip
1384  * @dd: the infinipath device
1385  * @tidptr: pointer to the expected TID (in chip) to udpate
1386  * @tidtype: 0 for eager, 1 for expected
1387  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1388  *
1389  * This exists as a separate routine to allow for special locking etc.
1390  * It's used for both the full cleanup on exit, as well as the normal
1391  * setup and teardown.
1392  */
1393 static void ipath_ht_put_tid(struct ipath_devdata *dd,
1394                              u64 __iomem *tidptr, u32 type,
1395                              unsigned long pa)
1396 {
1397         if (pa != dd->ipath_tidinvalid) {
1398                 if (unlikely((pa & ~INFINIPATH_RT_ADDR_MASK))) {
1399                         dev_info(&dd->pcidev->dev,
1400                                  "physaddr %lx has more than "
1401                                  "40 bits, using only 40!!!\n", pa);
1402                         pa &= INFINIPATH_RT_ADDR_MASK;
1403                 }
1404                 if (type == 0)
1405                         pa |= dd->ipath_tidtemplate;
1406                 else {
1407                         /* in words (fixed, full page).  */
1408                         u64 lenvalid = PAGE_SIZE >> 2;
1409                         lenvalid <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1410                         pa |= lenvalid | INFINIPATH_RT_VALID;
1411                 }
1412         }
1413         if (dd->ipath_kregbase)
1414                 writeq(pa, tidptr);
1415 }
1416
1417 /**
1418  * ipath_ht_clear_tid - clear all TID entries for a port, expected and eager
1419  * @dd: the infinipath device
1420  * @port: the port
1421  *
1422  * Used from ipath_close(), and at chip initialization.
1423  */
1424 static void ipath_ht_clear_tids(struct ipath_devdata *dd, unsigned port)
1425 {
1426         u64 __iomem *tidbase;
1427         int i;
1428
1429         if (!dd->ipath_kregbase)
1430                 return;
1431
1432         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1433
1434         /*
1435          * need to invalidate all of the expected TID entries for this
1436          * port, so we don't have valid entries that might somehow get
1437          * used (early in next use of this port, or through some bug)
1438          */
1439         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1440                                    dd->ipath_rcvtidbase +
1441                                    port * dd->ipath_rcvtidcnt *
1442                                    sizeof(*tidbase));
1443         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1444                 ipath_ht_put_tid(dd, &tidbase[i], 1, dd->ipath_tidinvalid);
1445
1446         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1447                                    dd->ipath_rcvegrbase +
1448                                    port * dd->ipath_rcvegrcnt *
1449                                    sizeof(*tidbase));
1450
1451         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1452                 ipath_ht_put_tid(dd, &tidbase[i], 0, dd->ipath_tidinvalid);
1453 }
1454
1455 /**
1456  * ipath_ht_tidtemplate - setup constants for TID updates
1457  * @dd: the infinipath device
1458  *
1459  * We setup stuff that we use a lot, to avoid calculating each time
1460  */
1461 static void ipath_ht_tidtemplate(struct ipath_devdata *dd)
1462 {
1463         dd->ipath_tidtemplate = dd->ipath_ibmaxlen >> 2;
1464         dd->ipath_tidtemplate <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1465         dd->ipath_tidtemplate |= INFINIPATH_RT_VALID;
1466
1467         /*
1468          * work around chip errata bug 7358, by marking invalid tids
1469          * as having max length
1470          */
1471         dd->ipath_tidinvalid = (-1LL & INFINIPATH_RT_BUFSIZE_MASK) <<
1472                 INFINIPATH_RT_BUFSIZE_SHIFT;
1473 }
1474
1475 static int ipath_ht_early_init(struct ipath_devdata *dd)
1476 {
1477         u32 __iomem *piobuf;
1478         u32 pioincr, val32, egrsize;
1479         int i;
1480
1481         /*
1482          * one cache line; long IB headers will spill over into received
1483          * buffer
1484          */
1485         dd->ipath_rcvhdrentsize = 16;
1486         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1487
1488         /*
1489          * For HT, we allocate a somewhat overly large eager buffer,
1490          * such that we can guarantee that we can receive the largest
1491          * packet that we can send out.  To truly support a 4KB MTU,
1492          * we need to bump this to a large value.  To date, other than
1493          * testing, we have never encountered an HCA that can really
1494          * send 4KB MTU packets, so we do not handle that (we'll get
1495          * errors interrupts if we ever see one).
1496          */
1497         dd->ipath_rcvegrbufsize = dd->ipath_piosize2k;
1498         egrsize = dd->ipath_rcvegrbufsize;
1499
1500         /*
1501          * the min() check here is currently a nop, but it may not
1502          * always be, depending on just how we do ipath_rcvegrbufsize
1503          */
1504         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1505                                  dd->ipath_rcvegrbufsize);
1506         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1507         ipath_ht_tidtemplate(dd);
1508
1509         /*
1510          * zero all the TID entries at startup.  We do this for sanity,
1511          * in case of a previous driver crash of some kind, and also
1512          * because the chip powers up with these memories in an unknown
1513          * state.  Use portcnt, not cfgports, since this is for the
1514          * full chip, not for current (possibly different) configuration
1515          * value.
1516          * Chip Errata bug 6447
1517          */
1518         for (val32 = 0; val32 < dd->ipath_portcnt; val32++)
1519                 ipath_ht_clear_tids(dd, val32);
1520
1521         /*
1522          * write the pbc of each buffer, to be sure it's initialized, then
1523          * cancel all the buffers, and also abort any packets that might
1524          * have been in flight for some reason (the latter is for driver
1525          * unload/reload, but isn't a bad idea at first init).  PIO send
1526          * isn't enabled at this point, so there is no danger of sending
1527          * these out on the wire.
1528          * Chip Errata bug 6610
1529          */
1530         piobuf = (u32 __iomem *) (((char __iomem *)(dd->ipath_kregbase)) +
1531                                   dd->ipath_piobufbase);
1532         pioincr = dd->ipath_palign / sizeof(*piobuf);
1533         for (i = 0; i < dd->ipath_piobcnt2k; i++) {
1534                 /*
1535                  * reasonable word count, just to init pbc
1536                  */
1537                 writel(16, piobuf);
1538                 piobuf += pioincr;
1539         }
1540         /*
1541          * self-clearing
1542          */
1543         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1544                          INFINIPATH_S_ABORT);
1545
1546         ipath_get_eeprom_info(dd);
1547         if(dd->ipath_boardrev == 5 && dd->ipath_serial[0] == '1' &&
1548                 dd->ipath_serial[1] == '2' && dd->ipath_serial[2] == '8') {
1549                 /*
1550                  * Later production QHT7040 has same changes as QHT7140, so
1551                  * can use GPIO interrupts.  They have serial #'s starting
1552                  * with 128, rather than 112.
1553                  */
1554                 dd->ipath_flags |= IPATH_GPIO_INTR;
1555                 dd->ipath_flags &= ~IPATH_POLL_RX_INTR;
1556         }
1557         return 0;
1558 }
1559
1560 /**
1561  * ipath_init_ht_get_base_info - set chip-specific flags for user code
1562  * @dd: the infinipath device
1563  * @kbase: ipath_base_info pointer
1564  *
1565  * We set the PCIE flag because the lower bandwidth on PCIe vs
1566  * HyperTransport can affect some user packet algorithims.
1567  */
1568 static int ipath_ht_get_base_info(struct ipath_portdata *pd, void *kbase)
1569 {
1570         struct ipath_base_info *kinfo = kbase;
1571
1572         kinfo->spi_runtime_flags |= IPATH_RUNTIME_HT |
1573                 IPATH_RUNTIME_RCVHDR_COPY;
1574
1575         return 0;
1576 }
1577
1578 /**
1579  * ipath_init_iba6110_funcs - set up the chip-specific function pointers
1580  * @dd: the infinipath device
1581  *
1582  * This is global, and is called directly at init to set up the
1583  * chip-specific function pointers for later use.
1584  */
1585 void ipath_init_iba6110_funcs(struct ipath_devdata *dd)
1586 {
1587         dd->ipath_f_intrsetup = ipath_ht_intconfig;
1588         dd->ipath_f_bus = ipath_setup_ht_config;
1589         dd->ipath_f_reset = ipath_setup_ht_reset;
1590         dd->ipath_f_get_boardname = ipath_ht_boardname;
1591         dd->ipath_f_init_hwerrors = ipath_ht_init_hwerrors;
1592         dd->ipath_f_early_init = ipath_ht_early_init;
1593         dd->ipath_f_handle_hwerrors = ipath_ht_handle_hwerrors;
1594         dd->ipath_f_quiet_serdes = ipath_ht_quiet_serdes;
1595         dd->ipath_f_bringup_serdes = ipath_ht_bringup_serdes;
1596         dd->ipath_f_clear_tids = ipath_ht_clear_tids;
1597         dd->ipath_f_put_tid = ipath_ht_put_tid;
1598         dd->ipath_f_cleanup = ipath_setup_ht_cleanup;
1599         dd->ipath_f_setextled = ipath_setup_ht_setextled;
1600         dd->ipath_f_get_base_info = ipath_ht_get_base_info;
1601
1602         /*
1603          * initialize chip-specific variables
1604          */
1605         dd->ipath_f_tidtemplate = ipath_ht_tidtemplate;
1606
1607         /*
1608          * setup the register offsets, since they are different for each
1609          * chip
1610          */
1611         dd->ipath_kregs = &ipath_ht_kregs;
1612         dd->ipath_cregs = &ipath_ht_cregs;
1613
1614         /*
1615          * do very early init that is needed before ipath_f_bus is
1616          * called
1617          */
1618         ipath_init_ht_variables(dd);
1619 }