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   1 /*
   2  *  linux/arch/arm/mach-realview/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/config.h>
  22 #include <linux/init.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/sysdev.h>
  26 #include <linux/interrupt.h>
  27
  28 #include <asm/system.h>
  29 #include <asm/hardware.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/leds.h>
  33 #include <asm/mach-types.h>
  34 #include <asm/hardware/amba.h>
  35 #include <asm/hardware/amba_clcd.h>
  36 #include <asm/hardware/arm_timer.h>
  37 #include <asm/hardware/icst307.h>
  38
  39 #include <asm/mach/arch.h>
  40 #include <asm/mach/flash.h>
  41 #include <asm/mach/irq.h>
  42 #include <asm/mach/time.h>
  43 #include <asm/mach/map.h>
  44 #include <asm/mach/mmc.h>
  45
  46 #include <asm/hardware/gic.h>
  47
  48 #include "core.h"
  49 #include "clock.h"
  50
  51 #define REALVIEW_REFCOUNTER     (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
  52
  53 /*
  54  * This is the RealView sched_clock implementation.  This has
  55  * a resolution of 41.7ns, and a maximum value of about 179s.
  56  */
  57 unsigned long long sched_clock(void)
  58 {
  59         unsigned long long v;
  60
  61         v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
  62         do_div(v, 3);
  63
  64         return v;
  65 }
  66
  67
  68 #define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
  69
  70 static int realview_flash_init(void)
  71 {
  72         u32 val;
  73
  74         val = __raw_readl(REALVIEW_FLASHCTRL);
  75         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  76         __raw_writel(val, REALVIEW_FLASHCTRL);
  77
  78         return 0;
  79 }
  80
  81 static void realview_flash_exit(void)
  82 {
  83         u32 val;
  84
  85         val = __raw_readl(REALVIEW_FLASHCTRL);
  86         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  87         __raw_writel(val, REALVIEW_FLASHCTRL);
  88 }
  89
  90 static void realview_flash_set_vpp(int on)
  91 {
  92         u32 val;
  93
  94         val = __raw_readl(REALVIEW_FLASHCTRL);
  95         if (on)
  96                 val |= REALVIEW_FLASHPROG_FLVPPEN;
  97         else
  98                 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  99         __raw_writel(val, REALVIEW_FLASHCTRL);
 100 }
 101
 102 static struct flash_platform_data realview_flash_data = {
 103         .map_name               = "cfi_probe",
 104         .width                  = 4,
 105         .init                   = realview_flash_init,
 106         .exit                   = realview_flash_exit,
 107         .set_vpp                = realview_flash_set_vpp,
 108 };
 109
 110 static struct resource realview_flash_resource = {
 111         .start                  = REALVIEW_FLASH_BASE,
 112         .end                    = REALVIEW_FLASH_BASE + REALVIEW_FLASH_SIZE,
 113         .flags                  = IORESOURCE_MEM,
 114 };
 115
 116 struct platform_device realview_flash_device = {
 117         .name                   = "armflash",
 118         .id                     = 0,
 119         .dev                    = {
 120                 .platform_data  = &realview_flash_data,
 121         },
 122         .num_resources          = 1,
 123         .resource               = &realview_flash_resource,
 124 };
 125
 126 static struct resource realview_smc91x_resources[] = {
 127         [0] = {
 128                 .start          = REALVIEW_ETH_BASE,
 129                 .end            = REALVIEW_ETH_BASE + SZ_64K - 1,
 130                 .flags          = IORESOURCE_MEM,
 131         },
 132         [1] = {
 133                 .start          = IRQ_ETH,
 134                 .end            = IRQ_ETH,
 135                 .flags          = IORESOURCE_IRQ,
 136         },
 137 };
 138
 139 struct platform_device realview_smc91x_device = {
 140         .name           = "smc91x",
 141         .id             = 0,
 142         .num_resources  = ARRAY_SIZE(realview_smc91x_resources),
 143         .resource       = realview_smc91x_resources,
 144 };
 145
 146 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
 147
 148 static unsigned int realview_mmc_status(struct device *dev)
 149 {
 150         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 151         u32 mask;
 152
 153         if (adev->res.start == REALVIEW_MMCI0_BASE)
 154                 mask = 1;
 155         else
 156                 mask = 2;
 157
 158         return readl(REALVIEW_SYSMCI) & mask;
 159 }
 160
 161 struct mmc_platform_data realview_mmc0_plat_data = {
 162         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 163         .status         = realview_mmc_status,
 164 };
 165
 166 struct mmc_platform_data realview_mmc1_plat_data = {
 167         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 168         .status         = realview_mmc_status,
 169 };
 170
 171 /*
 172  * Clock handling
 173  */
 174 static const struct icst307_params realview_oscvco_params = {
 175         .ref            = 24000,
 176         .vco_max        = 200000,
 177         .vd_min         = 4 + 8,
 178         .vd_max         = 511 + 8,
 179         .rd_min         = 1 + 2,
 180         .rd_max         = 127 + 2,
 181 };
 182
 183 static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
 184 {
 185         void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
 186         void __iomem *sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC1_OFFSET;
 187         u32 val;
 188
 189         val = readl(sys_osc) & ~0x7ffff;
 190         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 191
 192         writel(0xa05f, sys_lock);
 193         writel(val, sys_osc);
 194         writel(0, sys_lock);
 195 }
 196
 197 struct clk realview_clcd_clk = {
 198         .name   = "CLCDCLK",
 199         .params = &realview_oscvco_params,
 200         .setvco = realview_oscvco_set,
 201 };
 202
 203 /*
 204  * CLCD support.
 205  */
 206 #define SYS_CLCD_MODE_MASK      (3 << 0)
 207 #define SYS_CLCD_MODE_888       (0 << 0)
 208 #define SYS_CLCD_MODE_5551      (1 << 0)
 209 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
 210 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
 211 #define SYS_CLCD_NLCDIOON       (1 << 2)
 212 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 213 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 214 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 215 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 216 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 217 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 218 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 219 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 220
 221 static struct clcd_panel vga = {
 222         .mode           = {
 223                 .name           = "VGA",
 224                 .refresh        = 60,
 225                 .xres           = 640,
 226                 .yres           = 480,
 227                 .pixclock       = 39721,
 228                 .left_margin    = 40,
 229                 .right_margin   = 24,
 230                 .upper_margin   = 32,
 231                 .lower_margin   = 11,
 232                 .hsync_len      = 96,
 233                 .vsync_len      = 2,
 234                 .sync           = 0,
 235                 .vmode          = FB_VMODE_NONINTERLACED,
 236         },
 237         .width          = -1,
 238         .height         = -1,
 239         .tim2           = TIM2_BCD | TIM2_IPC,
 240         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 241         .bpp            = 16,
 242 };
 243
 244 static struct clcd_panel sanyo_3_8_in = {
 245         .mode           = {
 246                 .name           = "Sanyo QVGA",
 247                 .refresh        = 116,
 248                 .xres           = 320,
 249                 .yres           = 240,
 250                 .pixclock       = 100000,
 251                 .left_margin    = 6,
 252                 .right_margin   = 6,
 253                 .upper_margin   = 5,
 254                 .lower_margin   = 5,
 255                 .hsync_len      = 6,
 256                 .vsync_len      = 6,
 257                 .sync           = 0,
 258                 .vmode          = FB_VMODE_NONINTERLACED,
 259         },
 260         .width          = -1,
 261         .height         = -1,
 262         .tim2           = TIM2_BCD,
 263         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 264         .bpp            = 16,
 265 };
 266
 267 static struct clcd_panel sanyo_2_5_in = {
 268         .mode           = {
 269                 .name           = "Sanyo QVGA Portrait",
 270                 .refresh        = 116,
 271                 .xres           = 240,
 272                 .yres           = 320,
 273                 .pixclock       = 100000,
 274                 .left_margin    = 20,
 275                 .right_margin   = 10,
 276                 .upper_margin   = 2,
 277                 .lower_margin   = 2,
 278                 .hsync_len      = 10,
 279                 .vsync_len      = 2,
 280                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 281                 .vmode          = FB_VMODE_NONINTERLACED,
 282         },
 283         .width          = -1,
 284         .height         = -1,
 285         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 286         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 287         .bpp            = 16,
 288 };
 289
 290 static struct clcd_panel epson_2_2_in = {
 291         .mode           = {
 292                 .name           = "Epson QCIF",
 293                 .refresh        = 390,
 294                 .xres           = 176,
 295                 .yres           = 220,
 296                 .pixclock       = 62500,
 297                 .left_margin    = 3,
 298                 .right_margin   = 2,
 299                 .upper_margin   = 1,
 300                 .lower_margin   = 0,
 301                 .hsync_len      = 3,
 302                 .vsync_len      = 2,
 303                 .sync           = 0,
 304                 .vmode          = FB_VMODE_NONINTERLACED,
 305         },
 306         .width          = -1,
 307         .height         = -1,
 308         .tim2           = TIM2_BCD | TIM2_IPC,
 309         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 310         .bpp            = 16,
 311 };
 312
 313 /*
 314  * Detect which LCD panel is connected, and return the appropriate
 315  * clcd_panel structure.  Note: we do not have any information on
 316  * the required timings for the 8.4in panel, so we presently assume
 317  * VGA timings.
 318  */
 319 static struct clcd_panel *realview_clcd_panel(void)
 320 {
 321         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 322         struct clcd_panel *panel = &vga;
 323         u32 val;
 324
 325         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 326         if (val == SYS_CLCD_ID_SANYO_3_8)
 327                 panel = &sanyo_3_8_in;
 328         else if (val == SYS_CLCD_ID_SANYO_2_5)
 329                 panel = &sanyo_2_5_in;
 330         else if (val == SYS_CLCD_ID_EPSON_2_2)
 331                 panel = &epson_2_2_in;
 332         else if (val == SYS_CLCD_ID_VGA)
 333                 panel = &vga;
 334         else {
 335                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 336                         val);
 337                 panel = &vga;
 338         }
 339
 340         return panel;
 341 }
 342
 343 /*
 344  * Disable all display connectors on the interface module.
 345  */
 346 static void realview_clcd_disable(struct clcd_fb *fb)
 347 {
 348         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 349         u32 val;
 350
 351         val = readl(sys_clcd);
 352         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 353         writel(val, sys_clcd);
 354 }
 355
 356 /*
 357  * Enable the relevant connector on the interface module.
 358  */
 359 static void realview_clcd_enable(struct clcd_fb *fb)
 360 {
 361         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 362         u32 val;
 363
 364         val = readl(sys_clcd);
 365         val &= ~SYS_CLCD_MODE_MASK;
 366
 367         switch (fb->fb.var.green.length) {
 368         case 5:
 369                 val |= SYS_CLCD_MODE_5551;
 370                 break;
 371         case 6:
 372                 val |= SYS_CLCD_MODE_565_RLSB;
 373                 break;
 374         case 8:
 375                 val |= SYS_CLCD_MODE_888;
 376                 break;
 377         }
 378
 379         /*
 380          * Set the MUX
 381          */
 382         writel(val, sys_clcd);
 383
 384         /*
 385          * And now enable the PSUs
 386          */
 387         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 388         writel(val, sys_clcd);
 389 }
 390
 391 static unsigned long framesize = SZ_1M;
 392
 393 static int realview_clcd_setup(struct clcd_fb *fb)
 394 {
 395         dma_addr_t dma;
 396
 397         fb->panel               = realview_clcd_panel();
 398
 399         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 400                                                     &dma, GFP_KERNEL);
 401         if (!fb->fb.screen_base) {
 402                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 403                 return -ENOMEM;
 404         }
 405
 406         fb->fb.fix.smem_start   = dma;
 407         fb->fb.fix.smem_len     = framesize;
 408
 409         return 0;
 410 }
 411
 412 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 413 {
 414         return dma_mmap_writecombine(&fb->dev->dev, vma,
 415                                      fb->fb.screen_base,
 416                                      fb->fb.fix.smem_start,
 417                                      fb->fb.fix.smem_len);
 418 }
 419
 420 static void realview_clcd_remove(struct clcd_fb *fb)
 421 {
 422         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 423                               fb->fb.screen_base, fb->fb.fix.smem_start);
 424 }
 425
 426 struct clcd_board clcd_plat_data = {
 427         .name           = "RealView",
 428         .check          = clcdfb_check,
 429         .decode         = clcdfb_decode,
 430         .disable        = realview_clcd_disable,
 431         .enable         = realview_clcd_enable,
 432         .setup          = realview_clcd_setup,
 433         .mmap           = realview_clcd_mmap,
 434         .remove         = realview_clcd_remove,
 435 };
 436
 437 #ifdef CONFIG_LEDS
 438 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
 439
 440 void realview_leds_event(led_event_t ledevt)
 441 {
 442         unsigned long flags;
 443         u32 val;
 444
 445         local_irq_save(flags);
 446         val = readl(VA_LEDS_BASE);
 447
 448         switch (ledevt) {
 449         case led_idle_start:
 450                 val = val & ~REALVIEW_SYS_LED0;
 451                 break;
 452
 453         case led_idle_end:
 454                 val = val | REALVIEW_SYS_LED0;
 455                 break;
 456
 457         case led_timer:
 458                 val = val ^ REALVIEW_SYS_LED1;
 459                 break;
 460
 461         case led_halted:
 462                 val = 0;
 463                 break;
 464
 465         default:
 466                 break;
 467         }
 468
 469         writel(val, VA_LEDS_BASE);
 470         local_irq_restore(flags);
 471 }
 472 #endif  /* CONFIG_LEDS */
 473
 474 /*
 475  * Where is the timer (VA)?
 476  */
 477 #define TIMER0_VA_BASE           __io_address(REALVIEW_TIMER0_1_BASE)
 478 #define TIMER1_VA_BASE          (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20)
 479 #define TIMER2_VA_BASE           __io_address(REALVIEW_TIMER2_3_BASE)
 480 #define TIMER3_VA_BASE          (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20)
 481
 482 /*
 483  * How long is the timer interval?
 484  */
 485 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 486 #if TIMER_INTERVAL >= 0x100000
 487 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
 488 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
 489 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 490 #elif TIMER_INTERVAL >= 0x10000
 491 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
 492 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
 493 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 494 #else
 495 #define TIMER_RELOAD    (TIMER_INTERVAL)
 496 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
 497 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 498 #endif
 499
 500 /*
 501  * Returns number of ms since last clock interrupt.  Note that interrupts
 502  * will have been disabled by do_gettimeoffset()
 503  */
 504 static unsigned long realview_gettimeoffset(void)
 505 {
 506         unsigned long ticks1, ticks2, status;
 507
 508         /*
 509          * Get the current number of ticks.  Note that there is a race
 510          * condition between us reading the timer and checking for
 511          * an interrupt.  We get around this by ensuring that the
 512          * counter has not reloaded between our two reads.
 513          */
 514         ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
 515         do {
 516                 ticks1 = ticks2;
 517                 status = __raw_readl(__io_address(REALVIEW_GIC_DIST_BASE + GIC_DIST_PENDING_SET)
 518                                      + ((IRQ_TIMERINT0_1 >> 5) << 2));
 519                 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
 520         } while (ticks2 > ticks1);
 521
 522         /*
 523          * Number of ticks since last interrupt.
 524          */
 525         ticks1 = TIMER_RELOAD - ticks2;
 526
 527         /*
 528          * Interrupt pending?  If so, we've reloaded once already.
 529          *
 530          * FIXME: Need to check this is effectively timer 0 that expires
 531          */
 532         if (status & IRQMASK_TIMERINT0_1)
 533                 ticks1 += TIMER_RELOAD;
 534
 535         /*
 536          * Convert the ticks to usecs
 537          */
 538         return TICKS2USECS(ticks1);
 539 }
 540
 541 /*
 542  * IRQ handler for the timer
 543  */
 544 static irqreturn_t realview_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 545 {
 546         write_seqlock(&xtime_lock);
 547
 548         // ...clear the interrupt
 549         writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
 550
 551         timer_tick(regs);
 552
 553 #ifdef CONFIG_SMP
 554         smp_send_timer();
 555         update_process_times(user_mode(regs));
 556 #endif
 557
 558         write_sequnlock(&xtime_lock);
 559
 560         return IRQ_HANDLED;
 561 }
 562
 563 static struct irqaction realview_timer_irq = {
 564         .name           = "RealView Timer Tick",
 565         .flags          = SA_INTERRUPT | SA_TIMER,
 566         .handler        = realview_timer_interrupt,
 567 };
 568
 569 /*
 570  * Set up timer interrupt, and return the current time in seconds.
 571  */
 572 static void __init realview_timer_init(void)
 573 {
 574         u32 val;
 575
 576         /*
 577          * set clock frequency:
 578          *      REALVIEW_REFCLK is 32KHz
 579          *      REALVIEW_TIMCLK is 1MHz
 580          */
 581         val = readl(__io_address(REALVIEW_SCTL_BASE));
 582         writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
 583                (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
 584                (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
 585                (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
 586                __io_address(REALVIEW_SCTL_BASE));
 587
 588         /*
 589          * Initialise to a known state (all timers off)
 590          */
 591         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 592         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 593         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 594         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 595
 596         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
 597         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
 598         writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
 599                TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
 600
 601         /*
 602          * Make irqs happen for the system timer
 603          */
 604         setup_irq(IRQ_TIMERINT0_1, &realview_timer_irq);
 605 }
 606
 607 struct sys_timer realview_timer = {
 608         .init           = realview_timer_init,
 609         .offset         = realview_gettimeoffset,
 610 };