Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/teigland/dlm
[linux-2.6] / drivers / net / wireless / b43 / phy_a.c
1 /*
2
3   Broadcom B43 wireless driver
4   IEEE 802.11a PHY driver
5
6   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
7   Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
8   Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
9   Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
10   Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11
12   This program is free software; you can redistribute it and/or modify
13   it under the terms of the GNU General Public License as published by
14   the Free Software Foundation; either version 2 of the License, or
15   (at your option) any later version.
16
17   This program is distributed in the hope that it will be useful,
18   but WITHOUT ANY WARRANTY; without even the implied warranty of
19   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20   GNU General Public License for more details.
21
22   You should have received a copy of the GNU General Public License
23   along with this program; see the file COPYING.  If not, write to
24   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
25   Boston, MA 02110-1301, USA.
26
27 */
28
29 #include "b43.h"
30 #include "phy_a.h"
31 #include "phy_common.h"
32 #include "wa.h"
33 #include "tables.h"
34 #include "main.h"
35
36
37 /* Get the freq, as it has to be written to the device. */
38 static inline u16 channel2freq_a(u8 channel)
39 {
40         B43_WARN_ON(channel > 200);
41
42         return (5000 + 5 * channel);
43 }
44
45 static inline u16 freq_r3A_value(u16 frequency)
46 {
47         u16 value;
48
49         if (frequency < 5091)
50                 value = 0x0040;
51         else if (frequency < 5321)
52                 value = 0x0000;
53         else if (frequency < 5806)
54                 value = 0x0080;
55         else
56                 value = 0x0040;
57
58         return value;
59 }
60
61 #if 0
62 /* This function converts a TSSI value to dBm in Q5.2 */
63 static s8 b43_aphy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
64 {
65         struct b43_phy *phy = &dev->phy;
66         struct b43_phy_a *aphy = phy->a;
67         s8 dbm = 0;
68         s32 tmp;
69
70         tmp = (aphy->tgt_idle_tssi - aphy->cur_idle_tssi + tssi);
71         tmp += 0x80;
72         tmp = clamp_val(tmp, 0x00, 0xFF);
73         dbm = aphy->tssi2dbm[tmp];
74         //TODO: There's a FIXME on the specs
75
76         return dbm;
77 }
78 #endif
79
80 static void b43_radio_set_tx_iq(struct b43_wldev *dev)
81 {
82         static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
83         static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
84         u16 tmp = b43_radio_read16(dev, 0x001E);
85         int i, j;
86
87         for (i = 0; i < 5; i++) {
88                 for (j = 0; j < 5; j++) {
89                         if (tmp == (data_high[i] << 4 | data_low[j])) {
90                                 b43_phy_write(dev, 0x0069,
91                                               (i - j) << 8 | 0x00C0);
92                                 return;
93                         }
94                 }
95         }
96 }
97
98 static void aphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
99 {
100         u16 freq, r8, tmp;
101
102         freq = channel2freq_a(channel);
103
104         r8 = b43_radio_read16(dev, 0x0008);
105         b43_write16(dev, 0x03F0, freq);
106         b43_radio_write16(dev, 0x0008, r8);
107
108         //TODO: write max channel TX power? to Radio 0x2D
109         tmp = b43_radio_read16(dev, 0x002E);
110         tmp &= 0x0080;
111         //TODO: OR tmp with the Power out estimation for this channel?
112         b43_radio_write16(dev, 0x002E, tmp);
113
114         if (freq >= 4920 && freq <= 5500) {
115                 /*
116                  * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
117                  *    = (freq * 0.025862069
118                  */
119                 r8 = 3 * freq / 116;    /* is equal to r8 = freq * 0.025862 */
120         }
121         b43_radio_write16(dev, 0x0007, (r8 << 4) | r8);
122         b43_radio_write16(dev, 0x0020, (r8 << 4) | r8);
123         b43_radio_write16(dev, 0x0021, (r8 << 4) | r8);
124         b43_radio_maskset(dev, 0x0022, 0x000F, (r8 << 4));
125         b43_radio_write16(dev, 0x002A, (r8 << 4));
126         b43_radio_write16(dev, 0x002B, (r8 << 4));
127         b43_radio_maskset(dev, 0x0008, 0x00F0, (r8 << 4));
128         b43_radio_maskset(dev, 0x0029, 0xFF0F, 0x00B0);
129         b43_radio_write16(dev, 0x0035, 0x00AA);
130         b43_radio_write16(dev, 0x0036, 0x0085);
131         b43_radio_maskset(dev, 0x003A, 0xFF20, freq_r3A_value(freq));
132         b43_radio_mask(dev, 0x003D, 0x00FF);
133         b43_radio_maskset(dev, 0x0081, 0xFF7F, 0x0080);
134         b43_radio_mask(dev, 0x0035, 0xFFEF);
135         b43_radio_maskset(dev, 0x0035, 0xFFEF, 0x0010);
136         b43_radio_set_tx_iq(dev);
137         //TODO: TSSI2dbm workaround
138 //FIXME b43_phy_xmitpower(dev);
139 }
140
141 static void b43_radio_init2060(struct b43_wldev *dev)
142 {
143         b43_radio_write16(dev, 0x0004, 0x00C0);
144         b43_radio_write16(dev, 0x0005, 0x0008);
145         b43_radio_write16(dev, 0x0009, 0x0040);
146         b43_radio_write16(dev, 0x0005, 0x00AA);
147         b43_radio_write16(dev, 0x0032, 0x008F);
148         b43_radio_write16(dev, 0x0006, 0x008F);
149         b43_radio_write16(dev, 0x0034, 0x008F);
150         b43_radio_write16(dev, 0x002C, 0x0007);
151         b43_radio_write16(dev, 0x0082, 0x0080);
152         b43_radio_write16(dev, 0x0080, 0x0000);
153         b43_radio_write16(dev, 0x003F, 0x00DA);
154         b43_radio_mask(dev, 0x0005, ~0x0008);
155         b43_radio_mask(dev, 0x0081, ~0x0010);
156         b43_radio_mask(dev, 0x0081, ~0x0020);
157         b43_radio_mask(dev, 0x0081, ~0x0020);
158         msleep(1);              /* delay 400usec */
159
160         b43_radio_maskset(dev, 0x0081, ~0x0020, 0x0010);
161         msleep(1);              /* delay 400usec */
162
163         b43_radio_maskset(dev, 0x0005, ~0x0008, 0x0008);
164         b43_radio_mask(dev, 0x0085, ~0x0010);
165         b43_radio_mask(dev, 0x0005, ~0x0008);
166         b43_radio_mask(dev, 0x0081, ~0x0040);
167         b43_radio_maskset(dev, 0x0081, ~0x0040, 0x0040);
168         b43_radio_write16(dev, 0x0005,
169                           (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);
170         b43_phy_write(dev, 0x0063, 0xDDC6);
171         b43_phy_write(dev, 0x0069, 0x07BE);
172         b43_phy_write(dev, 0x006A, 0x0000);
173
174         aphy_channel_switch(dev, dev->phy.ops->get_default_chan(dev));
175
176         msleep(1);
177 }
178
179 static void b43_phy_rssiagc(struct b43_wldev *dev, u8 enable)
180 {
181         int i;
182
183         if (dev->phy.rev < 3) {
184                 if (enable)
185                         for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
186                                 b43_ofdmtab_write16(dev,
187                                         B43_OFDMTAB_LNAHPFGAIN1, i, 0xFFF8);
188                                 b43_ofdmtab_write16(dev,
189                                         B43_OFDMTAB_WRSSI, i, 0xFFF8);
190                         }
191                 else
192                         for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
193                                 b43_ofdmtab_write16(dev,
194                                         B43_OFDMTAB_LNAHPFGAIN1, i, b43_tab_rssiagc1[i]);
195                                 b43_ofdmtab_write16(dev,
196                                         B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc1[i]);
197                         }
198         } else {
199                 if (enable)
200                         for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++)
201                                 b43_ofdmtab_write16(dev,
202                                         B43_OFDMTAB_WRSSI, i, 0x0820);
203                 else
204                         for (i = 0; i < B43_TAB_RSSIAGC2_SIZE; i++)
205                                 b43_ofdmtab_write16(dev,
206                                         B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc2[i]);
207         }
208 }
209
210 static void b43_phy_ww(struct b43_wldev *dev)
211 {
212         u16 b, curr_s, best_s = 0xFFFF;
213         int i;
214
215         b43_phy_mask(dev, B43_PHY_CRS0, ~B43_PHY_CRS0_EN);
216         b43_phy_set(dev, B43_PHY_OFDM(0x1B), 0x1000);
217         b43_phy_maskset(dev, B43_PHY_OFDM(0x82), 0xF0FF, 0x0300);
218         b43_radio_set(dev, 0x0009, 0x0080);
219         b43_radio_maskset(dev, 0x0012, 0xFFFC, 0x0002);
220         b43_wa_initgains(dev);
221         b43_phy_write(dev, B43_PHY_OFDM(0xBA), 0x3ED5);
222         b = b43_phy_read(dev, B43_PHY_PWRDOWN);
223         b43_phy_write(dev, B43_PHY_PWRDOWN, (b & 0xFFF8) | 0x0005);
224         b43_radio_set(dev, 0x0004, 0x0004);
225         for (i = 0x10; i <= 0x20; i++) {
226                 b43_radio_write16(dev, 0x0013, i);
227                 curr_s = b43_phy_read(dev, B43_PHY_OTABLEQ) & 0x00FF;
228                 if (!curr_s) {
229                         best_s = 0x0000;
230                         break;
231                 } else if (curr_s >= 0x0080)
232                         curr_s = 0x0100 - curr_s;
233                 if (curr_s < best_s)
234                         best_s = curr_s;
235         }
236         b43_phy_write(dev, B43_PHY_PWRDOWN, b);
237         b43_radio_mask(dev, 0x0004, 0xFFFB);
238         b43_radio_write16(dev, 0x0013, best_s);
239         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 0xFFEC);
240         b43_phy_write(dev, B43_PHY_OFDM(0xB7), 0x1E80);
241         b43_phy_write(dev, B43_PHY_OFDM(0xB6), 0x1C00);
242         b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0);
243         b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0);
244         b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF);
245         b43_phy_maskset(dev, B43_PHY_OFDM(0xBB), 0xF000, 0x0053);
246         b43_phy_maskset(dev, B43_PHY_OFDM61, 0xFE1F, 0x0120);
247         b43_phy_maskset(dev, B43_PHY_OFDM(0x13), 0x0FFF, 0x3000);
248         b43_phy_maskset(dev, B43_PHY_OFDM(0x14), 0x0FFF, 0x3000);
249         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017);
250         for (i = 0; i < 6; i++)
251                 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F);
252         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0D, 0x000E);
253         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0E, 0x0011);
254         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0F, 0x0013);
255         b43_phy_write(dev, B43_PHY_OFDM(0x33), 0x5030);
256         b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN);
257 }
258
259 static void hardware_pctl_init_aphy(struct b43_wldev *dev)
260 {
261         //TODO
262 }
263
264 void b43_phy_inita(struct b43_wldev *dev)
265 {
266         struct ssb_bus *bus = dev->dev->bus;
267         struct b43_phy *phy = &dev->phy;
268
269         /* This lowlevel A-PHY init is also called from G-PHY init.
270          * So we must not access phy->a, if called from G-PHY code.
271          */
272         B43_WARN_ON((phy->type != B43_PHYTYPE_A) &&
273                     (phy->type != B43_PHYTYPE_G));
274
275         might_sleep();
276
277         if (phy->rev >= 6) {
278                 if (phy->type == B43_PHYTYPE_A)
279                         b43_phy_mask(dev, B43_PHY_OFDM(0x1B), ~0x1000);
280                 if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)
281                         b43_phy_set(dev, B43_PHY_ENCORE, 0x0010);
282                 else
283                         b43_phy_mask(dev, B43_PHY_ENCORE, ~0x1010);
284         }
285
286         b43_wa_all(dev);
287
288         if (phy->type == B43_PHYTYPE_A) {
289                 if (phy->gmode && (phy->rev < 3))
290                         b43_phy_set(dev, 0x0034, 0x0001);
291                 b43_phy_rssiagc(dev, 0);
292
293                 b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN);
294
295                 b43_radio_init2060(dev);
296
297                 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
298                     ((bus->boardinfo.type == SSB_BOARD_BU4306) ||
299                      (bus->boardinfo.type == SSB_BOARD_BU4309))) {
300                         ; //TODO: A PHY LO
301                 }
302
303                 if (phy->rev >= 3)
304                         b43_phy_ww(dev);
305
306                 hardware_pctl_init_aphy(dev);
307
308                 //TODO: radar detection
309         }
310
311         if ((phy->type == B43_PHYTYPE_G) &&
312             (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)) {
313                 b43_phy_maskset(dev, B43_PHY_OFDM(0x6E), 0xE000, 0x3CF);
314         }
315 }
316
317 /* Initialise the TSSI->dBm lookup table */
318 static int b43_aphy_init_tssi2dbm_table(struct b43_wldev *dev)
319 {
320         struct b43_phy *phy = &dev->phy;
321         struct b43_phy_a *aphy = phy->a;
322         s16 pab0, pab1, pab2;
323
324         pab0 = (s16) (dev->dev->bus->sprom.pa1b0);
325         pab1 = (s16) (dev->dev->bus->sprom.pa1b1);
326         pab2 = (s16) (dev->dev->bus->sprom.pa1b2);
327
328         if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
329             pab0 != -1 && pab1 != -1 && pab2 != -1) {
330                 /* The pabX values are set in SPROM. Use them. */
331                 if ((s8) dev->dev->bus->sprom.itssi_a != 0 &&
332                     (s8) dev->dev->bus->sprom.itssi_a != -1)
333                         aphy->tgt_idle_tssi =
334                             (s8) (dev->dev->bus->sprom.itssi_a);
335                 else
336                         aphy->tgt_idle_tssi = 62;
337                 aphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0,
338                                                                pab1, pab2);
339                 if (!aphy->tssi2dbm)
340                         return -ENOMEM;
341         } else {
342                 /* pabX values not set in SPROM,
343                  * but APHY needs a generated table. */
344                 aphy->tssi2dbm = NULL;
345                 b43err(dev->wl, "Could not generate tssi2dBm "
346                        "table (wrong SPROM info)!\n");
347                 return -ENODEV;
348         }
349
350         return 0;
351 }
352
353 static int b43_aphy_op_allocate(struct b43_wldev *dev)
354 {
355         struct b43_phy_a *aphy;
356         int err;
357
358         aphy = kzalloc(sizeof(*aphy), GFP_KERNEL);
359         if (!aphy)
360                 return -ENOMEM;
361         dev->phy.a = aphy;
362
363         err = b43_aphy_init_tssi2dbm_table(dev);
364         if (err)
365                 goto err_free_aphy;
366
367         return 0;
368
369 err_free_aphy:
370         kfree(aphy);
371         dev->phy.a = NULL;
372
373         return err;
374 }
375
376 static void b43_aphy_op_prepare_structs(struct b43_wldev *dev)
377 {
378         struct b43_phy *phy = &dev->phy;
379         struct b43_phy_a *aphy = phy->a;
380         const void *tssi2dbm;
381         int tgt_idle_tssi;
382
383         /* tssi2dbm table is constant, so it is initialized at alloc time.
384          * Save a copy of the pointer. */
385         tssi2dbm = aphy->tssi2dbm;
386         tgt_idle_tssi = aphy->tgt_idle_tssi;
387
388         /* Zero out the whole PHY structure. */
389         memset(aphy, 0, sizeof(*aphy));
390
391         aphy->tssi2dbm = tssi2dbm;
392         aphy->tgt_idle_tssi = tgt_idle_tssi;
393
394         //TODO init struct b43_phy_a
395
396 }
397
398 static void b43_aphy_op_free(struct b43_wldev *dev)
399 {
400         struct b43_phy *phy = &dev->phy;
401         struct b43_phy_a *aphy = phy->a;
402
403         kfree(aphy->tssi2dbm);
404         aphy->tssi2dbm = NULL;
405
406         kfree(aphy);
407         dev->phy.a = NULL;
408 }
409
410 static int b43_aphy_op_init(struct b43_wldev *dev)
411 {
412         b43_phy_inita(dev);
413
414         return 0;
415 }
416
417 static inline u16 adjust_phyreg(struct b43_wldev *dev, u16 offset)
418 {
419         /* OFDM registers are base-registers for the A-PHY. */
420         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
421                 offset &= ~B43_PHYROUTE;
422                 offset |= B43_PHYROUTE_BASE;
423         }
424
425 #if B43_DEBUG
426         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
427                 /* Ext-G registers are only available on G-PHYs */
428                 b43err(dev->wl, "Invalid EXT-G PHY access at "
429                        "0x%04X on A-PHY\n", offset);
430                 dump_stack();
431         }
432         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_N_BMODE) {
433                 /* N-BMODE registers are only available on N-PHYs */
434                 b43err(dev->wl, "Invalid N-BMODE PHY access at "
435                        "0x%04X on A-PHY\n", offset);
436                 dump_stack();
437         }
438 #endif /* B43_DEBUG */
439
440         return offset;
441 }
442
443 static u16 b43_aphy_op_read(struct b43_wldev *dev, u16 reg)
444 {
445         reg = adjust_phyreg(dev, reg);
446         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
447         return b43_read16(dev, B43_MMIO_PHY_DATA);
448 }
449
450 static void b43_aphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
451 {
452         reg = adjust_phyreg(dev, reg);
453         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
454         b43_write16(dev, B43_MMIO_PHY_DATA, value);
455 }
456
457 static u16 b43_aphy_op_radio_read(struct b43_wldev *dev, u16 reg)
458 {
459         /* Register 1 is a 32-bit register. */
460         B43_WARN_ON(reg == 1);
461         /* A-PHY needs 0x40 for read access */
462         reg |= 0x40;
463
464         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
465         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
466 }
467
468 static void b43_aphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
469 {
470         /* Register 1 is a 32-bit register. */
471         B43_WARN_ON(reg == 1);
472
473         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
474         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
475 }
476
477 static bool b43_aphy_op_supports_hwpctl(struct b43_wldev *dev)
478 {
479         return (dev->phy.rev >= 5);
480 }
481
482 static void b43_aphy_op_software_rfkill(struct b43_wldev *dev,
483                                         enum rfkill_state state)
484 {
485         struct b43_phy *phy = &dev->phy;
486
487         if (state == RFKILL_STATE_UNBLOCKED) {
488                 if (phy->radio_on)
489                         return;
490                 b43_radio_write16(dev, 0x0004, 0x00C0);
491                 b43_radio_write16(dev, 0x0005, 0x0008);
492                 b43_phy_mask(dev, 0x0010, 0xFFF7);
493                 b43_phy_mask(dev, 0x0011, 0xFFF7);
494                 b43_radio_init2060(dev);
495         } else {
496                 b43_radio_write16(dev, 0x0004, 0x00FF);
497                 b43_radio_write16(dev, 0x0005, 0x00FB);
498                 b43_phy_set(dev, 0x0010, 0x0008);
499                 b43_phy_set(dev, 0x0011, 0x0008);
500         }
501 }
502
503 static int b43_aphy_op_switch_channel(struct b43_wldev *dev,
504                                       unsigned int new_channel)
505 {
506         if (new_channel > 200)
507                 return -EINVAL;
508         aphy_channel_switch(dev, new_channel);
509
510         return 0;
511 }
512
513 static unsigned int b43_aphy_op_get_default_chan(struct b43_wldev *dev)
514 {
515         return 36; /* Default to channel 36 */
516 }
517
518 static void b43_aphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
519 {//TODO
520         struct b43_phy *phy = &dev->phy;
521         u64 hf;
522         u16 tmp;
523         int autodiv = 0;
524
525         if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
526                 autodiv = 1;
527
528         hf = b43_hf_read(dev);
529         hf &= ~B43_HF_ANTDIVHELP;
530         b43_hf_write(dev, hf);
531
532         tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
533         tmp &= ~B43_PHY_BBANDCFG_RXANT;
534         tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
535             << B43_PHY_BBANDCFG_RXANT_SHIFT;
536         b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
537
538         if (autodiv) {
539                 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
540                 if (antenna == B43_ANTENNA_AUTO0)
541                         tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
542                 else
543                         tmp |= B43_PHY_ANTDWELL_AUTODIV1;
544                 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
545         }
546         if (phy->rev < 3) {
547                 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
548                 tmp = (tmp & 0xFF00) | 0x24;
549                 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
550         } else {
551                 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
552                 tmp |= 0x10;
553                 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
554                 if (phy->analog == 3) {
555                         b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
556                                       0x1D);
557                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
558                                       8);
559                 } else {
560                         b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
561                                       0x3A);
562                         tmp =
563                             b43_phy_read(dev,
564                                          B43_PHY_ADIVRELATED);
565                         tmp = (tmp & 0xFF00) | 8;
566                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
567                                       tmp);
568                 }
569         }
570
571         hf |= B43_HF_ANTDIVHELP;
572         b43_hf_write(dev, hf);
573 }
574
575 static void b43_aphy_op_adjust_txpower(struct b43_wldev *dev)
576 {//TODO
577 }
578
579 static enum b43_txpwr_result b43_aphy_op_recalc_txpower(struct b43_wldev *dev,
580                                                         bool ignore_tssi)
581 {//TODO
582         return B43_TXPWR_RES_DONE;
583 }
584
585 static void b43_aphy_op_pwork_15sec(struct b43_wldev *dev)
586 {//TODO
587 }
588
589 static void b43_aphy_op_pwork_60sec(struct b43_wldev *dev)
590 {//TODO
591 }
592
593 const struct b43_phy_operations b43_phyops_a = {
594         .allocate               = b43_aphy_op_allocate,
595         .free                   = b43_aphy_op_free,
596         .prepare_structs        = b43_aphy_op_prepare_structs,
597         .init                   = b43_aphy_op_init,
598         .phy_read               = b43_aphy_op_read,
599         .phy_write              = b43_aphy_op_write,
600         .radio_read             = b43_aphy_op_radio_read,
601         .radio_write            = b43_aphy_op_radio_write,
602         .supports_hwpctl        = b43_aphy_op_supports_hwpctl,
603         .software_rfkill        = b43_aphy_op_software_rfkill,
604         .switch_analog          = b43_phyop_switch_analog_generic,
605         .switch_channel         = b43_aphy_op_switch_channel,
606         .get_default_chan       = b43_aphy_op_get_default_chan,
607         .set_rx_antenna         = b43_aphy_op_set_rx_antenna,
608         .recalc_txpower         = b43_aphy_op_recalc_txpower,
609         .adjust_txpower         = b43_aphy_op_adjust_txpower,
610         .pwork_15sec            = b43_aphy_op_pwork_15sec,
611         .pwork_60sec            = b43_aphy_op_pwork_60sec,
612 };