2 * arch/arm/mach-ixp2000/ixdp2x00.c
4 * Code common to IXDP2400 and IXDP2800 platforms.
6 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
9 * Copyright (C) 2002 Intel Corp.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
17 #include <linux/kernel.h>
18 #include <linux/init.h>
20 #include <linux/sched.h>
21 #include <linux/interrupt.h>
22 #include <linux/platform_device.h>
23 #include <linux/bitops.h>
24 #include <linux/pci.h>
25 #include <linux/ioport.h>
26 #include <linux/slab.h>
27 #include <linux/delay.h>
31 #include <asm/pgtable.h>
33 #include <asm/system.h>
34 #include <mach/hardware.h>
35 #include <asm/mach-types.h>
37 #include <asm/mach/pci.h>
38 #include <asm/mach/map.h>
39 #include <asm/mach/irq.h>
40 #include <asm/mach/time.h>
41 #include <asm/mach/flash.h>
42 #include <asm/mach/arch.h>
44 #include <mach/gpio.h>
47 /*************************************************************************
48 * IXDP2x00 IRQ Initialization
49 *************************************************************************/
50 static volatile unsigned long *board_irq_mask;
51 static volatile unsigned long *board_irq_stat;
52 static unsigned long board_irq_count;
54 #ifdef CONFIG_ARCH_IXDP2400
56 * Slowport configuration for accessing CPLD registers on IXDP2x00
58 static struct slowport_cfg slowport_cpld_cfg = {
59 .CCR = SLOWPORT_CCR_DIV_2,
62 .PCR = SLOWPORT_MODE_FLASH,
63 .ADC = SLOWPORT_ADDR_WIDTH_24 | SLOWPORT_DATA_WIDTH_8
67 static void ixdp2x00_irq_mask(unsigned int irq)
70 static struct slowport_cfg old_cfg;
73 * This is ugly in common code but really don't know
74 * of a better way to handle it. :(
76 #ifdef CONFIG_ARCH_IXDP2400
77 if (machine_is_ixdp2400())
78 ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg);
81 dummy = *board_irq_mask;
82 dummy |= IXP2000_BOARD_IRQ_MASK(irq);
83 ixp2000_reg_wrb(board_irq_mask, dummy);
85 #ifdef CONFIG_ARCH_IXDP2400
86 if (machine_is_ixdp2400())
87 ixp2000_release_slowport(&old_cfg);
91 static void ixdp2x00_irq_unmask(unsigned int irq)
94 static struct slowport_cfg old_cfg;
96 #ifdef CONFIG_ARCH_IXDP2400
97 if (machine_is_ixdp2400())
98 ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg);
101 dummy = *board_irq_mask;
102 dummy &= ~IXP2000_BOARD_IRQ_MASK(irq);
103 ixp2000_reg_wrb(board_irq_mask, dummy);
105 if (machine_is_ixdp2400())
106 ixp2000_release_slowport(&old_cfg);
109 static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc)
111 volatile u32 ex_interrupt = 0;
112 static struct slowport_cfg old_cfg;
115 desc->chip->mask(irq);
117 #ifdef CONFIG_ARCH_IXDP2400
118 if (machine_is_ixdp2400())
119 ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg);
121 ex_interrupt = *board_irq_stat & 0xff;
122 if (machine_is_ixdp2400())
123 ixp2000_release_slowport(&old_cfg);
126 printk(KERN_ERR "Spurious IXDP2x00 CPLD interrupt!\n");
130 for(i = 0; i < board_irq_count; i++) {
131 if(ex_interrupt & (1 << i)) {
132 int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
133 generic_handle_irq(cpld_irq);
137 desc->chip->unmask(irq);
140 static struct irq_chip ixdp2x00_cpld_irq_chip = {
141 .ack = ixdp2x00_irq_mask,
142 .mask = ixdp2x00_irq_mask,
143 .unmask = ixdp2x00_irq_unmask
146 void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long *mask_reg, unsigned long nr_of_irqs)
152 if (!ixdp2x00_master_npu())
155 board_irq_stat = stat_reg;
156 board_irq_mask = mask_reg;
157 board_irq_count = nr_of_irqs;
159 *board_irq_mask = 0xffffffff;
161 for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) {
162 set_irq_chip(irq, &ixdp2x00_cpld_irq_chip);
163 set_irq_handler(irq, handle_level_irq);
164 set_irq_flags(irq, IRQF_VALID);
167 /* Hook into PCI interrupt */
168 set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler);
171 /*************************************************************************
172 * IXDP2x00 memory map
173 *************************************************************************/
174 static struct map_desc ixdp2x00_io_desc __initdata = {
175 .virtual = IXDP2X00_VIRT_CPLD_BASE,
176 .pfn = __phys_to_pfn(IXDP2X00_PHYS_CPLD_BASE),
177 .length = IXDP2X00_CPLD_SIZE,
181 void __init ixdp2x00_map_io(void)
185 iotable_init(&ixdp2x00_io_desc, 1);
188 /*************************************************************************
189 * IXDP2x00-common PCI init
191 * The IXDP2[48]00 has a horrid PCI bus layout. Basically the board
192 * contains two NPUs (ingress and egress) connected over PCI, both running
193 * instances of the kernel. So far so good. Peers on the PCI bus running
194 * Linux is a common design in telecom systems. The problem is that instead
195 * of all the devices being controlled by a single host, different
196 * devices are controlled by different NPUs on the same bus, leading to
197 * multiple hosts on the bus. The exact bus layout looks like:
200 * Master NPU <-------------------+-------------------> Slave NPU
207 * <--+------+---------+---------+------+-->
210 * ... Dev PMC Media Eth0 Eth1 ...
212 * The master controls all but Eth1, which is controlled by the
213 * slave. What this means is that the both the master and the slave
214 * have to scan the bus, but only one of them can enumerate the bus.
215 * In addition, after the bus is scanned, each kernel must remove
216 * the device(s) it does not control from the PCI dev list otherwise
217 * a driver on each NPU will try to manage it and we will have horrible
218 * conflicts. Oh..and the slave NPU needs to see the master NPU
219 * for Intel's drivers to work properly. Closed source drivers...
221 * The way we deal with this is fairly simple but ugly:
223 * 1) Let master scan and enumerate the bus completely.
224 * 2) Master deletes Eth1 from device list.
225 * 3) Slave scans bus and then deletes all but Eth1 (Eth0 on slave)
227 * 4) Find HW designers and LART them.
229 * The boards also do not do normal PCI IRQ routing, or any sort of
230 * sensical swizzling, so we just need to check where on the bus a
231 * device sits and figure out to which CPLD pin the interrupt is routed.
232 * See ixdp2[48]00.c files.
234 *************************************************************************/
235 void ixdp2x00_slave_pci_postinit(void)
240 * Remove PMC device is there is one
242 if((dev = pci_get_bus_and_slot(1, IXDP2X00_PMC_DEVFN))) {
243 pci_remove_bus_device(dev);
247 dev = pci_get_bus_and_slot(0, IXDP2X00_21555_DEVFN);
248 pci_remove_bus_device(dev);
252 /**************************************************************************
253 * IXDP2x00 Machine Setup
254 *************************************************************************/
255 static struct flash_platform_data ixdp2x00_platform_data = {
256 .map_name = "cfi_probe",
260 static struct ixp2000_flash_data ixdp2x00_flash_data = {
261 .platform_data = &ixdp2x00_platform_data,
265 static struct resource ixdp2x00_flash_resource = {
267 .end = 0xc4000000 + 0x00ffffff,
268 .flags = IORESOURCE_MEM,
271 static struct platform_device ixdp2x00_flash = {
272 .name = "IXP2000-Flash",
275 .platform_data = &ixdp2x00_flash_data,
278 .resource = &ixdp2x00_flash_resource,
281 static struct ixp2000_i2c_pins ixdp2x00_i2c_gpio_pins = {
282 .sda_pin = IXDP2X00_GPIO_SDA,
283 .scl_pin = IXDP2X00_GPIO_SCL,
286 static struct platform_device ixdp2x00_i2c_controller = {
287 .name = "IXP2000-I2C",
290 .platform_data = &ixdp2x00_i2c_gpio_pins,
295 static struct platform_device *ixdp2x00_devices[] __initdata = {
297 &ixdp2x00_i2c_controller
300 void __init ixdp2x00_init_machine(void)
302 gpio_line_set(IXDP2X00_GPIO_I2C_ENABLE, 1);
303 gpio_line_config(IXDP2X00_GPIO_I2C_ENABLE, GPIO_OUT);
305 platform_add_devices(ixdp2x00_devices, ARRAY_SIZE(ixdp2x00_devices));