Merge branch 'fix/hda' into for-linus
[linux-2.6] / arch / arm / mach-omap2 / clock24xx.c
1 /*
2  *  linux/arch/arm/mach-omap2/clock.c
3  *
4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
5  *  Copyright (C) 2004-2008 Nokia Corporation
6  *
7  *  Contacts:
8  *  Richard Woodruff <r-woodruff2@ti.com>
9  *  Paul Walmsley
10  *
11  *  Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12  *  Gordon McNutt and RidgeRun, Inc.
13  *
14  * This program is free software; you can redistribute it and/or modify
15  * it under the terms of the GNU General Public License version 2 as
16  * published by the Free Software Foundation.
17  */
18 #undef DEBUG
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/device.h>
23 #include <linux/list.h>
24 #include <linux/errno.h>
25 #include <linux/delay.h>
26 #include <linux/clk.h>
27 #include <linux/io.h>
28 #include <linux/cpufreq.h>
29 #include <linux/bitops.h>
30
31 #include <mach/clock.h>
32 #include <mach/sram.h>
33 #include <asm/div64.h>
34 #include <asm/clkdev.h>
35
36 #include <mach/sdrc.h>
37 #include "clock.h"
38 #include "prm.h"
39 #include "prm-regbits-24xx.h"
40 #include "cm.h"
41 #include "cm-regbits-24xx.h"
42
43 static const struct clkops clkops_oscck;
44 static const struct clkops clkops_fixed;
45
46 #include "clock24xx.h"
47
48 struct omap_clk {
49         u32             cpu;
50         struct clk_lookup lk;
51 };
52
53 #define CLK(dev, con, ck, cp)           \
54         {                               \
55                  .cpu = cp,             \
56                 .lk = {                 \
57                         .dev_id = dev,  \
58                         .con_id = con,  \
59                         .clk = ck,      \
60                 },                      \
61         }
62
63 #define CK_243X                 RATE_IN_243X
64 #define CK_242X                 RATE_IN_242X
65
66 static struct omap_clk omap24xx_clks[] = {
67         /* external root sources */
68         CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_243X | CK_242X),
69         CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X),
70         CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X | CK_242X),
71         CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X | CK_242X),
72         CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X | CK_242X),
73         /* internal analog sources */
74         CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X | CK_242X),
75         CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_243X | CK_242X),
76         CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_243X | CK_242X),
77         /* internal prcm root sources */
78         CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X | CK_242X),
79         CLK(NULL,       "core_ck",      &core_ck,       CK_243X | CK_242X),
80         CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X | CK_242X),
81         CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X | CK_242X),
82         CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X | CK_242X),
83         CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_243X | CK_242X),
84         CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
85         CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_243X | CK_242X),
86         CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src, CK_242X),
87         CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_242X),
88         CLK(NULL,       "emul_ck",      &emul_ck,       CK_242X),
89         /* mpu domain clocks */
90         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_243X | CK_242X),
91         /* dsp domain clocks */
92         CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_243X | CK_242X),
93         CLK(NULL,       "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
94         CLK(NULL,       "dsp_ick",      &dsp_ick,       CK_242X),
95         CLK(NULL,       "iva2_1_ick",   &iva2_1_ick,    CK_243X),
96         CLK(NULL,       "iva1_ifck",    &iva1_ifck,     CK_242X),
97         CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
98         /* GFX domain clocks */
99         CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_243X | CK_242X),
100         CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_243X | CK_242X),
101         CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_243X | CK_242X),
102         /* Modem domain clocks */
103         CLK(NULL,       "mdm_ick",      &mdm_ick,       CK_243X),
104         CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
105         /* DSS domain clocks */
106         CLK("omapfb",   "ick",          &dss_ick,       CK_243X | CK_242X),
107         CLK("omapfb",   "dss1_fck",     &dss1_fck,      CK_243X | CK_242X),
108         CLK("omapfb",   "dss2_fck",     &dss2_fck,      CK_243X | CK_242X),
109         CLK("omapfb",   "tv_fck",       &dss_54m_fck,   CK_243X | CK_242X),
110         /* L3 domain clocks */
111         CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_243X | CK_242X),
112         CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_243X | CK_242X),
113         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_243X | CK_242X),
114         /* L4 domain clocks */
115         CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X | CK_242X),
116         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X | CK_242X),
117         /* virtual meta-group clock */
118         CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
119         /* general l4 interface ck, multi-parent functional clk */
120         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_243X | CK_242X),
121         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_243X | CK_242X),
122         CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_243X | CK_242X),
123         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_243X | CK_242X),
124         CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_243X | CK_242X),
125         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_243X | CK_242X),
126         CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_243X | CK_242X),
127         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_243X | CK_242X),
128         CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_243X | CK_242X),
129         CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_243X | CK_242X),
130         CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_243X | CK_242X),
131         CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_243X | CK_242X),
132         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_243X | CK_242X),
133         CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_243X | CK_242X),
134         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_243X | CK_242X),
135         CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_243X | CK_242X),
136         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_243X | CK_242X),
137         CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_243X | CK_242X),
138         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_243X | CK_242X),
139         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_243X | CK_242X),
140         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_243X | CK_242X),
141         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_243X | CK_242X),
142         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X | CK_242X),
143         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X | CK_242X),
144         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X | CK_242X),
145         CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_243X | CK_242X),
146         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X | CK_242X),
147         CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_243X | CK_242X),
148         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
149         CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_243X),
150         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
151         CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_243X),
152         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
153         CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_243X),
154         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X | CK_242X),
155         CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_243X | CK_242X),
156         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X | CK_242X),
157         CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_243X | CK_242X),
158         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
159         CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_243X),
160         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X | CK_242X),
161         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X | CK_242X),
162         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_243X | CK_242X),
163         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_243X | CK_242X),
164         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_243X | CK_242X),
165         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_243X | CK_242X),
166         CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X | CK_242X),
167         CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X | CK_242X),
168         CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X | CK_242X),
169         CLK("omap_wdt", "fck",          &mpu_wdt_fck,   CK_243X | CK_242X),
170         CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X | CK_242X),
171         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X | CK_242X),
172         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X | CK_242X),
173         CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
174         CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X | CK_242X),
175         CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X | CK_242X),
176         CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X | CK_242X),
177         CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X | CK_242X),
178         CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X | CK_242X),
179         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_242X),
180         CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_242X),
181         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_243X | CK_242X),
182         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_243X | CK_242X),
183         CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
184         CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
185         CLK(NULL,       "fac_ick",      &fac_ick,       CK_243X | CK_242X),
186         CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X | CK_242X),
187         CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
188         CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
189         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X | CK_242X),
190         CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X | CK_242X),
191         CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_243X | CK_242X),
192         CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_242X),
193         CLK("i2c_omap.1", "fck",        &i2chs1_fck,    CK_243X),
194         CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_243X | CK_242X),
195         CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_242X),
196         CLK("i2c_omap.2", "fck",        &i2chs2_fck,    CK_243X),
197         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X | CK_242X),
198         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X | CK_242X),
199         CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_243X | CK_242X),
200         CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
201         CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
202         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_243X),
203         CLK(NULL,       "des_ick",      &des_ick,       CK_243X | CK_242X),
204         CLK(NULL,       "sha_ick",      &sha_ick,       CK_243X | CK_242X),
205         CLK("omap_rng", "ick",          &rng_ick,       CK_243X | CK_242X),
206         CLK(NULL,       "aes_ick",      &aes_ick,       CK_243X | CK_242X),
207         CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X | CK_242X),
208         CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X | CK_242X),
209         CLK("musb_hdrc",        "ick",  &usbhs_ick,     CK_243X),
210         CLK("mmci-omap-hs.0", "ick",    &mmchs1_ick,    CK_243X),
211         CLK("mmci-omap-hs.0", "fck",    &mmchs1_fck,    CK_243X),
212         CLK("mmci-omap-hs.1", "ick",    &mmchs2_ick,    CK_243X),
213         CLK("mmci-omap-hs.1", "fck",    &mmchs2_fck,    CK_243X),
214         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
215         CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
216         CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
217         CLK("mmci-omap-hs.0", "mmchsdb_fck",    &mmchsdb1_fck,  CK_243X),
218         CLK("mmci-omap-hs.1", "mmchsdb_fck",    &mmchsdb2_fck,  CK_243X),
219 };
220
221 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
222 #define EN_APLL_STOPPED                 0
223 #define EN_APLL_LOCKED                  3
224
225 /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
226 #define APLLS_CLKIN_19_2MHZ             0
227 #define APLLS_CLKIN_13MHZ               2
228 #define APLLS_CLKIN_12MHZ               3
229
230 /* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
231
232 static struct prcm_config *curr_prcm_set;
233 static struct clk *vclk;
234 static struct clk *sclk;
235
236 /*-------------------------------------------------------------------------
237  * Omap24xx specific clock functions
238  *-------------------------------------------------------------------------*/
239
240 /**
241  * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
242  * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
243  *
244  * Returns the CORE_CLK rate.  CORE_CLK can have one of three rate
245  * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
246  * (the latter is unusual).  This currently should be called with
247  * struct clk *dpll_ck, which is a composite clock of dpll_ck and
248  * core_ck.
249  */
250 static unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
251 {
252         long long core_clk;
253         u32 v;
254
255         core_clk = omap2_get_dpll_rate(clk);
256
257         v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
258         v &= OMAP24XX_CORE_CLK_SRC_MASK;
259
260         if (v == CORE_CLK_SRC_32K)
261                 core_clk = 32768;
262         else
263                 core_clk *= v;
264
265         return core_clk;
266 }
267
268 static int omap2_enable_osc_ck(struct clk *clk)
269 {
270         u32 pcc;
271
272         pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
273
274         __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
275                       OMAP24XX_PRCM_CLKSRC_CTRL);
276
277         return 0;
278 }
279
280 static void omap2_disable_osc_ck(struct clk *clk)
281 {
282         u32 pcc;
283
284         pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
285
286         __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK,
287                       OMAP24XX_PRCM_CLKSRC_CTRL);
288 }
289
290 static const struct clkops clkops_oscck = {
291         .enable         = &omap2_enable_osc_ck,
292         .disable        = &omap2_disable_osc_ck,
293 };
294
295 #ifdef OLD_CK
296 /* Recalculate SYST_CLK */
297 static void omap2_sys_clk_recalc(struct clk * clk)
298 {
299         u32 div = PRCM_CLKSRC_CTRL;
300         div &= (1 << 7) | (1 << 6);     /* Test if ext clk divided by 1 or 2 */
301         div >>= clk->rate_offset;
302         clk->rate = (clk->parent->rate / div);
303         propagate_rate(clk);
304 }
305 #endif  /* OLD_CK */
306
307 /* Enable an APLL if off */
308 static int omap2_clk_fixed_enable(struct clk *clk)
309 {
310         u32 cval, apll_mask;
311
312         apll_mask = EN_APLL_LOCKED << clk->enable_bit;
313
314         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
315
316         if ((cval & apll_mask) == apll_mask)
317                 return 0;   /* apll already enabled */
318
319         cval &= ~apll_mask;
320         cval |= apll_mask;
321         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
322
323         if (clk == &apll96_ck)
324                 cval = OMAP24XX_ST_96M_APLL;
325         else if (clk == &apll54_ck)
326                 cval = OMAP24XX_ST_54M_APLL;
327
328         omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
329                             clk->name);
330
331         /*
332          * REVISIT: Should we return an error code if omap2_wait_clock_ready()
333          * fails?
334          */
335         return 0;
336 }
337
338 /* Stop APLL */
339 static void omap2_clk_fixed_disable(struct clk *clk)
340 {
341         u32 cval;
342
343         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
344         cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
345         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
346 }
347
348 static const struct clkops clkops_fixed = {
349         .enable         = &omap2_clk_fixed_enable,
350         .disable        = &omap2_clk_fixed_disable,
351 };
352
353 /*
354  * Uses the current prcm set to tell if a rate is valid.
355  * You can go slower, but not faster within a given rate set.
356  */
357 static long omap2_dpllcore_round_rate(unsigned long target_rate)
358 {
359         u32 high, low, core_clk_src;
360
361         core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
362         core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
363
364         if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
365                 high = curr_prcm_set->dpll_speed * 2;
366                 low = curr_prcm_set->dpll_speed;
367         } else {                                /* DPLL clockout x 2 */
368                 high = curr_prcm_set->dpll_speed;
369                 low = curr_prcm_set->dpll_speed / 2;
370         }
371
372 #ifdef DOWN_VARIABLE_DPLL
373         if (target_rate > high)
374                 return high;
375         else
376                 return target_rate;
377 #else
378         if (target_rate > low)
379                 return high;
380         else
381                 return low;
382 #endif
383
384 }
385
386 static unsigned long omap2_dpllcore_recalc(struct clk *clk)
387 {
388         return omap2xxx_clk_get_core_rate(clk);
389 }
390
391 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
392 {
393         u32 cur_rate, low, mult, div, valid_rate, done_rate;
394         u32 bypass = 0;
395         struct prcm_config tmpset;
396         const struct dpll_data *dd;
397
398         cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
399         mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
400         mult &= OMAP24XX_CORE_CLK_SRC_MASK;
401
402         if ((rate == (cur_rate / 2)) && (mult == 2)) {
403                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
404         } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
405                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
406         } else if (rate != cur_rate) {
407                 valid_rate = omap2_dpllcore_round_rate(rate);
408                 if (valid_rate != rate)
409                         return -EINVAL;
410
411                 if (mult == 1)
412                         low = curr_prcm_set->dpll_speed;
413                 else
414                         low = curr_prcm_set->dpll_speed / 2;
415
416                 dd = clk->dpll_data;
417                 if (!dd)
418                         return -EINVAL;
419
420                 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
421                 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
422                                            dd->div1_mask);
423                 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
424                 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
425                 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
426                 if (rate > low) {
427                         tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
428                         mult = ((rate / 2) / 1000000);
429                         done_rate = CORE_CLK_SRC_DPLL_X2;
430                 } else {
431                         tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
432                         mult = (rate / 1000000);
433                         done_rate = CORE_CLK_SRC_DPLL;
434                 }
435                 tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
436                 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
437
438                 /* Worst case */
439                 tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
440
441                 if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
442                         bypass = 1;
443
444                 /* For omap2xxx_sdrc_init_params() */
445                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
446
447                 /* Force dll lock mode */
448                 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
449                                bypass);
450
451                 /* Errata: ret dll entry state */
452                 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
453                 omap2xxx_sdrc_reprogram(done_rate, 0);
454         }
455
456         return 0;
457 }
458
459 /**
460  * omap2_table_mpu_recalc - just return the MPU speed
461  * @clk: virt_prcm_set struct clk
462  *
463  * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
464  */
465 static unsigned long omap2_table_mpu_recalc(struct clk *clk)
466 {
467         return curr_prcm_set->mpu_speed;
468 }
469
470 /*
471  * Look for a rate equal or less than the target rate given a configuration set.
472  *
473  * What's not entirely clear is "which" field represents the key field.
474  * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
475  * just uses the ARM rates.
476  */
477 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
478 {
479         struct prcm_config *ptr;
480         long highest_rate;
481
482         if (clk != &virt_prcm_set)
483                 return -EINVAL;
484
485         highest_rate = -EINVAL;
486
487         for (ptr = rate_table; ptr->mpu_speed; ptr++) {
488                 if (!(ptr->flags & cpu_mask))
489                         continue;
490                 if (ptr->xtal_speed != sys_ck.rate)
491                         continue;
492
493                 highest_rate = ptr->mpu_speed;
494
495                 /* Can check only after xtal frequency check */
496                 if (ptr->mpu_speed <= rate)
497                         break;
498         }
499         return highest_rate;
500 }
501
502 /* Sets basic clocks based on the specified rate */
503 static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
504 {
505         u32 cur_rate, done_rate, bypass = 0, tmp;
506         struct prcm_config *prcm;
507         unsigned long found_speed = 0;
508         unsigned long flags;
509
510         if (clk != &virt_prcm_set)
511                 return -EINVAL;
512
513         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
514                 if (!(prcm->flags & cpu_mask))
515                         continue;
516
517                 if (prcm->xtal_speed != sys_ck.rate)
518                         continue;
519
520                 if (prcm->mpu_speed <= rate) {
521                         found_speed = prcm->mpu_speed;
522                         break;
523                 }
524         }
525
526         if (!found_speed) {
527                 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
528                        rate / 1000000);
529                 return -EINVAL;
530         }
531
532         curr_prcm_set = prcm;
533         cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
534
535         if (prcm->dpll_speed == cur_rate / 2) {
536                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
537         } else if (prcm->dpll_speed == cur_rate * 2) {
538                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
539         } else if (prcm->dpll_speed != cur_rate) {
540                 local_irq_save(flags);
541
542                 if (prcm->dpll_speed == prcm->xtal_speed)
543                         bypass = 1;
544
545                 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
546                     CORE_CLK_SRC_DPLL_X2)
547                         done_rate = CORE_CLK_SRC_DPLL_X2;
548                 else
549                         done_rate = CORE_CLK_SRC_DPLL;
550
551                 /* MPU divider */
552                 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
553
554                 /* dsp + iva1 div(2420), iva2.1(2430) */
555                 cm_write_mod_reg(prcm->cm_clksel_dsp,
556                                  OMAP24XX_DSP_MOD, CM_CLKSEL);
557
558                 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
559
560                 /* Major subsystem dividers */
561                 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
562                 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
563                                  CM_CLKSEL1);
564
565                 if (cpu_is_omap2430())
566                         cm_write_mod_reg(prcm->cm_clksel_mdm,
567                                          OMAP2430_MDM_MOD, CM_CLKSEL);
568
569                 /* x2 to enter omap2xxx_sdrc_init_params() */
570                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
571
572                 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
573                                bypass);
574
575                 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
576                 omap2xxx_sdrc_reprogram(done_rate, 0);
577
578                 local_irq_restore(flags);
579         }
580
581         return 0;
582 }
583
584 #ifdef CONFIG_CPU_FREQ
585 /*
586  * Walk PRCM rate table and fillout cpufreq freq_table
587  */
588 static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
589
590 void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
591 {
592         struct prcm_config *prcm;
593         int i = 0;
594
595         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
596                 if (!(prcm->flags & cpu_mask))
597                         continue;
598                 if (prcm->xtal_speed != sys_ck.rate)
599                         continue;
600
601                 /* don't put bypass rates in table */
602                 if (prcm->dpll_speed == prcm->xtal_speed)
603                         continue;
604
605                 freq_table[i].index = i;
606                 freq_table[i].frequency = prcm->mpu_speed / 1000;
607                 i++;
608         }
609
610         if (i == 0) {
611                 printk(KERN_WARNING "%s: failed to initialize frequency "
612                        "table\n", __func__);
613                 return;
614         }
615
616         freq_table[i].index = i;
617         freq_table[i].frequency = CPUFREQ_TABLE_END;
618
619         *table = &freq_table[0];
620 }
621 #endif
622
623 static struct clk_functions omap2_clk_functions = {
624         .clk_enable             = omap2_clk_enable,
625         .clk_disable            = omap2_clk_disable,
626         .clk_round_rate         = omap2_clk_round_rate,
627         .clk_set_rate           = omap2_clk_set_rate,
628         .clk_set_parent         = omap2_clk_set_parent,
629         .clk_disable_unused     = omap2_clk_disable_unused,
630 #ifdef  CONFIG_CPU_FREQ
631         .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
632 #endif
633 };
634
635 static u32 omap2_get_apll_clkin(void)
636 {
637         u32 aplls, srate = 0;
638
639         aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
640         aplls &= OMAP24XX_APLLS_CLKIN_MASK;
641         aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
642
643         if (aplls == APLLS_CLKIN_19_2MHZ)
644                 srate = 19200000;
645         else if (aplls == APLLS_CLKIN_13MHZ)
646                 srate = 13000000;
647         else if (aplls == APLLS_CLKIN_12MHZ)
648                 srate = 12000000;
649
650         return srate;
651 }
652
653 static u32 omap2_get_sysclkdiv(void)
654 {
655         u32 div;
656
657         div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
658         div &= OMAP_SYSCLKDIV_MASK;
659         div >>= OMAP_SYSCLKDIV_SHIFT;
660
661         return div;
662 }
663
664 static unsigned long omap2_osc_clk_recalc(struct clk *clk)
665 {
666         return omap2_get_apll_clkin() * omap2_get_sysclkdiv();
667 }
668
669 static unsigned long omap2_sys_clk_recalc(struct clk *clk)
670 {
671         return clk->parent->rate / omap2_get_sysclkdiv();
672 }
673
674 /*
675  * Set clocks for bypass mode for reboot to work.
676  */
677 void omap2_clk_prepare_for_reboot(void)
678 {
679         u32 rate;
680
681         if (vclk == NULL || sclk == NULL)
682                 return;
683
684         rate = clk_get_rate(sclk);
685         clk_set_rate(vclk, rate);
686 }
687
688 /*
689  * Switch the MPU rate if specified on cmdline.
690  * We cannot do this early until cmdline is parsed.
691  */
692 static int __init omap2_clk_arch_init(void)
693 {
694         if (!mpurate)
695                 return -EINVAL;
696
697         if (clk_set_rate(&virt_prcm_set, mpurate))
698                 printk(KERN_ERR "Could not find matching MPU rate\n");
699
700         recalculate_root_clocks();
701
702         printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
703                "%ld.%01ld/%ld/%ld MHz\n",
704                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
705                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
706
707         return 0;
708 }
709 arch_initcall(omap2_clk_arch_init);
710
711 int __init omap2_clk_init(void)
712 {
713         struct prcm_config *prcm;
714         struct omap_clk *c;
715         u32 clkrate;
716
717         if (cpu_is_omap242x())
718                 cpu_mask = RATE_IN_242X;
719         else if (cpu_is_omap2430())
720                 cpu_mask = RATE_IN_243X;
721
722         clk_init(&omap2_clk_functions);
723
724         for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
725                 clk_init_one(c->lk.clk);
726
727         osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
728         propagate_rate(&osc_ck);
729         sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
730         propagate_rate(&sys_ck);
731
732         for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
733                 if (c->cpu & cpu_mask) {
734                         clkdev_add(&c->lk);
735                         clk_register(c->lk.clk);
736                 }
737
738         /* Check the MPU rate set by bootloader */
739         clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
740         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
741                 if (!(prcm->flags & cpu_mask))
742                         continue;
743                 if (prcm->xtal_speed != sys_ck.rate)
744                         continue;
745                 if (prcm->dpll_speed <= clkrate)
746                          break;
747         }
748         curr_prcm_set = prcm;
749
750         recalculate_root_clocks();
751
752         printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
753                "%ld.%01ld/%ld/%ld MHz\n",
754                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
755                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
756
757         /*
758          * Only enable those clocks we will need, let the drivers
759          * enable other clocks as necessary
760          */
761         clk_enable_init_clocks();
762
763         /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
764         vclk = clk_get(NULL, "virt_prcm_set");
765         sclk = clk_get(NULL, "sys_ck");
766
767         return 0;
768 }