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   1 /*
   2  * General Purpose functions for the global management of the
   3  * 8260 Communication Processor Module.
   4  * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
   5  * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
   6  *      2.3.99 Updates
   7  *
   8  * 2006 (c) MontaVista Software, Inc.
   9  * Vitaly Bordug <vbordug@ru.mvista.com>
  10  *      Merged to arch/powerpc from arch/ppc/syslib/cpm2_common.c
  11  *
  12  * This file is licensed under the terms of the GNU General Public License
  13  * version 2. This program is licensed "as is" without any warranty of any
  14  * kind, whether express or implied.
  15  */
  16
  17 /*
  18  *
  19  * In addition to the individual control of the communication
  20  * channels, there are a few functions that globally affect the
  21  * communication processor.
  22  *
  23  * Buffer descriptors must be allocated from the dual ported memory
  24  * space.  The allocator for that is here.  When the communication
  25  * process is reset, we reclaim the memory available.  There is
  26  * currently no deallocator for this memory.
  27  */
  28 #include <linux/errno.h>
  29 #include <linux/sched.h>
  30 #include <linux/kernel.h>
  31 #include <linux/param.h>
  32 #include <linux/string.h>
  33 #include <linux/mm.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/module.h>
  36 #include <linux/of.h>
  37
  38 #include <asm/io.h>
  39 #include <asm/irq.h>
  40 #include <asm/mpc8260.h>
  41 #include <asm/page.h>
  42 #include <asm/pgtable.h>
  43 #include <asm/cpm2.h>
  44 #include <asm/rheap.h>
  45 #include <asm/fs_pd.h>
  46
  47 #include <sysdev/fsl_soc.h>
  48
  49 cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */
  50
  51 /* We allocate this here because it is used almost exclusively for
  52  * the communication processor devices.
  53  */
  54 cpm2_map_t __iomem *cpm2_immr;
  55
  56 #define CPM_MAP_SIZE    (0x40000)       /* 256k - the PQ3 reserve this amount
  57                                            of space for CPM as it is larger
  58                                            than on PQ2 */
  59
  60 void __init cpm2_reset(void)
  61 {
  62 #ifdef CONFIG_PPC_85xx
  63         cpm2_immr = ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
  64 #else
  65         cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE);
  66 #endif
  67
  68         /* Reclaim the DP memory for our use.
  69          */
  70         cpm_muram_init();
  71
  72         /* Tell everyone where the comm processor resides.
  73          */
  74         cpmp = &cpm2_immr->im_cpm;
  75
  76 #ifndef CONFIG_PPC_EARLY_DEBUG_CPM
  77         /* Reset the CPM.
  78          */
  79         cpm_command(CPM_CR_RST, 0);
  80 #endif
  81 }
  82
  83 static DEFINE_SPINLOCK(cmd_lock);
  84
  85 #define MAX_CR_CMD_LOOPS        10000
  86
  87 int cpm_command(u32 command, u8 opcode)
  88 {
  89         int i, ret;
  90         unsigned long flags;
  91
  92         spin_lock_irqsave(&cmd_lock, flags);
  93
  94         ret = 0;
  95         out_be32(&cpmp->cp_cpcr, command | opcode | CPM_CR_FLG);
  96         for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
  97                 if ((in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
  98                         goto out;
  99
 100         printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
 101         ret = -EIO;
 102 out:
 103         spin_unlock_irqrestore(&cmd_lock, flags);
 104         return ret;
 105 }
 106 EXPORT_SYMBOL(cpm_command);
 107
 108 /* Set a baud rate generator.  This needs lots of work.  There are
 109  * eight BRGs, which can be connected to the CPM channels or output
 110  * as clocks.  The BRGs are in two different block of internal
 111  * memory mapped space.
 112  * The baud rate clock is the system clock divided by something.
 113  * It was set up long ago during the initial boot phase and is
 114  * is given to us.
 115  * Baud rate clocks are zero-based in the driver code (as that maps
 116  * to port numbers).  Documentation uses 1-based numbering.
 117  */
 118 void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src)
 119 {
 120         u32 __iomem *bp;
 121         u32 val;
 122
 123         /* This is good enough to get SMCs running.....
 124         */
 125         if (brg < 4) {
 126                 bp = cpm2_map_size(im_brgc1, 16);
 127         } else {
 128                 bp = cpm2_map_size(im_brgc5, 16);
 129                 brg -= 4;
 130         }
 131         bp += brg;
 132         /* Round the clock divider to the nearest integer. */
 133         val = (((clk * 2 / rate) - 1) & ~1) | CPM_BRG_EN | src;
 134         if (div16)
 135                 val |= CPM_BRG_DIV16;
 136
 137         out_be32(bp, val);
 138         cpm2_unmap(bp);
 139 }
 140 EXPORT_SYMBOL(__cpm2_setbrg);
 141
 142 int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
 143 {
 144         int ret = 0;
 145         int shift;
 146         int i, bits = 0;
 147         cpmux_t __iomem *im_cpmux;
 148         u32 __iomem *reg;
 149         u32 mask = 7;
 150
 151         u8 clk_map[][3] = {
 152                 {CPM_CLK_FCC1, CPM_BRG5, 0},
 153                 {CPM_CLK_FCC1, CPM_BRG6, 1},
 154                 {CPM_CLK_FCC1, CPM_BRG7, 2},
 155                 {CPM_CLK_FCC1, CPM_BRG8, 3},
 156                 {CPM_CLK_FCC1, CPM_CLK9, 4},
 157                 {CPM_CLK_FCC1, CPM_CLK10, 5},
 158                 {CPM_CLK_FCC1, CPM_CLK11, 6},
 159                 {CPM_CLK_FCC1, CPM_CLK12, 7},
 160                 {CPM_CLK_FCC2, CPM_BRG5, 0},
 161                 {CPM_CLK_FCC2, CPM_BRG6, 1},
 162                 {CPM_CLK_FCC2, CPM_BRG7, 2},
 163                 {CPM_CLK_FCC2, CPM_BRG8, 3},
 164                 {CPM_CLK_FCC2, CPM_CLK13, 4},
 165                 {CPM_CLK_FCC2, CPM_CLK14, 5},
 166                 {CPM_CLK_FCC2, CPM_CLK15, 6},
 167                 {CPM_CLK_FCC2, CPM_CLK16, 7},
 168                 {CPM_CLK_FCC3, CPM_BRG5, 0},
 169                 {CPM_CLK_FCC3, CPM_BRG6, 1},
 170                 {CPM_CLK_FCC3, CPM_BRG7, 2},
 171                 {CPM_CLK_FCC3, CPM_BRG8, 3},
 172                 {CPM_CLK_FCC3, CPM_CLK13, 4},
 173                 {CPM_CLK_FCC3, CPM_CLK14, 5},
 174                 {CPM_CLK_FCC3, CPM_CLK15, 6},
 175                 {CPM_CLK_FCC3, CPM_CLK16, 7},
 176                 {CPM_CLK_SCC1, CPM_BRG1, 0},
 177                 {CPM_CLK_SCC1, CPM_BRG2, 1},
 178                 {CPM_CLK_SCC1, CPM_BRG3, 2},
 179                 {CPM_CLK_SCC1, CPM_BRG4, 3},
 180                 {CPM_CLK_SCC1, CPM_CLK11, 4},
 181                 {CPM_CLK_SCC1, CPM_CLK12, 5},
 182                 {CPM_CLK_SCC1, CPM_CLK3, 6},
 183                 {CPM_CLK_SCC1, CPM_CLK4, 7},
 184                 {CPM_CLK_SCC2, CPM_BRG1, 0},
 185                 {CPM_CLK_SCC2, CPM_BRG2, 1},
 186                 {CPM_CLK_SCC2, CPM_BRG3, 2},
 187                 {CPM_CLK_SCC2, CPM_BRG4, 3},
 188                 {CPM_CLK_SCC2, CPM_CLK11, 4},
 189                 {CPM_CLK_SCC2, CPM_CLK12, 5},
 190                 {CPM_CLK_SCC2, CPM_CLK3, 6},
 191                 {CPM_CLK_SCC2, CPM_CLK4, 7},
 192                 {CPM_CLK_SCC3, CPM_BRG1, 0},
 193                 {CPM_CLK_SCC3, CPM_BRG2, 1},
 194                 {CPM_CLK_SCC3, CPM_BRG3, 2},
 195                 {CPM_CLK_SCC3, CPM_BRG4, 3},
 196                 {CPM_CLK_SCC3, CPM_CLK5, 4},
 197                 {CPM_CLK_SCC3, CPM_CLK6, 5},
 198                 {CPM_CLK_SCC3, CPM_CLK7, 6},
 199                 {CPM_CLK_SCC3, CPM_CLK8, 7},
 200                 {CPM_CLK_SCC4, CPM_BRG1, 0},
 201                 {CPM_CLK_SCC4, CPM_BRG2, 1},
 202                 {CPM_CLK_SCC4, CPM_BRG3, 2},
 203                 {CPM_CLK_SCC4, CPM_BRG4, 3},
 204                 {CPM_CLK_SCC4, CPM_CLK5, 4},
 205                 {CPM_CLK_SCC4, CPM_CLK6, 5},
 206                 {CPM_CLK_SCC4, CPM_CLK7, 6},
 207                 {CPM_CLK_SCC4, CPM_CLK8, 7},
 208         };
 209
 210         im_cpmux = cpm2_map(im_cpmux);
 211
 212         switch (target) {
 213         case CPM_CLK_SCC1:
 214                 reg = &im_cpmux->cmx_scr;
 215                 shift = 24;
 216                 break;
 217         case CPM_CLK_SCC2:
 218                 reg = &im_cpmux->cmx_scr;
 219                 shift = 16;
 220                 break;
 221         case CPM_CLK_SCC3:
 222                 reg = &im_cpmux->cmx_scr;
 223                 shift = 8;
 224                 break;
 225         case CPM_CLK_SCC4:
 226                 reg = &im_cpmux->cmx_scr;
 227                 shift = 0;
 228                 break;
 229         case CPM_CLK_FCC1:
 230                 reg = &im_cpmux->cmx_fcr;
 231                 shift = 24;
 232                 break;
 233         case CPM_CLK_FCC2:
 234                 reg = &im_cpmux->cmx_fcr;
 235                 shift = 16;
 236                 break;
 237         case CPM_CLK_FCC3:
 238                 reg = &im_cpmux->cmx_fcr;
 239                 shift = 8;
 240                 break;
 241         default:
 242                 printk(KERN_ERR "cpm2_clock_setup: invalid clock target\n");
 243                 return -EINVAL;
 244         }
 245
 246         if (mode == CPM_CLK_RX)
 247                 shift += 3;
 248
 249         for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
 250                 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
 251                         bits = clk_map[i][2];
 252                         break;
 253                 }
 254         }
 255         if (i == ARRAY_SIZE(clk_map))
 256             ret = -EINVAL;
 257
 258         bits <<= shift;
 259         mask <<= shift;
 260
 261         out_be32(reg, (in_be32(reg) & ~mask) | bits);
 262
 263         cpm2_unmap(im_cpmux);
 264         return ret;
 265 }
 266
 267 int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
 268 {
 269         int ret = 0;
 270         int shift;
 271         int i, bits = 0;
 272         cpmux_t __iomem *im_cpmux;
 273         u8 __iomem *reg;
 274         u8 mask = 3;
 275
 276         u8 clk_map[][3] = {
 277                 {CPM_CLK_SMC1, CPM_BRG1, 0},
 278                 {CPM_CLK_SMC1, CPM_BRG7, 1},
 279                 {CPM_CLK_SMC1, CPM_CLK7, 2},
 280                 {CPM_CLK_SMC1, CPM_CLK9, 3},
 281                 {CPM_CLK_SMC2, CPM_BRG2, 0},
 282                 {CPM_CLK_SMC2, CPM_BRG8, 1},
 283                 {CPM_CLK_SMC2, CPM_CLK4, 2},
 284                 {CPM_CLK_SMC2, CPM_CLK15, 3},
 285         };
 286
 287         im_cpmux = cpm2_map(im_cpmux);
 288
 289         switch (target) {
 290         case CPM_CLK_SMC1:
 291                 reg = &im_cpmux->cmx_smr;
 292                 mask = 3;
 293                 shift = 4;
 294                 break;
 295         case CPM_CLK_SMC2:
 296                 reg = &im_cpmux->cmx_smr;
 297                 mask = 3;
 298                 shift = 0;
 299                 break;
 300         default:
 301                 printk(KERN_ERR "cpm2_smc_clock_setup: invalid clock target\n");
 302                 return -EINVAL;
 303         }
 304
 305         for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
 306                 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
 307                         bits = clk_map[i][2];
 308                         break;
 309                 }
 310         }
 311         if (i == ARRAY_SIZE(clk_map))
 312             ret = -EINVAL;
 313
 314         bits <<= shift;
 315         mask <<= shift;
 316
 317         out_8(reg, (in_8(reg) & ~mask) | bits);
 318
 319         cpm2_unmap(im_cpmux);
 320         return ret;
 321 }
 322
 323 struct cpm2_ioports {
 324         u32 dir, par, sor, odr, dat;
 325         u32 res[3];
 326 };
 327
 328 void cpm2_set_pin(int port, int pin, int flags)
 329 {
 330         struct cpm2_ioports __iomem *iop =
 331                 (struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport;
 332
 333         pin = 1 << (31 - pin);
 334
 335         if (flags & CPM_PIN_OUTPUT)
 336                 setbits32(&iop[port].dir, pin);
 337         else
 338                 clrbits32(&iop[port].dir, pin);
 339
 340         if (!(flags & CPM_PIN_GPIO))
 341                 setbits32(&iop[port].par, pin);
 342         else
 343                 clrbits32(&iop[port].par, pin);
 344
 345         if (flags & CPM_PIN_SECONDARY)
 346                 setbits32(&iop[port].sor, pin);
 347         else
 348                 clrbits32(&iop[port].sor, pin);
 349
 350         if (flags & CPM_PIN_OPENDRAIN)
 351                 setbits32(&iop[port].odr, pin);
 352         else
 353                 clrbits32(&iop[port].odr, pin);
 354 }
 355
 356 static int cpm_init_par_io(void)
 357 {
 358         struct device_node *np;
 359
 360         for_each_compatible_node(np, NULL, "fsl,cpm2-pario-bank")
 361                 cpm2_gpiochip_add32(np);
 362         return 0;
 363 }
 364 arch_initcall(cpm_init_par_io);
 365