Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394...
[linux-2.6] / drivers / i2c / busses / i2c-davinci.c
1 /*
2  * TI DAVINCI I2C adapter driver.
3  *
4  * Copyright (C) 2006 Texas Instruments.
5  * Copyright (C) 2007 MontaVista Software Inc.
6  *
7  * Updated by Vinod & Sudhakar Feb 2005
8  *
9  * ----------------------------------------------------------------------------
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License, or
14  * (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24  * ----------------------------------------------------------------------------
25  *
26  */
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/delay.h>
30 #include <linux/i2c.h>
31 #include <linux/clk.h>
32 #include <linux/errno.h>
33 #include <linux/sched.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/platform_device.h>
37 #include <linux/io.h>
38
39 #include <asm/hardware.h>
40 #include <asm/mach-types.h>
41
42 #include <asm/arch/i2c.h>
43
44 /* ----- global defines ----------------------------------------------- */
45
46 #define DAVINCI_I2C_TIMEOUT     (1*HZ)
47 #define I2C_DAVINCI_INTR_ALL    (DAVINCI_I2C_IMR_AAS | \
48                                  DAVINCI_I2C_IMR_SCD | \
49                                  DAVINCI_I2C_IMR_ARDY | \
50                                  DAVINCI_I2C_IMR_NACK | \
51                                  DAVINCI_I2C_IMR_AL)
52
53 #define DAVINCI_I2C_OAR_REG     0x00
54 #define DAVINCI_I2C_IMR_REG     0x04
55 #define DAVINCI_I2C_STR_REG     0x08
56 #define DAVINCI_I2C_CLKL_REG    0x0c
57 #define DAVINCI_I2C_CLKH_REG    0x10
58 #define DAVINCI_I2C_CNT_REG     0x14
59 #define DAVINCI_I2C_DRR_REG     0x18
60 #define DAVINCI_I2C_SAR_REG     0x1c
61 #define DAVINCI_I2C_DXR_REG     0x20
62 #define DAVINCI_I2C_MDR_REG     0x24
63 #define DAVINCI_I2C_IVR_REG     0x28
64 #define DAVINCI_I2C_EMDR_REG    0x2c
65 #define DAVINCI_I2C_PSC_REG     0x30
66
67 #define DAVINCI_I2C_IVR_AAS     0x07
68 #define DAVINCI_I2C_IVR_SCD     0x06
69 #define DAVINCI_I2C_IVR_XRDY    0x05
70 #define DAVINCI_I2C_IVR_RDR     0x04
71 #define DAVINCI_I2C_IVR_ARDY    0x03
72 #define DAVINCI_I2C_IVR_NACK    0x02
73 #define DAVINCI_I2C_IVR_AL      0x01
74
75 #define DAVINCI_I2C_STR_BB      (1 << 12)
76 #define DAVINCI_I2C_STR_RSFULL  (1 << 11)
77 #define DAVINCI_I2C_STR_SCD     (1 << 5)
78 #define DAVINCI_I2C_STR_ARDY    (1 << 2)
79 #define DAVINCI_I2C_STR_NACK    (1 << 1)
80 #define DAVINCI_I2C_STR_AL      (1 << 0)
81
82 #define DAVINCI_I2C_MDR_NACK    (1 << 15)
83 #define DAVINCI_I2C_MDR_STT     (1 << 13)
84 #define DAVINCI_I2C_MDR_STP     (1 << 11)
85 #define DAVINCI_I2C_MDR_MST     (1 << 10)
86 #define DAVINCI_I2C_MDR_TRX     (1 << 9)
87 #define DAVINCI_I2C_MDR_XA      (1 << 8)
88 #define DAVINCI_I2C_MDR_RM      (1 << 7)
89 #define DAVINCI_I2C_MDR_IRS     (1 << 5)
90
91 #define DAVINCI_I2C_IMR_AAS     (1 << 6)
92 #define DAVINCI_I2C_IMR_SCD     (1 << 5)
93 #define DAVINCI_I2C_IMR_XRDY    (1 << 4)
94 #define DAVINCI_I2C_IMR_RRDY    (1 << 3)
95 #define DAVINCI_I2C_IMR_ARDY    (1 << 2)
96 #define DAVINCI_I2C_IMR_NACK    (1 << 1)
97 #define DAVINCI_I2C_IMR_AL      (1 << 0)
98
99 #define MOD_REG_BIT(val, mask, set) do { \
100         if (set) { \
101                 val |= mask; \
102         } else { \
103                 val &= ~mask; \
104         } \
105 } while (0)
106
107 struct davinci_i2c_dev {
108         struct device           *dev;
109         void __iomem            *base;
110         struct completion       cmd_complete;
111         struct clk              *clk;
112         int                     cmd_err;
113         u8                      *buf;
114         size_t                  buf_len;
115         int                     irq;
116         u8                      terminate;
117         struct i2c_adapter      adapter;
118 };
119
120 /* default platform data to use if not supplied in the platform_device */
121 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
122         .bus_freq       = 100,
123         .bus_delay      = 0,
124 };
125
126 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
127                                          int reg, u16 val)
128 {
129         __raw_writew(val, i2c_dev->base + reg);
130 }
131
132 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
133 {
134         return __raw_readw(i2c_dev->base + reg);
135 }
136
137 /*
138  * This functions configures I2C and brings I2C out of reset.
139  * This function is called during I2C init function. This function
140  * also gets called if I2C encounters any errors.
141  */
142 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
143 {
144         struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
145         u16 psc;
146         u32 clk;
147         u32 d;
148         u32 clkh;
149         u32 clkl;
150         u32 input_clock = clk_get_rate(dev->clk);
151         u16 w;
152
153         if (!pdata)
154                 pdata = &davinci_i2c_platform_data_default;
155
156         /* put I2C into reset */
157         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
158         MOD_REG_BIT(w, DAVINCI_I2C_MDR_IRS, 0);
159         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
160
161         /* NOTE: I2C Clock divider programming info
162          * As per I2C specs the following formulas provide prescaler
163          * and low/high divider values
164          * input clk --> PSC Div -----------> ICCL/H Div --> output clock
165          *                       module clk
166          *
167          * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
168          *
169          * Thus,
170          * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
171          *
172          * where if PSC == 0, d = 7,
173          *       if PSC == 1, d = 6
174          *       if PSC > 1 , d = 5
175          */
176
177         /* get minimum of 7 MHz clock, but max of 12 MHz */
178         psc = (input_clock / 7000000) - 1;
179         if ((input_clock / (psc + 1)) > 12000000)
180                 psc++;  /* better to run under spec than over */
181         d = (psc >= 2) ? 5 : 7 - psc;
182
183         clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1);
184         clkh = clk >> 1;
185         clkl = clk - clkh;
186
187         davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
188         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
189         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
190
191         dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
192         dev_dbg(dev->dev, "PSC  = %d\n",
193                 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
194         dev_dbg(dev->dev, "CLKL = %d\n",
195                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
196         dev_dbg(dev->dev, "CLKH = %d\n",
197                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
198         dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
199                 pdata->bus_freq, pdata->bus_delay);
200
201         /* Take the I2C module out of reset: */
202         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
203         MOD_REG_BIT(w, DAVINCI_I2C_MDR_IRS, 1);
204         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
205
206         /* Enable interrupts */
207         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
208
209         return 0;
210 }
211
212 /*
213  * Waiting for bus not busy
214  */
215 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
216                                          char allow_sleep)
217 {
218         unsigned long timeout;
219
220         timeout = jiffies + DAVINCI_I2C_TIMEOUT;
221         while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
222                & DAVINCI_I2C_STR_BB) {
223                 if (time_after(jiffies, timeout)) {
224                         dev_warn(dev->dev,
225                                  "timeout waiting for bus ready\n");
226                         return -ETIMEDOUT;
227                 }
228                 if (allow_sleep)
229                         schedule_timeout(1);
230         }
231
232         return 0;
233 }
234
235 /*
236  * Low level master read/write transaction. This function is called
237  * from i2c_davinci_xfer.
238  */
239 static int
240 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
241 {
242         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
243         struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
244         u32 flag;
245         u16 w;
246         int r;
247
248         if (msg->len == 0)
249                 return -EINVAL;
250
251         if (!pdata)
252                 pdata = &davinci_i2c_platform_data_default;
253         /* Introduce a delay, required for some boards (e.g Davinci EVM) */
254         if (pdata->bus_delay)
255                 udelay(pdata->bus_delay);
256
257         /* set the slave address */
258         davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
259
260         dev->buf = msg->buf;
261         dev->buf_len = msg->len;
262
263         davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
264
265         INIT_COMPLETION(dev->cmd_complete);
266         dev->cmd_err = 0;
267
268         /* Take I2C out of reset, configure it as master and set the
269          * start bit */
270         flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST | DAVINCI_I2C_MDR_STT;
271
272         /* if the slave address is ten bit address, enable XA bit */
273         if (msg->flags & I2C_M_TEN)
274                 flag |= DAVINCI_I2C_MDR_XA;
275         if (!(msg->flags & I2C_M_RD))
276                 flag |= DAVINCI_I2C_MDR_TRX;
277         if (stop)
278                 flag |= DAVINCI_I2C_MDR_STP;
279
280         /* Enable receive or transmit interrupts */
281         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
282         if (msg->flags & I2C_M_RD)
283                 MOD_REG_BIT(w, DAVINCI_I2C_IMR_RRDY, 1);
284         else
285                 MOD_REG_BIT(w, DAVINCI_I2C_IMR_XRDY, 1);
286         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
287
288         dev->terminate = 0;
289         /* write the data into mode register */
290         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
291
292         r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
293                                                       DAVINCI_I2C_TIMEOUT);
294         if (r == 0) {
295                 dev_err(dev->dev, "controller timed out\n");
296                 i2c_davinci_init(dev);
297                 dev->buf_len = 0;
298                 return -ETIMEDOUT;
299         }
300         if (dev->buf_len) {
301                 /* This should be 0 if all bytes were transferred
302                  * or dev->cmd_err denotes an error.
303                  * A signal may have aborted the transfer.
304                  */
305                 if (r >= 0) {
306                         dev_err(dev->dev, "abnormal termination buf_len=%i\n",
307                                 dev->buf_len);
308                         r = -EREMOTEIO;
309                 }
310                 dev->terminate = 1;
311                 wmb();
312                 dev->buf_len = 0;
313         }
314         if (r < 0)
315                 return r;
316
317         /* no error */
318         if (likely(!dev->cmd_err))
319                 return msg->len;
320
321         /* We have an error */
322         if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
323                 i2c_davinci_init(dev);
324                 return -EIO;
325         }
326
327         if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
328                 if (msg->flags & I2C_M_IGNORE_NAK)
329                         return msg->len;
330                 if (stop) {
331                         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
332                         MOD_REG_BIT(w, DAVINCI_I2C_MDR_STP, 1);
333                         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
334                 }
335                 return -EREMOTEIO;
336         }
337         return -EIO;
338 }
339
340 /*
341  * Prepare controller for a transaction and call i2c_davinci_xfer_msg
342  */
343 static int
344 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
345 {
346         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
347         int i;
348         int ret;
349
350         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
351
352         ret = i2c_davinci_wait_bus_not_busy(dev, 1);
353         if (ret < 0) {
354                 dev_warn(dev->dev, "timeout waiting for bus ready\n");
355                 return ret;
356         }
357
358         for (i = 0; i < num; i++) {
359                 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
360                 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
361                         ret);
362                 if (ret < 0)
363                         return ret;
364         }
365         return num;
366 }
367
368 static u32 i2c_davinci_func(struct i2c_adapter *adap)
369 {
370         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
371 }
372
373 static void terminate_read(struct davinci_i2c_dev *dev)
374 {
375         u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
376         w |= DAVINCI_I2C_MDR_NACK;
377         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
378
379         /* Throw away data */
380         davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
381         if (!dev->terminate)
382                 dev_err(dev->dev, "RDR IRQ while no data requested\n");
383 }
384 static void terminate_write(struct davinci_i2c_dev *dev)
385 {
386         u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
387         w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
388         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
389
390         if (!dev->terminate)
391                 dev_err(dev->dev, "TDR IRQ while no data to send\n");
392 }
393
394 /*
395  * Interrupt service routine. This gets called whenever an I2C interrupt
396  * occurs.
397  */
398 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
399 {
400         struct davinci_i2c_dev *dev = dev_id;
401         u32 stat;
402         int count = 0;
403         u16 w;
404
405         while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
406                 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
407                 if (count++ == 100) {
408                         dev_warn(dev->dev, "Too much work in one IRQ\n");
409                         break;
410                 }
411
412                 switch (stat) {
413                 case DAVINCI_I2C_IVR_AL:
414                         /* Arbitration lost, must retry */
415                         dev->cmd_err |= DAVINCI_I2C_STR_AL;
416                         dev->buf_len = 0;
417                         complete(&dev->cmd_complete);
418                         break;
419
420                 case DAVINCI_I2C_IVR_NACK:
421                         dev->cmd_err |= DAVINCI_I2C_STR_NACK;
422                         dev->buf_len = 0;
423                         complete(&dev->cmd_complete);
424                         break;
425
426                 case DAVINCI_I2C_IVR_ARDY:
427                         davinci_i2c_write_reg(dev,
428                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
429                         complete(&dev->cmd_complete);
430                         break;
431
432                 case DAVINCI_I2C_IVR_RDR:
433                         if (dev->buf_len) {
434                                 *dev->buf++ =
435                                     davinci_i2c_read_reg(dev,
436                                                          DAVINCI_I2C_DRR_REG);
437                                 dev->buf_len--;
438                                 if (dev->buf_len)
439                                         continue;
440
441                                 davinci_i2c_write_reg(dev,
442                                         DAVINCI_I2C_STR_REG,
443                                         DAVINCI_I2C_IMR_RRDY);
444                         } else {
445                                 /* signal can terminate transfer */
446                                 terminate_read(dev);
447                         }
448                         break;
449
450                 case DAVINCI_I2C_IVR_XRDY:
451                         if (dev->buf_len) {
452                                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
453                                                       *dev->buf++);
454                                 dev->buf_len--;
455                                 if (dev->buf_len)
456                                         continue;
457
458                                 w = davinci_i2c_read_reg(dev,
459                                                          DAVINCI_I2C_IMR_REG);
460                                 MOD_REG_BIT(w, DAVINCI_I2C_IMR_XRDY, 0);
461                                 davinci_i2c_write_reg(dev,
462                                                       DAVINCI_I2C_IMR_REG,
463                                                       w);
464                         } else {
465                                 /* signal can terminate transfer */
466                                 terminate_write(dev);
467                         }
468                         break;
469
470                 case DAVINCI_I2C_IVR_SCD:
471                         davinci_i2c_write_reg(dev,
472                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
473                         complete(&dev->cmd_complete);
474                         break;
475
476                 case DAVINCI_I2C_IVR_AAS:
477                         dev_warn(dev->dev, "Address as slave interrupt\n");
478                 }/* switch */
479         }/* while */
480
481         return count ? IRQ_HANDLED : IRQ_NONE;
482 }
483
484 static struct i2c_algorithm i2c_davinci_algo = {
485         .master_xfer    = i2c_davinci_xfer,
486         .functionality  = i2c_davinci_func,
487 };
488
489 static int davinci_i2c_probe(struct platform_device *pdev)
490 {
491         struct davinci_i2c_dev *dev;
492         struct i2c_adapter *adap;
493         struct resource *mem, *irq, *ioarea;
494         int r;
495
496         /* NOTE: driver uses the static register mapping */
497         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
498         if (!mem) {
499                 dev_err(&pdev->dev, "no mem resource?\n");
500                 return -ENODEV;
501         }
502
503         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
504         if (!irq) {
505                 dev_err(&pdev->dev, "no irq resource?\n");
506                 return -ENODEV;
507         }
508
509         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
510                                     pdev->name);
511         if (!ioarea) {
512                 dev_err(&pdev->dev, "I2C region already claimed\n");
513                 return -EBUSY;
514         }
515
516         dev = kzalloc(sizeof(struct davinci_i2c_dev), GFP_KERNEL);
517         if (!dev) {
518                 r = -ENOMEM;
519                 goto err_release_region;
520         }
521
522         init_completion(&dev->cmd_complete);
523         dev->dev = get_device(&pdev->dev);
524         dev->irq = irq->start;
525         platform_set_drvdata(pdev, dev);
526
527         dev->clk = clk_get(&pdev->dev, "I2CCLK");
528         if (IS_ERR(dev->clk)) {
529                 r = -ENODEV;
530                 goto err_free_mem;
531         }
532         clk_enable(dev->clk);
533
534         dev->base = (void __iomem *)IO_ADDRESS(mem->start);
535         i2c_davinci_init(dev);
536
537         r = request_irq(dev->irq, i2c_davinci_isr, 0, pdev->name, dev);
538         if (r) {
539                 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
540                 goto err_unuse_clocks;
541         }
542
543         adap = &dev->adapter;
544         i2c_set_adapdata(adap, dev);
545         adap->owner = THIS_MODULE;
546         adap->class = I2C_CLASS_HWMON;
547         strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
548         adap->algo = &i2c_davinci_algo;
549         adap->dev.parent = &pdev->dev;
550
551         /* FIXME */
552         adap->timeout = 1;
553
554         adap->nr = pdev->id;
555         r = i2c_add_numbered_adapter(adap);
556         if (r) {
557                 dev_err(&pdev->dev, "failure adding adapter\n");
558                 goto err_free_irq;
559         }
560
561         return 0;
562
563 err_free_irq:
564         free_irq(dev->irq, dev);
565 err_unuse_clocks:
566         clk_disable(dev->clk);
567         clk_put(dev->clk);
568         dev->clk = NULL;
569 err_free_mem:
570         platform_set_drvdata(pdev, NULL);
571         put_device(&pdev->dev);
572         kfree(dev);
573 err_release_region:
574         release_mem_region(mem->start, (mem->end - mem->start) + 1);
575
576         return r;
577 }
578
579 static int davinci_i2c_remove(struct platform_device *pdev)
580 {
581         struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
582         struct resource *mem;
583
584         platform_set_drvdata(pdev, NULL);
585         i2c_del_adapter(&dev->adapter);
586         put_device(&pdev->dev);
587
588         clk_disable(dev->clk);
589         clk_put(dev->clk);
590         dev->clk = NULL;
591
592         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
593         free_irq(IRQ_I2C, dev);
594         kfree(dev);
595
596         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
597         release_mem_region(mem->start, (mem->end - mem->start) + 1);
598         return 0;
599 }
600
601 /* work with hotplug and coldplug */
602 MODULE_ALIAS("platform:i2c_davinci");
603
604 static struct platform_driver davinci_i2c_driver = {
605         .probe          = davinci_i2c_probe,
606         .remove         = davinci_i2c_remove,
607         .driver         = {
608                 .name   = "i2c_davinci",
609                 .owner  = THIS_MODULE,
610         },
611 };
612
613 /* I2C may be needed to bring up other drivers */
614 static int __init davinci_i2c_init_driver(void)
615 {
616         return platform_driver_register(&davinci_i2c_driver);
617 }
618 subsys_initcall(davinci_i2c_init_driver);
619
620 static void __exit davinci_i2c_exit_driver(void)
621 {
622         platform_driver_unregister(&davinci_i2c_driver);
623 }
624 module_exit(davinci_i2c_exit_driver);
625
626 MODULE_AUTHOR("Texas Instruments India");
627 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
628 MODULE_LICENSE("GPL");