2 * Intel AGPGART routines.
5 #include <linux/module.h>
7 #include <linux/init.h>
8 #include <linux/pagemap.h>
9 #include <linux/agp_backend.h>
12 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
13 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
14 #define PCI_DEVICE_ID_INTEL_82965G_1_HB 0x2980
15 #define PCI_DEVICE_ID_INTEL_82965G_1_IG 0x2982
16 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
17 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
18 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
19 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
21 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
22 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
23 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
24 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB)
27 /* Intel 815 register */
28 #define INTEL_815_APCONT 0x51
29 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
31 /* Intel i820 registers */
32 #define INTEL_I820_RDCR 0x51
33 #define INTEL_I820_ERRSTS 0xc8
35 /* Intel i840 registers */
36 #define INTEL_I840_MCHCFG 0x50
37 #define INTEL_I840_ERRSTS 0xc8
39 /* Intel i850 registers */
40 #define INTEL_I850_MCHCFG 0x50
41 #define INTEL_I850_ERRSTS 0xc8
43 /* intel 915G registers */
44 #define I915_GMADDR 0x18
45 #define I915_MMADDR 0x10
46 #define I915_PTEADDR 0x1C
47 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
48 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
50 /* Intel 965G registers */
51 #define I965_MSAC 0x62
53 /* Intel 7505 registers */
54 #define INTEL_I7505_APSIZE 0x74
55 #define INTEL_I7505_NCAPID 0x60
56 #define INTEL_I7505_NISTAT 0x6c
57 #define INTEL_I7505_ATTBASE 0x78
58 #define INTEL_I7505_ERRSTS 0x42
59 #define INTEL_I7505_AGPCTRL 0x70
60 #define INTEL_I7505_MCHCFG 0x50
62 static struct aper_size_info_fixed intel_i810_sizes[] =
65 /* The 32M mode still requires a 64k gatt */
69 #define AGP_DCACHE_MEMORY 1
70 #define AGP_PHYS_MEMORY 2
72 static struct gatt_mask intel_i810_masks[] =
74 {.mask = I810_PTE_VALID, .type = 0},
75 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
76 {.mask = I810_PTE_VALID, .type = 0}
79 static struct _intel_i810_private {
80 struct pci_dev *i810_dev; /* device one */
81 volatile u8 __iomem *registers;
82 int num_dcache_entries;
85 static int intel_i810_fetch_size(void)
88 struct aper_size_info_fixed *values;
90 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
91 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
93 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
94 printk(KERN_WARNING PFX "i810 is disabled\n");
97 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
98 agp_bridge->previous_size =
99 agp_bridge->current_size = (void *) (values + 1);
100 agp_bridge->aperture_size_idx = 1;
101 return values[1].size;
103 agp_bridge->previous_size =
104 agp_bridge->current_size = (void *) (values);
105 agp_bridge->aperture_size_idx = 0;
106 return values[0].size;
112 static int intel_i810_configure(void)
114 struct aper_size_info_fixed *current_size;
118 current_size = A_SIZE_FIX(agp_bridge->current_size);
120 pci_read_config_dword(intel_i810_private.i810_dev, I810_MMADDR, &temp);
123 intel_i810_private.registers = ioremap(temp, 128 * 4096);
124 if (!intel_i810_private.registers) {
125 printk(KERN_ERR PFX "Unable to remap memory.\n");
129 if ((readl(intel_i810_private.registers+I810_DRAM_CTL)
130 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
131 /* This will need to be dynamically assigned */
132 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
133 intel_i810_private.num_dcache_entries = 1024;
135 pci_read_config_dword(intel_i810_private.i810_dev, I810_GMADDR, &temp);
136 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
137 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_i810_private.registers+I810_PGETBL_CTL);
138 readl(intel_i810_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
140 if (agp_bridge->driver->needs_scratch_page) {
141 for (i = 0; i < current_size->num_entries; i++) {
142 writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4));
143 readl(intel_i810_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */
146 global_cache_flush();
150 static void intel_i810_cleanup(void)
152 writel(0, intel_i810_private.registers+I810_PGETBL_CTL);
153 readl(intel_i810_private.registers); /* PCI Posting. */
154 iounmap(intel_i810_private.registers);
157 static void intel_i810_tlbflush(struct agp_memory *mem)
162 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
167 /* Exists to support ARGB cursors */
168 static void *i8xx_alloc_pages(void)
172 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
176 if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) {
184 atomic_inc(&agp_bridge->current_memory_agp);
185 return page_address(page);
188 static void i8xx_destroy_pages(void *addr)
195 page = virt_to_page(addr);
196 change_page_attr(page, 4, PAGE_KERNEL);
200 free_pages((unsigned long)addr, 2);
201 atomic_dec(&agp_bridge->current_memory_agp);
204 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
207 int i, j, num_entries;
210 temp = agp_bridge->current_size;
211 num_entries = A_SIZE_FIX(temp)->num_entries;
213 if ((pg_start + mem->page_count) > num_entries)
216 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
217 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
221 if (type != 0 || mem->type != 0) {
222 if ((type == AGP_DCACHE_MEMORY) && (mem->type == AGP_DCACHE_MEMORY)) {
224 global_cache_flush();
225 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
226 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, intel_i810_private.registers+I810_PTE_BASE+(i*4));
227 readl(intel_i810_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
229 global_cache_flush();
230 agp_bridge->driver->tlb_flush(mem);
233 if ((type == AGP_PHYS_MEMORY) && (mem->type == AGP_PHYS_MEMORY))
239 global_cache_flush();
240 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
241 writel(agp_bridge->driver->mask_memory(agp_bridge,
242 mem->memory[i], mem->type),
243 intel_i810_private.registers+I810_PTE_BASE+(j*4));
244 readl(intel_i810_private.registers+I810_PTE_BASE+(j*4)); /* PCI Posting. */
246 global_cache_flush();
248 agp_bridge->driver->tlb_flush(mem);
252 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
257 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
258 writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4));
259 readl(intel_i810_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
262 global_cache_flush();
263 agp_bridge->driver->tlb_flush(mem);
268 * The i810/i830 requires a physical address to program its mouse
269 * pointer into hardware.
270 * However the Xserver still writes to it through the agp aperture.
272 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
274 struct agp_memory *new;
277 if (pg_count != 1 && pg_count != 4)
281 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
285 /* kludge to get 4 physical pages for ARGB cursor */
286 addr = i8xx_alloc_pages();
295 new = agp_create_memory(pg_count);
299 new->memory[0] = virt_to_gart(addr);
301 /* kludge to get 4 physical pages for ARGB cursor */
302 new->memory[1] = new->memory[0] + PAGE_SIZE;
303 new->memory[2] = new->memory[1] + PAGE_SIZE;
304 new->memory[3] = new->memory[2] + PAGE_SIZE;
306 new->page_count = pg_count;
307 new->num_scratch_pages = pg_count;
308 new->type = AGP_PHYS_MEMORY;
309 new->physical = new->memory[0];
313 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
315 struct agp_memory *new;
317 if (type == AGP_DCACHE_MEMORY) {
318 if (pg_count != intel_i810_private.num_dcache_entries)
321 new = agp_create_memory(1);
325 new->type = AGP_DCACHE_MEMORY;
326 new->page_count = pg_count;
327 new->num_scratch_pages = 0;
331 if (type == AGP_PHYS_MEMORY)
332 return alloc_agpphysmem_i8xx(pg_count, type);
337 static void intel_i810_free_by_type(struct agp_memory *curr)
339 agp_free_key(curr->key);
340 if (curr->type == AGP_PHYS_MEMORY) {
341 if (curr->page_count == 4)
342 i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
344 agp_bridge->driver->agp_destroy_page(
345 gart_to_virt(curr->memory[0]));
353 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
354 unsigned long addr, int type)
356 /* Type checking must be done elsewhere */
357 return addr | bridge->driver->masks[type].mask;
360 static struct aper_size_info_fixed intel_i830_sizes[] =
363 /* The 64M mode still requires a 128k gatt */
369 static struct _intel_i830_private {
370 struct pci_dev *i830_dev; /* device one */
371 volatile u8 __iomem *registers;
372 volatile u32 __iomem *gtt; /* I915G */
374 } intel_i830_private;
376 static void intel_i830_init_gtt_entries(void)
382 static const int ddt[4] = { 0, 16, 32, 64 };
385 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
387 /* We obtain the size of the GTT, which is also stored (for some
388 * reason) at the top of stolen memory. Then we add 4KB to that
389 * for the video BIOS popup, which is also stored in there. */
390 size = agp_bridge->driver->fetch_size() + 4;
392 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
393 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
394 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
395 case I830_GMCH_GMS_STOLEN_512:
396 gtt_entries = KB(512) - KB(size);
398 case I830_GMCH_GMS_STOLEN_1024:
399 gtt_entries = MB(1) - KB(size);
401 case I830_GMCH_GMS_STOLEN_8192:
402 gtt_entries = MB(8) - KB(size);
404 case I830_GMCH_GMS_LOCAL:
405 rdct = readb(intel_i830_private.registers+I830_RDRAM_CHANNEL_TYPE);
406 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
407 MB(ddt[I830_RDRAM_DDT(rdct)]);
415 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
416 case I855_GMCH_GMS_STOLEN_1M:
417 gtt_entries = MB(1) - KB(size);
419 case I855_GMCH_GMS_STOLEN_4M:
420 gtt_entries = MB(4) - KB(size);
422 case I855_GMCH_GMS_STOLEN_8M:
423 gtt_entries = MB(8) - KB(size);
425 case I855_GMCH_GMS_STOLEN_16M:
426 gtt_entries = MB(16) - KB(size);
428 case I855_GMCH_GMS_STOLEN_32M:
429 gtt_entries = MB(32) - KB(size);
431 case I915_GMCH_GMS_STOLEN_48M:
432 /* Check it's really I915G */
433 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
434 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
435 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
436 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || IS_I965 )
437 gtt_entries = MB(48) - KB(size);
441 case I915_GMCH_GMS_STOLEN_64M:
442 /* Check it's really I915G */
443 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
444 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
445 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
446 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || IS_I965)
447 gtt_entries = MB(64) - KB(size);
456 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
457 gtt_entries / KB(1), local ? "local" : "stolen");
460 "No pre-allocated video memory detected.\n");
461 gtt_entries /= KB(4);
463 intel_i830_private.gtt_entries = gtt_entries;
466 /* The intel i830 automatically initializes the agp aperture during POST.
467 * Use the memory already set aside for in the GTT.
469 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
472 struct aper_size_info_fixed *size;
476 size = agp_bridge->current_size;
477 page_order = size->page_order;
478 num_entries = size->num_entries;
479 agp_bridge->gatt_table_real = NULL;
481 pci_read_config_dword(intel_i830_private.i830_dev,I810_MMADDR,&temp);
484 intel_i830_private.registers = ioremap(temp,128 * 4096);
485 if (!intel_i830_private.registers)
488 temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000;
489 global_cache_flush(); /* FIXME: ?? */
491 /* we have to call this as early as possible after the MMIO base address is known */
492 intel_i830_init_gtt_entries();
494 agp_bridge->gatt_table = NULL;
496 agp_bridge->gatt_bus_addr = temp;
501 /* Return the gatt table to a sane state. Use the top of stolen
502 * memory for the GTT.
504 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
509 static int intel_i830_fetch_size(void)
512 struct aper_size_info_fixed *values;
514 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
516 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
517 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
518 /* 855GM/852GM/865G has 128MB aperture size */
519 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
520 agp_bridge->aperture_size_idx = 0;
521 return values[0].size;
524 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
526 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
527 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
528 agp_bridge->aperture_size_idx = 0;
529 return values[0].size;
531 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
532 agp_bridge->aperture_size_idx = 1;
533 return values[1].size;
539 static int intel_i830_configure(void)
541 struct aper_size_info_fixed *current_size;
546 current_size = A_SIZE_FIX(agp_bridge->current_size);
548 pci_read_config_dword(intel_i830_private.i830_dev,I810_GMADDR,&temp);
549 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
551 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
552 gmch_ctrl |= I830_GMCH_ENABLED;
553 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
555 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL);
556 readl(intel_i830_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
558 if (agp_bridge->driver->needs_scratch_page) {
559 for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) {
560 writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4));
561 readl(intel_i830_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
565 global_cache_flush();
569 static void intel_i830_cleanup(void)
571 iounmap(intel_i830_private.registers);
574 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
579 temp = agp_bridge->current_size;
580 num_entries = A_SIZE_FIX(temp)->num_entries;
582 if (pg_start < intel_i830_private.gtt_entries) {
583 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n",
584 pg_start,intel_i830_private.gtt_entries);
586 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
590 if ((pg_start + mem->page_count) > num_entries)
593 /* The i830 can't check the GTT for entries since its read only,
594 * depend on the caller to make the correct offset decisions.
597 if ((type != 0 && type != AGP_PHYS_MEMORY) ||
598 (mem->type != 0 && mem->type != AGP_PHYS_MEMORY))
601 global_cache_flush(); /* FIXME: Necessary ?*/
603 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
604 writel(agp_bridge->driver->mask_memory(agp_bridge,
605 mem->memory[i], mem->type),
606 intel_i830_private.registers+I810_PTE_BASE+(j*4));
607 readl(intel_i830_private.registers+I810_PTE_BASE+(j*4)); /* PCI Posting. */
610 global_cache_flush();
611 agp_bridge->driver->tlb_flush(mem);
615 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
620 global_cache_flush();
622 if (pg_start < intel_i830_private.gtt_entries) {
623 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
627 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
628 writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4));
629 readl(intel_i830_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
632 global_cache_flush();
633 agp_bridge->driver->tlb_flush(mem);
637 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
639 if (type == AGP_PHYS_MEMORY)
640 return alloc_agpphysmem_i8xx(pg_count, type);
642 /* always return NULL for other allocation types for now */
646 static int intel_i915_configure(void)
648 struct aper_size_info_fixed *current_size;
653 current_size = A_SIZE_FIX(agp_bridge->current_size);
655 pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp);
657 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
659 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
660 gmch_ctrl |= I830_GMCH_ENABLED;
661 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
663 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL);
664 readl(intel_i830_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
666 if (agp_bridge->driver->needs_scratch_page) {
667 for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) {
668 writel(agp_bridge->scratch_page, intel_i830_private.gtt+i);
669 readl(intel_i830_private.gtt+i); /* PCI Posting. */
673 global_cache_flush();
677 static void intel_i915_cleanup(void)
679 iounmap(intel_i830_private.gtt);
680 iounmap(intel_i830_private.registers);
683 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
689 temp = agp_bridge->current_size;
690 num_entries = A_SIZE_FIX(temp)->num_entries;
692 if (pg_start < intel_i830_private.gtt_entries) {
693 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n",
694 pg_start,intel_i830_private.gtt_entries);
696 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
700 if ((pg_start + mem->page_count) > num_entries)
703 /* The i830 can't check the GTT for entries since its read only,
704 * depend on the caller to make the correct offset decisions.
707 if ((type != 0 && type != AGP_PHYS_MEMORY) ||
708 (mem->type != 0 && mem->type != AGP_PHYS_MEMORY))
711 global_cache_flush();
713 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
714 writel(agp_bridge->driver->mask_memory(agp_bridge,
715 mem->memory[i], mem->type), intel_i830_private.gtt+j);
716 readl(intel_i830_private.gtt+j); /* PCI Posting. */
719 global_cache_flush();
720 agp_bridge->driver->tlb_flush(mem);
724 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
729 global_cache_flush();
731 if (pg_start < intel_i830_private.gtt_entries) {
732 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
736 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
737 writel(agp_bridge->scratch_page, intel_i830_private.gtt+i);
738 readl(intel_i830_private.gtt+i);
741 global_cache_flush();
742 agp_bridge->driver->tlb_flush(mem);
746 static int intel_i915_fetch_size(void)
748 struct aper_size_info_fixed *values;
751 #define I915_256MB_ADDRESS_MASK (1<<27)
753 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
755 pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp);
756 if (temp & I915_256MB_ADDRESS_MASK)
757 offset = 0; /* 128MB aperture */
759 offset = 2; /* 256MB aperture */
760 agp_bridge->previous_size = agp_bridge->current_size = (void *)(values + offset);
761 return values[offset].size;
764 /* The intel i915 automatically initializes the agp aperture during POST.
765 * Use the memory already set aside for in the GTT.
767 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
770 struct aper_size_info_fixed *size;
774 size = agp_bridge->current_size;
775 page_order = size->page_order;
776 num_entries = size->num_entries;
777 agp_bridge->gatt_table_real = NULL;
779 pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp);
780 pci_read_config_dword(intel_i830_private.i830_dev, I915_PTEADDR,&temp2);
782 intel_i830_private.gtt = ioremap(temp2, 256 * 1024);
783 if (!intel_i830_private.gtt)
788 intel_i830_private.registers = ioremap(temp,128 * 4096);
789 if (!intel_i830_private.registers)
792 temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000;
793 global_cache_flush(); /* FIXME: ? */
795 /* we have to call this as early as possible after the MMIO base address is known */
796 intel_i830_init_gtt_entries();
798 agp_bridge->gatt_table = NULL;
800 agp_bridge->gatt_bus_addr = temp;
806 * The i965 supports 36-bit physical addresses, but to keep
807 * the format of the GTT the same, the bits that don't fit
808 * in a 32-bit word are shifted down to bits 4..7.
810 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
811 * is always zero on 32-bit architectures, so no need to make
814 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
815 unsigned long addr, int type)
817 /* Shift high bits down */
818 addr |= (addr >> 28) & 0xf0;
820 /* Type checking must be done elsewhere */
821 return addr | bridge->driver->masks[type].mask;
824 static int intel_i965_fetch_size(void)
826 struct aper_size_info_fixed *values;
830 #define I965_512MB_ADDRESS_MASK (3<<1)
832 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
834 pci_read_config_byte(intel_i830_private.i830_dev, I965_MSAC, &temp);
835 temp &= I965_512MB_ADDRESS_MASK;
838 offset = 0; /* 128MB */
841 offset = 3; /* 512MB */
845 offset = 2; /* 256MB */
849 agp_bridge->previous_size = agp_bridge->current_size = (void *)(values + offset);
851 /* The i965 GTT is always sized as if it had a 512kB aperture size */
855 /* The intel i965 automatically initializes the agp aperture during POST.
856 + * Use the memory already set aside for in the GTT.
858 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
861 struct aper_size_info_fixed *size;
865 size = agp_bridge->current_size;
866 page_order = size->page_order;
867 num_entries = size->num_entries;
868 agp_bridge->gatt_table_real = NULL;
870 pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp);
873 intel_i830_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
875 if (!intel_i830_private.gtt)
879 intel_i830_private.registers = ioremap(temp,128 * 4096);
880 if (!intel_i830_private.registers)
883 temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000;
884 global_cache_flush(); /* FIXME: ? */
886 /* we have to call this as early as possible after the MMIO base address is known */
887 intel_i830_init_gtt_entries();
889 agp_bridge->gatt_table = NULL;
891 agp_bridge->gatt_bus_addr = temp;
897 static int intel_fetch_size(void)
901 struct aper_size_info_16 *values;
903 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
904 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
906 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
907 if (temp == values[i].size_value) {
908 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
909 agp_bridge->aperture_size_idx = i;
910 return values[i].size;
917 static int __intel_8xx_fetch_size(u8 temp)
920 struct aper_size_info_8 *values;
922 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
924 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
925 if (temp == values[i].size_value) {
926 agp_bridge->previous_size =
927 agp_bridge->current_size = (void *) (values + i);
928 agp_bridge->aperture_size_idx = i;
929 return values[i].size;
935 static int intel_8xx_fetch_size(void)
939 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
940 return __intel_8xx_fetch_size(temp);
943 static int intel_815_fetch_size(void)
947 /* Intel 815 chipsets have a _weird_ APSIZE register with only
948 * one non-reserved bit, so mask the others out ... */
949 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
952 return __intel_8xx_fetch_size(temp);
955 static void intel_tlbflush(struct agp_memory *mem)
957 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
958 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
962 static void intel_8xx_tlbflush(struct agp_memory *mem)
965 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
966 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
967 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
968 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
972 static void intel_cleanup(void)
975 struct aper_size_info_16 *previous_size;
977 previous_size = A_SIZE_16(agp_bridge->previous_size);
978 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
979 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
980 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
984 static void intel_8xx_cleanup(void)
987 struct aper_size_info_8 *previous_size;
989 previous_size = A_SIZE_8(agp_bridge->previous_size);
990 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
991 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
992 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
996 static int intel_configure(void)
1000 struct aper_size_info_16 *current_size;
1002 current_size = A_SIZE_16(agp_bridge->current_size);
1005 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1007 /* address to map to */
1008 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1009 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1011 /* attbase - aperture base */
1012 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1015 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1018 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1019 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1020 (temp2 & ~(1 << 10)) | (1 << 9));
1021 /* clear any possible error conditions */
1022 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1026 static int intel_815_configure(void)
1030 struct aper_size_info_8 *current_size;
1032 /* attbase - aperture base */
1033 /* the Intel 815 chipset spec. says that bits 29-31 in the
1034 * ATTBASE register are reserved -> try not to write them */
1035 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1036 printk (KERN_EMERG PFX "gatt bus addr too high");
1040 current_size = A_SIZE_8(agp_bridge->current_size);
1043 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1044 current_size->size_value);
1046 /* address to map to */
1047 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1048 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1050 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1051 addr &= INTEL_815_ATTBASE_MASK;
1052 addr |= agp_bridge->gatt_bus_addr;
1053 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1056 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1059 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1060 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1062 /* clear any possible error conditions */
1063 /* Oddness : this chipset seems to have no ERRSTS register ! */
1067 static void intel_820_tlbflush(struct agp_memory *mem)
1072 static void intel_820_cleanup(void)
1075 struct aper_size_info_8 *previous_size;
1077 previous_size = A_SIZE_8(agp_bridge->previous_size);
1078 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1079 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1081 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1082 previous_size->size_value);
1086 static int intel_820_configure(void)
1090 struct aper_size_info_8 *current_size;
1092 current_size = A_SIZE_8(agp_bridge->current_size);
1095 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1097 /* address to map to */
1098 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1099 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1101 /* attbase - aperture base */
1102 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1105 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1107 /* global enable aperture access */
1108 /* This flag is not accessed through MCHCFG register as in */
1110 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1111 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1112 /* clear any possible AGP-related error conditions */
1113 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1117 static int intel_840_configure(void)
1121 struct aper_size_info_8 *current_size;
1123 current_size = A_SIZE_8(agp_bridge->current_size);
1126 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1128 /* address to map to */
1129 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1130 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1132 /* attbase - aperture base */
1133 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1136 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1139 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1140 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1141 /* clear any possible error conditions */
1142 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1146 static int intel_845_configure(void)
1150 struct aper_size_info_8 *current_size;
1152 current_size = A_SIZE_8(agp_bridge->current_size);
1155 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1157 if (agp_bridge->apbase_config != 0) {
1158 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1159 agp_bridge->apbase_config);
1161 /* address to map to */
1162 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1163 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1164 agp_bridge->apbase_config = temp;
1167 /* attbase - aperture base */
1168 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1171 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1174 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1175 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1176 /* clear any possible error conditions */
1177 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1181 static int intel_850_configure(void)
1185 struct aper_size_info_8 *current_size;
1187 current_size = A_SIZE_8(agp_bridge->current_size);
1190 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1192 /* address to map to */
1193 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1194 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1196 /* attbase - aperture base */
1197 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1200 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1203 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1204 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1205 /* clear any possible AGP-related error conditions */
1206 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1210 static int intel_860_configure(void)
1214 struct aper_size_info_8 *current_size;
1216 current_size = A_SIZE_8(agp_bridge->current_size);
1219 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1221 /* address to map to */
1222 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1223 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1225 /* attbase - aperture base */
1226 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1229 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1232 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1233 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1234 /* clear any possible AGP-related error conditions */
1235 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1239 static int intel_830mp_configure(void)
1243 struct aper_size_info_8 *current_size;
1245 current_size = A_SIZE_8(agp_bridge->current_size);
1248 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1250 /* address to map to */
1251 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1252 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1254 /* attbase - aperture base */
1255 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1258 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1261 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1262 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1263 /* clear any possible AGP-related error conditions */
1264 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1268 static int intel_7505_configure(void)
1272 struct aper_size_info_8 *current_size;
1274 current_size = A_SIZE_8(agp_bridge->current_size);
1277 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1279 /* address to map to */
1280 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1281 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1283 /* attbase - aperture base */
1284 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1287 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1290 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1291 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1296 /* Setup function */
1297 static struct gatt_mask intel_generic_masks[] =
1299 {.mask = 0x00000017, .type = 0}
1302 static struct aper_size_info_8 intel_815_sizes[2] =
1308 static struct aper_size_info_8 intel_8xx_sizes[7] =
1311 {128, 32768, 5, 32},
1319 static struct aper_size_info_16 intel_generic_sizes[7] =
1322 {128, 32768, 5, 32},
1330 static struct aper_size_info_8 intel_830mp_sizes[4] =
1333 {128, 32768, 5, 32},
1338 static struct agp_bridge_driver intel_generic_driver = {
1339 .owner = THIS_MODULE,
1340 .aperture_sizes = intel_generic_sizes,
1341 .size_type = U16_APER_SIZE,
1342 .num_aperture_sizes = 7,
1343 .configure = intel_configure,
1344 .fetch_size = intel_fetch_size,
1345 .cleanup = intel_cleanup,
1346 .tlb_flush = intel_tlbflush,
1347 .mask_memory = agp_generic_mask_memory,
1348 .masks = intel_generic_masks,
1349 .agp_enable = agp_generic_enable,
1350 .cache_flush = global_cache_flush,
1351 .create_gatt_table = agp_generic_create_gatt_table,
1352 .free_gatt_table = agp_generic_free_gatt_table,
1353 .insert_memory = agp_generic_insert_memory,
1354 .remove_memory = agp_generic_remove_memory,
1355 .alloc_by_type = agp_generic_alloc_by_type,
1356 .free_by_type = agp_generic_free_by_type,
1357 .agp_alloc_page = agp_generic_alloc_page,
1358 .agp_destroy_page = agp_generic_destroy_page,
1361 static struct agp_bridge_driver intel_810_driver = {
1362 .owner = THIS_MODULE,
1363 .aperture_sizes = intel_i810_sizes,
1364 .size_type = FIXED_APER_SIZE,
1365 .num_aperture_sizes = 2,
1366 .needs_scratch_page = TRUE,
1367 .configure = intel_i810_configure,
1368 .fetch_size = intel_i810_fetch_size,
1369 .cleanup = intel_i810_cleanup,
1370 .tlb_flush = intel_i810_tlbflush,
1371 .mask_memory = intel_i810_mask_memory,
1372 .masks = intel_i810_masks,
1373 .agp_enable = intel_i810_agp_enable,
1374 .cache_flush = global_cache_flush,
1375 .create_gatt_table = agp_generic_create_gatt_table,
1376 .free_gatt_table = agp_generic_free_gatt_table,
1377 .insert_memory = intel_i810_insert_entries,
1378 .remove_memory = intel_i810_remove_entries,
1379 .alloc_by_type = intel_i810_alloc_by_type,
1380 .free_by_type = intel_i810_free_by_type,
1381 .agp_alloc_page = agp_generic_alloc_page,
1382 .agp_destroy_page = agp_generic_destroy_page,
1385 static struct agp_bridge_driver intel_815_driver = {
1386 .owner = THIS_MODULE,
1387 .aperture_sizes = intel_815_sizes,
1388 .size_type = U8_APER_SIZE,
1389 .num_aperture_sizes = 2,
1390 .configure = intel_815_configure,
1391 .fetch_size = intel_815_fetch_size,
1392 .cleanup = intel_8xx_cleanup,
1393 .tlb_flush = intel_8xx_tlbflush,
1394 .mask_memory = agp_generic_mask_memory,
1395 .masks = intel_generic_masks,
1396 .agp_enable = agp_generic_enable,
1397 .cache_flush = global_cache_flush,
1398 .create_gatt_table = agp_generic_create_gatt_table,
1399 .free_gatt_table = agp_generic_free_gatt_table,
1400 .insert_memory = agp_generic_insert_memory,
1401 .remove_memory = agp_generic_remove_memory,
1402 .alloc_by_type = agp_generic_alloc_by_type,
1403 .free_by_type = agp_generic_free_by_type,
1404 .agp_alloc_page = agp_generic_alloc_page,
1405 .agp_destroy_page = agp_generic_destroy_page,
1408 static struct agp_bridge_driver intel_830_driver = {
1409 .owner = THIS_MODULE,
1410 .aperture_sizes = intel_i830_sizes,
1411 .size_type = FIXED_APER_SIZE,
1412 .num_aperture_sizes = 4,
1413 .needs_scratch_page = TRUE,
1414 .configure = intel_i830_configure,
1415 .fetch_size = intel_i830_fetch_size,
1416 .cleanup = intel_i830_cleanup,
1417 .tlb_flush = intel_i810_tlbflush,
1418 .mask_memory = intel_i810_mask_memory,
1419 .masks = intel_i810_masks,
1420 .agp_enable = intel_i810_agp_enable,
1421 .cache_flush = global_cache_flush,
1422 .create_gatt_table = intel_i830_create_gatt_table,
1423 .free_gatt_table = intel_i830_free_gatt_table,
1424 .insert_memory = intel_i830_insert_entries,
1425 .remove_memory = intel_i830_remove_entries,
1426 .alloc_by_type = intel_i830_alloc_by_type,
1427 .free_by_type = intel_i810_free_by_type,
1428 .agp_alloc_page = agp_generic_alloc_page,
1429 .agp_destroy_page = agp_generic_destroy_page,
1432 static struct agp_bridge_driver intel_820_driver = {
1433 .owner = THIS_MODULE,
1434 .aperture_sizes = intel_8xx_sizes,
1435 .size_type = U8_APER_SIZE,
1436 .num_aperture_sizes = 7,
1437 .configure = intel_820_configure,
1438 .fetch_size = intel_8xx_fetch_size,
1439 .cleanup = intel_820_cleanup,
1440 .tlb_flush = intel_820_tlbflush,
1441 .mask_memory = agp_generic_mask_memory,
1442 .masks = intel_generic_masks,
1443 .agp_enable = agp_generic_enable,
1444 .cache_flush = global_cache_flush,
1445 .create_gatt_table = agp_generic_create_gatt_table,
1446 .free_gatt_table = agp_generic_free_gatt_table,
1447 .insert_memory = agp_generic_insert_memory,
1448 .remove_memory = agp_generic_remove_memory,
1449 .alloc_by_type = agp_generic_alloc_by_type,
1450 .free_by_type = agp_generic_free_by_type,
1451 .agp_alloc_page = agp_generic_alloc_page,
1452 .agp_destroy_page = agp_generic_destroy_page,
1455 static struct agp_bridge_driver intel_830mp_driver = {
1456 .owner = THIS_MODULE,
1457 .aperture_sizes = intel_830mp_sizes,
1458 .size_type = U8_APER_SIZE,
1459 .num_aperture_sizes = 4,
1460 .configure = intel_830mp_configure,
1461 .fetch_size = intel_8xx_fetch_size,
1462 .cleanup = intel_8xx_cleanup,
1463 .tlb_flush = intel_8xx_tlbflush,
1464 .mask_memory = agp_generic_mask_memory,
1465 .masks = intel_generic_masks,
1466 .agp_enable = agp_generic_enable,
1467 .cache_flush = global_cache_flush,
1468 .create_gatt_table = agp_generic_create_gatt_table,
1469 .free_gatt_table = agp_generic_free_gatt_table,
1470 .insert_memory = agp_generic_insert_memory,
1471 .remove_memory = agp_generic_remove_memory,
1472 .alloc_by_type = agp_generic_alloc_by_type,
1473 .free_by_type = agp_generic_free_by_type,
1474 .agp_alloc_page = agp_generic_alloc_page,
1475 .agp_destroy_page = agp_generic_destroy_page,
1478 static struct agp_bridge_driver intel_840_driver = {
1479 .owner = THIS_MODULE,
1480 .aperture_sizes = intel_8xx_sizes,
1481 .size_type = U8_APER_SIZE,
1482 .num_aperture_sizes = 7,
1483 .configure = intel_840_configure,
1484 .fetch_size = intel_8xx_fetch_size,
1485 .cleanup = intel_8xx_cleanup,
1486 .tlb_flush = intel_8xx_tlbflush,
1487 .mask_memory = agp_generic_mask_memory,
1488 .masks = intel_generic_masks,
1489 .agp_enable = agp_generic_enable,
1490 .cache_flush = global_cache_flush,
1491 .create_gatt_table = agp_generic_create_gatt_table,
1492 .free_gatt_table = agp_generic_free_gatt_table,
1493 .insert_memory = agp_generic_insert_memory,
1494 .remove_memory = agp_generic_remove_memory,
1495 .alloc_by_type = agp_generic_alloc_by_type,
1496 .free_by_type = agp_generic_free_by_type,
1497 .agp_alloc_page = agp_generic_alloc_page,
1498 .agp_destroy_page = agp_generic_destroy_page,
1501 static struct agp_bridge_driver intel_845_driver = {
1502 .owner = THIS_MODULE,
1503 .aperture_sizes = intel_8xx_sizes,
1504 .size_type = U8_APER_SIZE,
1505 .num_aperture_sizes = 7,
1506 .configure = intel_845_configure,
1507 .fetch_size = intel_8xx_fetch_size,
1508 .cleanup = intel_8xx_cleanup,
1509 .tlb_flush = intel_8xx_tlbflush,
1510 .mask_memory = agp_generic_mask_memory,
1511 .masks = intel_generic_masks,
1512 .agp_enable = agp_generic_enable,
1513 .cache_flush = global_cache_flush,
1514 .create_gatt_table = agp_generic_create_gatt_table,
1515 .free_gatt_table = agp_generic_free_gatt_table,
1516 .insert_memory = agp_generic_insert_memory,
1517 .remove_memory = agp_generic_remove_memory,
1518 .alloc_by_type = agp_generic_alloc_by_type,
1519 .free_by_type = agp_generic_free_by_type,
1520 .agp_alloc_page = agp_generic_alloc_page,
1521 .agp_destroy_page = agp_generic_destroy_page,
1524 static struct agp_bridge_driver intel_850_driver = {
1525 .owner = THIS_MODULE,
1526 .aperture_sizes = intel_8xx_sizes,
1527 .size_type = U8_APER_SIZE,
1528 .num_aperture_sizes = 7,
1529 .configure = intel_850_configure,
1530 .fetch_size = intel_8xx_fetch_size,
1531 .cleanup = intel_8xx_cleanup,
1532 .tlb_flush = intel_8xx_tlbflush,
1533 .mask_memory = agp_generic_mask_memory,
1534 .masks = intel_generic_masks,
1535 .agp_enable = agp_generic_enable,
1536 .cache_flush = global_cache_flush,
1537 .create_gatt_table = agp_generic_create_gatt_table,
1538 .free_gatt_table = agp_generic_free_gatt_table,
1539 .insert_memory = agp_generic_insert_memory,
1540 .remove_memory = agp_generic_remove_memory,
1541 .alloc_by_type = agp_generic_alloc_by_type,
1542 .free_by_type = agp_generic_free_by_type,
1543 .agp_alloc_page = agp_generic_alloc_page,
1544 .agp_destroy_page = agp_generic_destroy_page,
1547 static struct agp_bridge_driver intel_860_driver = {
1548 .owner = THIS_MODULE,
1549 .aperture_sizes = intel_8xx_sizes,
1550 .size_type = U8_APER_SIZE,
1551 .num_aperture_sizes = 7,
1552 .configure = intel_860_configure,
1553 .fetch_size = intel_8xx_fetch_size,
1554 .cleanup = intel_8xx_cleanup,
1555 .tlb_flush = intel_8xx_tlbflush,
1556 .mask_memory = agp_generic_mask_memory,
1557 .masks = intel_generic_masks,
1558 .agp_enable = agp_generic_enable,
1559 .cache_flush = global_cache_flush,
1560 .create_gatt_table = agp_generic_create_gatt_table,
1561 .free_gatt_table = agp_generic_free_gatt_table,
1562 .insert_memory = agp_generic_insert_memory,
1563 .remove_memory = agp_generic_remove_memory,
1564 .alloc_by_type = agp_generic_alloc_by_type,
1565 .free_by_type = agp_generic_free_by_type,
1566 .agp_alloc_page = agp_generic_alloc_page,
1567 .agp_destroy_page = agp_generic_destroy_page,
1570 static struct agp_bridge_driver intel_915_driver = {
1571 .owner = THIS_MODULE,
1572 .aperture_sizes = intel_i830_sizes,
1573 .size_type = FIXED_APER_SIZE,
1574 .num_aperture_sizes = 4,
1575 .needs_scratch_page = TRUE,
1576 .configure = intel_i915_configure,
1577 .fetch_size = intel_i915_fetch_size,
1578 .cleanup = intel_i915_cleanup,
1579 .tlb_flush = intel_i810_tlbflush,
1580 .mask_memory = intel_i810_mask_memory,
1581 .masks = intel_i810_masks,
1582 .agp_enable = intel_i810_agp_enable,
1583 .cache_flush = global_cache_flush,
1584 .create_gatt_table = intel_i915_create_gatt_table,
1585 .free_gatt_table = intel_i830_free_gatt_table,
1586 .insert_memory = intel_i915_insert_entries,
1587 .remove_memory = intel_i915_remove_entries,
1588 .alloc_by_type = intel_i830_alloc_by_type,
1589 .free_by_type = intel_i810_free_by_type,
1590 .agp_alloc_page = agp_generic_alloc_page,
1591 .agp_destroy_page = agp_generic_destroy_page,
1594 static struct agp_bridge_driver intel_i965_driver = {
1595 .owner = THIS_MODULE,
1596 .aperture_sizes = intel_i830_sizes,
1597 .size_type = FIXED_APER_SIZE,
1598 .num_aperture_sizes = 4,
1599 .needs_scratch_page = TRUE,
1600 .configure = intel_i915_configure,
1601 .fetch_size = intel_i965_fetch_size,
1602 .cleanup = intel_i915_cleanup,
1603 .tlb_flush = intel_i810_tlbflush,
1604 .mask_memory = intel_i965_mask_memory,
1605 .masks = intel_i810_masks,
1606 .agp_enable = intel_i810_agp_enable,
1607 .cache_flush = global_cache_flush,
1608 .create_gatt_table = intel_i965_create_gatt_table,
1609 .free_gatt_table = intel_i830_free_gatt_table,
1610 .insert_memory = intel_i915_insert_entries,
1611 .remove_memory = intel_i915_remove_entries,
1612 .alloc_by_type = intel_i830_alloc_by_type,
1613 .free_by_type = intel_i810_free_by_type,
1614 .agp_alloc_page = agp_generic_alloc_page,
1615 .agp_destroy_page = agp_generic_destroy_page,
1618 static struct agp_bridge_driver intel_7505_driver = {
1619 .owner = THIS_MODULE,
1620 .aperture_sizes = intel_8xx_sizes,
1621 .size_type = U8_APER_SIZE,
1622 .num_aperture_sizes = 7,
1623 .configure = intel_7505_configure,
1624 .fetch_size = intel_8xx_fetch_size,
1625 .cleanup = intel_8xx_cleanup,
1626 .tlb_flush = intel_8xx_tlbflush,
1627 .mask_memory = agp_generic_mask_memory,
1628 .masks = intel_generic_masks,
1629 .agp_enable = agp_generic_enable,
1630 .cache_flush = global_cache_flush,
1631 .create_gatt_table = agp_generic_create_gatt_table,
1632 .free_gatt_table = agp_generic_free_gatt_table,
1633 .insert_memory = agp_generic_insert_memory,
1634 .remove_memory = agp_generic_remove_memory,
1635 .alloc_by_type = agp_generic_alloc_by_type,
1636 .free_by_type = agp_generic_free_by_type,
1637 .agp_alloc_page = agp_generic_alloc_page,
1638 .agp_destroy_page = agp_generic_destroy_page,
1641 static int find_i810(u16 device)
1643 struct pci_dev *i810_dev;
1645 i810_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1648 intel_i810_private.i810_dev = i810_dev;
1652 static int find_i830(u16 device)
1654 struct pci_dev *i830_dev;
1656 i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1657 if (i830_dev && PCI_FUNC(i830_dev->devfn) != 0) {
1658 i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
1665 intel_i830_private.i830_dev = i830_dev;
1669 static int __devinit agp_intel_probe(struct pci_dev *pdev,
1670 const struct pci_device_id *ent)
1672 struct agp_bridge_data *bridge;
1673 char *name = "(unknown)";
1677 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
1679 bridge = agp_alloc_bridge();
1683 switch (pdev->device) {
1684 case PCI_DEVICE_ID_INTEL_82443LX_0:
1685 bridge->driver = &intel_generic_driver;
1688 case PCI_DEVICE_ID_INTEL_82443BX_0:
1689 bridge->driver = &intel_generic_driver;
1692 case PCI_DEVICE_ID_INTEL_82443GX_0:
1693 bridge->driver = &intel_generic_driver;
1696 case PCI_DEVICE_ID_INTEL_82810_MC1:
1698 if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG1))
1700 bridge->driver = &intel_810_driver;
1702 case PCI_DEVICE_ID_INTEL_82810_MC3:
1703 name = "i810 DC100";
1704 if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG3))
1706 bridge->driver = &intel_810_driver;
1708 case PCI_DEVICE_ID_INTEL_82810E_MC:
1710 if (!find_i810(PCI_DEVICE_ID_INTEL_82810E_IG))
1712 bridge->driver = &intel_810_driver;
1714 case PCI_DEVICE_ID_INTEL_82815_MC:
1716 * The i815 can operate either as an i810 style
1717 * integrated device, or as an AGP4X motherboard.
1719 if (find_i810(PCI_DEVICE_ID_INTEL_82815_CGC))
1720 bridge->driver = &intel_810_driver;
1722 bridge->driver = &intel_815_driver;
1725 case PCI_DEVICE_ID_INTEL_82820_HB:
1726 case PCI_DEVICE_ID_INTEL_82820_UP_HB:
1727 bridge->driver = &intel_820_driver;
1730 case PCI_DEVICE_ID_INTEL_82830_HB:
1731 if (find_i830(PCI_DEVICE_ID_INTEL_82830_CGC))
1732 bridge->driver = &intel_830_driver;
1734 bridge->driver = &intel_830mp_driver;
1737 case PCI_DEVICE_ID_INTEL_82840_HB:
1738 bridge->driver = &intel_840_driver;
1741 case PCI_DEVICE_ID_INTEL_82845_HB:
1742 bridge->driver = &intel_845_driver;
1745 case PCI_DEVICE_ID_INTEL_82845G_HB:
1746 if (find_i830(PCI_DEVICE_ID_INTEL_82845G_IG))
1747 bridge->driver = &intel_830_driver;
1749 bridge->driver = &intel_845_driver;
1752 case PCI_DEVICE_ID_INTEL_82850_HB:
1753 bridge->driver = &intel_850_driver;
1756 case PCI_DEVICE_ID_INTEL_82855PM_HB:
1757 bridge->driver = &intel_845_driver;
1760 case PCI_DEVICE_ID_INTEL_82855GM_HB:
1761 if (find_i830(PCI_DEVICE_ID_INTEL_82855GM_IG)) {
1762 bridge->driver = &intel_830_driver;
1765 bridge->driver = &intel_845_driver;
1769 case PCI_DEVICE_ID_INTEL_82860_HB:
1770 bridge->driver = &intel_860_driver;
1773 case PCI_DEVICE_ID_INTEL_82865_HB:
1774 if (find_i830(PCI_DEVICE_ID_INTEL_82865_IG))
1775 bridge->driver = &intel_830_driver;
1777 bridge->driver = &intel_845_driver;
1780 case PCI_DEVICE_ID_INTEL_82875_HB:
1781 bridge->driver = &intel_845_driver;
1784 case PCI_DEVICE_ID_INTEL_82915G_HB:
1785 if (find_i830(PCI_DEVICE_ID_INTEL_82915G_IG))
1786 bridge->driver = &intel_915_driver;
1788 bridge->driver = &intel_845_driver;
1791 case PCI_DEVICE_ID_INTEL_82915GM_HB:
1792 if (find_i830(PCI_DEVICE_ID_INTEL_82915GM_IG))
1793 bridge->driver = &intel_915_driver;
1795 bridge->driver = &intel_845_driver;
1798 case PCI_DEVICE_ID_INTEL_82945G_HB:
1799 if (find_i830(PCI_DEVICE_ID_INTEL_82945G_IG))
1800 bridge->driver = &intel_915_driver;
1802 bridge->driver = &intel_845_driver;
1805 case PCI_DEVICE_ID_INTEL_82945GM_HB:
1806 if (find_i830(PCI_DEVICE_ID_INTEL_82945GM_IG))
1807 bridge->driver = &intel_915_driver;
1809 bridge->driver = &intel_845_driver;
1812 case PCI_DEVICE_ID_INTEL_82946GZ_HB:
1813 if (find_i830(PCI_DEVICE_ID_INTEL_82946GZ_IG))
1814 bridge->driver = &intel_i965_driver;
1816 bridge->driver = &intel_845_driver;
1819 case PCI_DEVICE_ID_INTEL_82965G_1_HB:
1820 if (find_i830(PCI_DEVICE_ID_INTEL_82965G_1_IG))
1821 bridge->driver = &intel_i965_driver;
1823 bridge->driver = &intel_845_driver;
1826 case PCI_DEVICE_ID_INTEL_82965Q_HB:
1827 if (find_i830(PCI_DEVICE_ID_INTEL_82965Q_IG))
1828 bridge->driver = &intel_i965_driver;
1830 bridge->driver = &intel_845_driver;
1833 case PCI_DEVICE_ID_INTEL_82965G_HB:
1834 if (find_i830(PCI_DEVICE_ID_INTEL_82965G_IG))
1835 bridge->driver = &intel_i965_driver;
1837 bridge->driver = &intel_845_driver;
1841 case PCI_DEVICE_ID_INTEL_7505_0:
1842 bridge->driver = &intel_7505_driver;
1845 case PCI_DEVICE_ID_INTEL_7205_0:
1846 bridge->driver = &intel_7505_driver;
1851 printk(KERN_WARNING PFX "Unsupported Intel chipset (device id: %04x)\n",
1853 agp_put_bridge(bridge);
1858 bridge->capndx = cap_ptr;
1860 if (bridge->driver == &intel_810_driver)
1861 bridge->dev_private_data = &intel_i810_private;
1862 else if (bridge->driver == &intel_830_driver)
1863 bridge->dev_private_data = &intel_i830_private;
1865 printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n", name);
1868 * The following fixes the case where the BIOS has "forgotten" to
1869 * provide an address range for the GART.
1870 * 20030610 - hamish@zot.org
1872 r = &pdev->resource[0];
1873 if (!r->start && r->end) {
1874 if (pci_assign_resource(pdev, 0)) {
1875 printk(KERN_ERR PFX "could not assign resource 0\n");
1876 agp_put_bridge(bridge);
1882 * If the device has not been properly setup, the following will catch
1883 * the problem and should stop the system from crashing.
1884 * 20030610 - hamish@zot.org
1886 if (pci_enable_device(pdev)) {
1887 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
1888 agp_put_bridge(bridge);
1892 /* Fill in the mode register */
1894 pci_read_config_dword(pdev,
1895 bridge->capndx+PCI_AGP_STATUS,
1899 pci_set_drvdata(pdev, bridge);
1900 return agp_add_bridge(bridge);
1903 printk(KERN_ERR PFX "Detected an Intel %s chipset, "
1904 "but could not find the secondary device.\n", name);
1905 agp_put_bridge(bridge);
1909 static void __devexit agp_intel_remove(struct pci_dev *pdev)
1911 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1913 agp_remove_bridge(bridge);
1915 if (intel_i810_private.i810_dev)
1916 pci_dev_put(intel_i810_private.i810_dev);
1917 if (intel_i830_private.i830_dev)
1918 pci_dev_put(intel_i830_private.i830_dev);
1920 agp_put_bridge(bridge);
1924 static int agp_intel_resume(struct pci_dev *pdev)
1926 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1928 pci_restore_state(pdev);
1930 if (bridge->driver == &intel_generic_driver)
1932 else if (bridge->driver == &intel_850_driver)
1933 intel_850_configure();
1934 else if (bridge->driver == &intel_845_driver)
1935 intel_845_configure();
1936 else if (bridge->driver == &intel_830mp_driver)
1937 intel_830mp_configure();
1938 else if (bridge->driver == &intel_915_driver)
1939 intel_i915_configure();
1940 else if (bridge->driver == &intel_830_driver)
1941 intel_i830_configure();
1942 else if (bridge->driver == &intel_810_driver)
1943 intel_i810_configure();
1944 else if (bridge->driver == &intel_i965_driver)
1945 intel_i915_configure();
1951 static struct pci_device_id agp_intel_pci_table[] = {
1954 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
1956 .vendor = PCI_VENDOR_ID_INTEL, \
1958 .subvendor = PCI_ANY_ID, \
1959 .subdevice = PCI_ANY_ID, \
1961 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
1962 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
1963 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
1964 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
1965 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
1966 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
1967 ID(PCI_DEVICE_ID_INTEL_82815_MC),
1968 ID(PCI_DEVICE_ID_INTEL_82820_HB),
1969 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
1970 ID(PCI_DEVICE_ID_INTEL_82830_HB),
1971 ID(PCI_DEVICE_ID_INTEL_82840_HB),
1972 ID(PCI_DEVICE_ID_INTEL_82845_HB),
1973 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
1974 ID(PCI_DEVICE_ID_INTEL_82850_HB),
1975 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
1976 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
1977 ID(PCI_DEVICE_ID_INTEL_82860_HB),
1978 ID(PCI_DEVICE_ID_INTEL_82865_HB),
1979 ID(PCI_DEVICE_ID_INTEL_82875_HB),
1980 ID(PCI_DEVICE_ID_INTEL_7505_0),
1981 ID(PCI_DEVICE_ID_INTEL_7205_0),
1982 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
1983 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
1984 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
1985 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
1986 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
1987 ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
1988 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
1989 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
1993 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
1995 static struct pci_driver agp_intel_pci_driver = {
1996 .name = "agpgart-intel",
1997 .id_table = agp_intel_pci_table,
1998 .probe = agp_intel_probe,
1999 .remove = __devexit_p(agp_intel_remove),
2001 .resume = agp_intel_resume,
2005 static int __init agp_intel_init(void)
2009 return pci_register_driver(&agp_intel_pci_driver);
2012 static void __exit agp_intel_cleanup(void)
2014 pci_unregister_driver(&agp_intel_pci_driver);
2017 module_init(agp_intel_init);
2018 module_exit(agp_intel_cleanup);
2020 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2021 MODULE_LICENSE("GPL and additional rights");