git.oblomov.eu Git - linux-2.6/blob - drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/init.h>
  39 #include <linux/string.h>
  40 #include <linux/slab.h>
  41
  42 #include <rdma/ib_verbs.h>
  43 #include <rdma/ib_cache.h>
  44 #include <rdma/ib_pack.h>
  45
  46 #include "mthca_dev.h"
  47 #include "mthca_cmd.h"
  48 #include "mthca_memfree.h"
  49 #include "mthca_wqe.h"
  50
  51 enum {
  52         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  53         MTHCA_ACK_REQ_FREQ       = 10,
  54         MTHCA_FLIGHT_LIMIT       = 9,
  55         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  56         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  57         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  58 };
  59
  60 enum {
  61         MTHCA_QP_STATE_RST  = 0,
  62         MTHCA_QP_STATE_INIT = 1,
  63         MTHCA_QP_STATE_RTR  = 2,
  64         MTHCA_QP_STATE_RTS  = 3,
  65         MTHCA_QP_STATE_SQE  = 4,
  66         MTHCA_QP_STATE_SQD  = 5,
  67         MTHCA_QP_STATE_ERR  = 6,
  68         MTHCA_QP_STATE_DRAINING = 7
  69 };
  70
  71 enum {
  72         MTHCA_QP_ST_RC  = 0x0,
  73         MTHCA_QP_ST_UC  = 0x1,
  74         MTHCA_QP_ST_RD  = 0x2,
  75         MTHCA_QP_ST_UD  = 0x3,
  76         MTHCA_QP_ST_MLX = 0x7
  77 };
  78
  79 enum {
  80         MTHCA_QP_PM_MIGRATED = 0x3,
  81         MTHCA_QP_PM_ARMED    = 0x0,
  82         MTHCA_QP_PM_REARM    = 0x1
  83 };
  84
  85 enum {
  86         /* qp_context flags */
  87         MTHCA_QP_BIT_DE  = 1 <<  8,
  88         /* params1 */
  89         MTHCA_QP_BIT_SRE = 1 << 15,
  90         MTHCA_QP_BIT_SWE = 1 << 14,
  91         MTHCA_QP_BIT_SAE = 1 << 13,
  92         MTHCA_QP_BIT_SIC = 1 <<  4,
  93         MTHCA_QP_BIT_SSC = 1 <<  3,
  94         /* params2 */
  95         MTHCA_QP_BIT_RRE = 1 << 15,
  96         MTHCA_QP_BIT_RWE = 1 << 14,
  97         MTHCA_QP_BIT_RAE = 1 << 13,
  98         MTHCA_QP_BIT_RIC = 1 <<  4,
  99         MTHCA_QP_BIT_RSC = 1 <<  3
 100 };
 101
 102 enum {
 103         MTHCA_SEND_DOORBELL_FENCE = 1 << 5
 104 };
 105
 106 struct mthca_qp_path {
 107         __be32 port_pkey;
 108         u8     rnr_retry;
 109         u8     g_mylmc;
 110         __be16 rlid;
 111         u8     ackto;
 112         u8     mgid_index;
 113         u8     static_rate;
 114         u8     hop_limit;
 115         __be32 sl_tclass_flowlabel;
 116         u8     rgid[16];
 117 } __attribute__((packed));
 118
 119 struct mthca_qp_context {
 120         __be32 flags;
 121         __be32 tavor_sched_queue; /* Reserved on Arbel */
 122         u8     mtu_msgmax;
 123         u8     rq_size_stride;  /* Reserved on Tavor */
 124         u8     sq_size_stride;  /* Reserved on Tavor */
 125         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 126         __be32 usr_page;
 127         __be32 local_qpn;
 128         __be32 remote_qpn;
 129         u32    reserved1[2];
 130         struct mthca_qp_path pri_path;
 131         struct mthca_qp_path alt_path;
 132         __be32 rdd;
 133         __be32 pd;
 134         __be32 wqe_base;
 135         __be32 wqe_lkey;
 136         __be32 params1;
 137         __be32 reserved2;
 138         __be32 next_send_psn;
 139         __be32 cqn_snd;
 140         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 141         __be32 snd_db_index;    /* (debugging only entries) */
 142         __be32 last_acked_psn;
 143         __be32 ssn;
 144         __be32 params2;
 145         __be32 rnr_nextrecvpsn;
 146         __be32 ra_buff_indx;
 147         __be32 cqn_rcv;
 148         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 149         __be32 rcv_db_index;    /* (debugging only entries) */
 150         __be32 qkey;
 151         __be32 srqn;
 152         __be32 rmsn;
 153         __be16 rq_wqe_counter;  /* reserved on Tavor */
 154         __be16 sq_wqe_counter;  /* reserved on Tavor */
 155         u32    reserved3[18];
 156 } __attribute__((packed));
 157
 158 struct mthca_qp_param {
 159         __be32 opt_param_mask;
 160         u32    reserved1;
 161         struct mthca_qp_context context;
 162         u32    reserved2[62];
 163 } __attribute__((packed));
 164
 165 enum {
 166         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 167         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 168         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 169         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 170         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 171         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 172         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 173         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 174         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 175         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 176         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 177         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 178         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 179         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 180         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 181         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 182         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 183 };
 184
 185 static const u8 mthca_opcode[] = {
 186         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 187         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 188         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 189         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 190         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 191         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 192         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 193 };
 194
 195 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 196 {
 197         return qp->qpn >= dev->qp_table.sqp_start &&
 198                 qp->qpn <= dev->qp_table.sqp_start + 3;
 199 }
 200
 201 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 202 {
 203         return qp->qpn >= dev->qp_table.sqp_start &&
 204                 qp->qpn <= dev->qp_table.sqp_start + 1;
 205 }
 206
 207 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 208 {
 209         if (qp->is_direct)
 210                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 211         else
 212                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 213                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 214 }
 215
 216 static void *get_send_wqe(struct mthca_qp *qp, int n)
 217 {
 218         if (qp->is_direct)
 219                 return qp->queue.direct.buf + qp->send_wqe_offset +
 220                         (n << qp->sq.wqe_shift);
 221         else
 222                 return qp->queue.page_list[(qp->send_wqe_offset +
 223                                             (n << qp->sq.wqe_shift)) >>
 224                                            PAGE_SHIFT].buf +
 225                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 226                          (PAGE_SIZE - 1));
 227 }
 228
 229 static void mthca_wq_reset(struct mthca_wq *wq)
 230 {
 231         wq->next_ind  = 0;
 232         wq->last_comp = wq->max - 1;
 233         wq->head      = 0;
 234         wq->tail      = 0;
 235 }
 236
 237 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 238                     enum ib_event_type event_type)
 239 {
 240         struct mthca_qp *qp;
 241         struct ib_event event;
 242
 243         spin_lock(&dev->qp_table.lock);
 244         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 245         if (qp)
 246                 ++qp->refcount;
 247         spin_unlock(&dev->qp_table.lock);
 248
 249         if (!qp) {
 250                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 251                 return;
 252         }
 253
 254         if (event_type == IB_EVENT_PATH_MIG)
 255                 qp->port = qp->alt_port;
 256
 257         event.device      = &dev->ib_dev;
 258         event.event       = event_type;
 259         event.element.qp  = &qp->ibqp;
 260         if (qp->ibqp.event_handler)
 261                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 262
 263         spin_lock(&dev->qp_table.lock);
 264         if (!--qp->refcount)
 265                 wake_up(&qp->wait);
 266         spin_unlock(&dev->qp_table.lock);
 267 }
 268
 269 static int to_mthca_state(enum ib_qp_state ib_state)
 270 {
 271         switch (ib_state) {
 272         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 273         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 274         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 275         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 276         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 277         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 278         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 279         default:                return -1;
 280         }
 281 }
 282
 283 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 284
 285 static int to_mthca_st(int transport)
 286 {
 287         switch (transport) {
 288         case RC:  return MTHCA_QP_ST_RC;
 289         case UC:  return MTHCA_QP_ST_UC;
 290         case UD:  return MTHCA_QP_ST_UD;
 291         case RD:  return MTHCA_QP_ST_RD;
 292         case MLX: return MTHCA_QP_ST_MLX;
 293         default:  return -1;
 294         }
 295 }
 296
 297 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 298                         int attr_mask)
 299 {
 300         if (attr_mask & IB_QP_PKEY_INDEX)
 301                 sqp->pkey_index = attr->pkey_index;
 302         if (attr_mask & IB_QP_QKEY)
 303                 sqp->qkey = attr->qkey;
 304         if (attr_mask & IB_QP_SQ_PSN)
 305                 sqp->send_psn = attr->sq_psn;
 306 }
 307
 308 static void init_port(struct mthca_dev *dev, int port)
 309 {
 310         int err;
 311         u8 status;
 312         struct mthca_init_ib_param param;
 313
 314         memset(&param, 0, sizeof param);
 315
 316         param.port_width = dev->limits.port_width_cap;
 317         param.vl_cap     = dev->limits.vl_cap;
 318         param.mtu_cap    = dev->limits.mtu_cap;
 319         param.gid_cap    = dev->limits.gid_table_len;
 320         param.pkey_cap   = dev->limits.pkey_table_len;
 321
 322         err = mthca_INIT_IB(dev, &param, port, &status);
 323         if (err)
 324                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 325         if (status)
 326                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 327 }
 328
 329 static __be32 get_hw_access_flags(struct mthca_qp *qp, struct ib_qp_attr *attr,
 330                                   int attr_mask)
 331 {
 332         u8 dest_rd_atomic;
 333         u32 access_flags;
 334         u32 hw_access_flags = 0;
 335
 336         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 337                 dest_rd_atomic = attr->max_dest_rd_atomic;
 338         else
 339                 dest_rd_atomic = qp->resp_depth;
 340
 341         if (attr_mask & IB_QP_ACCESS_FLAGS)
 342                 access_flags = attr->qp_access_flags;
 343         else
 344                 access_flags = qp->atomic_rd_en;
 345
 346         if (!dest_rd_atomic)
 347                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 348
 349         if (access_flags & IB_ACCESS_REMOTE_READ)
 350                 hw_access_flags |= MTHCA_QP_BIT_RRE;
 351         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 352                 hw_access_flags |= MTHCA_QP_BIT_RAE;
 353         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 354                 hw_access_flags |= MTHCA_QP_BIT_RWE;
 355
 356         return cpu_to_be32(hw_access_flags);
 357 }
 358
 359 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
 360 {
 361         switch (mthca_state) {
 362         case MTHCA_QP_STATE_RST:      return IB_QPS_RESET;
 363         case MTHCA_QP_STATE_INIT:     return IB_QPS_INIT;
 364         case MTHCA_QP_STATE_RTR:      return IB_QPS_RTR;
 365         case MTHCA_QP_STATE_RTS:      return IB_QPS_RTS;
 366         case MTHCA_QP_STATE_DRAINING:
 367         case MTHCA_QP_STATE_SQD:      return IB_QPS_SQD;
 368         case MTHCA_QP_STATE_SQE:      return IB_QPS_SQE;
 369         case MTHCA_QP_STATE_ERR:      return IB_QPS_ERR;
 370         default:                      return -1;
 371         }
 372 }
 373
 374 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
 375 {
 376         switch (mthca_mig_state) {
 377         case 0:  return IB_MIG_ARMED;
 378         case 1:  return IB_MIG_REARM;
 379         case 3:  return IB_MIG_MIGRATED;
 380         default: return -1;
 381         }
 382 }
 383
 384 static int to_ib_qp_access_flags(int mthca_flags)
 385 {
 386         int ib_flags = 0;
 387
 388         if (mthca_flags & MTHCA_QP_BIT_RRE)
 389                 ib_flags |= IB_ACCESS_REMOTE_READ;
 390         if (mthca_flags & MTHCA_QP_BIT_RWE)
 391                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
 392         if (mthca_flags & MTHCA_QP_BIT_RAE)
 393                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
 394
 395         return ib_flags;
 396 }
 397
 398 static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr,
 399                                 struct mthca_qp_path *path)
 400 {
 401         memset(ib_ah_attr, 0, sizeof *path);
 402         ib_ah_attr->port_num      = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
 403
 404         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->limits.num_ports)
 405                 return;
 406
 407         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
 408         ib_ah_attr->sl            = be32_to_cpu(path->sl_tclass_flowlabel) >> 28;
 409         ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f;
 410         ib_ah_attr->static_rate   = mthca_rate_to_ib(dev,
 411                                                      path->static_rate & 0x7,
 412                                                      ib_ah_attr->port_num);
 413         ib_ah_attr->ah_flags      = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
 414         if (ib_ah_attr->ah_flags) {
 415                 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1);
 416                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
 417                 ib_ah_attr->grh.traffic_class =
 418                         (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff;
 419                 ib_ah_attr->grh.flow_label =
 420                         be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff;
 421                 memcpy(ib_ah_attr->grh.dgid.raw,
 422                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
 423         }
 424 }
 425
 426 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
 427                    struct ib_qp_init_attr *qp_init_attr)
 428 {
 429         struct mthca_dev *dev = to_mdev(ibqp->device);
 430         struct mthca_qp *qp = to_mqp(ibqp);
 431         int err;
 432         struct mthca_mailbox *mailbox;
 433         struct mthca_qp_param *qp_param;
 434         struct mthca_qp_context *context;
 435         int mthca_state;
 436         u8 status;
 437
 438         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 439         if (IS_ERR(mailbox))
 440                 return PTR_ERR(mailbox);
 441
 442         err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status);
 443         if (err)
 444                 goto out;
 445         if (status) {
 446                 mthca_warn(dev, "QUERY_QP returned status %02x\n", status);
 447                 err = -EINVAL;
 448                 goto out;
 449         }
 450
 451         qp_param    = mailbox->buf;
 452         context     = &qp_param->context;
 453         mthca_state = be32_to_cpu(context->flags) >> 28;
 454
 455         qp_attr->qp_state            = to_ib_qp_state(mthca_state);
 456         qp_attr->cur_qp_state        = qp_attr->qp_state;
 457         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
 458         qp_attr->path_mig_state      =
 459                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
 460         qp_attr->qkey                = be32_to_cpu(context->qkey);
 461         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
 462         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
 463         qp_attr->dest_qp_num         = be32_to_cpu(context->remote_qpn) & 0xffffff;
 464         qp_attr->qp_access_flags     =
 465                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
 466         qp_attr->cap.max_send_wr     = qp->sq.max;
 467         qp_attr->cap.max_recv_wr     = qp->rq.max;
 468         qp_attr->cap.max_send_sge    = qp->sq.max_gs;
 469         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
 470         qp_attr->cap.max_inline_data = qp->max_inline_data;
 471
 472         if (qp->transport == RC || qp->transport == UC) {
 473                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
 474                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
 475         }
 476
 477         qp_attr->pkey_index     = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
 478         qp_attr->alt_pkey_index = be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
 479
 480         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
 481         qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
 482
 483         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
 484
 485         qp_attr->max_dest_rd_atomic =
 486                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
 487         qp_attr->min_rnr_timer      =
 488                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
 489         qp_attr->port_num           = qp_attr->ah_attr.port_num;
 490         qp_attr->timeout            = context->pri_path.ackto >> 3;
 491         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
 492         qp_attr->rnr_retry          = context->pri_path.rnr_retry >> 5;
 493         qp_attr->alt_port_num       = qp_attr->alt_ah_attr.port_num;
 494         qp_attr->alt_timeout        = context->alt_path.ackto >> 3;
 495         qp_init_attr->cap           = qp_attr->cap;
 496
 497 out:
 498         mthca_free_mailbox(dev, mailbox);
 499         return err;
 500 }
 501
 502 static int mthca_path_set(struct mthca_dev *dev, struct ib_ah_attr *ah,
 503                           struct mthca_qp_path *path, u8 port)
 504 {
 505         path->g_mylmc     = ah->src_path_bits & 0x7f;
 506         path->rlid        = cpu_to_be16(ah->dlid);
 507         path->static_rate = mthca_get_rate(dev, ah->static_rate, port);
 508
 509         if (ah->ah_flags & IB_AH_GRH) {
 510                 if (ah->grh.sgid_index >= dev->limits.gid_table_len) {
 511                         mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
 512                                   ah->grh.sgid_index, dev->limits.gid_table_len-1);
 513                         return -1;
 514                 }
 515
 516                 path->g_mylmc   |= 1 << 7;
 517                 path->mgid_index = ah->grh.sgid_index;
 518                 path->hop_limit  = ah->grh.hop_limit;
 519                 path->sl_tclass_flowlabel =
 520                         cpu_to_be32((ah->sl << 28)                |
 521                                     (ah->grh.traffic_class << 20) |
 522                                     (ah->grh.flow_label));
 523                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 524         } else
 525                 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28);
 526
 527         return 0;
 528 }
 529
 530 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
 531 {
 532         struct mthca_dev *dev = to_mdev(ibqp->device);
 533         struct mthca_qp *qp = to_mqp(ibqp);
 534         enum ib_qp_state cur_state, new_state;
 535         struct mthca_mailbox *mailbox;
 536         struct mthca_qp_param *qp_param;
 537         struct mthca_qp_context *qp_context;
 538         u32 sqd_event = 0;
 539         u8 status;
 540         int err = -EINVAL;
 541
 542         mutex_lock(&qp->mutex);
 543
 544         if (attr_mask & IB_QP_CUR_STATE) {
 545                 cur_state = attr->cur_qp_state;
 546         } else {
 547                 spin_lock_irq(&qp->sq.lock);
 548                 spin_lock(&qp->rq.lock);
 549                 cur_state = qp->state;
 550                 spin_unlock(&qp->rq.lock);
 551                 spin_unlock_irq(&qp->sq.lock);
 552         }
 553
 554         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
 555
 556         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
 557                 mthca_dbg(dev, "Bad QP transition (transport %d) "
 558                           "%d->%d with attr 0x%08x\n",
 559                           qp->transport, cur_state, new_state,
 560                           attr_mask);
 561                 goto out;
 562         }
 563
 564         if ((attr_mask & IB_QP_PKEY_INDEX) &&
 565              attr->pkey_index >= dev->limits.pkey_table_len) {
 566                 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
 567                           attr->pkey_index, dev->limits.pkey_table_len-1);
 568                 goto out;
 569         }
 570
 571         if ((attr_mask & IB_QP_PORT) &&
 572             (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
 573                 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
 574                 goto out;
 575         }
 576
 577         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
 578             attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
 579                 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
 580                           attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
 581                 goto out;
 582         }
 583
 584         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
 585             attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
 586                 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
 587                           attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
 588                 goto out;
 589         }
 590
 591         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 592         if (IS_ERR(mailbox)) {
 593                 err = PTR_ERR(mailbox);
 594                 goto out;
 595         }
 596         qp_param = mailbox->buf;
 597         qp_context = &qp_param->context;
 598         memset(qp_param, 0, sizeof *qp_param);
 599
 600         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 601                                              (to_mthca_st(qp->transport) << 16));
 602         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 603         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 604                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 605         else {
 606                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 607                 switch (attr->path_mig_state) {
 608                 case IB_MIG_MIGRATED:
 609                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 610                         break;
 611                 case IB_MIG_REARM:
 612                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 613                         break;
 614                 case IB_MIG_ARMED:
 615                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 616                         break;
 617                 }
 618         }
 619
 620         /* leave tavor_sched_queue as 0 */
 621
 622         if (qp->transport == MLX || qp->transport == UD)
 623                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 624         else if (attr_mask & IB_QP_PATH_MTU) {
 625                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
 626                         mthca_dbg(dev, "path MTU (%u) is invalid\n",
 627                                   attr->path_mtu);
 628                         goto out_mailbox;
 629                 }
 630                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 631         }
 632
 633         if (mthca_is_memfree(dev)) {
 634                 if (qp->rq.max)
 635                         qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
 636                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
 637
 638                 if (qp->sq.max)
 639                         qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
 640                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
 641         }
 642
 643         /* leave arbel_sched_queue as 0 */
 644
 645         if (qp->ibqp.uobject)
 646                 qp_context->usr_page =
 647                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 648         else
 649                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 650         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 651         if (attr_mask & IB_QP_DEST_QPN) {
 652                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 653         }
 654
 655         if (qp->transport == MLX)
 656                 qp_context->pri_path.port_pkey |=
 657                         cpu_to_be32(qp->port << 24);
 658         else {
 659                 if (attr_mask & IB_QP_PORT) {
 660                         qp_context->pri_path.port_pkey |=
 661                                 cpu_to_be32(attr->port_num << 24);
 662                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 663                 }
 664         }
 665
 666         if (attr_mask & IB_QP_PKEY_INDEX) {
 667                 qp_context->pri_path.port_pkey |=
 668                         cpu_to_be32(attr->pkey_index);
 669                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 670         }
 671
 672         if (attr_mask & IB_QP_RNR_RETRY) {
 673                 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
 674                         attr->rnr_retry << 5;
 675                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
 676                                                         MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
 677         }
 678
 679         if (attr_mask & IB_QP_AV) {
 680                 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
 681                                    attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
 682                         goto out_mailbox;
 683
 684                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 685         }
 686
 687         if (attr_mask & IB_QP_TIMEOUT) {
 688                 qp_context->pri_path.ackto = attr->timeout << 3;
 689                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 690         }
 691
 692         if (attr_mask & IB_QP_ALT_PATH) {
 693                 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
 694                         mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
 695                                   attr->alt_pkey_index, dev->limits.pkey_table_len-1);
 696                         goto out_mailbox;
 697                 }
 698
 699                 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
 700                         mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
 701                                 attr->alt_port_num);
 702                         goto out_mailbox;
 703                 }
 704
 705                 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
 706                                    attr->alt_ah_attr.port_num))
 707                         goto out_mailbox;
 708
 709                 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
 710                                                               attr->alt_port_num << 24);
 711                 qp_context->alt_path.ackto = attr->alt_timeout << 3;
 712                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
 713         }
 714
 715         /* leave rdd as 0 */
 716         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 717         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 718         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 719         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 720                                              (MTHCA_FLIGHT_LIMIT << 24) |
 721                                              MTHCA_QP_BIT_SWE);
 722         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 723                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 724         if (attr_mask & IB_QP_RETRY_CNT) {
 725                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 726                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 727         }
 728
 729         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 730                 if (attr->max_rd_atomic) {
 731                         qp_context->params1 |=
 732                                 cpu_to_be32(MTHCA_QP_BIT_SRE |
 733                                             MTHCA_QP_BIT_SAE);
 734                         qp_context->params1 |=
 735                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 736                 }
 737                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 738         }
 739
 740         if (attr_mask & IB_QP_SQ_PSN)
 741                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 742         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 743
 744         if (mthca_is_memfree(dev)) {
 745                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 746                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 747         }
 748
 749         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 750                 if (attr->max_dest_rd_atomic)
 751                         qp_context->params2 |=
 752                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 753
 754                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 755         }
 756
 757         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
 758                 qp_context->params2      |= get_hw_access_flags(qp, attr, attr_mask);
 759                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 760                                                         MTHCA_QP_OPTPAR_RRE |
 761                                                         MTHCA_QP_OPTPAR_RAE);
 762         }
 763
 764         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 765
 766         if (ibqp->srq)
 767                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
 768
 769         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 770                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 771                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 772         }
 773         if (attr_mask & IB_QP_RQ_PSN)
 774                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 775
 776         qp_context->ra_buff_indx =
 777                 cpu_to_be32(dev->qp_table.rdb_base +
 778                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 779                              dev->qp_table.rdb_shift));
 780
 781         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 782
 783         if (mthca_is_memfree(dev))
 784                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 785
 786         if (attr_mask & IB_QP_QKEY) {
 787                 qp_context->qkey = cpu_to_be32(attr->qkey);
 788                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 789         }
 790
 791         if (ibqp->srq)
 792                 qp_context->srqn = cpu_to_be32(1 << 24 |
 793                                                to_msrq(ibqp->srq)->srqn);
 794
 795         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
 796             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY               &&
 797             attr->en_sqd_async_notify)
 798                 sqd_event = 1 << 31;
 799
 800         err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
 801                               mailbox, sqd_event, &status);
 802         if (err)
 803                 goto out_mailbox;
 804         if (status) {
 805                 mthca_warn(dev, "modify QP %d->%d returned status %02x.\n",
 806                            cur_state, new_state, status);
 807                 err = -EINVAL;
 808                 goto out_mailbox;
 809         }
 810
 811         qp->state = new_state;
 812         if (attr_mask & IB_QP_ACCESS_FLAGS)
 813                 qp->atomic_rd_en = attr->qp_access_flags;
 814         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 815                 qp->resp_depth = attr->max_dest_rd_atomic;
 816         if (attr_mask & IB_QP_PORT)
 817                 qp->port = attr->port_num;
 818         if (attr_mask & IB_QP_ALT_PATH)
 819                 qp->alt_port = attr->alt_port_num;
 820
 821         if (is_sqp(dev, qp))
 822                 store_attrs(to_msqp(qp), attr, attr_mask);
 823
 824         /*
 825          * If we moved QP0 to RTR, bring the IB link up; if we moved
 826          * QP0 to RESET or ERROR, bring the link back down.
 827          */
 828         if (is_qp0(dev, qp)) {
 829                 if (cur_state != IB_QPS_RTR &&
 830                     new_state == IB_QPS_RTR)
 831                         init_port(dev, qp->port);
 832
 833                 if (cur_state != IB_QPS_RESET &&
 834                     cur_state != IB_QPS_ERR &&
 835                     (new_state == IB_QPS_RESET ||
 836                      new_state == IB_QPS_ERR))
 837                         mthca_CLOSE_IB(dev, qp->port, &status);
 838         }
 839
 840         /*
 841          * If we moved a kernel QP to RESET, clean up all old CQ
 842          * entries and reinitialize the QP.
 843          */
 844         if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
 845                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn,
 846                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 847                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
 848                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
 849                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 850
 851                 mthca_wq_reset(&qp->sq);
 852                 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
 853
 854                 mthca_wq_reset(&qp->rq);
 855                 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
 856
 857                 if (mthca_is_memfree(dev)) {
 858                         *qp->sq.db = 0;
 859                         *qp->rq.db = 0;
 860                 }
 861         }
 862
 863 out_mailbox:
 864         mthca_free_mailbox(dev, mailbox);
 865
 866 out:
 867         mutex_unlock(&qp->mutex);
 868         return err;
 869 }
 870
 871 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
 872 {
 873         /*
 874          * Calculate the maximum size of WQE s/g segments, excluding
 875          * the next segment and other non-data segments.
 876          */
 877         int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
 878
 879         switch (qp->transport) {
 880         case MLX:
 881                 max_data_size -= 2 * sizeof (struct mthca_data_seg);
 882                 break;
 883
 884         case UD:
 885                 if (mthca_is_memfree(dev))
 886                         max_data_size -= sizeof (struct mthca_arbel_ud_seg);
 887                 else
 888                         max_data_size -= sizeof (struct mthca_tavor_ud_seg);
 889                 break;
 890
 891         default:
 892                 max_data_size -= sizeof (struct mthca_raddr_seg);
 893                 break;
 894         }
 895
 896         return max_data_size;
 897 }
 898
 899 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
 900 {
 901         /* We don't support inline data for kernel QPs (yet). */
 902         return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
 903 }
 904
 905 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
 906                                  struct mthca_pd *pd,
 907                                  struct mthca_qp *qp)
 908 {
 909         int max_data_size = mthca_max_data_size(dev, qp,
 910                                                 min(dev->limits.max_desc_sz,
 911                                                     1 << qp->sq.wqe_shift));
 912
 913         qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
 914
 915         qp->sq.max_gs = min_t(int, dev->limits.max_sg,
 916                               max_data_size / sizeof (struct mthca_data_seg));
 917         qp->rq.max_gs = min_t(int, dev->limits.max_sg,
 918                                (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
 919                                 sizeof (struct mthca_next_seg)) /
 920                                sizeof (struct mthca_data_seg));
 921 }
 922
 923 /*
 924  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 925  * rq.max_gs and sq.max_gs must all be assigned.
 926  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 927  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 928  * queue)
 929  */
 930 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 931                                struct mthca_pd *pd,
 932                                struct mthca_qp *qp)
 933 {
 934         int size;
 935         int err = -ENOMEM;
 936
 937         size = sizeof (struct mthca_next_seg) +
 938                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 939
 940         if (size > dev->limits.max_desc_sz)
 941                 return -EINVAL;
 942
 943         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 944              qp->rq.wqe_shift++)
 945                 ; /* nothing */
 946
 947         size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
 948         switch (qp->transport) {
 949         case MLX:
 950                 size += 2 * sizeof (struct mthca_data_seg);
 951                 break;
 952
 953         case UD:
 954                 size += mthca_is_memfree(dev) ?
 955                         sizeof (struct mthca_arbel_ud_seg) :
 956                         sizeof (struct mthca_tavor_ud_seg);
 957                 break;
 958
 959         case UC:
 960                 size += sizeof (struct mthca_raddr_seg);
 961                 break;
 962
 963         case RC:
 964                 size += sizeof (struct mthca_raddr_seg);
 965                 /*
 966                  * An atomic op will require an atomic segment, a
 967                  * remote address segment and one scatter entry.
 968                  */
 969                 size = max_t(int, size,
 970                              sizeof (struct mthca_atomic_seg) +
 971                              sizeof (struct mthca_raddr_seg) +
 972                              sizeof (struct mthca_data_seg));
 973                 break;
 974
 975         default:
 976                 break;
 977         }
 978
 979         /* Make sure that we have enough space for a bind request */
 980         size = max_t(int, size, sizeof (struct mthca_bind_seg));
 981
 982         size += sizeof (struct mthca_next_seg);
 983
 984         if (size > dev->limits.max_desc_sz)
 985                 return -EINVAL;
 986
 987         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
 988              qp->sq.wqe_shift++)
 989                 ; /* nothing */
 990
 991         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
 992                                     1 << qp->sq.wqe_shift);
 993
 994         /*
 995          * If this is a userspace QP, we don't actually have to
 996          * allocate anything.  All we need is to calculate the WQE
 997          * sizes and the send_wqe_offset, so we're done now.
 998          */
 999         if (pd->ibpd.uobject)
1000                 return 0;
1001
1002         size = PAGE_ALIGN(qp->send_wqe_offset +
1003                           (qp->sq.max << qp->sq.wqe_shift));
1004
1005         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1006                            GFP_KERNEL);
1007         if (!qp->wrid)
1008                 goto err_out;
1009
1010         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1011                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1012         if (err)
1013                 goto err_out;
1014
1015         return 0;
1016
1017 err_out:
1018         kfree(qp->wrid);
1019         return err;
1020 }
1021
1022 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1023                                struct mthca_qp *qp)
1024 {
1025         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1026                                        (qp->sq.max << qp->sq.wqe_shift)),
1027                        &qp->queue, qp->is_direct, &qp->mr);
1028         kfree(qp->wrid);
1029 }
1030
1031 static int mthca_map_memfree(struct mthca_dev *dev,
1032                              struct mthca_qp *qp)
1033 {
1034         int ret;
1035
1036         if (mthca_is_memfree(dev)) {
1037                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1038                 if (ret)
1039                         return ret;
1040
1041                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1042                 if (ret)
1043                         goto err_qpc;
1044
1045                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1046                                       qp->qpn << dev->qp_table.rdb_shift);
1047                 if (ret)
1048                         goto err_eqpc;
1049
1050         }
1051
1052         return 0;
1053
1054 err_eqpc:
1055         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1056
1057 err_qpc:
1058         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1059
1060         return ret;
1061 }
1062
1063 static void mthca_unmap_memfree(struct mthca_dev *dev,
1064                                 struct mthca_qp *qp)
1065 {
1066         mthca_table_put(dev, dev->qp_table.rdb_table,
1067                         qp->qpn << dev->qp_table.rdb_shift);
1068         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1069         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1070 }
1071
1072 static int mthca_alloc_memfree(struct mthca_dev *dev,
1073                                struct mthca_qp *qp)
1074 {
1075         int ret = 0;
1076
1077         if (mthca_is_memfree(dev)) {
1078                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1079                                                  qp->qpn, &qp->rq.db);
1080                 if (qp->rq.db_index < 0)
1081                         return ret;
1082
1083                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1084                                                  qp->qpn, &qp->sq.db);
1085                 if (qp->sq.db_index < 0)
1086                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1087         }
1088
1089         return ret;
1090 }
1091
1092 static void mthca_free_memfree(struct mthca_dev *dev,
1093                                struct mthca_qp *qp)
1094 {
1095         if (mthca_is_memfree(dev)) {
1096                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1097                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1098         }
1099 }
1100
1101 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1102                                  struct mthca_pd *pd,
1103                                  struct mthca_cq *send_cq,
1104                                  struct mthca_cq *recv_cq,
1105                                  enum ib_sig_type send_policy,
1106                                  struct mthca_qp *qp)
1107 {
1108         int ret;
1109         int i;
1110
1111         qp->refcount = 1;
1112         init_waitqueue_head(&qp->wait);
1113         mutex_init(&qp->mutex);
1114         qp->state        = IB_QPS_RESET;
1115         qp->atomic_rd_en = 0;
1116         qp->resp_depth   = 0;
1117         qp->sq_policy    = send_policy;
1118         mthca_wq_reset(&qp->sq);
1119         mthca_wq_reset(&qp->rq);
1120
1121         spin_lock_init(&qp->sq.lock);
1122         spin_lock_init(&qp->rq.lock);
1123
1124         ret = mthca_map_memfree(dev, qp);
1125         if (ret)
1126                 return ret;
1127
1128         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1129         if (ret) {
1130                 mthca_unmap_memfree(dev, qp);
1131                 return ret;
1132         }
1133
1134         mthca_adjust_qp_caps(dev, pd, qp);
1135
1136         /*
1137          * If this is a userspace QP, we're done now.  The doorbells
1138          * will be allocated and buffers will be initialized in
1139          * userspace.
1140          */
1141         if (pd->ibpd.uobject)
1142                 return 0;
1143
1144         ret = mthca_alloc_memfree(dev, qp);
1145         if (ret) {
1146                 mthca_free_wqe_buf(dev, qp);
1147                 mthca_unmap_memfree(dev, qp);
1148                 return ret;
1149         }
1150
1151         if (mthca_is_memfree(dev)) {
1152                 struct mthca_next_seg *next;
1153                 struct mthca_data_seg *scatter;
1154                 int size = (sizeof (struct mthca_next_seg) +
1155                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1156
1157                 for (i = 0; i < qp->rq.max; ++i) {
1158                         next = get_recv_wqe(qp, i);
1159                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1160                                                    qp->rq.wqe_shift);
1161                         next->ee_nds = cpu_to_be32(size);
1162
1163                         for (scatter = (void *) (next + 1);
1164                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1165                              ++scatter)
1166                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1167                 }
1168
1169                 for (i = 0; i < qp->sq.max; ++i) {
1170                         next = get_send_wqe(qp, i);
1171                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1172                                                     qp->sq.wqe_shift) +
1173                                                    qp->send_wqe_offset);
1174                 }
1175         }
1176
1177         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1178         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1179
1180         return 0;
1181 }
1182
1183 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1184                              struct mthca_pd *pd, struct mthca_qp *qp)
1185 {
1186         int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1187
1188         /* Sanity check QP size before proceeding */
1189         if (cap->max_send_wr     > dev->limits.max_wqes ||
1190             cap->max_recv_wr     > dev->limits.max_wqes ||
1191             cap->max_send_sge    > dev->limits.max_sg   ||
1192             cap->max_recv_sge    > dev->limits.max_sg   ||
1193             cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1194                 return -EINVAL;
1195
1196         /*
1197          * For MLX transport we need 2 extra S/G entries:
1198          * one for the header and one for the checksum at the end
1199          */
1200         if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg)
1201                 return -EINVAL;
1202
1203         if (mthca_is_memfree(dev)) {
1204                 qp->rq.max = cap->max_recv_wr ?
1205                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1206                 qp->sq.max = cap->max_send_wr ?
1207                         roundup_pow_of_two(cap->max_send_wr) : 0;
1208         } else {
1209                 qp->rq.max = cap->max_recv_wr;
1210                 qp->sq.max = cap->max_send_wr;
1211         }
1212
1213         qp->rq.max_gs = cap->max_recv_sge;
1214         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1215                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1216                                     MTHCA_INLINE_CHUNK_SIZE) /
1217                               sizeof (struct mthca_data_seg));
1218
1219         return 0;
1220 }
1221
1222 int mthca_alloc_qp(struct mthca_dev *dev,
1223                    struct mthca_pd *pd,
1224                    struct mthca_cq *send_cq,
1225                    struct mthca_cq *recv_cq,
1226                    enum ib_qp_type type,
1227                    enum ib_sig_type send_policy,
1228                    struct ib_qp_cap *cap,
1229                    struct mthca_qp *qp)
1230 {
1231         int err;
1232
1233         switch (type) {
1234         case IB_QPT_RC: qp->transport = RC; break;
1235         case IB_QPT_UC: qp->transport = UC; break;
1236         case IB_QPT_UD: qp->transport = UD; break;
1237         default: return -EINVAL;
1238         }
1239
1240         err = mthca_set_qp_size(dev, cap, pd, qp);
1241         if (err)
1242                 return err;
1243
1244         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1245         if (qp->qpn == -1)
1246                 return -ENOMEM;
1247
1248         /* initialize port to zero for error-catching. */
1249         qp->port = 0;
1250
1251         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1252                                     send_policy, qp);
1253         if (err) {
1254                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1255                 return err;
1256         }
1257
1258         spin_lock_irq(&dev->qp_table.lock);
1259         mthca_array_set(&dev->qp_table.qp,
1260                         qp->qpn & (dev->limits.num_qps - 1), qp);
1261         spin_unlock_irq(&dev->qp_table.lock);
1262
1263         return 0;
1264 }
1265
1266 static void mthca_lock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1267 {
1268         if (send_cq == recv_cq)
1269                 spin_lock_irq(&send_cq->lock);
1270         else if (send_cq->cqn < recv_cq->cqn) {
1271                 spin_lock_irq(&send_cq->lock);
1272                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1273         } else {
1274                 spin_lock_irq(&recv_cq->lock);
1275                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1276         }
1277 }
1278
1279 static void mthca_unlock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1280 {
1281         if (send_cq == recv_cq)
1282                 spin_unlock_irq(&send_cq->lock);
1283         else if (send_cq->cqn < recv_cq->cqn) {
1284                 spin_unlock(&recv_cq->lock);
1285                 spin_unlock_irq(&send_cq->lock);
1286         } else {
1287                 spin_unlock(&send_cq->lock);
1288                 spin_unlock_irq(&recv_cq->lock);
1289         }
1290 }
1291
1292 int mthca_alloc_sqp(struct mthca_dev *dev,
1293                     struct mthca_pd *pd,
1294                     struct mthca_cq *send_cq,
1295                     struct mthca_cq *recv_cq,
1296                     enum ib_sig_type send_policy,
1297                     struct ib_qp_cap *cap,
1298                     int qpn,
1299                     int port,
1300                     struct mthca_sqp *sqp)
1301 {
1302         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1303         int err;
1304
1305         sqp->qp.transport = MLX;
1306         err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1307         if (err)
1308                 return err;
1309
1310         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1311         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1312                                              &sqp->header_dma, GFP_KERNEL);
1313         if (!sqp->header_buf)
1314                 return -ENOMEM;
1315
1316         spin_lock_irq(&dev->qp_table.lock);
1317         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1318                 err = -EBUSY;
1319         else
1320                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1321         spin_unlock_irq(&dev->qp_table.lock);
1322
1323         if (err)
1324                 goto err_out;
1325
1326         sqp->qp.port      = port;
1327         sqp->qp.qpn       = mqpn;
1328         sqp->qp.transport = MLX;
1329
1330         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1331                                     send_policy, &sqp->qp);
1332         if (err)
1333                 goto err_out_free;
1334
1335         atomic_inc(&pd->sqp_count);
1336
1337         return 0;
1338
1339  err_out_free:
1340         /*
1341          * Lock CQs here, so that CQ polling code can do QP lookup
1342          * without taking a lock.
1343          */
1344         mthca_lock_cqs(send_cq, recv_cq);
1345
1346         spin_lock(&dev->qp_table.lock);
1347         mthca_array_clear(&dev->qp_table.qp, mqpn);
1348         spin_unlock(&dev->qp_table.lock);
1349
1350         mthca_unlock_cqs(send_cq, recv_cq);
1351
1352  err_out:
1353         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1354                           sqp->header_buf, sqp->header_dma);
1355
1356         return err;
1357 }
1358
1359 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp)
1360 {
1361         int c;
1362
1363         spin_lock_irq(&dev->qp_table.lock);
1364         c = qp->refcount;
1365         spin_unlock_irq(&dev->qp_table.lock);
1366
1367         return c;
1368 }
1369
1370 void mthca_free_qp(struct mthca_dev *dev,
1371                    struct mthca_qp *qp)
1372 {
1373         u8 status;
1374         struct mthca_cq *send_cq;
1375         struct mthca_cq *recv_cq;
1376
1377         send_cq = to_mcq(qp->ibqp.send_cq);
1378         recv_cq = to_mcq(qp->ibqp.recv_cq);
1379
1380         /*
1381          * Lock CQs here, so that CQ polling code can do QP lookup
1382          * without taking a lock.
1383          */
1384         mthca_lock_cqs(send_cq, recv_cq);
1385
1386         spin_lock(&dev->qp_table.lock);
1387         mthca_array_clear(&dev->qp_table.qp,
1388                           qp->qpn & (dev->limits.num_qps - 1));
1389         --qp->refcount;
1390         spin_unlock(&dev->qp_table.lock);
1391
1392         mthca_unlock_cqs(send_cq, recv_cq);
1393
1394         wait_event(qp->wait, !get_qp_refcount(dev, qp));
1395
1396         if (qp->state != IB_QPS_RESET)
1397                 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1398                                 NULL, 0, &status);
1399
1400         /*
1401          * If this is a userspace QP, the buffers, MR, CQs and so on
1402          * will be cleaned up in userspace, so all we have to do is
1403          * unref the mem-free tables and free the QPN in our table.
1404          */
1405         if (!qp->ibqp.uobject) {
1406                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn,
1407                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1408                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1409                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
1410                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1411
1412                 mthca_free_memfree(dev, qp);
1413                 mthca_free_wqe_buf(dev, qp);
1414         }
1415
1416         mthca_unmap_memfree(dev, qp);
1417
1418         if (is_sqp(dev, qp)) {
1419                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1420                 dma_free_coherent(&dev->pdev->dev,
1421                                   to_msqp(qp)->header_buf_size,
1422                                   to_msqp(qp)->header_buf,
1423                                   to_msqp(qp)->header_dma);
1424         } else
1425                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1426 }
1427
1428 /* Create UD header for an MLX send and build a data segment for it */
1429 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1430                             int ind, struct ib_send_wr *wr,
1431                             struct mthca_mlx_seg *mlx,
1432                             struct mthca_data_seg *data)
1433 {
1434         int header_size;
1435         int err;
1436         u16 pkey;
1437
1438         ib_ud_header_init(256, /* assume a MAD */
1439                           mthca_ah_grh_present(to_mah(wr->wr.ud.ah)),
1440                           &sqp->ud_header);
1441
1442         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1443         if (err)
1444                 return err;
1445         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1446         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1447                                   (sqp->ud_header.lrh.destination_lid ==
1448                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1449                                   (sqp->ud_header.lrh.service_level << 8));
1450         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1451         mlx->vcrc = 0;
1452
1453         switch (wr->opcode) {
1454         case IB_WR_SEND:
1455                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1456                 sqp->ud_header.immediate_present = 0;
1457                 break;
1458         case IB_WR_SEND_WITH_IMM:
1459                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1460                 sqp->ud_header.immediate_present = 1;
1461                 sqp->ud_header.immediate_data = wr->imm_data;
1462                 break;
1463         default:
1464                 return -EINVAL;
1465         }
1466
1467         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1468         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1469                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1470         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1471         if (!sqp->qp.ibqp.qp_num)
1472                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1473                                    sqp->pkey_index, &pkey);
1474         else
1475                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1476                                    wr->wr.ud.pkey_index, &pkey);
1477         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1478         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1479         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1480         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1481                                                sqp->qkey : wr->wr.ud.remote_qkey);
1482         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1483
1484         header_size = ib_ud_header_pack(&sqp->ud_header,
1485                                         sqp->header_buf +
1486                                         ind * MTHCA_UD_HEADER_SIZE);
1487
1488         data->byte_count = cpu_to_be32(header_size);
1489         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1490         data->addr       = cpu_to_be64(sqp->header_dma +
1491                                        ind * MTHCA_UD_HEADER_SIZE);
1492
1493         return 0;
1494 }
1495
1496 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1497                                     struct ib_cq *ib_cq)
1498 {
1499         unsigned cur;
1500         struct mthca_cq *cq;
1501
1502         cur = wq->head - wq->tail;
1503         if (likely(cur + nreq < wq->max))
1504                 return 0;
1505
1506         cq = to_mcq(ib_cq);
1507         spin_lock(&cq->lock);
1508         cur = wq->head - wq->tail;
1509         spin_unlock(&cq->lock);
1510
1511         return cur + nreq >= wq->max;
1512 }
1513
1514 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1515                           struct ib_send_wr **bad_wr)
1516 {
1517         struct mthca_dev *dev = to_mdev(ibqp->device);
1518         struct mthca_qp *qp = to_mqp(ibqp);
1519         void *wqe;
1520         void *prev_wqe;
1521         unsigned long flags;
1522         int err = 0;
1523         int nreq;
1524         int i;
1525         int size;
1526         int size0 = 0;
1527         u32 f0;
1528         int ind;
1529         u8 op0 = 0;
1530
1531         spin_lock_irqsave(&qp->sq.lock, flags);
1532
1533         /* XXX check that state is OK to post send */
1534
1535         ind = qp->sq.next_ind;
1536
1537         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1538                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1539                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1540                                         " %d max, %d nreq)\n", qp->qpn,
1541                                         qp->sq.head, qp->sq.tail,
1542                                         qp->sq.max, nreq);
1543                         err = -ENOMEM;
1544                         *bad_wr = wr;
1545                         goto out;
1546                 }
1547
1548                 wqe = get_send_wqe(qp, ind);
1549                 prev_wqe = qp->sq.last;
1550                 qp->sq.last = wqe;
1551
1552                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1553                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1554                 ((struct mthca_next_seg *) wqe)->flags =
1555                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1556                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1557                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1558                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1559                         cpu_to_be32(1);
1560                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1561                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1562                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1563
1564                 wqe += sizeof (struct mthca_next_seg);
1565                 size = sizeof (struct mthca_next_seg) / 16;
1566
1567                 switch (qp->transport) {
1568                 case RC:
1569                         switch (wr->opcode) {
1570                         case IB_WR_ATOMIC_CMP_AND_SWP:
1571                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1572                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1573                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1574                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1575                                         cpu_to_be32(wr->wr.atomic.rkey);
1576                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1577
1578                                 wqe += sizeof (struct mthca_raddr_seg);
1579
1580                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1581                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1582                                                 cpu_to_be64(wr->wr.atomic.swap);
1583                                         ((struct mthca_atomic_seg *) wqe)->compare =
1584                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1585                                 } else {
1586                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1587                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1588                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1589                                 }
1590
1591                                 wqe += sizeof (struct mthca_atomic_seg);
1592                                 size += (sizeof (struct mthca_raddr_seg) +
1593                                          sizeof (struct mthca_atomic_seg)) / 16;
1594                                 break;
1595
1596                         case IB_WR_RDMA_WRITE:
1597                         case IB_WR_RDMA_WRITE_WITH_IMM:
1598                         case IB_WR_RDMA_READ:
1599                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1600                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1601                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1602                                         cpu_to_be32(wr->wr.rdma.rkey);
1603                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1604                                 wqe += sizeof (struct mthca_raddr_seg);
1605                                 size += sizeof (struct mthca_raddr_seg) / 16;
1606                                 break;
1607
1608                         default:
1609                                 /* No extra segments required for sends */
1610                                 break;
1611                         }
1612
1613                         break;
1614
1615                 case UC:
1616                         switch (wr->opcode) {
1617                         case IB_WR_RDMA_WRITE:
1618                         case IB_WR_RDMA_WRITE_WITH_IMM:
1619                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1620                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1621                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1622                                         cpu_to_be32(wr->wr.rdma.rkey);
1623                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1624                                 wqe += sizeof (struct mthca_raddr_seg);
1625                                 size += sizeof (struct mthca_raddr_seg) / 16;
1626                                 break;
1627
1628                         default:
1629                                 /* No extra segments required for sends */
1630                                 break;
1631                         }
1632
1633                         break;
1634
1635                 case UD:
1636                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1637                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1638                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1639                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1640                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1641                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1642                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1643                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1644
1645                         wqe += sizeof (struct mthca_tavor_ud_seg);
1646                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1647                         break;
1648
1649                 case MLX:
1650                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1651                                                wqe - sizeof (struct mthca_next_seg),
1652                                                wqe);
1653                         if (err) {
1654                                 *bad_wr = wr;
1655                                 goto out;
1656                         }
1657                         wqe += sizeof (struct mthca_data_seg);
1658                         size += sizeof (struct mthca_data_seg) / 16;
1659                         break;
1660                 }
1661
1662                 if (wr->num_sge > qp->sq.max_gs) {
1663                         mthca_err(dev, "too many gathers\n");
1664                         err = -EINVAL;
1665                         *bad_wr = wr;
1666                         goto out;
1667                 }
1668
1669                 for (i = 0; i < wr->num_sge; ++i) {
1670                         ((struct mthca_data_seg *) wqe)->byte_count =
1671                                 cpu_to_be32(wr->sg_list[i].length);
1672                         ((struct mthca_data_seg *) wqe)->lkey =
1673                                 cpu_to_be32(wr->sg_list[i].lkey);
1674                         ((struct mthca_data_seg *) wqe)->addr =
1675                                 cpu_to_be64(wr->sg_list[i].addr);
1676                         wqe += sizeof (struct mthca_data_seg);
1677                         size += sizeof (struct mthca_data_seg) / 16;
1678                 }
1679
1680                 /* Add one more inline data segment for ICRC */
1681                 if (qp->transport == MLX) {
1682                         ((struct mthca_data_seg *) wqe)->byte_count =
1683                                 cpu_to_be32((1 << 31) | 4);
1684                         ((u32 *) wqe)[1] = 0;
1685                         wqe += sizeof (struct mthca_data_seg);
1686                         size += sizeof (struct mthca_data_seg) / 16;
1687                 }
1688
1689                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1690
1691                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1692                         mthca_err(dev, "opcode invalid\n");
1693                         err = -EINVAL;
1694                         *bad_wr = wr;
1695                         goto out;
1696                 }
1697
1698                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1699                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1700                                      qp->send_wqe_offset) |
1701                                     mthca_opcode[wr->opcode]);
1702                 wmb();
1703                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1704                         cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size |
1705                                     ((wr->send_flags & IB_SEND_FENCE) ?
1706                                     MTHCA_NEXT_FENCE : 0));
1707
1708                 if (!size0) {
1709                         size0 = size;
1710                         op0   = mthca_opcode[wr->opcode];
1711                         f0    = wr->send_flags & IB_SEND_FENCE ?
1712                                 MTHCA_SEND_DOORBELL_FENCE : 0;
1713                 }
1714
1715                 ++ind;
1716                 if (unlikely(ind >= qp->sq.max))
1717                         ind -= qp->sq.max;
1718         }
1719
1720 out:
1721         if (likely(nreq)) {
1722                 __be32 doorbell[2];
1723
1724                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1725                                            qp->send_wqe_offset) | f0 | op0);
1726                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1727
1728                 wmb();
1729
1730                 mthca_write64(doorbell,
1731                               dev->kar + MTHCA_SEND_DOORBELL,
1732                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1733         }
1734
1735         qp->sq.next_ind = ind;
1736         qp->sq.head    += nreq;
1737
1738         spin_unlock_irqrestore(&qp->sq.lock, flags);
1739         return err;
1740 }
1741
1742 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1743                              struct ib_recv_wr **bad_wr)
1744 {
1745         struct mthca_dev *dev = to_mdev(ibqp->device);
1746         struct mthca_qp *qp = to_mqp(ibqp);
1747         __be32 doorbell[2];
1748         unsigned long flags;
1749         int err = 0;
1750         int nreq;
1751         int i;
1752         int size;
1753         int size0 = 0;
1754         int ind;
1755         void *wqe;
1756         void *prev_wqe;
1757
1758         spin_lock_irqsave(&qp->rq.lock, flags);
1759
1760         /* XXX check that state is OK to post receive */
1761
1762         ind = qp->rq.next_ind;
1763
1764         for (nreq = 0; wr; wr = wr->next) {
1765                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1766                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1767                                         " %d max, %d nreq)\n", qp->qpn,
1768                                         qp->rq.head, qp->rq.tail,
1769                                         qp->rq.max, nreq);
1770                         err = -ENOMEM;
1771                         *bad_wr = wr;
1772                         goto out;
1773                 }
1774
1775                 wqe = get_recv_wqe(qp, ind);
1776                 prev_wqe = qp->rq.last;
1777                 qp->rq.last = wqe;
1778
1779                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1780                 ((struct mthca_next_seg *) wqe)->ee_nds =
1781                         cpu_to_be32(MTHCA_NEXT_DBD);
1782                 ((struct mthca_next_seg *) wqe)->flags = 0;
1783
1784                 wqe += sizeof (struct mthca_next_seg);
1785                 size = sizeof (struct mthca_next_seg) / 16;
1786
1787                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1788                         err = -EINVAL;
1789                         *bad_wr = wr;
1790                         goto out;
1791                 }
1792
1793                 for (i = 0; i < wr->num_sge; ++i) {
1794                         ((struct mthca_data_seg *) wqe)->byte_count =
1795                                 cpu_to_be32(wr->sg_list[i].length);
1796                         ((struct mthca_data_seg *) wqe)->lkey =
1797                                 cpu_to_be32(wr->sg_list[i].lkey);
1798                         ((struct mthca_data_seg *) wqe)->addr =
1799                                 cpu_to_be64(wr->sg_list[i].addr);
1800                         wqe += sizeof (struct mthca_data_seg);
1801                         size += sizeof (struct mthca_data_seg) / 16;
1802                 }
1803
1804                 qp->wrid[ind] = wr->wr_id;
1805
1806                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1807                         cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1808                 wmb();
1809                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1810                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1811
1812                 if (!size0)
1813                         size0 = size;
1814
1815                 ++ind;
1816                 if (unlikely(ind >= qp->rq.max))
1817                         ind -= qp->rq.max;
1818
1819                 ++nreq;
1820                 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1821                         nreq = 0;
1822
1823                         doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1824                         doorbell[1] = cpu_to_be32(qp->qpn << 8);
1825
1826                         wmb();
1827
1828                         mthca_write64(doorbell,
1829                                       dev->kar + MTHCA_RECEIVE_DOORBELL,
1830                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1831
1832                         qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1833                         size0 = 0;
1834                 }
1835         }
1836
1837 out:
1838         if (likely(nreq)) {
1839                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1840                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1841
1842                 wmb();
1843
1844                 mthca_write64(doorbell,
1845                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1846                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1847         }
1848
1849         qp->rq.next_ind = ind;
1850         qp->rq.head    += nreq;
1851
1852         spin_unlock_irqrestore(&qp->rq.lock, flags);
1853         return err;
1854 }
1855
1856 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1857                           struct ib_send_wr **bad_wr)
1858 {
1859         struct mthca_dev *dev = to_mdev(ibqp->device);
1860         struct mthca_qp *qp = to_mqp(ibqp);
1861         __be32 doorbell[2];
1862         void *wqe;
1863         void *prev_wqe;
1864         unsigned long flags;
1865         int err = 0;
1866         int nreq;
1867         int i;
1868         int size;
1869         int size0 = 0;
1870         u32 f0;
1871         int ind;
1872         u8 op0 = 0;
1873
1874         spin_lock_irqsave(&qp->sq.lock, flags);
1875
1876         /* XXX check that state is OK to post send */
1877
1878         ind = qp->sq.head & (qp->sq.max - 1);
1879
1880         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1881                 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1882                         nreq = 0;
1883
1884                         doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1885                                                   ((qp->sq.head & 0xffff) << 8) |
1886                                                   f0 | op0);
1887                         doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1888
1889                         qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1890                         size0 = 0;
1891
1892                         /*
1893                          * Make sure that descriptors are written before
1894                          * doorbell record.
1895                          */
1896                         wmb();
1897                         *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1898
1899                         /*
1900                          * Make sure doorbell record is written before we
1901                          * write MMIO send doorbell.
1902                          */
1903                         wmb();
1904                         mthca_write64(doorbell,
1905                                       dev->kar + MTHCA_SEND_DOORBELL,
1906                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1907                 }
1908
1909                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1910                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1911                                         " %d max, %d nreq)\n", qp->qpn,
1912                                         qp->sq.head, qp->sq.tail,
1913                                         qp->sq.max, nreq);
1914                         err = -ENOMEM;
1915                         *bad_wr = wr;
1916                         goto out;
1917                 }
1918
1919                 wqe = get_send_wqe(qp, ind);
1920                 prev_wqe = qp->sq.last;
1921                 qp->sq.last = wqe;
1922
1923                 ((struct mthca_next_seg *) wqe)->flags =
1924                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1925                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1926                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1927                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1928                         cpu_to_be32(1);
1929                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1930                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1931                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1932
1933                 wqe += sizeof (struct mthca_next_seg);
1934                 size = sizeof (struct mthca_next_seg) / 16;
1935
1936                 switch (qp->transport) {
1937                 case RC:
1938                         switch (wr->opcode) {
1939                         case IB_WR_ATOMIC_CMP_AND_SWP:
1940                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1941                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1942                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1943                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1944                                         cpu_to_be32(wr->wr.atomic.rkey);
1945                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1946
1947                                 wqe += sizeof (struct mthca_raddr_seg);
1948
1949                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1950                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1951                                                 cpu_to_be64(wr->wr.atomic.swap);
1952                                         ((struct mthca_atomic_seg *) wqe)->compare =
1953                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1954                                 } else {
1955                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1956                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1957                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1958                                 }
1959
1960                                 wqe += sizeof (struct mthca_atomic_seg);
1961                                 size += (sizeof (struct mthca_raddr_seg) +
1962                                          sizeof (struct mthca_atomic_seg)) / 16;
1963                                 break;
1964
1965                         case IB_WR_RDMA_READ:
1966                         case IB_WR_RDMA_WRITE:
1967                         case IB_WR_RDMA_WRITE_WITH_IMM:
1968                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1969                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1970                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1971                                         cpu_to_be32(wr->wr.rdma.rkey);
1972                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1973                                 wqe += sizeof (struct mthca_raddr_seg);
1974                                 size += sizeof (struct mthca_raddr_seg) / 16;
1975                                 break;
1976
1977                         default:
1978                                 /* No extra segments required for sends */
1979                                 break;
1980                         }
1981
1982                         break;
1983
1984                 case UC:
1985                         switch (wr->opcode) {
1986                         case IB_WR_RDMA_WRITE:
1987                         case IB_WR_RDMA_WRITE_WITH_IMM:
1988                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1989                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1990                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1991                                         cpu_to_be32(wr->wr.rdma.rkey);
1992                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1993                                 wqe += sizeof (struct mthca_raddr_seg);
1994                                 size += sizeof (struct mthca_raddr_seg) / 16;
1995                                 break;
1996
1997                         default:
1998                                 /* No extra segments required for sends */
1999                                 break;
2000                         }
2001
2002                         break;
2003
2004                 case UD:
2005                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
2006                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
2007                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
2008                                 cpu_to_be32(wr->wr.ud.remote_qpn);
2009                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
2010                                 cpu_to_be32(wr->wr.ud.remote_qkey);
2011
2012                         wqe += sizeof (struct mthca_arbel_ud_seg);
2013                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
2014                         break;
2015
2016                 case MLX:
2017                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
2018                                                wqe - sizeof (struct mthca_next_seg),
2019                                                wqe);
2020                         if (err) {
2021                                 *bad_wr = wr;
2022                                 goto out;
2023                         }
2024                         wqe += sizeof (struct mthca_data_seg);
2025                         size += sizeof (struct mthca_data_seg) / 16;
2026                         break;
2027                 }
2028
2029                 if (wr->num_sge > qp->sq.max_gs) {
2030                         mthca_err(dev, "too many gathers\n");
2031                         err = -EINVAL;
2032                         *bad_wr = wr;
2033                         goto out;
2034                 }
2035
2036                 for (i = 0; i < wr->num_sge; ++i) {
2037                         ((struct mthca_data_seg *) wqe)->byte_count =
2038                                 cpu_to_be32(wr->sg_list[i].length);
2039                         ((struct mthca_data_seg *) wqe)->lkey =
2040                                 cpu_to_be32(wr->sg_list[i].lkey);
2041                         ((struct mthca_data_seg *) wqe)->addr =
2042                                 cpu_to_be64(wr->sg_list[i].addr);
2043                         wqe += sizeof (struct mthca_data_seg);
2044                         size += sizeof (struct mthca_data_seg) / 16;
2045                 }
2046
2047                 /* Add one more inline data segment for ICRC */
2048                 if (qp->transport == MLX) {
2049                         ((struct mthca_data_seg *) wqe)->byte_count =
2050                                 cpu_to_be32((1 << 31) | 4);
2051                         ((u32 *) wqe)[1] = 0;
2052                         wqe += sizeof (struct mthca_data_seg);
2053                         size += sizeof (struct mthca_data_seg) / 16;
2054                 }
2055
2056                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2057
2058                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2059                         mthca_err(dev, "opcode invalid\n");
2060                         err = -EINVAL;
2061                         *bad_wr = wr;
2062                         goto out;
2063                 }
2064
2065                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2066                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
2067                                      qp->send_wqe_offset) |
2068                                     mthca_opcode[wr->opcode]);
2069                 wmb();
2070                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2071                         cpu_to_be32(MTHCA_NEXT_DBD | size |
2072                                     ((wr->send_flags & IB_SEND_FENCE) ?
2073                                      MTHCA_NEXT_FENCE : 0));
2074
2075                 if (!size0) {
2076                         size0 = size;
2077                         op0   = mthca_opcode[wr->opcode];
2078                         f0    = wr->send_flags & IB_SEND_FENCE ?
2079                                 MTHCA_SEND_DOORBELL_FENCE : 0;
2080                 }
2081
2082                 ++ind;
2083                 if (unlikely(ind >= qp->sq.max))
2084                         ind -= qp->sq.max;
2085         }
2086
2087 out:
2088         if (likely(nreq)) {
2089                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
2090                                           ((qp->sq.head & 0xffff) << 8) |
2091                                           f0 | op0);
2092                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2093
2094                 qp->sq.head += nreq;
2095
2096                 /*
2097                  * Make sure that descriptors are written before
2098                  * doorbell record.
2099                  */
2100                 wmb();
2101                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2102
2103                 /*
2104                  * Make sure doorbell record is written before we
2105                  * write MMIO send doorbell.
2106                  */
2107                 wmb();
2108                 mthca_write64(doorbell,
2109                               dev->kar + MTHCA_SEND_DOORBELL,
2110                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2111         }
2112
2113         spin_unlock_irqrestore(&qp->sq.lock, flags);
2114         return err;
2115 }
2116
2117 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2118                              struct ib_recv_wr **bad_wr)
2119 {
2120         struct mthca_dev *dev = to_mdev(ibqp->device);
2121         struct mthca_qp *qp = to_mqp(ibqp);
2122         unsigned long flags;
2123         int err = 0;
2124         int nreq;
2125         int ind;
2126         int i;
2127         void *wqe;
2128
2129         spin_lock_irqsave(&qp->rq.lock, flags);
2130
2131         /* XXX check that state is OK to post receive */
2132
2133         ind = qp->rq.head & (qp->rq.max - 1);
2134
2135         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2136                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2137                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2138                                         " %d max, %d nreq)\n", qp->qpn,
2139                                         qp->rq.head, qp->rq.tail,
2140                                         qp->rq.max, nreq);
2141                         err = -ENOMEM;
2142                         *bad_wr = wr;
2143                         goto out;
2144                 }
2145
2146                 wqe = get_recv_wqe(qp, ind);
2147
2148                 ((struct mthca_next_seg *) wqe)->flags = 0;
2149
2150                 wqe += sizeof (struct mthca_next_seg);
2151
2152                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2153                         err = -EINVAL;
2154                         *bad_wr = wr;
2155                         goto out;
2156                 }
2157
2158                 for (i = 0; i < wr->num_sge; ++i) {
2159                         ((struct mthca_data_seg *) wqe)->byte_count =
2160                                 cpu_to_be32(wr->sg_list[i].length);
2161                         ((struct mthca_data_seg *) wqe)->lkey =
2162                                 cpu_to_be32(wr->sg_list[i].lkey);
2163                         ((struct mthca_data_seg *) wqe)->addr =
2164                                 cpu_to_be64(wr->sg_list[i].addr);
2165                         wqe += sizeof (struct mthca_data_seg);
2166                 }
2167
2168                 if (i < qp->rq.max_gs) {
2169                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2170                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2171                         ((struct mthca_data_seg *) wqe)->addr = 0;
2172                 }
2173
2174                 qp->wrid[ind] = wr->wr_id;
2175
2176                 ++ind;
2177                 if (unlikely(ind >= qp->rq.max))
2178                         ind -= qp->rq.max;
2179         }
2180 out:
2181         if (likely(nreq)) {
2182                 qp->rq.head += nreq;
2183
2184                 /*
2185                  * Make sure that descriptors are written before
2186                  * doorbell record.
2187                  */
2188                 wmb();
2189                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2190         }
2191
2192         spin_unlock_irqrestore(&qp->rq.lock, flags);
2193         return err;
2194 }
2195
2196 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2197                         int index, int *dbd, __be32 *new_wqe)
2198 {
2199         struct mthca_next_seg *next;
2200
2201         /*
2202          * For SRQs, all WQEs generate a CQE, so we're always at the
2203          * end of the doorbell chain.
2204          */
2205         if (qp->ibqp.srq) {
2206                 *new_wqe = 0;
2207                 return;
2208         }
2209
2210         if (is_send)
2211                 next = get_send_wqe(qp, index);
2212         else
2213                 next = get_recv_wqe(qp, index);
2214
2215         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2216         if (next->ee_nds & cpu_to_be32(0x3f))
2217                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2218                         (next->ee_nds & cpu_to_be32(0x3f));
2219         else
2220                 *new_wqe = 0;
2221 }
2222
2223 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2224 {
2225         int err;
2226         u8 status;
2227         int i;
2228
2229         spin_lock_init(&dev->qp_table.lock);
2230
2231         /*
2232          * We reserve 2 extra QPs per port for the special QPs.  The
2233          * special QP for port 1 has to be even, so round up.
2234          */
2235         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2236         err = mthca_alloc_init(&dev->qp_table.alloc,
2237                                dev->limits.num_qps,
2238                                (1 << 24) - 1,
2239                                dev->qp_table.sqp_start +
2240                                MTHCA_MAX_PORTS * 2);
2241         if (err)
2242                 return err;
2243
2244         err = mthca_array_init(&dev->qp_table.qp,
2245                                dev->limits.num_qps);
2246         if (err) {
2247                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2248                 return err;
2249         }
2250
2251         for (i = 0; i < 2; ++i) {
2252                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2253                                             dev->qp_table.sqp_start + i * 2,
2254                                             &status);
2255                 if (err)
2256                         goto err_out;
2257                 if (status) {
2258                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2259                                    "status %02x, aborting.\n",
2260                                    status);
2261                         err = -EINVAL;
2262                         goto err_out;
2263                 }
2264         }
2265         return 0;
2266
2267  err_out:
2268         for (i = 0; i < 2; ++i)
2269                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2270
2271         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2272         mthca_alloc_cleanup(&dev->qp_table.alloc);
2273
2274         return err;
2275 }
2276
2277 void mthca_cleanup_qp_table(struct mthca_dev *dev)
2278 {
2279         int i;
2280         u8 status;
2281
2282         for (i = 0; i < 2; ++i)
2283                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2284
2285         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2286         mthca_alloc_cleanup(&dev->qp_table.alloc);
2287 }