2 * Copyright (C) 2001,2002,2003 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 #include <linux/init.h>
21 #include <asm/regdef.h>
22 #include <asm/mipsregs.h>
23 #include <asm/stackframe.h>
24 #include <asm/cacheops.h>
25 #include <asm/sibyte/board.h>
27 #define C0_ERRCTL $26 /* CP0: Error info */
28 #define C0_CERR_I $27 /* CP0: Icache error */
29 #define C0_CERR_D $27,1 /* CP0: Dcache error */
32 * Based on SiByte sample software cache-err/cerr.S
33 * CVS revision 1.8. Only the 'unrecoverable' case
44 * sb1_cerr_vec: code to be copied to the Cache Error
45 * Exception vector. The code must be pushed out to memory
46 * (either by copying to Kseg0 and Kseg1 both, or by flushing
47 * the L1 and L2) since it is fetched as 0xa0000100.
49 * NOTE: Be sure this handler is at most 28 instructions long
50 * since the final 16 bytes of the exception vector memory
51 * (0x170-0x17f) are used to preserve k0, k1, and ra.
56 * If this error is recoverable, we need to exit the handler
57 * without having dirtied any registers. To do this,
58 * save/restore k0 and k1 from low memory (Useg is direct
59 * mapped while ERL=1). Note that we can't save to a
60 * CPU-specific location without ruining a register in the
61 * process. This means we are vulnerable to data corruption
62 * whenever the handler is reentered by a second CPU.
67 #if CONFIG_SB1_CEX_ALWAYS_FATAL
72 * M_ERRCTL_RECOVERABLE is bit 31, which makes it easy to tell
73 * if we can fast-path out of here for a h/w-recovered error.
76 bgtz k1,attempt_recovery
81 * Unlock CacheErr-D (which in turn unlocks CacheErr-DPA).
82 * Ought to log the occurence of this recovered dcache error.
89 * k0 has C0_ERRCTL << 1, which puts 'DC' at bit 31. Any
90 * Dcache errors we can recover from will take more extensive
91 * processing. For now, they are considered "unrecoverable".
92 * Note that 'DC' becoming set (outside of ERL mode) will
93 * cause 'IC' to clear; so if there's an Icache error, we'll
94 * only find out about it if we recover from this error and
101 * k0 has C0_ERRCTL << 2, which puts 'IC' at bit 31. If an
102 * Icache error isn't indicated, I'm not sure why we got here.
103 * Consider that case "unrecoverable" for now.
105 bgez k0,unrecoverable
107 attempt_icache_recovery:
109 * External icache errors are due to uncorrectable ECC errors
110 * in the L2 cache or Memory Controller and cannot be
113 mfc0 k0,C0_CERR_I /* delay slot */
114 li k1,1 << 26 /* ICACHE_EXTERNAL */
116 bnez k1,unrecoverable
120 * Since the error is internal, the 'IDX' field from
121 * CacheErr-I is valid and we can just invalidate all blocks
124 cache Index_Invalidate_I,(0<<13)(k0)
125 cache Index_Invalidate_I,(1<<13)(k0)
126 cache Index_Invalidate_I,(2<<13)(k0)
127 cache Index_Invalidate_I,(3<<13)(k0)
129 /* Ought to log this recovered icache error */
132 /* Restore the saved registers */
138 /* Unrecoverable Icache or Dcache error; log it and/or fail */
147 LEAF(handle_vec2_sb1)
151 ori k0,k0,CONF_CM_UNCACHED
161 sll k0, k0, 3 # check CU0 (kernel?)
165 /* Get a valid Kseg0 stack pointer. Any task's stack pointer
166 * will do, although if we ever want to resume execution we
167 * better not have corrupted any state. */